KR102522132B1 - Integrated circuit providing galvanic isolation and semiconductor package including the same - Google Patents

Abstract

The integrated circuit includes a first inductor formed in the first conductive layer, a second inductor formed in a second conductive layer over the first conductive layer and inductively coupled to the first inductor, and a second inductor formed between the first conductive layer and the second conductive layer. It is formed on the three conductive layers and is at least partially in a direction perpendicular to at least one first pattern including the outermost pattern of the first inductor and at least one second pattern including the outermost pattern of the second inductor. An overlapping first shield may be included, and the first shield may be removed from a first area overlapping at least one first pattern and at least one second pattern in a vertical direction.

Description

An integrated circuit providing galvanic separation and a semiconductor package including the same

The technical idea of the present disclosure relates to an integrated circuit and a semiconductor package, and more particularly, to an integrated circuit providing galvanic separation and a semiconductor package including the same.

An isolation driver may be used to transmit and receive signals between circuits having different reference potentials. For example, galvanic isolation may refer to a principle that enables signal transmission while blocking current flow between circuits having different reference potentials, and an isolation driver based on galvanic isolation is a galvanic isolator. ) can be referred to as Demand for a separate driver is increasing in various applications, and thus a galvanic isolator providing high efficiency and high reliability may be required.

The technical idea of the present disclosure is to provide an integrated circuit providing galvanic separation having both high efficiency and high reliability, and a semiconductor package including the same.

An integrated circuit according to one aspect of the technical idea of the present disclosure includes a first inductor formed on a first conductive layer, a second inductor formed on a second conductive layer over the first conductive layer and inductively coupled to the first inductor, and a second inductor formed on the first conductive layer. At least one first pattern formed in the third conductive layer between the first conductive layer and the second conductive layer and including the outermost pattern of the first inductor and at least one including the outermost pattern of the second inductor. It may include a first shield that at least partially overlaps the second pattern in a vertical direction, wherein the first shield is removed from a first region overlapping at least one first pattern and at least one second pattern in a vertical direction. It can be.

According to an exemplary embodiment of the present disclosure, the first shield may not overlap the innermost pattern of the first inductor and the innermost pattern of the second inductor in a vertical direction.

According to an exemplary embodiment of the present disclosure, the integrated circuit may further include a passive element coupled between the first shield and the potentiostatic node.

According to an exemplary embodiment of the present disclosure, the third conductive layer may be closer to the first conductive layer than the second conductive layer.

According to an exemplary embodiment of the present disclosure, the first shield may be further removed in a second region overlapping at least one first pattern and at least one second pattern in a vertical direction.

According to an exemplary embodiment of the present disclosure, the integrated circuit may further include a first pattern extending from the third conductive layer through the first region and electrically connected to the innermost pattern of the first conductive layer.

According to an exemplary embodiment of the present disclosure, an integrated circuit includes a pad formed in a second conductive layer or a fourth conductive layer above the second conductive layer, electrically connected to an innermost pattern of the second inductor, and configured to be connected with a bonding wire. may further include.

According to an exemplary embodiment of the present disclosure, an integrated circuit is formed on a first conductive layer, connected to the first inductor, a third inductor having the same structure as the first inductor, formed on the second conductive layer, and a second inductor. It may further include a fourth inductor connected to the two inductors and having the same structure as the second inductor, and a second shield formed on the third conductive layer and having the same structure as the first shield.

According to an exemplary embodiment of the present disclosure, the integrated circuit may further include a modulator configured to generate a modulated signal based on an input signal and provide the modulated signal to the first inductor and the second inductor.

A semiconductor package according to one aspect of the technical idea of the present disclosure includes a first integrated circuit having the same structure as the above-described integrated circuit, a first wire electrically connected to the first integrated circuit, and a first wire from the first integrated circuit. and a second integrated circuit configured to receive the modulated signal.

According to an exemplary embodiment of the present disclosure, the second integrated circuit includes a first inductor formed in the first conductive layer. A second inductor formed in a second conductive layer over the first conductive layer, electrically connected to the first wire, and inductively coupled to the first inductor, and formed in a third conductive layer between the first conductive layer and the second conductive layer. and at least partially overlaps at least one first pattern including the outermost pattern of the first inductor and at least one second pattern including the outermost pattern of the second inductor in a vertical direction. , and the first shield may be removed from a first area overlapping at least one first pattern and at least one second pattern in a vertical direction.

According to an exemplary embodiment of the present disclosure, the second integrated circuit is formed on the first conductive layer, is connected to the first inductor, and a third inductor having the same structure as the first inductor is formed on the second conductive layer. , a fourth inductor connected to the second inductor and having the same structure as the second inductor, and a second shield formed on the third conductive layer and having the same structure as the first shield, It may further include a second wire electrically connected to the circuit and the fourth inductor, and the second integrated circuit may be configured to receive the modulated signal through the first wire and the second wire.

According to the integrated circuit and the semiconductor package according to exemplary embodiments of the present disclosure, galvanic separation can be effectively implemented in an integrated circuit manufactured by a semiconductor process, and thus galvanic separation can be easily employed in various applications. .

In addition, according to the integrated circuit and the semiconductor package according to the exemplary embodiment of the present disclosure, malfunction due to a sudden change in signal can be prevented, and thus galvanic separation with high reliability can be provided.

Effects obtainable in the exemplary embodiments of the present disclosure are not limited to the effects mentioned above, and other effects not mentioned are common knowledge in the art to which exemplary embodiments of the present disclosure belong from the following description. can be clearly derived and understood by those who have That is, unintended effects according to the implementation of the exemplary embodiments of the present disclosure may also be derived by those skilled in the art from the exemplary embodiments of the present disclosure.

1 is a block diagram illustrating a system according to an exemplary embodiment of the present disclosure.
2 is a timing diagram illustrating the signals of FIG. 1 according to an exemplary embodiment of the present disclosure.
3 is a circuit diagram illustrating a galvanic separator according to an exemplary embodiment of the present disclosure.
4 is a perspective view illustrating a galvanic separator according to an exemplary embodiment of the present disclosure.
FIG. 5 is a cross-sectional view showing a cross-section of a galvanic separator taken along line X1-X1' in FIG. 4 according to an exemplary embodiment of the present disclosure.
6A and 6B are diagrams illustrating examples of a shield according to exemplary embodiments of the present disclosure.
7A and 7B are diagrams illustrating examples of semiconductor packages according to exemplary embodiments of the present disclosure.

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings. The embodiments of the present invention are provided to more completely explain the present invention to those skilled in the art. Since the present invention can have various changes and various forms, specific embodiments will be illustrated in the drawings and described in detail. However, it should be understood that this is not intended to limit the present invention to the specific disclosed form, and includes all modifications, equivalents, and substitutes included in the spirit and scope of the present invention. In describing each figure, like reference numbers are used for like elements. In the accompanying drawings, the dimensions of the structures are shown enlarged or reduced than actual for clarity of the present invention.

Terms used in this application are only used to describe specific embodiments, and are not intended to limit the present invention. Singular expressions include plural expressions unless the context clearly dictates otherwise. In this application, terms such as "comprise" or "have" are intended to designate that there is a feature, number, step, operation, component, part, or combination thereof described in the specification, but one or more other features It should be understood that it does not preclude the possibility of the presence or addition of numbers, steps, operations, components, parts, or combinations thereof.

Unless defined otherwise, all terms used herein, including technical or scientific terms, have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs. Terms such as those defined in commonly used dictionaries should be interpreted as having a meaning consistent with the meaning in the context of the related art, and unless explicitly defined in the present application, interpreted in an ideal or excessively formal meaning. It doesn't work.

In this specification, the X-axis direction and the Y-axis direction may be referred to as a first horizontal direction and a second horizontal direction, respectively, and the Z-axis direction may be referred to as a vertical direction. The plane made up of the X and Y axes can be referred to as the horizontal plane, and components disposed in the +Z direction relative to other components can be referred to as being above other components, and -Z relative to other components. Components placed in the direction may be referred to as being below other components. Also, the area of an element may refer to a size occupied by an element on a plane parallel to a horizontal plane, and the width of an element may refer to a length in a direction orthogonal to a direction in which the element extends. A surface exposed in the +Z direction may be referred to as a top surface, a surface exposed in the -Z direction may be referred to as a bottom surface, and a surface exposed in the ±X direction or ±Y direction may be referred to as a bottom surface. It can be referred to as a side. For convenience of illustration, only some layers may be shown in the drawings, and a pattern made of a conductive material, such as a pattern of a conductive layer such as a wiring layer, may be referred to as a conductive pattern or may simply be referred to as a pattern.

1 is a block diagram illustrating a system 100 according to an exemplary embodiment of the present disclosure. As shown in FIG. 1 , system 100 may include a transmitter 120 , a galvanic separator 140 and a receiver 160 . Transmitter 120 and receiver 160 may each have different reference potentials, and galvanic separator 140 may transfer a signal containing information between transmitter 120 and receiver 160 .

In some embodiments, the system 100 may be an electronic device such as a TV or personal computer (PC), a vehicle, a vehicle, or a vehicle such as a personal mobility (PM) device, or may be a component included in the foregoing. In some embodiments, system 100 may correspond to a semiconductor package manufactured by a semiconductor process. For example, the transmitter 120, the galvanic separator 140, and the receiver 160 may be included in at least one integrated circuit (chip or die), and the system 100 may include a semiconductor package in which the at least one integrated circuit is packaged. can respond to As will be described later with reference to the drawings, galvanic separation can be provided by one semiconductor package, and thus galvanic separation can be easily employed in various applications.

Transmitter 120 may include a modulator 122 . The modulator 122 may receive an input signal IN and generate a modulated signal MOD by modulating the input signal IN. In some embodiments, modulator 122 may generate a modulated signal MOD from an input signal IN based on on/off keying (OOK). The input signal IN may include information to be provided to the receiver 160, and may be generated inside the transmitter 120 or received from the outside of the transmitter 120. In some embodiments, the galvanic separator 140 may include an inductor, and the modulator 122 may generate the modulated signal MOD using a resonant frequency based on the inductor included in the galvanic separator 140. . Examples of the input signal IN and the modulated signal MOD will be described later with reference to FIG. 2 .

The galvanic separator 140 may receive the modulated signal MOD from the transmitter 120 and generate a signal MOD′ derived from the modulated signal MOD. In some embodiments, the derived signal MOD′ may correspond to an attenuated signal from the modulated signal MOD. As described below with reference to the figures, the galvanic separator 140 may include inductively coupled inductors and may include a shield to reduce parasitic capacitance between the inductors. Accordingly, the galvanic separator 140 can be easily implemented in an integrated circuit manufactured by a semiconductor process and can be freed from malfunction due to rapid signal change.

Receiver 160 may include a demodulator 162 . The demodulator 162 may receive the derived signal MOD′ and generate an output signal OUT by demodulating the derived signal MOD′. In some embodiments, demodulator 162 may generate an output signal OUT from a derived signal MOD′ based on OOK. The output signal OUT may include information included in the input signal IN. In some embodiments, a driver that amplifies output signal OUT may be included in receiver 160 or included in system 100 external to receiver 160 . In some embodiments, the galvanic separator 140 may include an inductor, and the demodulator 162 may be included in the galvanic separator 140 to process a signal MOD′ derived using a resonant frequency based on the inductor. can

2 is a timing diagram illustrating the signals of FIG. 1 according to an exemplary embodiment of the present disclosure. It is noted that FIG. 2 is only an example, and the signals in FIG. 1 are not limited to the example in FIG. 2 . For convenience of illustration, delays between signals are ignored in FIG. 2 . In the following, FIG. 2 will be described with reference to FIG. 1 .

Referring to FIG. 2 , the input signal IN may be a pulse signal having an active state or an inactive state. For example, as shown in FIG. 2 , the input signal IN may be activated at times t1 and t3, while deactivated at times t2 and t4. The modulator 122 may generate a modulated signal MOD that oscillates in response to activation of the input signal IN. For example, as shown in FIG. 2 , the modulated signal MOD may oscillate from time t1 to time t2 and may oscillate from time t3 to time t4.

The galvanic separator 140 may generate an oscillating induced signal MOD′ from the oscillating modulated signal MOD. For example, as shown in FIG. 2 , the induced signal MOD′ may oscillate from time t1 to time t2 and may oscillate from time t3 to time t4. As shown in FIG. 2 , the magnitude (ie, amplitude or peak-to-peak value) of the induced signal MOD′ may be smaller than that of the modulated signal MOD. The demodulator 162 may generate an activated output signal OUT in response to the oscillating induced signal MOD'. For example, as shown in FIG. 2 , the output signal OUT may be activated from time t1 to time t2 and may be activated from time t3 to time t4.

3 is a circuit diagram illustrating a galvanic separator 300 according to an exemplary embodiment of the present disclosure. For example, the circuit diagram of FIG. 3 shows an equivalent circuit of the galvanic separator 300. In some embodiments, the modulated signal MOD and the derived signal MOD′ in FIG. 1 may be differential signals, and the galvanic separator 300 has an input terminal receiving the modulated signal MOD. (P11, P12) and output terminals (P21, P22) from which the derived signal (MOD') is output. Also, as shown in FIG. 3 , the galvanic separator 300 may have a balanced structure for differential signals.

Referring to FIG. 3 , the galvanic separator 300 may include inductors L11 and L12 connected in series on the transmitting side (or primary side), and inductors connected in series on the receiving side (or secondary side). (L21, L22). The transmitting-side inductors L11 and L12 may be inductively coupled to the receiving-side inductors L21 and L22, respectively, and may have a coupling coefficient k. Accordingly, the AC signal (ie, the AC component of the induced signal MOD′) corresponding to the AC signal (ie, the AC component of the modulated signal MOD) applied to the input terminals P11 and P12 corresponds to the An alternating current signal may be generated at the output terminals P21 and P22.

The transmit-side resistors R11 and R12 may correspond to the parasitic resistances of the transmit-side inductors L11 and L12, and the receive-side resistors R21 and R22 may correspond to the receive-side inductors L21 and L22. ) can correspond to the parasitic resistances of In addition, the first capacitor C1 and the second capacitor C2 may correspond to parasitic capacitors between the transmission-side inductors L11 and L12 and the reception-side inductors L21 and L22. As the parasitic capacitance, that is, the capacitances of the first capacitor C1 and the second capacitor C2 are lower, the galvanic separator 300 and the transmitter and receiver connected to the galvanic separator 300 can stably operate as designed. For example, when a large voltage change (ie, high dv/dt) occurs in the receiver 160 or a driver operating based on an output signal of the receiver 160, the first capacitor C1 and/or the second capacitor C1 A large current may be transmitted to the transmitter 120 through the capacitor C2, and as a result, a circuit included in the transmitter 120 may malfunction or even be destroyed. The higher the voltage change rate (that is, dv/dt) and the larger the capacitances of the first capacitor C1 and the second capacitor C2, the larger the current transferred. Accordingly, the transmission-side inductors L11 and L12 And reducing the parasitic capacitance between the inductors L21 and L22 of the receiving side may be required for stable operation and high reliability of the circuit. As described below with reference to the drawings, the galvanic separator 300 may include a shield at least partially shielding between the transmitting inductors L11 and L22 and the receiving inductors L21 and L22. and, accordingly, may have a reduced parasitic capacitance.

4 is a perspective view showing a galvanic separator 400 according to an exemplary embodiment of the present disclosure, and FIG. 5 is a galvanic separator 400 cut along line X1-X1′ in FIG. 4 according to an exemplary embodiment of the present disclosure. It is a cross-sectional view showing a cross-section of The galvanic separator 400 may correspond to the equivalent circuit of FIG. 3 and may include transmission-side inductors L11 and L12 and reception-side inductors L21 and L22. As described above with reference to FIG. 3, the galvanic separator 400 may be based on a differential signal and may have a balanced structure. Accordingly, the transmitting-side inductors L11 and L12 may have the same (eg, symmetrical) structure, and the receiving-side inductors L21 and L22 may have the same (eg, symmetrical) structure. The first shield S1 and the second shield S2 may have the same (eg, symmetrical) structure.

Referring to FIG. 4 , the galvanic separator 400 may be included in an integrated circuit manufactured by a semiconductor process. For example, an integrated circuit may include a plurality of conductive layers each formed and stacked by a series of sub-processes included in a semiconductor process, and the galvanic separator 400 may include patterns formed on the conductive layers. there is. As shown in FIG. 4 , the transmitting-side inductors L11 and L12 may be formed on the first conductive layer Mp, and the receiving-side inductors L21 and L22 may be formed on the second conductive layer Ms. can be formed in The transmitting-side inductors L11 and L12 may overlap the receiving-side inductors L21 and L22 in a vertical direction, that is, in the Z-axis direction, and thus may be inductively coupled to each other. It is noted that the inductor of the galvanic separator 400 is not limited to the shape and number of turns shown in FIG. 4 .

The galvanic separator 400 may include patterns 401 and 402 for applying signals to the inductors L11 and L12 of the transmission side. For example, as shown in FIG. 4 , the galvanic separator 400 may include patterns 401 and 402 extending from the fourth conductive layer Mq, and the patterns 401 and 402 may include vias. It may be electrically connected to the inductors L11 and L12 of the transmission side through the . In some embodiments, patterns 401 and 402 may correspond to input terminals P11 and P12 of FIG. 3 , respectively. In some embodiments, the patterns 401 and 402 may be formed on the same conductive layer as the first and second shields S1 and S2 described below (ie, Mq=Mr).

The galvanic separator 400 may include patterns 405 and 406 for outputting signals from the receiving-side inductors L21 and L22. For example, as shown in FIG. 5 , the galvanic separator 400 may include patterns 405 and 406 formed in the center of the inductors L21 and L22 in the second conductive layer Ms. In some embodiments, the patterns 405 and 406 may be pads exposed to the outside of the integrated circuit, and bonding wires may be connected to the patterns 405 and 406, respectively. In some embodiments, the patterns 405 and 406 may be electrically connected to pads formed on the upper conductive layer of the second conductive layer Ms, respectively, and bonding wires may be connected to the pads, respectively.

The galvanic separator 400 may include a shield at least partially shielding between the transmitting inductors L11 and L12 and the receiving inductors L21 and L22. For example, as shown in FIG. 4 , the first shield S1 may be formed on the third conductive layer Mr between the first conductive layer Mp and the second conductive layer Ms, and the transmission side It may be at least partially shielded between the inductor L11 of the receiving side and the inductor L21 of the receiving side. In addition, the second shield S2 may be formed on the third conductive layer Mr between the first conductive layer Mp and the second conductive layer Ms, and the transmission side inductor L12 and the reception side inductor (L22) can be at least partially shielded. As shown in FIG. 4 , the first shield S1 may be connected to a potentiostatic node (eg, a ground node) through a first passive element 403, and the second shield S2 may be connected to a second passive element ( 404) to a potentiostatic node (eg, a ground node). Each of the first passive element 403 and the second passive element 404 may have an impedance Z, and may include a resistance in some embodiments.

The shield may be removed in at least one region overlapping the inductors in a vertical direction. For example, as shown in FIG. 4 , the first shield S1 and the second shield S2 may be removed near the region where the patterns 401 and 402 extend. Accordingly, as will be described later with reference to FIGS. 6A and 6B , blocking of the magnetic field generated by the transmitting inductors L11 and L12 can be prevented.

Referring to FIG. 5 , the transmission-side inductor L11 may include patterns 410 to 419 extending in the Y-axis direction, and the reception-side inductor L21 may include patterns extending in the Y-axis direction ( 420 to 429). In addition, the first shield S1 may include patterns 431 and 432 extending in the Y-axis direction. As shown in FIG. 5 , the first conductive layer Mp on which the transmitting-side inductor L11 is formed may be closer to the substrate than the second conductive layer Ms on which the receiving-side inductor L21 is formed. That is, the first conductive layer Mp may be closer to an element (eg, transistor) of an integrated circuit than the second conductive layer Ms. In some embodiments, the first conductive layer Mp may correspond to a conductive layer closest to an element among conductive layers (ie, wiring layers) in which patterns for interconnecting elements are formed, and the second conductive layer ( Ms) may correspond to the conductive layer farthest from the element. As shown in FIG. 5, the thickness (or height) H1 of the patterns 410 to 419 included in the inductor L11 on the transmission side is the pattern 420 to 420 to 419 included in the inductor L21 on the reception side. 429) may be smaller than the thickness (or height) H2.

An insulator may be filled between the inductor L11 on the transmission side and the inductor L21 on the reception side. Also, as shown in FIG. 5 , the third conductive layer Mr on which the first shield S1 is formed may be closer to the first conductive layer Mp than the second conductive layer Ms. Accordingly, a high withstand voltage can be achieved due to the distance between the first shield S1 and the receiving side inductor L21. As described above with reference to FIG. 3 , parasitic capacitance may occur between inductors. In the galvanic separator 400 of FIG. 4 , the outermost pattern of the inductor may have a longer length than the innermost pattern, and accordingly, the parasitic capacitance generated by patterns located outside the inductor is reduced. It may be higher than the parasitic capacitance caused by patterns located inside.

In some embodiments, the shield may at least partially overlap in a vertical direction with at least one pattern including an outermost pattern of the inductor. For example, as shown in FIG. 5, the patterns 431 and 432 of the first shield S1 are the outermost patterns 410 and 415 of the inductor L11 on the transmission side and the inductor ( L21) may overlap with the outermost patterns 420 and 425 in a vertical direction. In addition, the patterns 431 and 432 of the first shield S1 are the patterns 411, 412, 416 and 417 of the inductor L11 on the transmission side and the patterns 421 and 421 of the inductor L21 on the reception side. 422, 426, 427) may additionally overlap. Accordingly, parasitic capacitance between overlapping patterns (eg, 410 and 420) by the first shield S1 may be removed, and as a result, parasitic capacitance may be reduced.

In some embodiments, the shield may not overlap in a vertical direction with at least one pattern including an innermost pattern of the inductor. For example, as shown in FIG. 5 , the patterns 431 and 432 of the first shield S1 are the innermost patterns 414 and 419 of the transmitting side inductor L11 and the receiving side inductor ( It may not overlap with the innermost patterns 424 and 429 of L21 in the vertical direction. In addition, the patterns 431 and 432 of the first shield S1 may not additionally overlap the patterns 413 and 418 of the inductor L11 on the transmission side and the patterns 423 and 428 on the reception side. . Accordingly, as shown by dotted arrows in FIG. 5 , the patterns (eg, 413, 414, 418, and 419) included in the inductor L11 of the transmitting side, which are not overlapped by the first shield S1, A magnetic field may be provided to the inductor L21 of the receiving side. In addition, as will be described later with reference to FIGS. 6A and 6B , the magnetic field generated by the first shield S1 is generated by the inductor L21 on the receiving side due to the eddy current generated in the first shield S1. can be provided additionally.

6A and 6B are diagrams illustrating examples of a shield according to exemplary embodiments of the present disclosure. For example, FIGS. 6A and 6B respectively show the current induced by the inductor with the shield and the eddy currents generated in the shield. In the following descriptions of FIGS. 6A and 6B , overlapping contents will be omitted.

Referring to FIG. 6A , the shield 60a may vertically overlap at least one pattern including the outermost pattern of the inductor and may be removed from the region R60. As shown in FIG. 6A, when current flows in the direction of the dotted line F61 in the inductor on the transmission side under the shield 60a, the eddy current in the outer portion of the shield 60a flows in the direction of the dotted line F61 and It can flow in the opposite direction (F62). Due to the shield 60a removed from the region R60, the eddy current may flow in a direction F62 opposite to the direction F63 from the inner portion to the outer portion. In the inner portion of the shield 60a, the eddy current can flow in the same direction as the current flowing in the inductor on the transmission side, and accordingly, as described above with reference to FIG. can be provided in In some embodiments, shield 60a may have a different shape than shown in FIG. 6A . For example, the shield 60a may have a rounded shape at four corners.

Referring to FIG. 6B , in some embodiments, the shield may include a plurality of patterns separated from each other. For example, as shown in FIG. 6B, the shield 60b may be removed from the first to fourth regions R61 to R64, respectively, and thus the first to fourth patterns 61b to 64b separated from each other. ) may be included. When current is generated in the direction of the dotted line F61 in the transmission-side inductor, eddy currents are generated along the directions F62, F64, F66, and F68 at the outer portions of the first to fourth patterns 61b to 64b, respectively. can Eddy currents may be generated in the inner portions of the first to fourth patterns 61b to 64b along the directions F63, F65, F67, and F69, respectively, and accordingly, the magnetic field generated by the shield 60b is may be provided in the inductor. In some embodiments, the shield may include any number of patterns of two or more, unlike that shown in FIG. 6B .

7A and 7B are diagrams illustrating examples of semiconductor packages according to exemplary embodiments of the present disclosure. As described above with reference to the drawings, the galvanic isolator may be included in an integrated circuit, and thus, in some embodiments, system 100 of FIG. 1 may be implemented in a single semiconductor package. Hereinafter, overlapping descriptions of FIGS. 7A and 7B will be omitted.

Referring to FIG. 7A , a semiconductor package 700a may include a first integrated circuit 710 and a second integrated circuit 720, and the first integrated circuit 710 and the second integrated circuit 720 respectively A connected first bonding wire W71 and a second bonding wire W72 may be included. Integrated circuits may be manufactured by semiconductor processing. For example, a semiconductor process may include a plurality of sub-processes for processing a wafer including a plurality of integrated circuits, and the integrated circuit (chip or die) may be separated from the wafer through dicing. The semiconductor package 700a may be a multi-chip package (MCP) including two or more chips.

The first integrated circuit 710 may include a modulator 712 and a galvanic separator 714 . The modulator 712 may be included in the same integrated circuit as the galvanic separator 714, namely the first integrated circuit 710. For example, the modulator 712 may include patterns formed on the same conductive layer as the conductive layer on which the transmission-side inductor of the galvanic separator 714 is formed. The modulator 712 may generate a differential signal, that is, a positive modulated signal MODp and a negative modulated signal MODn, by modulating the input signal IN. The galvanic separator 714 may have a balanced structure and may receive a positive modulated signal MODp and a negative modulated signal MODn from the modulator 712 .

The first bonding wire W71 may be connected to the inductor of the receiving side included in the galvanic separator 714 and may be connected to the first pad P21 of the second integrated circuit 720 . In addition, the second bonding wire W72 may be connected to another inductor on the receiving side included in the galvanic separator 714 and may be connected to the second pad P22 of the second integrated circuit 720 .

The second integrated circuit 720 may include a first pad P1 , a second pad P2 and a demodulator 722 . The demodulator 722 may receive a positive derived signal MODp′ from the first pad P1 and a negative derived signal MODn′ from the second pad P2. The demodulator 722 may generate an output signal OUT by demodulating the positive derived signal MODp' and the negative derived signal MODn'.

Referring to FIG. 7B , a semiconductor package 700b may include a first integrated circuit 710 and a second integrated circuit 720, and the first integrated circuit 710 and the second integrated circuit 720 respectively A connected first bonding wire W71 and a second bonding wire W72 may be included. The first integrated circuit 710 may include a modulator 712 and a galvanic separator 714 , and the second integrated circuit 720 may include a demodulator 722 and a galvanic separator 724 . Compared to the semiconductor package 700a of FIG. 7A , the second integrated circuit 720 of FIG. 7B may further include a galvanic separator 724 . Accordingly, the semiconductor package 700b of FIG. 7B may provide higher reliability (eg, higher breakdown voltage) than the semiconductor package 700a of FIG. 7A .

As above, exemplary embodiments have been disclosed in the drawings and specifications. Although the embodiments have been described using specific terms in this specification, they are only used for the purpose of explaining the technical idea of the present disclosure, and are not used to limit the scope of the present disclosure described in the claims. . Therefore, those of ordinary skill in the art will understand that various modifications and equivalent other embodiments are possible therefrom. Therefore, the true technical scope of protection of the present disclosure should be determined by the technical spirit of the appended claims.

Claims (12)

a first inductor formed on the first conductive layer;
a second inductor formed on a second conductive layer above the first conductive layer and inductively coupled to the first inductor; and
at least one first pattern formed in a third conductive layer between the first conductive layer and the second conductive layer and including an outermost pattern of the first inductor and an outermost pattern of the second inductor; A first shield at least partially overlapping in a vertical direction with at least one second pattern comprising
The first shield is removed from a first region overlapping the at least one first pattern and the at least one second pattern in a vertical direction. The method of claim 1,
The integrated circuit according to claim 1 , wherein the first shield does not overlap an innermost pattern of the first inductor and an innermost pattern of the second inductor in a vertical direction. The method of claim 1,
and a passive element coupled between the first shield and the potentiostatic node. The method of claim 1,
wherein the third conductive layer is closer to the first conductive layer than the second conductive layer. The method of claim 1,
The integrated circuit according to claim 1 , wherein the first shield is further removed from a second region overlapping the at least one first pattern and the at least one second pattern in a vertical direction. The method of claim 1,
and a first pattern extending from the third conductive layer through the first region and electrically connected to an innermost pattern of the first conductive layer. The method of claim 1,
and a pad formed on the second conductive layer or a fourth conductive layer above the second conductive layer, electrically connected to an innermost pattern of the second inductor, and configured to be connected to a bonding wire. The method of claim 1,
a third inductor formed on the first conductive layer, connected to the first inductor, and having the same structure as the first inductor;
a fourth inductor formed on the second conductive layer, connected to the second inductor, and having the same structure as the second inductor; and
and a second shield formed on the third conductive layer and having the same structure as the first shield. The method of claim 8,
and a modulator configured to generate a modulated signal based on an input signal and provide the modulated signal to the first inductor and the second inductor. a first integrated circuit having the same structure as the integrated circuit of claim 1;
a first wire electrically connected to the first integrated circuit;
and a second integrated circuit configured to receive a modulated signal from the first integrated circuit through the first wire. The method of claim 10,
The second integrated circuit,
a first inductor formed on the first conductive layer;
a second inductor formed on a second conductive layer above the first conductive layer, electrically connected to the first wire, and inductively coupled to the first inductor; and
at least one first pattern formed in a third conductive layer between the first conductive layer and the second conductive layer and including an outermost pattern of the first inductor and an outermost pattern of the second inductor; A first shield at least partially overlapping in a vertical direction with at least one second pattern comprising
The semiconductor package of claim 1 , wherein the first shield is removed from a first region overlapping the at least one first pattern and the at least one second pattern in a vertical direction. The method of claim 11,
The second integrated circuit,
a third inductor formed on the first conductive layer, connected to the first inductor, and having the same structure as the first inductor;
a fourth inductor formed on the second conductive layer, connected to the second inductor, and having the same structure as the second inductor; and
Further comprising a second shield formed on the third conductive layer and having the same structure as the first shield,
a second wire electrically connected to the first integrated circuit and the fourth inductor;
The semiconductor package, characterized in that the second integrated circuit is configured to receive the modulated signal through the first wire and the second wire.

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