KR102519809B1 - Methods of Updating Weight of Synapses of Neuromorphic Devices - Google Patents

Abstract

A method of updating synaptic weights of a neuromorphic device including a transistor and a memristor having a first electrode connected to a source electrode of the transistor is proposed.
The method inputs a low spike to the drain electrode of the transistor at a first timing, inputs a column spike to the second electrode of the memristor of the synapse at a second timing, and delays by a first delay time from the second timing. A low pulse is input to the drain electrode of the transistor at a third timing, a column pulse is input to the second electrode of the memristor at a fourth timing delayed by a second delay time from the second timing, and and inputting a gating pulse to the gate electrode of the transistor at a fifth timing delayed from timing 4 by a third delay time.

Description

Methods of Updating Weight of Synapses of Neuromorphic Devices {Methods of Updating Weight of Synapses of Neuromorphic Devices}

The technical spirit of the present invention relates to methods for updating weights of synapses of a neuromorphic device.

Recently, neuromorphic technology that imitates the human brain is attracting attention. Neuromorphic technology includes multiple pre-synaptic neurons, multiple post-synaptic neurons, and multiple synapses. Neuromorphic devices used in neuromorphic technology output pulses or spikes of various levels, sizes, or time according to learned states. A spike-time-dependent plasticity (STDP) method has been proposed as a method of updating the weights of synapses of a neuromorphic device. The STDP method is a method of generating pulses in a pre-synaptic neuron and a post-synaptic neuron, respectively, and updating synaptic weights according to overlapping regions of the pulses. In order to implement this STDP technology, a time division multiplexing (TDM) method and a method using a plurality of memristors have been proposed. However, the TDM method uses multiple timing periods synchronized to the global clock to implement STDP. Therefore, the TDM method requires a long time, so the update speed is very slow, and the method using a plurality of memristors has low stability of update because all the memristors must operate normally.

An object to be solved by the present invention is to provide methods for updating the weights of synapses of a neuromorphic device.

An object of the present invention is to provide methods capable of strengthening or suppressing the weight of synapses of a neuromorphic device within a short period of time.

An object to be solved by the present invention is to provide methods capable of effectively controlling the enhancement rate and inhibition rate of synapses of a neuromorphic device.

Various problems to be solved by the present invention are not limited to the problems mentioned above, and other problems not mentioned will be clearly understood by those skilled in the art from the description below.

A method for updating a synaptic weight of a neuromorphic device including a transistor and a memristor having a first electrode connected to a source electrode of the transistor according to an embodiment of the technical idea of the present invention includes A low spike is input to the drain electrode, a column spike is input to the second electrode of the memristor of the synapse at a second timing, and the drain electrode of the transistor is input at a third timing delayed by a first delay time from the second timing. A low pulse is input to , a column pulse is input to the second electrode of the memristor at a fourth timing delayed by a second delay time from the second timing, and a column pulse is inputted to the second electrode delayed by a third delay time from the fourth timing. It may include inputting a gating pulse to the gate electrode of the transistor at timing 5 .

The low spike may be generated in a pre-synaptic neuron and input to the drain electrode of the transistor through a low line.

The column spike may be generated in a post-synaptic neuron and input to the second electrode of the memristor through a column line.

The low pulse may be generated in a pre-synaptic neuron and input to the drain electrode of the transistor through a low line.

The column pulse may be generated in a post-synaptic neuron and input to the second electrode of the memristor through a column line.

The row spike and the column spike may occur while a gating signal is input to a gate electrode of the transistor.

The gating signal may be generated by a gating controller and input to the gate electrode of the transistor through a gating line.

Updating the synaptic weight may be performed during overlapping times of the row pulse, the column pulse, and the gating pulse.

In a method for updating weights of synapses of a neuromorphic device according to an embodiment of the technical idea of the present invention, a first spike is input from a first neuron to a first synapse at a first timing, and a second spike delayed from the first timing At timing 2, a second spike is input from a second neuron to a second synapse, at a third timing, a third spike is input from a third neuron to the first synapse and the second synapse, respectively, and from the third timing A first pulse is input from the first neuron to the first synapse at a delayed fourth timing, a second pulse is input from the second neuron to the second synapse at a fifth timing delayed from the third timing, and A third pulse is input from the third neuron to the first synapse and the second synapse at timing 6, a first gating pulse is input to the first synapse at timing 7, and the second pulse is input at timing 8. It may include inputting the second gating pulse to the synapse.

If the first spike time difference from the first timing to the third timing is smaller than the second spike time difference from the second timing to the third timing, first gating from the sixth timing to the seventh timing The time difference may be smaller than the second gating time difference from the sixth timing to the eighth timing.

When the first gating time difference is smaller than the second gating time difference, the weight of the first synapse may be updated more than the weight of the second synapse.

The first synapse may include a first memristor having a first transistor and a first electrode connected to a source electrode of the first transistor. The second synapse may include a second memristor having a second transistor and a first electrode connected to a source electrode of the second transistor. The first neuron may be connected to the drain electrode of the first transistor of the first synapse. The second neuron may be connected to a drain electrode of the second transistor of the second synapse. The third neuron may be connected to a second electrode of the first memristor of the first synapse and a second electrode of the second memristor of the second synapse.

The first gating pulse may be generated from a first gating controller connected to a gate electrode of the first transistor. The second gating pulse may be generated from a second gating controller connected to a gate electrode of the second transistor.

A first synapse including a first memristor having a first transistor and a first electrode connected to a source electrode of the first transistor according to an embodiment of the technical idea of the present invention, and a second transistor and the second transistor A method of updating weights of a second synapse including a second memristor having a first electrode connected to a source electrode includes inputting a first gating signal generated from a first gating controller to a gate electrode of the first transistor, and The second gating signal generated from the gating controller is input to the gate electrode of the second transistor to turn on the first transistor and the second transistor, and a first signal generated from a first pre-synaptic neuron connected to the first synapse. A low spike is input to the drain electrode of the first transistor of the first synapse through a first row line and a second row spike generated from a second pre-synaptic neuron connected to the second synapse is connected through a second row line. A column spike generated from a post-synaptic neuron input to the drain electrode of the second transistor of the second synapse and connected to the first synapse and the second synapse in common is passed through a column line to the second of the first memristor. electrode and the second electrode of the second memristor, the first and second gating signals are stopped, the first transistor and the second transistor are turned off, and the first pre-synaptic neuron A first low pulse is input to the drain electrode of the first transistor, a second low pulse generated from the second pre-synaptic neuron is input to the drain electrode of the second transistor, and generated from the post-synaptic neuron A column pulse is input to the second electrode of the first memristor and the second electrode of the second memristor, and a first gating pulse generated from the first gating controller is applied to the gate electrode of the first transistor. and a second gating pulse generated from the second gating controller is input to the gate electrode of the second transistor to turn on the first transistor and the second transistor.

If a first spike time difference from the first row spike to the column spike is smaller than a second spike time difference from the second row spike to the column spike, the column A first gating time difference from a timing at which a pulse is generated to a timing at which the first gating pulse is generated may be less than a second gating time difference from a timing at which the column pulse is generated to a timing at which the second gating pulse is generated.

If a first spike time difference from the first row spike to the column spike is greater than a second spike time difference from the second row spike to the column spike, the column pulse A first gating time difference from a timing at which the first gating pulse occurs to a timing at which the first gating pulse is generated may be greater than a second gating time difference from a timing at which the column pulse is generated to a timing at which the second gating pulse is generated.

When the first and second row pulses have positive (+) voltages, the column pulses may have negative (-) voltages.

When the first and second row pulses have negative (-) voltages, the column pulses may have positive (+) voltages.

Details of other embodiments are included in the detailed description and drawings.

According to the technical idea of the present invention, the weights of synapses can be rapidly updated within a short time.

According to the technical concept of the present invention, since synapses have only one memristor, the area occupied by synapses can be minimized.

According to the technical concept of the present invention, weights of synapses can be updated in various ways. That is, the reinforcement rate and suppression rate can be controlled.

Other effects by various embodiments of the present invention that are not mentioned will be mentioned within the text.

1A to 1C are block diagrams conceptually illustrating neuromorphic devices according to various embodiments of the inventive concept.
2 is a block diagram showing in detail a part of a neuromorphic device according to an embodiment of the technical idea of the present invention.
FIG. 3A is a timing diagram illustrating a method of enhancing synapses of the neuromorphic device shown in FIG. 2, and FIG. 3B is a timing diagram illustrating a method of inhibiting synapses of the neuromorphic device.
4 is a block diagram showing in detail a part of a neuromorphic device according to an embodiment of the technical concept of the present invention.
5A is a timing diagram illustrating a method of selectively strengthening synapses of the neuromorphic device shown in FIG. 4, and FIG. 5B is timing diagrams of superimposed pulses.
6 is a block diagram showing in detail a part of a neuromorphic device according to an embodiment of the technical idea of the present invention.
7A is a timing diagram illustrating a method of selectively inhibiting synapses of the neuromorphic device shown in FIG. 6, and FIG. 7B is timing diagrams of superimposed pulses.
8 is a block diagram showing in detail a part of a neuromorphic device according to an embodiment of the technical idea of the present invention.
FIG. 9 is a timing diagram illustrating a method of selectively strengthening synapses of the neuromorphic device shown in FIG. 8 .
10 is a block diagram showing in detail a part of a neuromorphic device according to an embodiment of the technical idea of the present invention.
FIG. 11 is a timing diagram illustrating a method of selectively inhibiting synapses of the neuromorphic device shown in FIG. 10 .
12 is a block diagram conceptually illustrating a pattern recognition system according to an embodiment of the technical idea of the present invention.

Advantages and features of the present invention, and methods for achieving them, will become clear with reference to the embodiments described below in detail in conjunction with the accompanying drawings. However, the present invention is not limited to the embodiments disclosed below and may be implemented in various different forms, but only the present embodiments make the disclosure of the present invention complete, and the common knowledge in the art to which the present invention belongs It is provided to fully inform the holder of the scope of the invention, and the present invention is only defined by the scope of the claims.

Terms used in this specification are for describing embodiments and are not intended to limit the present invention. In this specification, singular forms also include plural forms unless specifically stated otherwise in a phrase. As used herein, 'comprises' and/or 'comprising' means that a stated component, step, operation, and/or element is the presence of one or more other components, steps, operations, and/or elements. or do not rule out additions.

One element is referred to as 'connected to' or 'coupled to' with another element when it is directly connected or coupled to another element or through another element in the middle. include all cases. On the other hand, when one element is referred to as 'directly connected to' or 'directly coupled to' with another element, it indicates that another element is not intervened. “And/or” includes each and every combination of one or more of the recited items.

The spatially relative terms 'below', 'beneath', 'lower', 'above', 'upper', etc. It can be used to easily describe the correlation between elements or components and other elements or components. Spatially relative terms should be understood as encompassing different orientations of elements in use or operation in addition to the orientations shown in the figures. For example, when an element shown in the drawing is reversed, an element described as 'below' or 'beneath' another element may be placed 'above' the other element.

In addition, the embodiments described in this specification will be described with reference to cross-sectional views and/or plan views, which are ideal exemplary views of the present invention. In the drawings, the thicknesses of films and regions are exaggerated for effective explanation of technical content. Accordingly, the shape of the illustrative drawings may be modified due to manufacturing techniques and/or tolerances. Therefore, embodiments of the present invention are not limited to the specific shapes shown, but also include changes in shapes generated according to manufacturing processes. For example, a region shown at right angles may be rounded or have a predetermined curvature. Accordingly, the regions illustrated in the drawings have schematic properties, and the shapes of the regions illustrated in the drawings are intended to illustrate a specific shape of a region of a device and are not intended to limit the scope of the invention.

Like reference numbers designate like elements throughout the specification. Accordingly, the same reference numerals or similar reference numerals may be described with reference to other drawings, even if not mentioned or described in the drawings. Also, even if reference numerals are not indicated, description may be made with reference to other drawings.

In this specification, potentiation, set, and learning are used with the same or similar terms, and depressing, reset, and initiation are used with the same or similar meanings. will be. For example, an operation to lower the resistance of synapses will be described as reinforcement, set, or learning, and an operation to increase the resistance of synapses will be described as inhibition, reset, or initialization. In addition, when the synapses are strengthened, set, or learned, a progressively higher voltage/current can be output because the conductance increases, and when the synapses are inhibited, reset, or initialized, a gradually lower voltage/current can be output because the conductance decreases. can For convenience of description, data patterns, electrical signals, pulses, spikes, and fires may be interpreted as having the same, similar, or interchangeable meanings. In addition, voltage and current may be interpreted as having the same or interchangeable meanings.

1A to 1C are block diagrams conceptually illustrating neuromorphic devices according to various embodiments of the inventive concept.

Referring to FIG. 1A, a neuromorphic device according to an embodiment of the technical idea of the present invention includes a plurality of pre-synaptic neurons 10_1 to 10_n, row lines 15_1 to 15_n, and post-synaptic neurons ( 20_1 to 20_n), column lines 25_1 to 25_n, synapses 30_11 to 30_nn, row gating controllers 41_1 to 41_n, and row gating lines 46_1 to 46_n. The synapses 30_11 to 30_nn may include transistors 31_11 to 31_nn and memristors 35_11 to 35_nn connected in series, respectively. The post-synaptic neurons 20_1 to 20_n may include integrators 21_1 to 21_n and comparators 22_1 to 22_n, respectively. The row lines 15_1 to 15_n and the row gating lines 46_1 to 46_n may be parallel.

The gate electrodes of the transistors 31_11 to 31_nn of the synapses 30_11 to 30_nn may be electrically connected to the row gating controllers 41_1 to 41_n through row gating lines 46_1 to 46_n, respectively, and the transistors ( Drain electrodes of 31_11 to 31_nn) may be electrically connected to pre-synaptic neurons 10_1 to 10_n through row lines 15_1 to 15_n, and source electrodes of transistors 31_11 to 31_nn are respectively , It may be electrically connected to the first electrodes of the memristors 35_11 to 35_nn. The second electrodes of the memristors 35_11 to 35_nn may be electrically connected to the post-synaptic neurons 20_1 to 20_n through the column lines 25_1 to 25_n, respectively.

The input terminals of the integrators 31_1 to 31_n of the post-synaptic neurons 20_1 to 20_n are electrically connected to the second electrodes of the memristors 35_1 to 35_n through the column lines 25_1 to 25_n, respectively. input terminals of the comparators 22_1 to 22_n may be electrically connected to output terminals of the integrators 21_1 to 21_n, respectively.

Pre-synaptic neurons 10_1 to 10_n have synapses 30_11 to 30_nn through low lines 15_1 to 15_n in learning mode, reset mode, or reading mode electrical signals can be transmitted.

The post-synaptic neurons 20_1 to 20_n may transmit electrical pulses to the synapses 30_11 to 30_nn through the column lines 25_1 to 25_n in the learning mode or reset mode, and the column lines ( Electrical signals may be received from synapses 30_11 to 30_nn through 25_1 to 25_n.

Each of the row lines 15_1 to 15_n may be electrically connected to a plurality of synapses 30_11 to 30_nn by extending in a row direction from one of the pre-synaptic neurons 10_1 to 10_n.

Each of the column lines 25_1 to 25_n may extend in a column direction from one of the post-synaptic neurons 20_1 to 20_n and be electrically connected to a plurality of synapses 30_11 to 30_nn.

The row gating controllers 41_1 to 41_n may provide gating signals to the synapses 30_11 to 30_nn through the row gating lines 46_1 to 46_n.

Each of the row gating lines 46_1 to 46_n may extend in a row direction from one of the row gating controllers 41_1 to 41_n and be electrically connected to a plurality of synapses 30_11 to 30_nn.

Synapses 30_11 to 30_nn may be disposed at intersections of row lines 15_1 to 15_n and column lines 25_1 to 25_n. Synapses 30_11 to 30_nn sharing the same row line 15_1 to 15_n may share the same row gating line 46_1 to 46_n.

Referring to FIG. 1B, the neuromorphic device according to an embodiment of the technical idea of the present invention includes a plurality of pre-synaptic neurons 10_1 to 10_n, row lines 15_1 to 15_n, and post-synaptic neurons ( 20_1 to 20_n), column lines 25_1 to 25_n, synapses 30_11 to 30_nn, column gating controllers 42_1 to 42_n, and column gating lines 47_1 to 47_n. The column gating controllers 42_1 to 42_n may provide gating signals to the synapses 30_11 to 30_nn through the column gating lines 47_1 to 47_n. Each of the column gating lines 47_1 to 47_n may extend in a column direction from one of the column gating controllers 42_1 to 42_n and be electrically connected to a plurality of synapses 30_11 to 30_nn. Synapses 30_11 to 30_nn sharing the same column line 25_1 to 25_n may share the same column gating line 47_1 to 47_n. The gate electrodes of the transistors 31_11 to 31_nn of the synapses 30_11 to 30_nn may be electrically connected to the column gating controllers 42_1 to 42_n through the column gating lines 47_1 to 47_n, respectively, and the transistors ( Drain electrodes of 31_11 to 31_nn) may be electrically connected to pre-synaptic neurons 10_1 to 10_n through row lines 15_1 to 15_n, and source electrodes of transistors 31_11 to 31_nn are respectively , It may be electrically connected to the first electrodes of the memristors 35_11 to 35_nn.

Referring to FIG. 1C, the neuromorphic device according to an embodiment of the technical idea of the present invention includes a plurality of pre-synaptic neurons 10_1 to 10_n, row lines 15_1 to 15_n, and post-synaptic neurons ( 20_1 to 20_n), column lines 25_1 to 25_n, synapses 30_11 to 30_nn, row gating controllers 41_1 to 41_n, column gating controllers 42_1 to 42_n, row gating lines 46_1 to 46_n ), and column gating lines 47_1 to 47_n. The row gating controllers 41_1 to 41_n may provide gating signals to the synapses 30_11 to 30_nn through the row gating lines 46_1 to 46_n, and the column gating controllers 42_1 to 42_n may perform column gating. A gating signal may be provided to the synapses 30_11 to 30_nn through the lines 47_1 to 47_n. Synapses 30_11 to 30_nn sharing the same row line 15_1 to 15_n may share the same row gating line 46_1 to 46_n, and synapses 30_11 to share the same column line 25_1 to 25_n ~30_nn) may share the same column gating line (47_1~47_n). That is, the synapses 30_11 to 30_nn include one row line 15_1 to 15_n, one column line 25_1 to 25_n, one row gating line 46_1 to 46_n, and one column gating line 47_1. ~47_n) and can be electrically connected.

The synapses 30_11 to 30_nn may include row transistors 31r_11 to 31r_nn, column transistors 31c_11 to 31c_nn, and memristors 35_11 to 25_nn. Gate electrodes of the row transistors 31r_11 to 31r_nn may be electrically connected to the row gating controllers 41_1 to 41_n through the row gating lines 46_1 to 46_n, respectively, and the gate electrodes of the column transistors 31c_11 to 31c_nn The electrodes may be electrically connected to the column gating controllers 42_1 to 42_n through the column gating lines 47_1 to 47_n, respectively. The gate electrodes of the row transistors 31r_11 to 31r_nn and the drain electrodes of the column transistors 31r_11 to 31r_nn are electrically connected to the pre-synaptic neurons 10_1 to 10_n through the row lines 15_1 to 15_n, respectively. and the gate electrodes of the row transistors 31r_11 to 31r_nn and the source electrodes of the column transistors 31r_11 to 31r_nn may be electrically connected to the first electrodes of the memristors 35_11 to 35_nn, respectively. there is.

2a and 2b are block diagrams showing in detail a part of a neuromorphic device according to embodiments of the technical idea of the present invention.

Referring to FIG. 2A, the synapse 30 of the neuromorphic device according to an embodiment of the technical idea of the present invention may include a transistor 31 and a memristor 35, and a post-synaptic neuron 20 ) may include an integrator 21 and a comparator 22. The gate electrode of the transistor 31 of the synapse 30 may be electrically connected to the gating controller 40 through the gating line 45, and the drain electrode of the transistor 31 may be pre-synaptic through the low line 15. It may be electrically connected to the neuron 10 , and the source electrode of the transistor 31 may be electrically connected to the first electrode of the memristor 35 . The second electrode of the memristor 35 may be electrically connected to the post-synaptic neuron 20 through the column line 25 . 1A and 1B , the gating controller 40 may be either a row gating controller 41_nn or a column gating controller 42_nn, and the gating line 45 may be a row gating line 46_nn or a column gating line It can be one of (47_nn). The input terminal of the integrator 21 of the post-synaptic neuron 20 may be electrically connected to the second electrode of the memristor 35 through the column line 25, and the input terminal of the comparator 22 may be connected to the integrator ( 21) can be electrically connected to the output terminal.

Referring to FIG. 2B, the synapse 30 of the neuromorphic device according to an embodiment of the technical concept of the present invention may include a row transistor 31r, a column transistor 31c, and a memristor 35, , and the post-synaptic neuron 20 may include an integrator 21 and a comparator 22. Accordingly, the synapse 30 may electrically operate when at least one of the row transistor 31r or the column transistor 31c is turned on.

FIG. 3A is a timing diagram illustrating a method of strengthening the synapse 30 of the neuromorphic device shown in FIG. 2, and FIG. 3B is a timing diagram illustrating a method of inhibiting the synapse 30 of the neuromorphic device. is the timing

2 and 3a, in the method of strengthening the synapse 30 of the neuromorphic device according to an embodiment of the technical idea of the present invention, first, the transistor 31 of the synapse 30 is turned on, That is, in a state where the gating signal Gs is input to the gate electrode, low spikes Rs from the pre-synaptic neuron 10 to the drain electrode of the transistor 31 of the synapse 30 through the low line 15 It may include periodically and repeatedly inputting. It is assumed and described that the last low spike Rs rises at the first timing t1. That is, a rising edge of the last low spike Rs may be located at the first timing t1. In another embodiment of the technical idea of the present invention, it may be assumed that the last low spike Rs falls at the first timing t1. That is, the falling edge of the last low spike Rs may be located at the first timing t1.

The method may include generating a column spike (Cs) from a post-synaptic neuron (20) to select a synapse (30) to strengthen. Alternatively, it may include generating a column spike Cs from the post-synaptic neuron 20 at the second timing t2 according to the accumulation of the plurality of row spikes Rs. For example, as the low spikes Rs accumulate, if the voltage/current value integrated in the integrator 21 of the post-synaptic neuron 20 becomes higher than the reference voltage of the comparator 22, the post-synaptic neuron 20 ) can fire. The timing at which the column spike Cs occurs, that is, the second timing t2, may have a spike time difference Δts from the timing at which the last row spike Rs occurs, that is, the first timing t1. (Δts = t2 - t1) In extended embodiments of the technical concept of the present invention, the spike time difference (Δts) is the timing at which the column spike (Cs) occurs from the timing at which the last row spike (Rs) disappears (polling timing) It may be the time until

The method may include stopping the gating signal Gs provided from the gating controller 40 to the gate electrode of the transistor 31 at the second timing t2 when the column spike Cs occurs. That is, the transistor 31 of the synapse 30 may be turned off. Also, the method may include stopping generation of row spikes Rs when column spikes Cs occur. The spike time difference (Δts) may be smaller than the time interval (ΔtRs) of the row spikes (Rs). Accordingly, another row spike Rs may not occur any more between the last row spike Rs and the column spike Cs.

The method may include generating a low pulse Rp at a third timing t3 delayed by a delay time td in the pre-synaptic neuron 10 after the column spike Cs occurs. That is, a low pulse Rp for strengthening the synapse 30 may be input from the pre-synaptic neuron 10 to the drain electrode of the transistor 31 of the synapse 30 . For example, the low pulse Rp may have a positive voltage (+Vset/2) equal to or greater than 1/2 of the set voltage Vset. The method may include generating a column pulse (Cp) for strengthening the synapse 30 in the post-synaptic neuron 20 at a fourth timing (t4) slightly delayed from the third timing (t3). there is. That is, it may include inputting a column pulse Cp for strengthening the synapse 30 from the post-synaptic neuron 20 to the second electrode of the memristor 35 of the synapse 30 . The column pulse Cp may have a negative voltage (−Vset/2) less than 1/2 of the set voltage Vset. Even if the column pulse Cp does not have a negative (-) voltage, if the voltage difference between the low pulse Rp and the column pulse Cp is greater than the set voltage Vset, the current flows through the transistor 31 of the synapse 30 ) will flow from the drain electrode of the memristor 35 to the second electrode. Therefore, the resistance of the memristor 35 of the synapse 30 can be lowered, and the synapse 30 can be strengthened.

The row pulse Rp and the column pulse Cp may mostly overlap. For example, the duration dRp of the row pulse Rp may be greater than the duration dCp of the column pulse Cp. In this embodiment, the row pulse Rp rises earlier than the column pulse Cp and falls later than the column pulse Cp. The row pulse Rp and the column pulse Cp may rise/fall and may fall/rise at substantially the same timing. In other extended embodiments of the technical concept of the present invention, the row pulse Rp and the column pulse Cp may overlap in various ways. For example, the row pulse Rp may rise later than the column pulse Cp, and may poll first.

The method is performed by the gating controller at a fifth timing t5 after the gating time difference Δtg has elapsed from the fourth timing t4 when the column pulse Cp is generated or when the column pulse Cp is input to the synapse 30. It may include generating a gating pulse (Gp) at (40). That is, the gating pulse Gp generated from the gating controller 40 may be input to the gate electrode of the transistor 31 of the synapse 30 through the gating line 45 .

When the transistor 31 is turned on by inputting the gating pulse Gp, the overlapping region of the low pulse Rp and the column pulse Cp, that is, both the low pulse Rp and the column pulse Cp are During the input reinforcement time (ΔtP = t6 - t5), the memristor 35 of the synapse 30 may be reinforced. That is, the spike-timing-dependent plasticity (STDP) technology can be simply and effectively implemented within a shorter time than the conventional time division multiplexing (TDM) technology. In addition, since only one memristor is included, synaptic errors due to non-uniformity of the memristors can be minimized compared to when a plurality of memristors are used.

When the input of the column pulse (Cp) and the row pulse (Rp) are terminated and the reinforcement of the synapse 30 is terminated, the input of the gating pulse (Gp) may also be terminated. Thereafter, while the gating signal Gs of the next cycle is input to the gate electrode of the transistor 31 of the synapse 30, it may enter a preparation state for strengthening or suppressing another synapse 30 again.

Referring to Figures 2 and 3b, in the method of suppressing the synapse 30 of the neuromorphic device according to an embodiment of the technical idea of the present invention, first, the transistor 31 of the synapse 30 is turned on, That is, in a state where the gating signal Gs is input to the gate electrode, a column spike (Cs) from the post-synaptic neuron 20 to the second electrode of the memristor 35 of the synapse 30 through the column line 25 ) periodically and repeatedly. It is assumed and described that the last column spike Cs rises at the first timing t1. That is, the rising edge of the last column spike Cs may be located at the first timing t1. In another embodiment of the technical idea of the present invention, it may be assumed that the last column spike Cs polls at the first timing t1. That is, the falling edge of the last column spike Cs may be located at the first timing t1.

The method may include generating a low spike (Rs) from a pre-synaptic neuron (10) to select a synapse (30) to inhibit. Alternatively, the method may include generating a row spike Rs from the pre-synaptic neuron 10 at a second timing t2 as the plurality of column spikes Cs accumulate. For example, it may include generating a row spike Rs from the pre-synaptic neuron 10 at the second timing t2 as the column spikes Cs accumulate. For example, as the column spikes Cs accumulate, the pre-synaptic neuron 10 may fire. As mentioned above, the second timing t2 may have a spike time difference Δts from the first timing t1. (Δts = t2 - t1)

The method may include stopping the gating signal Gs provided from the gating controller 40 to the gate electrode of the transistor 31 at the second timing t2 when the low spike Rs occurs. That is, the transistor 31 of the synapse 30 may be turned off. Also, the method may include stopping the generation of the column spike (Cs) when the row spike (Rs) occurs. The spike time difference (Δts) may be greater than the time interval (ΔtCs) of column spikes (Cs). Accordingly, another column spike Cs may not occur any more between the last column spike Cs and the row spike Rs.

The method may include generating a column pulse Cp at a third timing t3 delayed by a delay time td in the post-synaptic neuron 20 after the row spike Rs occurs. That is, a column pulse Cp for strengthening the synapse 30 may be input from the post-synaptic neuron 20 to the second electrode of the memristor 35 of the synapse 30 . For example, the column pulse Cp may have a positive voltage (+Vset/2) equal to or greater than 1/2 of the set voltage Vet. The method may include generating a low pulse (Rp) for inhibiting the synapse 30 in the pre-synaptic neuron 10 at a fourth timing (t4) slightly delayed from the third timing (t3). there is. That is, it may include inputting a low pulse (Rp) for inhibiting the synapse 30 from the pre-synaptic neuron 10 to the drain electrode of the transistor 31 of the synapse 30. For example, the low pulse Rp may have a negative voltage (-Vset/2) less than 1/2 of the set voltage Vset. Even if the low pulse Rp does not have a negative (-) voltage, if the difference between the column pulse Cp and the low pulse Rp is greater than the set voltage Vset, the current flows through the memristor 32 of the synapse 30 ) will flow from the second electrode to the drain electrode of the transistor 31. Therefore, the resistance of the memristor 35 of the synapse 30 can be increased, and the synapse 30 can be inhibited. As mentioned above, in extended embodiments of the technical idea of the present invention, the column pulse (Cp) and the row pulse (Rp) can rise / fall and fall / rise at substantially the same timing, and the synapse 30 ) can be entered.

In the method, the gating controller ( 40) may include generating a gating pulse (Gp). That is, the gating pulse Gp generated from the gating controller 40 may be input to the gate electrode of the transistor 31 of the synapse 30 through the gating line 45 . As mentioned earlier, the gating time difference (Δtg) may be proportional to the spike time difference (Δts).

When the transistor 31 is turned on by inputting the gating pulse Gp, the area where the column pulse Cp and the low pulse Rp overlap, that is, both the column pulse Cp and the low pulse Rp are The memristor 35 of the synapse 30 may be inhibited during the input inhibition time (ΔtP = t6 - t5).

4 is a block diagram showing in detail a part of a neuromorphic device according to an embodiment of the technical concept of the present invention. For example, a plurality of pre-synaptic neurons 10_1 to 10_n and a plurality of row gating controllers 41_1 to 41_n sharing one post-synaptic neuron 20_n and one column line 25_n are shown. It became.

FIG. 5A is a timing diagram illustrating a method of selectively strengthening the synapses 30_1n to 30_nn of the neuromorphic device shown in FIG. 4, and FIG. 5B is timing diagrams of superimposed pulses.

Referring to FIGS. 4 and 5A , a method for selectively strengthening synapses 30_1n to 30_nn of a neuromorphic device according to an embodiment of the technical idea of the present invention is first performed by using each row gating controller 41_1 to 41_n In a state where the gating signals (Gs1 to Gsn) generated from each of the synapses (30_1n to 30_nn) are being input to the gate electrodes of the transistors (31_1n to 31_nn), each pre-synaptic neuron (10_1 to 10_n) It may include that the low spikes Rs1 to Rsn generated from are input to the drain electrodes of the transistors 31_1n to 31_nn of the respective synapses 30_1n to 30_nn.

A column spike Csn may occur from a post-synaptic neuron 20_n connected to a column line 25_n to which synapses 30_1n to 30_nn to be strengthened are connected in common. Alternatively, the post-synaptic neuron 20_n may fire as each of the low spikes Rs1 to Rsn accumulates. The fired post-synaptic neuron 20_n may be one of the plurality of post-synaptic neurons 20_1 to 20_n shown in FIG. 1A , in which the cumulative voltage/current first becomes larger than the reference voltage of the comparators 22_1n to 2_nn. there is.

Referring to FIG. 1A , when one post-synaptic neuron 20_n is fired, that is, when a column spike (Csn) occurs, the remaining post-synaptic neurons 20_1 to 20_n may not be fired any more. That is, the Winner Takes All rule may be applied. Also, no more low spikes Rs1 to Rsn may occur. Generation periods ΔtRs1 to ΔtRsn of the row spikes Rs1 to Rsn may be different from each other. Generation periods ΔtRs1 to ΔtRsn of the row spikes Rs1 to Rsn may be greater than spike generation time differences Δts1 to Δtsn between the row spikes Rs1 to Rsn and the column spike Csn.

When the column spike Csn occurs, generation and input of the gating signals Gs1 to Gsn may be stopped. That is, the transistors 31_1n to 31_nn of each of the synapses 30_1n to 30_nn may be turned off. Low pulses Rp1 to Rpn may occur at a timing tRp delayed by a first delay time td1 from the timing tCs at which the column spike Csn occurred, and a timing delayed by a second delay time td2 A column pulse Cpn may occur at (tCp). For example, the low pulses Rp1 to Rpn may occur at substantially the same timing tRp. In extended embodiments of the technical concept of the present invention, the timing tCp at which the column pulse Cpn is generated may be earlier than the timing tRp at which the row pulses Rp1 to Rpn are generated, or the low pulses The timing tRp at which Rp1 to Rpn occurs may be substantially the same as the timing tCp at which the column pulse Cpn occurs.

The row pulses Rp1 to Rpn may be input from the pre-synaptic neurons 10_1 to 10_n to the drain electrodes of the transistors 31_1n to 31_nn of the respective synapses 30_1n to 30_nn, and the column pulse ( Cpn) may be input from the fired post-synaptic neuron 20_n to the second electrodes of the memristors 35_1n to 35_nn of the respective synapses 30_1n to _30nn. At this time, the transistors 31_1n to 31_nn of each of the synapses 30_1n to 30_nn may not be turned on yet.

Gating pulses Gp1 to Gpn may be generated from the row gating controllers 41_1 to 41_n according to the gating time differences Δtg1 to Δtgn that are proportional to the spike time differences Δts1 to Δtsn. For example, the gating time differences Δtg1 to Δtgn may be larger as the respective spike time differences Δts1 to Δtsn are larger, and may be smaller as the respective spike time differences Δts1 to Δtsn are smaller. That is, the gating pulse Gp1 may be input first to the synapse 30_1n having the smallest spike time difference Δtg1. The gating pulse Gpn may be input last to the synapse 30_nn having the largest spike time difference Δtgn. Each of the gating pulses (Gp1 to Gpn) is generated from the corresponding row gating controllers 41_1 to 41_n, and the respective synapses 30_1n to 30_nn are generated through the corresponding row gating lines 46_1 to 46_n. It may be input to the gate electrodes of the transistors 31_1n to 31_nn.

As the gating pulses Gp1 to Gpn are input, synapses 30_1n to 30_nn may be sequentially turned on. Therefore, each synapse (30_1n ~ 30_nn) can be sequentially strengthened. At this time, the memristors of each synapse 30_1n to 30_nn are as much as the regions S1 to Sn overlapped by the row pulses Rp1 to Rpn, the column pulses Cpn, and the gating pulses Gp1 to Gpn. (35_1n to 35_nn) may be reinforced.

After each synapse (30_1n to 30_nn) is strengthened, the gating signals (Gs1 to Gsn) for preparation for strengthening the synapses (30_11 to 30_nn) connected to other post-synaptic neurons (20_n) are applied to each synapse ( It may be input to the gate electrodes of the transistors 31_11 to 31_nn of 30_11 to 30_nn.

In the spirit of the present invention, the gating pulses Gp1 to Gpn may have a square shape or a triangular shape. In order to show various embodiments of the technical idea of the present invention, the gate pulses Gp1 to Gpn are shown in a triangular shape compared to FIGS. 3A and 3B.

In FIG. 5B , regions S1 to Sn overlapped by row pulses Rp1 to Rpn, column pulses Cp, and gating pulses Gp1 to Gpn are shown by hatching on the right side. The hatched regions may be overlapped integral values of corresponding row pulses Rp1 to Rpn, column pulses Cp, and corresponding gating pulses Gp1 to Gpn. Referring to FIG. 5B , it can be seen that overlapping areas of the row pulses Rp1 to Rpn, the column pulses Cpn, and the gating pulses Gp1 to Gp2 vary according to the gating time differences Δtg1 to Δtgn. . That is, it can be seen that the degree of strengthening of each of the synapses 30_1n to 30_nn is different according to the gating time differences Δtg1 to Δtgn. In detail, by generating the gating pulse Gp1 at the shortest gating time difference (Δtg1) according to the shortest spike time difference (Δts1), the specific synapse 30_1n can be strengthened for the longest time (Δtp1). Since the gating pulse Gpn is generated at the longest gating time difference Δtgn according to the longest spike time difference Δtgn, a specific synapse 30_nn can be strengthened for the shortest time Δtpn. In addition, since the gating pulses Gp1 to Gpn have a triangular shape, the spike time differences Δts1 to Δtsn and the reinforcement times Δtp1 of the synapses 30_1n to 30_nn according to the gating time differences Δtg1 to Δtgn. ~tpn) may be larger than when the gating pulses Gp1 to Gpn have a rectangular shape. According to the technical idea of the present invention, according to the gating time differences (Δtg1 to Δtgn), that is, the timings (tg1 to tgn) at which the gating pulses (Gp1 to Gpn) are generated and the shapes of the gating pulses (Gp1 to Gpn) The potentiation ratio of synapses (30_11 to 30_nn) may vary.

6 is a block diagram showing in detail a part of a neuromorphic device according to an embodiment of the technical idea of the present invention. For example, a plurality of post-synaptic neurons sharing one pre-synaptic neuron 10_n through one row line 15_n and one row gating controller 41_n through one row gating line 46_n Fields 20_1 to 20_n are shown.

FIG. 7A is a timing diagram illustrating a method of selectively inhibiting the synapses 30_n1 to 30_nn of the neuromorphic device shown in FIG. 6, and FIG. 7B is timing diagrams of superimposed pulses.

Referring to FIGS. 6 and 7A , a method for selectively inhibiting synapses 30_n1 to 30_nn of a neuromorphic device according to an embodiment of the technical idea of the present invention is first generated from a corresponding row gating controller 41_n. Column spikes generated from the post-synaptic neurons 20_1 to 20_n in a state where the gating signal Gsn is being input to the gate electrodes of the transistors 31_n1 to 31_nn of the corresponding synapses 30_n1 to 30_nn It may include inputting the fields Cs1 to Csn to the second electrodes of the memristors 35_1n to 35_nn of the respective synapses 30_1n to 30_nn. Generation periods ΔtCs1 to ΔtCsn of the column spikes Cs1 to Csn may be different from each other.

While each column spike (Cs1 ~ Csn) is input to each synapse (30_n1 ~ 30_nn), synapses (30_n1 ~ 30_nn) from pre-synaptic neurons (10_n) to which synapses to be inhibited (30_n1 ~ 30_nn) are commonly connected A low spike Rs may be generated and input to drain electrodes of the transistors 31_n1 to 31_nn of ). That is, synapses 30_n1 to 30_nn to be inhibited may be selected.

When the low spike Rs occurs, generation and input of the low gating signals Gs1 to Gsn may be stopped. That is, the transistors 31_n1 to 31_nn of the synapses 30_n1 to 30_nn may be turned off. Column pulses Cp1 to Cpn may be generated at a timing tCp delayed by a first delay time td1 from the timing tRs at which the row spike Rs occurred, and a timing delayed by a second delay time td2 A low pulse Rpn may occur at (tRp). For example, the column pulses Cp1 to Cpn may occur at substantially the same timing tCp. In extended embodiments of the technical idea of the present invention, the timing tRp of generating the row pulse Rpn may be earlier than the timing tCp of generating the column pulses Cp1 to Cpn, or the column pulses The timing tCp at which (Cp1 to Cpn) occurs may be substantially the same as the timing tRp at which the low pulse Rpn occurs.

Column pulses Cp1 to Cpn may be generated from post-synaptic neurons 20_1 to 20_n and input to second electrodes of memristors 35_n1 to 35_nn of synapses 30_n1 to 30_nn, And the low pulse Rp may be generated from the pre-synaptic neuron 10_n and input to the drain electrodes of the transistors 31_n1 to 31_nn of the respective synapses 30_n1 to 30_nn. The column pulses Cp1 to Cpn may occur at substantially the same timing tp. For example, the column pulses Cp1 to Cpn may have a positive (+) voltage (+Vset/2) of 1/2 or more of the set voltage (Vset), and the low pulse (Rpn) may be It may have a negative (-) voltage (-Vset/2) less than 1/2 of the set voltage (Vset). At this time, the transistors 31_n1 to 31_nn of each of the synapses 30_n1 to 30_nn may not be turned on yet.

According to the spike time differences (Δts1 to Δtsn) between the last column spikes (Cs1 to Csn) and the row spike (Rsn), the gating pulses (Gp1 to Gpn) are set at different timings (tg1 to tgn). It may be generated from the synapses 41_1 to 41_n and input to the gate electrodes of the transistors 31_n1 to 31_nn of the synapses 30_n1 to 30_nn. As mentioned above, the shorter the spike time differences Δts1 to Δtsn, the shorter the gating time differences Δtg1 to Δtgn. That is, as the spike time differences Δts1 to Δtsn are shorter, the gating pulses Gp1 to Gpn may be generated at a faster timing, and as the spike time differences Δts1 to Δtsn are longer, the gating pulses Gp1 to Gpn may be generated at a delayed timing. can happen

The transistors 31_n1 to 31_nn of the synapses 30_n1 to 30_nn may be turned on by the gating pulses Gp1 to Gpn, and the memristors 35_n1 to 35_nn of the synapses 30_n1 to 30_nn this can be suppressed.

After each synapse (30_n1 ~ 30_nn) is inhibited, the gating signals (Gs1 ~ Gsn) for preparation for inhibiting synapses (30_11 ~ 30_nn) connected to other pre-synaptic neurons (10_n) are applied to each synapse ( It may be input to the gate electrodes of the transistors 31_11 to 31_nn of 30_11 to 30_nn. As mentioned above, the gating pulses Gp1 to Gpn may have a square shape or a triangular shape.

In FIG. 7B , regions S1 to Sn overlapped by the column pulses Cp1 to Cpn, the row pulse Rp, and the gating pulses Gp1 to Gpn are shown using hatching on the right side. The hatched regions may be overlapped integral values of corresponding column pulses Cp1 to Cpn, row pulse Rp, and corresponding gating pulses Gp1 to Gpn. Referring to FIG. 7B , regions S1 to Sn overlap with column pulses Cp1 to Cpn, row pulses Rpn, and gating pulses Gp1 to Gpn according to gating time differences Δtg1 to Δtgn. this may vary. Synapses 30_1n to 30_nn may be inhibited according to the size of each region S1 to Sn. That is, the suppression rate of the memristors 35_n1 to 35_nn of the synapses 30_n1 to 30_nn may vary by the area S1 to Sn where the column pulses Cp1 to Cpn and the row pulse Rpn overlap. .

According to the technical idea of the present invention, according to the gating time differences (Δtg1 to Δtgn), that is, the timings (tg1 to tgn) at which the gating pulses (Gp1 to Gpn) are generated and the shapes of the gating pulses (Gp1 to Gpn) A deprssion ratio of synapses (30_11 to 30_nn) may vary.

8 is a block diagram showing in detail a part of a neuromorphic device according to an embodiment of the technical idea of the present invention. For example, a plurality of pre-synaptic neurons sharing one post-synaptic neuron 20_n, one column line 25_n, one column gating controller 43_n, and one column gating line 47_n ( 10_1 to 10_n) are shown. FIG. 9 is a timing diagram illustrating a method of selectively strengthening synapses 30_1n to 30_nn of the neuromorphic device shown in FIG. 8 .

Referring to FIGS. 8 and 9 , a method for selectively strengthening synapses 30_1n to 30_nn of a neuromorphic device according to an embodiment of the technical idea of the present invention first uses gating generated from a column gating controller 42_n. Low generated from each of the pro-synaptic neurons 10_1 to 10_n while the signals Gs1 to Gsn are being input to the gate electrodes of the transistors 31_1n to 31_nn of the respective synapses 30_1n to 30_nn Spikes Rs1 to Rsn may be input to drain electrodes of transistors 31_1n to 31_nn of synapses 30_1n to 30_nn.

A column spike Csn may occur from a post-synaptic neuron 20_n connected to a column line 25_n to which synapses 30_1n to 30_nn to be strengthened are connected in common. Alternatively, the post-synaptic neuron 20_n may fire as each of the low spikes Rs1 to Rsn accumulates. The fired post-synaptic neuron 20_n may be one of the plurality of post-synaptic neurons 20_1 to 20_n shown in FIG. 1B , in which the cumulative voltage/current first becomes larger than the reference voltage of the comparators 22_1n to 22_nn. there is. As mentioned earlier, a winner-takes-all rule may apply. Referring to FIG. 1B , when one post-synaptic neuron 20_n is fired, that is, when a column spike (Csn) occurs, the remaining post-synaptic neurons 20_1 to 20_n may not be fired any more. Also, no more low spikes Rs1 to Rsn may occur.

When the column spike Csn occurs, generation and input of the gating signals Gs1 to Gsn may be stopped. That is, the transistors 31_1n to 31_nn of each of the synapses 30_1n to 30_nn may be turned off. Low pulses Rp1 to Rpn may occur at a timing tRp delayed by a first delay time td1 from the timing tCs at which the column spike Csn occurred, and a timing delayed by a second delay time td2 A column pulse Cpn may occur at (tCp).

The row pulses Rp1 to Rpn may be input from the pre-synaptic neurons 10_1 to 10_n to the drain electrodes of the transistors 31_1n to 31_nn of the respective synapses 30_1n to 30_nn, and the column pulse ( Cpn) may be input from the post-synaptic neuron 20_n to the second electrodes of the memristors 35_1n to 35_nn of the respective synapses 30_1n to _30nn. At this time, the transistors 31_1n to 31_nn of each of the synapses 30_1n to 30_nn may not be turned on yet.

Gating pulses Gp1 to Gpn may be generated from the column gating controllers 42_1 to 42_n according to the gating time differences Δtg1 to Δtgn that are proportional to the spike time differences Δts1 to Δtsn. For example, the gating time differences Δtg1 to Δtgn may be larger as the respective spike time differences Δts1 to Δtsn are larger, and may be smaller as the respective spike time differences Δts1 to Δtsn are smaller. Each of the gating pulses Gp1 to Gpn is generated from the corresponding column gating controllers 42_1 to 42_n and passes through the corresponding column gating lines 47_1 to 47_n to the corresponding synapses 30_1n to 30_nn. It may be input to the gate electrodes of the transistors 31_1n to 31_nn.

As the gating pulses Gp1 to Gpn are input, synapses 30_1n to 30_nn may be sequentially turned on. Therefore, each synapse (30_1n ~ 30_nn) can be sequentially strengthened. At this time, the memristors of each synapse 30_1n to 30_nn are as much as the regions S1 to Sn overlapped by the row pulses Rp1 to Rpn, the column pulses Cpn, and the gating pulses Gp1 to Gpn. (35_1n to 35_nn) may be reinforced. According to the technical idea of the present invention, the reinforcement rate of the synapses 30_1n to 30_nn is increased according to the respective gating time differences Δtg1 to Δtgn, that is, the generation timings tg1 to tgn of the respective gating pulses Gp1 to Gpn. It can vary.

After each synapse (30_1n to 30_nn) is strengthened, the gating signals (Gs1 to Gsn) for preparation for strengthening the synapses (30_11 to 30_nn) connected to other post-synaptic neurons (20_n) are applied to each synapse ( It may be input to the gate electrodes of the transistors 31_11 to 31_nn of 30_11 to 30_nn.

According to the technical idea of the present invention, according to the gating time differences (Δtg1 to Δtgn), that is, the timings (tg1 to tgn) at which the gating pulses (Gp1 to Gpn) are generated and the shapes of the gating pulses (Gp1 to Gpn) Reinforcement rates of synapses (30_11 to 30_nn) may vary.

10 is a block diagram showing in detail a part of a neuromorphic device according to an embodiment of the technical idea of the present invention. For example, a plurality of post-synaptic neurons (20_1 to 20_n) sharing one pre-synaptic neuron (10_n) and one row line (21_n), a plurality of column lines (25_1 to 25_n), a plurality of Column gating controllers 42_1 to 42_n and a plurality of column gating lines 47_1 to 47_n are shown. FIG. 11 is a timing diagram illustrating a method of selectively inhibiting synapses 30_n1 to 30_nn of the neuromorphic device shown in FIG. 10 .

10 and 11, a method for selectively suppressing synapses 30_n1 to 30_nn of a neuromorphic device according to an embodiment of the technical idea of the present invention is first obtained from column gating controllers 42_1 to 42_n. In a state in which the generated gating signals (Gs1 to Gsn) are input to the gate electrodes of the transistors (31_n1 to 31_nn) of the corresponding synapses (30_n1 to 30_nn), the post-synaptic neurons (20_1 to 20_n) It may include that the column spikes Cs1 to Csn generated from are input to the second electrodes of the memristors 35_n1 to 35_nn of the respective synapses 30_n1 to 30_nn. Generation periods ΔtCs1 to ΔtCsn of the column spikes Cs1 to Csn may be different from each other.

While each column spike (Cs1 ~ Csn) is input to each synapse (30_n1 ~ 30_nn), synapses (30_n1 ~ 30_nn) from pre-synaptic neurons (10_n) to which synapses to be inhibited (30_n1 ~ 30_nn) are commonly connected A low spike Rs may be generated and input to drain electrodes of the transistors 31_n1 to 31_nn of ).

When the low spike Rs occurs, generation and input of the column gating signals Gs1 to Gsn may be stopped. That is, the transistors 31_n1 to 31_nn of the synapses 30_n1 to 30_nn may be turned off. Column pulses Cp1 to Cpn may be generated at a timing tCp delayed by a first delay time td1 from the timing tRs at which the row spike Rs occurred, and a timing delayed by a second delay time td2 A low pulse Rpn may occur at (tRp).

Column pulses Cp1 to Cpn may be generated from post-synaptic neurons 20_1 to 20_n and input to second electrodes of memristors 35_n1 to 35_nn of synapses 30_n1 to 30_nn, And the low pulse Rp may be generated from the pre-synaptic neuron 10_n and input to the drain electrodes of the transistors 31_n1 to 31_nn of the respective synapses 30_n1 to 30_nn. The column pulses Cp1 to Cpn may occur at substantially the same timing tp. For example, the column pulses Cp1 to Cpn may have a positive voltage (+Vset/2) equal to or greater than 1/2 of the set voltage Vset, and the low pulse Rpn may have a set voltage ( It may have a negative (-) voltage (-Vset/2) of 1/2 or less of Vset. In extended embodiments of the technical idea of the present invention, the row pulse Rpn may have a lower positive (+) voltage than the column pulses Cp1 to Cpn. At this time, the transistors 31_n1 to 31_nn of each of the synapses 30_n1 to 30_nn may not be turned on yet.

Column gating controller at different timings (tg1 to tgn) according to spike time differences (Δts1 to Δtsn) between the last column spikes (Cs1 to Csn) and the row spike (Rsn) It may be generated from the fields 42_1 to 42_n and input to the gate electrodes of the transistors 31_n1 to 31_nn of the synapses 30_n1 to 30_nn. As mentioned above, the shorter the spike time differences Δts1 to Δtsn, the shorter the gating time differences Δtg1 to Δtgn.

The transistors 31_n1 to 31_nn of the synapses 30_n1 to 30_nn may be turned on by the gating pulses Gp1 to Gpn, and the memristors 35_n1 to 35_nn of the synapses 30_n1 to 30_nn this can be suppressed.

After each synapse (30_n1 ~ 30_nn) is inhibited, the gating signals (Gs1 ~ Gsn) for preparation for inhibiting synapses (30_11 ~ 30_nn) connected to other pre-synaptic neurons (10_n) are applied to each synapse ( It may be input to the gate electrodes of the transistors 31_11 to 31_nn of 30_11 to 30_nn. As mentioned above, the gating pulses Gp1 to Gpn may have a square shape or a triangular shape.

According to the technical idea of the present invention, according to the gating time differences (Δtg1 to Δtgn), that is, the timings (tg1 to tgn) at which the gating pulses (Gp1 to Gpn) are generated and the shapes of the gating pulses (Gp1 to Gpn) The inhibition rate of synapses (30_11 to 30_nn) may vary.

12 is a block diagram conceptually illustrating a pattern recognition system 900 according to an embodiment of the technical idea of the present invention. For example, the pattern recognition system 900 may be a speech recognition system, an imaging recognition system, a code recognition system, a signal recognition system, or other It can be one of the systems for recognizing various patterns.

Referring to FIG. 12 , the pattern recognition system 900 according to an embodiment of the technical idea of the present invention includes a central processing unit 910, a memory unit 920, a communication control unit 930, a network 940, and an output unit ( 950), an input unit 960, an analog-to-digital converter 970, a neuromorphic unit 980, and/or a bus 990.

The central processing unit 910 generates and transmits various signals for learning of the neuromorphic unit 980, and various signals for recognizing patterns such as voice and video according to output from the neuromorphic unit 980. processing and functions. The central processing unit 910 may be connected to a memory unit 920, a communication control unit 930, an output unit 950, an analog-to-digital converter 970, and a neuromorphic unit 980 through a bus 990. can

The memory unit 920 may store various information required to be stored in the pattern recognition system 900 . The memory unit 920 includes a volatile memory device such as DRAM or SRAM, a non-volatile memory device such as PRAM, MRAM, ReRAM, or NAND flash memory. It may include at least one of a memory or various storage units such as a hard disk drive (HDD) or solid state drive (SSD).

The communication control unit 930 may transmit and/or receive recognized data such as voice and video to a communication control unit of another system through the network 940 .

The output unit 950 may output data such as recognized voice and video in various ways. For example, the output unit 950 may include a speaker, printer, monitor, display panel, beam projector, hologrammer, or other various output devices.

The input unit 960 may include at least one of a microphone, camera, scanner, touch pad, keyboard, mouse, mouse pen, or various sensors.

The analog-to-digital converter 970 may convert analog data input from the input device 960 into digital data.

The neuromorphic unit 980 may perform learning, recognition, etc. using the data output from the analog-to-digital converter 970, and may output data corresponding to the recognized pattern. . The neuromorphic unit 980 may include at least one of neuromorphic elements according to various embodiments of the inventive concept.

Although the embodiments of the present invention have been described with reference to the accompanying drawings, those skilled in the art can implement the present invention in other specific forms without changing the technical spirit or essential features. You will understand that there is Therefore, it should be understood that the embodiments described above are illustrative in all respects and not restrictive.

10: pre-synaptic neurons
15: low line
20: post-synaptic neuron
21: integrator
25: comparator
25: column line
30: Synapse
31: transistor
35: memristor
40: gating controller
41: low gating controller
42: column gating controller
45: gating line
46: low gating line
47: column gating line
Δtsn: spike time difference
Δtgn: gating time difference

Claims (18)

A method for updating a weight of a synapse comprising a transistor and a memristor having a first electrode connected to a source electrode of the transistor,
A low spike is input to the drain electrode of the transistor at a first timing;
At a second timing, a column spike is input to the second electrode of the memristor of the synapse;
inputting a low pulse to the drain electrode of the transistor at a third timing delayed by a first delay time from the second timing;
inputting a column pulse to the second electrode of the memristor at a fourth timing delayed by a second delay time from the second timing; and
A method of updating weights of synapses of a neuromorphic device comprising inputting a gating pulse to a gate electrode of the transistor at a fifth timing delayed by a third delay time from the fourth timing.
◈Claim 2 was abandoned when the registration fee was paid.◈ According to claim 1,
The low spike is generated in a pre-synaptic neuron and is input to the drain electrode of the transistor through a low line to update weights of synapses of a neuromorphic device. ◈Claim 3 was abandoned when the registration fee was paid.◈ According to claim 1,
The column spike is generated in a post-synaptic neuron and is input to the second electrode of the memristor through a column line to update weights of synapses of a neuromorphic device.
◈Claim 4 was abandoned when the registration fee was paid.◈ According to claim 1,
The low pulse is generated in a pre-synaptic neuron and is input to the drain electrode of the transistor through a low line to update weights of synapses of a neuromorphic device.
◈Claim 5 was abandoned when the registration fee was paid.◈ According to claim 1,
The column pulse is generated in a post-synaptic neuron and is input to the second electrode of the memristor through a column line to update weights of synapses of a neuromorphic device.
◈Claim 6 was abandoned when the registration fee was paid.◈ According to claim 1,
The row spike and the column spike occur while a gating signal is input to the gate electrode of the transistor.
◈Claim 7 was abandoned when the registration fee was paid.◈ According to claim 6,
The gating signal is generated in a gating controller and is input to the gate electrode of the transistor through a gating line to update weights of synapses of a neuromorphic device.
◈Claim 8 was abandoned when the registration fee was paid.◈ According to claim 1,
Updating the weights of the synapses is performed during the overlapping time of the row pulse, the column pulse, and the gating pulse.
A first spike is input from a first neuron to a first synapse at a first timing;
A second spike is input from a second neuron to a second synapse at a second timing delayed from the first timing,
At a third timing, a third spike is input from a third neuron to the first synapse and the second synapse, respectively;
A first pulse is input from the first neuron to the first synapse at a fourth timing delayed from the third timing;
A second pulse is input from the second neuron to the second synapse at a fifth timing delayed from the third timing;
A third pulse is input from the third neuron to the first synapse and the second synapse at a sixth timing;
A first gating pulse is input to the first synapse at a seventh timing, and
A method of updating weights of synapses of a neuromorphic device comprising inputting a second gating pulse to the second synapse at an eighth timing.
◈Claim 10 was abandoned when the registration fee was paid.◈ According to claim 9,
If a first spike time difference from the first timing to the third timing is smaller than a second spike time difference from the second timing to the third timing,
The method of updating weights of synapses of a neuromorphic device where a first gating time difference from the sixth timing to the seventh timing is less than a second gating time difference from the sixth timing to the eighth timing.
◈Claim 11 was abandoned when the registration fee was paid.◈ According to claim 10,
If the first gating time difference is smaller than the second gating time difference, the weight of the first synapse is updated more than the weight of the second synapse.
◈Claim 12 was abandoned when the registration fee was paid.◈ According to claim 9,
The first synapse includes a first transistor and a first memristor having a first electrode connected to a source electrode of the first transistor,
The second synapse includes a second transistor and a second memristor having a first electrode connected to a source electrode of the second transistor,
The first neuron is connected to the drain electrode of the first transistor of the first synapse,
The second neuron is connected to the drain electrode of the second transistor of the second synapse, and
wherein the third neuron is connected to a second electrode of the first memristor of the first synapse and a second electrode of the second memristor of the second synapse.
◈Claim 13 was abandoned when the registration fee was paid.◈ According to claim 12,
The first gating pulse is generated from a first gating controller connected to the gate electrode of the first transistor, and
The method of claim 1 , wherein the second gating pulse is generated from a second gating controller connected to the gate electrode of the second transistor.
A first synapse comprising a first memristor having a first transistor and a first electrode connected to the source electrode of the first transistor, and a second synapse having a second transistor and a first electrode connected to the source electrode of the second transistor. A method for updating weights of a second synapse including a memristor,
A first gating signal generated from a first gating controller is input to a gate electrode of the first transistor, and a second gating signal generated from a second gating controller is input to a gate electrode of the second transistor, thereby controlling the first transistor and the second gating signal. 2 transistor is turned on,
A first row spike generated from a first pre-synaptic neuron connected to the first synapse is input to a drain electrode of the first transistor of the first synapse through a first row line and a second free spike connected to the second synapse - A second row spike generated from a synaptic neuron is input to a drain electrode of the second transistor of the second synapse through a second row line;
A column spike generated from a post-synaptic neuron commonly connected to the first synapse and the second synapse is input to a second electrode of the first memristor and a second electrode of the second memristor through a column line;
The first and second gating signals are stopped so that the first transistor and the second transistor are turned off;
a first low pulse generated from the first pre-synaptic neuron is input to the drain electrode of the first transistor and a second low pulse generated from the second pre-synaptic neuron is input to the drain electrode of the second transistor; become,
A column pulse generated from the post-synaptic neuron is input to the second electrode of the first memristor and the second electrode of the second memristor, and
A first gating pulse generated from the first gating controller is input to the gate electrode of the first transistor, and a second gating pulse generated from the second gating controller is input to the gate electrode of the second transistor to generate the first gating pulse. A method of updating weights of synapses of a neuromorphic device comprising turning on a transistor and the second transistor.
◈Claim 15 was abandoned when the registration fee was paid.◈ According to claim 14,
If a first spike time difference from the first row spike to the column spike is smaller than a second spike time difference from the second row spike to the column spike,
A first gating time difference from the timing at which the column pulse is generated to the timing at which the first gating pulse is generated is less than a second gating time difference from the timing at which the column pulse is generated to the timing at which the second gating pulse is generated. How to update the weights of synapses of .
◈Claim 16 was abandoned when the registration fee was paid.◈ According to claim 15,
If a first spike time difference from the first row spike to the column spike is greater than a second spike time difference from the second row spike to the column spike;
A first gating time difference from the timing at which the column pulse is generated to the timing at which the first gating pulse is generated is greater than a second gating time difference from the timing at which the column pulse is generated to the timing at which the second gating pulse is generated. How to update the weights of synapses of .
◈Claim 17 was abandoned when the registration fee was paid.◈ According to claim 14,
The method of updating weights of synapses of a neuromorphic device in which the first and second row pulses have a positive (+) voltage and the column pulse has a negative (-) voltage.
◈Claim 18 was abandoned when the registration fee was paid.◈ According to claim 14,
The method of updating weights of synapses of a neuromorphic device in which the first and second row pulses have a negative (-) voltage and the column pulse has a positive (+) voltage.

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