KR102491579B1 - Memory device, memory module and memory system - Google Patents

Abstract

A memory device, memory module and memory system are disclosed. A memory device according to an embodiment of the present disclosure includes a memory cell array including a plurality of memory areas; a data pattern providing unit providing a preset data pattern; and a write circuit configured to write a data pattern provided from the data pattern provider into a memory area corresponding to the address when a first write command and an address are received from an external device.

Description

Memory device, memory module and memory system

The present disclosure relates to a semiconductor memory device, and relates to a memory device, a memory module, and a memory system that write preset data into a memory cell array without using an input/output circuit when a specific write command is received.

Semiconductor memory devices such as DRAM are widely used as main memories of computers, smart watches, smart phones, tablet PCs, and the like. As hardware becomes lighter and faster and software becomes more complex, there is a demand for a memory with reduced power consumption and increased operating speed. Accordingly, various technologies are being developed to provide a memory device that operates at low power and at high speed.

Prior Art 1: US Patent Application Publication No. US2011-0239021 (2011.09.29)
Prior Art 2: US Patent Application Publication No. US2014-0101381 (2014.04.10)

An object to be solved by the technical idea of the present disclosure is to provide a memory device in which circuit power consumption is reduced. Another object of the present invention is to provide a memory device, a memory module, and a memory system that operate at low power and high speed.

A memory device according to an embodiment of the present disclosure for achieving the above technical problem includes a memory cell array including a plurality of memory areas; a data pattern providing unit providing a preset data pattern; and a write circuit that writes the data pattern provided from the data pattern provider into a memory area corresponding to the address signal when a first write command and an address signal are received from an external device.

A memory system according to an embodiment of the present disclosure for achieving the above technical problem compares input data input from the outside with a preset data pattern, and when the input data and the data pattern match, a pattern write command and address information. a memory controller that transmits; and a memory device internally generating the data pattern in response to the pattern writing command and writing the data pattern into a memory area corresponding to the address information.

According to a memory device, a memory module, and a memory system according to technical concepts of the present disclosure, when data to be written in the memory device matches a preset data pattern, the memory device transmits the preset data pattern to a memory cell without receiving data from the outside. By writing to the array, power consumption of memory devices, memory modules and memory systems can be reduced. Also, since the occupancy time of the data bus used by the memory device is reduced, the efficiency of the data bus may be increased.

In order to more fully understand the drawings cited in the detailed description of the present disclosure, a brief description of each drawing is provided.
1 is a block diagram illustrating a memory system according to an exemplary embodiment of the present disclosure;
2 is a block diagram schematically illustrating a memory device according to an exemplary embodiment of the present disclosure.
3 is a block diagram illustrating an implementation example of a memory device according to an exemplary embodiment of the present disclosure.
FIG. 4 is a diagram illustrating an example of the data pattern providing unit of FIG. 3 .
5A and 5B are diagrams illustrating a method of setting a write command.
6 is a table showing an example of setting a write command according to an embodiment of the present disclosure.
7 is a timing diagram of an input signal of a memory device during a write operation according to an embodiment of the present disclosure.
8 is a timing diagram illustrating an example of address setting during a write operation according to an embodiment of the present disclosure.
9 is a flowchart illustrating a writing method of a memory device according to an exemplary embodiment of the present disclosure.
10 is a block diagram illustrating an implementation example of a memory controller according to an exemplary embodiment of the present disclosure.
11 is a flowchart illustrating a method of operating a memory controller according to an exemplary embodiment of the present disclosure.
12 is a flowchart illustrating a method of operating an electronic device to which a memory device according to an exemplary embodiment of the present disclosure is applied.
13 is a flowchart illustrating a writing method of a memory device according to an exemplary embodiment of the present disclosure.
14 is a flowchart illustrating an operating method of an electronic device to which a memory device according to an exemplary embodiment of the present disclosure is applied.
15A and 15B are diagrams illustrating an embodiment in which a memory controller and pattern buffers respectively provided in the memory device are updated in an electronic device according to an embodiment of the present disclosure.
16 is a table showing an example of setting a write command according to an embodiment of the present disclosure.
17 is a flowchart illustrating a writing method of a memory device according to an exemplary embodiment of the present disclosure.
18 is a flowchart illustrating an operating method of an electronic device to which a memory device according to an exemplary embodiment of the present disclosure is applied.
19 is a block diagram schematically illustrating a memory device according to an exemplary embodiment of the present disclosure.
20 is a block diagram illustrating a memory system according to an exemplary embodiment of the present disclosure.
21 is a block diagram illustrating an implementation example of a memory controller according to an exemplary embodiment of the present disclosure.
22 is a table illustrating an example of setting a write command according to an embodiment of the present disclosure.
23 is a block diagram illustrating a memory system according to an exemplary embodiment of the present disclosure.
24 is a block diagram schematically illustrating a memory device according to an exemplary embodiment of the present disclosure.
25 is a schematic block diagram of a memory controller according to an exemplary embodiment of the present disclosure.
26 is a flowchart illustrating an operating method of an electronic device to which a memory device according to an embodiment of the present disclosure is applied.
27 is a block diagram illustrating a memory system according to an exemplary embodiment of the present disclosure.
28 is a timing diagram of input signals applied to ranks of a memory system.
29A and 29B are block diagrams illustrating a memory controller and a memory module according to an exemplary embodiment of the present disclosure.
30 is a block diagram illustrating a stacked memory device including a plurality of semiconductor layers.
31 is a block diagram illustrating a computer system according to an embodiment of the present disclosure.
32 is a block diagram illustrating a computer system including a memory system according to an exemplary embodiment of the present disclosure.

Hereinafter, various embodiments of the present disclosure will be described in association with the accompanying drawings. Various embodiments of the present disclosure may have various changes and various embodiments, and specific embodiments are illustrated in the drawings and related detailed descriptions are described. However, this is not intended to limit the various embodiments of the present disclosure to specific embodiments, and should be understood to include all changes and/or equivalents or substitutes included in the spirit and technical scope of the various embodiments of the present disclosure. In connection with the description of the drawings, like reference numerals have been used for like elements.

Expressions such as “include” or “may include” that may be used in various embodiments of the present disclosure indicate the existence of a function, operation, or component that is disclosed, and may include one or more additional functions, operations, or components. components, etc. are not limited. In addition, in various embodiments of the present disclosure, terms such as "include" or "have" are intended to designate that there are features, numbers, steps, operations, components, parts, or combinations thereof described in the specification, It should be understood that it does not preclude the possibility of the presence or addition of one or more other features, numbers, steps, operations, components, parts, or combinations thereof.

Expressions such as “or” in various embodiments of this disclosure include any and all combinations of the words listed together. For example, "A or B" may include A, may include B, or may include both A and B.

Expressions such as “first,” “second,” “first,” or “second,” used in various embodiments of the present disclosure may modify various components of various embodiments, but limit the components. I never do that. For example, the above expressions do not limit the order and/or importance of corresponding components. The above expressions may be used to distinguish one component from another. For example, the first user device and the second user device are both user devices and represent different user devices. For example, a first element may be termed a second element, and similarly, a second element may also be termed a first element, without departing from the scope of rights of various embodiments of the present disclosure.

When an element is referred to as being "connected" or "connected" to another element, the element may be directly connected or connected to the other element, but with the other element. It should be understood that other new components may exist between the other components. On the other hand, when an element is referred to as being “directly connected” or “directly connected” to another element, it will be understood that no new element exists between the element and the other element. should be able to

Terms used in various embodiments of the present disclosure are only used to describe a specific embodiment, and are not intended to limit various embodiments of the present disclosure. Singular expressions include plural expressions unless the context clearly dictates otherwise.

Unless defined otherwise, all terms used herein, including technical or scientific terms, have the same meaning as commonly understood by one of ordinary skill in the art to which various embodiments of the present disclosure belong.

Terms such as those defined in commonly used dictionaries should be interpreted as having a meaning consistent with the meaning in the context of the related art, and unless explicitly defined in various embodiments of the present disclosure, ideal or excessively formal. not interpreted as meaning

1 is a block diagram illustrating a memory system according to an exemplary embodiment of the present disclosure.

Referring to FIG. 1 , a memory system 1000 may include a memory controller 200 and a memory device 100 . The memory controller 200 may include a data comparison unit 210 , and the memory device 100 may include a memory cell array 110 , a read/write circuit 150 and a data pattern providing unit 180 .

The memory controller 200 provides various signals for controlling the memory device 100 , for example, a command CMD and an address signal ADDR to the memory device 100 . The memory controller 200 may exchange data DATA with the memory device 100 .

The memory device 100 stores data DATA in the memory cell array 110 or transmits data stored in the memory cell array 110 to the memory controller 200 based on signals received from the memory controller 200 . can be provided to

When data DATA is written in the memory device 100, the memory controller 200 may transmit a write command, an address signal ADDR indicating a memory area to be written, and the data DATA to be written to the memory device 100. . Meanwhile, the memory controller 200 according to an embodiment of the present disclosure does not provide the data DATA to the memory device 100 when the data DATA to be written in the memory device 100 matches a preset data pattern. However, a command instructing writing of a preset data pattern (eg, a pattern write command) and an address signal ADDR may be provided to the memory device 100 .

In this case, the preset data pattern is data that is recognized as identical between the memory controller 200 and the memory device 100, and may be data previously agreed between the memory controller 200 and the memory device 100. For example, the data pattern may be data in which consecutive bits are '0' or '1'. Alternatively, the data pattern may be data previously provided to the memory device 100 as write data. As another example, the data pattern may be data set by a user (hereinafter referred to as user-set data). The user setting data refers to a data pattern set by a host during operation of the memory device 100 or the memory system 1000 . Also, the data pattern may be data frequently written to the memory device 100 . In addition, the data pattern may be data set during the operation of the memory device 100 and the memory system 1000 .

The memory controller 200 may provide a command instructing writing of a preset data pattern (eg, a pattern write command) and an address signal ADDR to the memory device 100 . At this time, the memory device 100 may internally generate the data pattern or select one of pre-stored data patterns and write the data pattern into the memory cell array 110 .

The memory controller 200 may include a data comparator 210 . When a write request is received from an external device, for example, a host, the data comparator 210 compares the data requested to be written with a preset data pattern and determines whether or not they match. When the data requested to be written matches the data pattern, the memory controller 200 may transmit the pattern write command and address ADDR to the memory device 100 . When data requested to be written does not match the data pattern, the memory controller 200 may transmit a normal write command, an address signal ADDR, and data DATA to the memory device 100 . Data DATA may be transmitted through a data bus (not shown) that transmits data between the memory controller 200 and the memory device 100 .

The memory device 100 may be a random access memory requiring high processing speed. As a random access memory, the memory device 100 may include dynamic random access memory (DRAM) cells. The memory device 100 may be a DRAM chip including DRAM cells. Alternatively, the memory device 100 may include other memory cells capable of random access, such as magnetic RAM (MRAM) cells, spin transfer torque magnetic RAM (STT-MRAM) cells, phase change RAM (PRAM) cells, and resistive RAM (RRAM) cells. may also include

The memory cell array 110 may include a plurality of memory areas composed of a plurality of memory cells. As described above, the memory cell may be a DRAM cell, and may include various types of memory cells capable of random access. Also, the memory cells may be single-level cells each storing single-bit data or multi-level cells storing at least two bits of data.

The data pattern provider 180 may generate a preset data pattern and provide the data pattern to the read/write circuit 150 . In one embodiment, the data pattern provider 180 may generate a data pattern in response to a pattern write command received from the memory controller 200 .

The read/write circuit 150 may write data DATA into the memory cell array 110 or read data DATA from the memory cell array 110 . The read/write circuit 150 may write data DATA into a memory area corresponding to the address ADDR received from the memory controller 200 or may read data DATA from the memory area. According to the present embodiment, when a pattern write command and an address ADDR are received from the memory controller 200, the read/write circuit 150 converts the data pattern provided from the data pattern providing unit 180 to the address signal ADDR. It is possible to write to the memory area corresponding to .

In the memory system 1000 according to the present embodiment, when data DATA requested to be written in the memory device 100 matches a preset data pattern, the memory controller 200 does not transmit the data DATA, and the pattern The write command and the address signal ADDR are provided to the memory device 100, the memory device 100 does not receive the data DATA from the memory controller 200, and data is internally generated based on the pattern write command. A data pattern selected in response to a pattern writing command among patterns or data patterns stored therein may be written into the memory cell array 110 . Accordingly, since data transmission/reception does not occur between the memory controller 200 and the memory device 100 , power consumption of the memory system 1000 may be reduced. Also, since the data transfer time between the memory controller 200 and the memory device 100 decreases during a write operation of the memory system 1000 , the operating speed of the memory system 1000 may increase.

2 is a block diagram schematically illustrating a memory device according to an exemplary embodiment of the present disclosure.

Referring to FIG. 2 , the memory device 100 includes a memory cell array 110, a control logic 120, an address register 130, a row decoder 140, a column decoder 160, and a read/write circuit 150. , an input/output buffer 170 and a data pattern providing unit 180. In addition, the memory device 100 may further include various types of circuits used for writing and reading data.

The memory cell array 110 may include memory cells disposed in an area where a plurality of bit lines BL and a plurality of word lines WL intersect. A plurality of memory cells may constitute a memory area, and each memory area may include memory cells in a write unit.

The control logic 120 includes a command decoder 121 and a mode register 122 and may control overall operations of the memory device 100 . The command decoder 121 receives signals related to a command CMD applied from the outside, for example, a chip select signal (/CS), a row address strobe signal (/RAS), and a column address strobe signal (Column Address Strobe). A decoded command signal may be internally generated by decoding an address strobe (/CAS), a write enable signal (/WE), and a clock enable signal (CKE). In one embodiment, the control logic 120 may also decode the address signal ADDR to generate a control signal related to the write command. The mode register 122 may set an internal register in response to a mode register signal for specifying an operation mode of the memory device 100 and an address signal ADDR.

The address register 130 may temporarily store an address signal ADDR input from the outside. Then, the address register 130 may transfer the row address X-ADD to the row decoder 140 and the column address Y-ADD to the column decoder 160 .

Each of the row decoder 140 and the column decoder 160 may include a plurality of switches. The row decoder 140 selects the word line WL in response to the row address X-ADDR, and the column decoder 160 selects the bit line BL in response to the column address Y-ADDR. .

The input/output buffer 170 provides data DATA read from the memory cell array 110 to the outside of the memory device 100, for example, a memory controller (200 in FIG. 1), or transmits data DATA received from the outside. It can be provided to the read/write circuit 150. Data DATA may be transmitted to the outside or received from the outside through the data pad DQ[m-1:0] (or referred to as a data pin).

The data pattern provider 180 may provide a preset data pattern to the read/write circuit 150 . The data pattern providing unit 180 may generate a data pattern in response to a pattern writing command received from the outside, for example, the memory controller 200 . In one embodiment, the data pattern providing unit 180 may select and output one of a plurality of preset data patterns in response to a pattern writing command. For example, the data pattern providing unit 180 may select a data pattern corresponding to a pattern write command from a pattern buffer (not shown) in which a plurality of data patterns are stored, and output the selected data pattern.

The read/write circuit 150 includes a write circuit 151 and a read circuit 152 and may write data to or read data from the memory cell array 110 . For example, the write circuit 151 may include a plurality of write drivers, and the read circuit 152 may include a plurality of sense amplifiers.

The write circuit 151 selectively transfers data DATA provided from the input/output buffer 170, that is, data received from the outside and data patterns provided from the data pattern providing unit 180 to the memory cell array 110. can be entered in When a normal write command is received from the outside, the write circuit 151 writes data DATA provided from the input/output buffer 170 into the memory cell array 110, and when a pattern write command is received from the outside, write The circuit 151 may write the data pattern provided from the data pattern provider 180 into the memory cell array 110 .

As described above, when a pattern write command and an address ADDR are received from the memory controller 200, the memory device 100 according to an embodiment of the present disclosure transmits a preset data pattern to a memory area corresponding to the address signal ADDR. can be entered in Accordingly, since data is not received from the outside when writing a preset data pattern, power consumption of the memory device 100 may be reduced. In addition, data DATA is transmitted from the memory controller 200 through a data bus. When a preset data pattern is written, data transmission/reception does not occur between the memory controller 200 and the memory device 100. Since the bus is not used, the data bus occupancy time can be reduced. At this time, since the data bus can be used for other operations of the memory device or other operations of the memory device 100 (for example, a read operation and a continuously performed write operation, etc.), data bus utilization increases. It can be.

3 is a block diagram illustrating an implementation example of a memory device according to an exemplary embodiment of the present disclosure. FIG. 3 shows main configurations of a memory device in relation to a write operation, and the configurations of the memory device shown in FIG. 2 may be included in the memory device of FIG. 3 . A write operation of the memory device will be described in detail with reference to FIG. 3 .

Referring to FIG. 3 , the memory device 100a includes a memory cell array 110, a command decoder 121, a write circuit 151, an input buffer 171, a data pattern provider 180, and a selector 190. can include

The command decoder 121 controls operations of the data pattern providing unit 180 and the selector 190 by decoding a command CMD related to a write operation received from the outside, for example, the memory controller (200 in FIG. 1 ). signals can be generated. During a write operation, the command decoder 121 may receive one of a normal write command NW and a pattern write command PW. Accordingly, the command decoder 121 may control the operations of the data pattern provider 180 and the selector 190 based on the normal write command NW and the pattern write command PW.

The data pattern provider 180 may output a preset data pattern in response to the pattern write command PW. In one embodiment, the data pattern providing unit 180 may selectively generate one of a plurality of preset data patterns in response to the pattern write command PW. For example, when the preset data pattern is data in which the same bit value, for example, '0' or '1' is consecutive, the data pattern providing unit 180 continuously repeats the same bit value according to the pattern write command PW. data patterns can be created. In embodiments, the data pattern provider 180 includes a pattern buffer 181 for storing a plurality of preset data patterns, and in response to a pattern write command PW, the plurality of data patterns stored in the pattern buffer 181. One of the data patterns of can be output.

The input buffer 171 is one component of the input/output buffer 170 of FIG. 2 and can receive data DATA from the outside through the data pad DQ. The input buffer 171 may temporarily store the data DATA and provide the data to the write circuit 151 .

The selector 190 selectively writes one of the data pattern DP output from the data pattern providing unit 180 and the input data IDATA output from the input buffer 171 based on the selection signal SEL. 151) can be output. The selector 190 selectively outputs the data pattern DP or input input data IDATA in response to the selection signal SEL whose level is set according to the pattern write command PW and the normal write command NW. can For example, when the normal write command NW is received, the select signal SEL is at a first level, eg, logic high, and when the pattern write command PW is received, the select signal SEL is at a second level, For example, it may be a logic high. The selector 190 may output input data IDATA in response to the selection signal SEL of the first level, and output the data pattern DP in response to the selection signal SEL of the second level. .

The write circuit 151 may write data output from the selector 190 into a memory area of the memory cell array 110 corresponding to the address signal ADDR.

When a normal write operation is performed, the memory device 100a may receive a normal write command NW, an address signal ADDR, and data DATA from the outside, for example, the memory controller 200 of FIG. 1 . At this time, the data pattern provider 180 does not output the data pattern. The selector 190 provides externally received data DATA output from the input buffer 171 to the writing circuit 151, and the writing circuit 151 stores the memory area corresponding to the address signal ADDR from the outside. Received data DATA can be written.

When pattern writing is performed, the memory device 100a may receive a pattern writing command PW and an address signal ADDR from the outside. The data pattern provider 180 may output a data pattern in response to the pattern write command PW. At this time, data DATA is not received from the outside. The selector 190 may provide the data pattern DP output from the pattern writing providing unit 180 to the writing circuit 151 . The write circuit 151 may write the data pattern DP in the memory area corresponding to the address signal ADDR.

FIG. 4 is a diagram illustrating an example of the data pattern providing unit 180 of FIG. 3 .

Referring to FIG. 4 , the data pattern provider 180 may include a pattern buffer 181 . The pattern buffer 181 may store one or more preset data patterns. In example embodiments, the data pattern may include data 181a in which successive bits are set to '0' or '1'. For example, the data pattern may be data in which all bits are set to '0' or '1'.

In some embodiments, the data pattern may include data 181b previously written to the memory cell array ( 110 in FIG. 3 ). The previously written data 181b refers to data received from the memory controller ( 200 in FIG. 1 ) together with the normal write command NW and written in the memory cell array ( 110 in FIG. 1 ). In an embodiment, the data pattern may include a plurality of previously written data (PWD1, PWD2, ...PWDk).

In example embodiments, the data pattern may be buffer data 181c requested to be written into the pattern buffer 181 from the memory controller (200 in FIG. 1 ). In an embodiment, the data pattern may include a plurality of buffer data (UDD1, UDD2, ..., UDDz) requested to be stored in the pattern buffer 181 by the memory controller 200. For example, the buffer data may include a data pattern set by a user or a data pattern frequently written to the memory device 100 .

In some embodiments, the pattern buffer 181 may store at least one data pattern among the various types of data patterns described above. However, this is exemplary, and the pattern buffer 181 may store other types of data patterns in addition to the aforementioned data patterns.

The data pattern provider 180 may select and output one of the data patterns stored in the pattern buffer 181 in response to the internal pattern write control signal IPW generated by decoding the pattern write command PW. In another embodiment, the data pattern providing unit 180 may generate a new data pattern by extending the selected data pattern. As an example, when the capacity of the memory area requested to write is 64 bytes and the selected data pattern is 32 bytes, the data pattern providing unit 180 generates a data pattern in which the selected data pattern is repeated twice. and output the generated data pattern.

5A and 5B are diagrams illustrating a method for setting a write command.

Referring to FIGS. 5A and 5B , the type of write command may be set by a combination of a general write command (WCMD) indicating a write instruction and a write mode command (MCMD) indicating a write mode. In the normal write command NW and the pattern write command PW, the setting of the general write command WCMD may be the same, but the write mode command MCMD may be different. Therefore, the normal write command NW and the pattern write command PW can be distinguished according to the setting value of the write mode command MCMD.

The general write command WCMD includes a chip select signal (/CS), a row address strobe signal (/RAS), a column address strobe signal (/CAS) received through command pins (or command pads) of the memory device 100, It can be set by the write enable signal (/WE). For example, in the general write command WCMD, the chip select signal /CS is at a low level, the row address strobe signal (/RAS) is at a high level, the column address strobe signal (/CAS) and the write enable signal ( /WE) is low level, it can be set. The general write command WCMD may be received in synchronization with the rising edge R edge of the clock signal CLK. However, it is not limited thereto, and the write command WCMD (or other signals) may be received in synchronization with at least one of the rising edge and the falling edge of the clock signal CLK. However, for convenience of explanation, it will be described on the assumption that the signals are received in synchronization with the rising edge of the clock signal CLK.

Meanwhile, the write mode command MCMD may be set by a signal received through the address pins CA Pins of the memory device 100 . Referring to FIG. 5A , the memory device 100 includes 12 address pins CA[11:0], of which address signals A0 to A8 are provided through 9 address pins CA[8:0]. ), for example, a column address signal may be received, and a write mode command MCMD may be received through the remaining three address pins CA[11:9]. According to setting values of the mode signals M0, M1, and M2 received through the address pins CA[11:9], a normal write command or a pattern write command may be set.

Referring to FIG. 5B , the memory device 100 includes six address pins CA[5:0], and is synchronized with two rising edges of the clock signal CLK through the six address pins, thereby generating the address signal. and a write mode command (MCMD) may be received. In synchronization with the first rising edge REdge1 of the clock signal CLK, the first to sixth address signals A0 to A5 are received through six address pins CA[5:0], and the clock signal ( In synchronization with the second rising edge REdge2 of CLK, the sixth to ninth address signals A6 to A8 are received through three address pins CA[2:0], and the remaining three address pins ( Mode signals M0, M1, and M2 may be received through CA[5:3]).

6 is a table showing an example of setting a write command according to an embodiment of the present disclosure.

As described above with reference to FIGS. 5A and 5B , the write command may be set by a combination of a general write command and a write mode command (MCMD). The write mode command MCMD may be transmitted through address pins (or address pads) of the memory device not used for transmission of address signals, for example, some address pins CAx, CAy, and CAz.

Referring to FIG. 6, when the mode signal '0 0 0' is received through the address pins CAx, CAy, and CAz, the normal write command NW is set, and in other cases, the pattern write command is set. It can be. In response to the normal write command NW, the memory device ( 100 in FIG. 1 ) may write data received from the memory controller 200 into the memory cell array 110 . At this time, since the memory device 100 receives data, the data pad DQ may be used. The data pad DQ includes a plurality of pads.

In one embodiment, in response to the normal write command NW, the memory device (100 in FIG. 1) transfers data received from the memory controller 200 to the pattern buffer 181 as well as the memory cell array 110. can be saved

In response to the pattern write command PW, the memory device ( 100 in FIG. 1 ) may internally write a preset data pattern into the memory cell array 110 . At this time, since the memory device 100 does not receive data, the data pad DQ is not used.

Meanwhile, one of a plurality of pattern write commands PW1 , PW2 , PW3 , and PW4 may be set according to a set value of a signal received through the address pins CAx , CAy , and CAz. For example, when signals received through the address pins CAx, CAy, and CAz are '0 0 1' or '0 1 0', the first pattern write command PW1 or the second pattern write command PW2 is set, and in response to the first pattern write command PW1 or the second pattern write command PW2, the memory device 100 writes a data pattern in which all bits are set to '0' or '1' in the memory cell array ( 110) can be entered. As another example, when the signal received through the address pins CAx, CAy, CAz is '0 1 1', the third pattern write command PW3 is set, and the signal is set to '1 0 0'. , the fourth pattern write command PW4 may be set. The memory device 100 may write previously written data into the memory cell array 110 as a data pattern in response to the third pattern write command PW3 . Also, the memory device 100 may write buffer data into the memory cell array 110 in response to the fourth pattern write command PW4 . As described above with reference to FIG. 4, the buffer data is a data pattern stored in the pattern buffer 181 requested to be written to the pattern buffer 181 from the memory controller (200 in FIG. 1), and the data pattern set by the user ( A user defined data pattern) or a data pattern frequently written to the memory device 100 may be included.

Meanwhile, in order to store the buffer data in the pattern buffer 181 of the memory device 100, the memory controller 200 instructs writing buffer data into the pattern buffer 181, a pattern storage command (PS) and data, In other words, the buffer data may be transmitted to the memory device 100, and the memory device 100 may store the buffer data received through the data pad DQ in the pattern buffer 181 when the pattern storage command PS is received. there is. The pattern storage command PS may be provided as one of write commands. As shown, when a mode signal of '1 0 1' is received through the address pins CAx, CAy, and CAz, the pattern storage command PS may be set.

In the above, the write command has been exemplarily described with reference to FIG. 6 . However, it is not limited thereto, and signals indicating the normal write command and the pattern write command may be set in various ways.

7 is a timing diagram of an input signal of a memory device during a write operation according to an embodiment of the present disclosure.

Referring to FIG. 7 , during a write operation, a command indicating write (for example, a general write command WCMD of FIGS. 5A and 5B ), an address signal ADDR, and a write command PW are synchronized with the rising edge of the clock signal CLK. , NW) may be received. The write commands PW and NW may be received through some of the address pins CA[n−1:0]. When the pattern write command PW is received, data is not received. When the normal write command NW is received, data Din may be received from the outside, for example, the memory controller ( 200 in FIG. 1 ). The data Din may be received a predetermined time after the normal write command NW is received. As shown, the time for receiving the data Din is not required in the first period T1 according to the pattern write command PW. Thus, a write command can be executed in a relatively short time. Also, since data is not received, power consumption of the memory device according to data reception may be reduced.

Meanwhile, in FIG. 7 , a case in which an address signal ADDR representing one memory area is transmitted during a write operation is shown. However, the present invention is not limited thereto, and during a write operation, address signals ADDR indicating a plurality of memory areas may be transmitted. This will be described with reference to FIG. 8 .

8 is a timing diagram illustrating an example of address setting during a write operation according to an embodiment of the present disclosure.

Referring to FIG. 8 , during a write operation, the memory device 100 may receive a start address signal Start ADDR and an end address signal End ADDR. The start address signal Start ADDR indicates a starting point at which data is stored in the memory cell array ( 110 in FIG. 1 ), and the end address signal End ADDR indicates a point at which data storage is completed. Address signals may be transmitted in synchronization with two rising edges of the clock signal CLK. For example, the start address signal Start ADDR may be received in synchronization with the first and second rising edges of the clock signal CLK. In one embodiment, as described with reference to FIG. 5B , the pattern write command PW may be received together with an address signal. The pattern write command PW may be received together with the start address signal Start ADDR in synchronization with the second rising edge of the clock signal CLK. Thereafter, the end address signal End ADDR may be received in synchronization with the next rising edge of the clock signal CLK, for example, the third rising edge and the fourth rising edge. The memory device 100 may write data patterns in a plurality of memory areas corresponding to a start address (Start ADDR) and an end address (End ADDR).

Meanwhile, as another embodiment, length information may be received in synchronization with the third rising edge after the start address signal Start ADDR and the pattern writing command PW are received. The length information may include information corresponding to the length of a memory area in which a data pattern is to be written. The memory device 100 may write an internally generated data pattern from a memory area corresponding to the start address signal Start ADDR to a memory area set according to the length information.

9 is a flowchart illustrating a writing method of a memory device according to an exemplary embodiment of the present disclosure.

Referring to FIG. 9 , the memory device 100 sets a data pattern (S110). The data pattern may be data predefined between the memory controller 200 and the memory device 100 . For example, the data pattern may be data in which consecutive bits are '0' or '1'. Alternatively, the data pattern may be data previously provided to the memory device 100 as write data. As another example, the data pattern may be data set by a user or data frequently written into the memory device 100 . In addition, the data pattern may be data set during the operation of the memory device 100 and the memory system 1000 . The memory device 100 may store data patterns in an internal buffer, for example, a pattern buffer ( 181 in FIG. 3 ).

When a pattern write command and an address signal are received from the memory controller 200 (S120), the memory device 100 may generate the data pattern, that is, a preset data pattern in response to the pattern write command (S130). . The memory device 100 may select and output a data pattern corresponding to the pattern write command from the pattern buffer 181 or generate a new data pattern by extending the selected data pattern.

The memory device 100 writes the data pattern into a memory area corresponding to the received address signal (S140).

In this way, when a pattern writing command is received from the memory controller, the memory device 100 internally generates a preset data pattern and writes the data pattern into the memory cell array, thereby writing separate data from the memory controller 200. It is possible to perform a write operation without receiving.

10 is a block diagram illustrating an implementation example of a memory controller according to an exemplary embodiment of the present disclosure.

Referring to FIG. 10 , the memory controller 200 may include a data comparator 210 and a pattern buffer 220 . In one embodiment, the pattern buffer 220 may be implemented as the same functional block as the data comparator 210 . In another embodiment, a part of a buffer included in the memory controller 200 may be used as the pattern buffer 220 .

A preset data pattern may be stored in the pattern buffer 220 . In one embodiment, a plurality of data patterns (Pattern 1 to Pattern m) may be stored in the pattern buffer 220 . The plurality of data patterns (Pattern 1 to Pattern m) is a plurality of data patterns (181a, 181b, 181c in FIG. 4) stored in the pattern buffer 181 of the data pattern providing unit 180 of the memory device (100a in FIG. 3). ) may be substantially the same as In embodiments, the plurality of data patterns (Pattern 1 to Pattern m) may include data in which all bits are set to '0' or '1'. In example embodiments, the plurality of data patterns (Pattern 1 to Pattern m) may include write data previously sent to the memory device 100 . In embodiments, the plurality of data patterns (Pattern 1 to Pattern m) are user-set data and may include data provided from a host.

When address information ADD and data DATA are received along with a write request from the host, the data comparator 210 compares the data DATA with a data pattern stored in the pattern buffer 220. . In one embodiment, the data comparator 210 may compare data DATA with a plurality of data patterns Pattern 1 to Pattern m. When the data DATA matches a data pattern, for example, one of a plurality of data patterns Pattern 1 to Pattern m, the memory controller 200 may generate a pattern writing command PW corresponding to the matched data pattern. . An embodiment related to this has been described with reference to FIG. 6, so a detailed description thereof will be omitted.

The memory controller 200 may transmit a command PW and an address signal ADDR to the memory device 100 . At this time, the address signal ADDR represents a memory area of the memory device corresponding to the address information ADD received from the host Host.

Meanwhile, if the data DATA does not match the data pattern, the memory controller 200 may generate a normal write command NW. The memory controller 200 may transmit a normal write command NW, an address signal ADDR, and data DATA to the memory device 100 .

11 is a flowchart illustrating a method of operating a memory controller according to an exemplary embodiment of the present disclosure.

Referring to FIG. 11 , the memory controller 200 sets a data pattern (S210). The data pattern may be data predefined between the memory device 100 and the memory controller 200 . For example, the data pattern may be data in which consecutive bits are '0' or '1'. Alternatively, the data pattern may be data previously sent to the memory device 100 as write data. As another example, the data pattern is data set by a user and may be data received from a host. As another example, the data pattern is data that is frequently written into the memory device 100, and the memory controller 200 analyzes the data requested to be written into the memory device 100 and exceeds a preset threshold value. Data requested to be written may be determined as frequently used data, and the data may be set as a data pattern. In addition, the data pattern may be various types of data set during the operation of the memory controller 200 and the memory system 1000 . The memory controller 200 may store information about data patterns or store data patterns in the pattern buffer 220 provided therein. The memory controller 200 provides information about the data pattern or the data pattern to the memory device 100, and the memory device 100, in step S110 of FIG. A data pattern can be set by storing the information or data pattern in the internal pattern buffer (181 in FIG. 3).

When data and address information are received along with a write request from the host (S220), the memory controller 200 compares whether the received data matches a preset data pattern (S230). If the received data matches the data pattern, the memory controller 200 transmits a pattern write command and an address signal to the memory device 100 (S240). If the received data does not match the data pattern, the memory controller 200 transmits a normal write command, data and address signals to the memory device 100 (S250).

12 is a flowchart illustrating a method of operating an electronic device to which a memory device according to an exemplary embodiment of the present disclosure is applied. The electronic device includes a host 300, a memory controller 200, and a memory device 100, and FIG. 12 shows a write operation among normal operations of the electronic device.

Referring to FIG. 12 , the memory device 100 and the memory controller 200 set data patterns (S311 and S312). As described above with reference to FIGS. 9 to 11 , the data pattern is data mutually agreed upon between the memory device 100 and the memory controller 200, and is commonly set in the memory controller 200 and the memory device 100. It can be.

When a write request is received from the host 300 (S320), the memory controller 200 compares the received data with a preset data pattern and determines whether they match (S330). If the data do not match, the memory controller 200 transmits the normal write command NW, the address signal ADDR, and the data DATA to the memory device 100 (S341). The memory device 100 writes the data DATA into a memory area corresponding to the address signal ADDR (S342).

Meanwhile, when the received data matches a preset data pattern, the memory controller 200 may transmit a pattern write command PW and an address signal ADDR to the memory device 100 (S351). The memory device 100 may generate a data pattern in response to the pattern write command PW (S352). In this case, the data pattern may be generated based on one of data patterns preset in step S312. In one embodiment, the generated data pattern may be one of a plurality of preset data patterns in step S312. The memory device 100 may write a data pattern in a memory area corresponding to the address signal ADDR (S353).

13 is a flowchart illustrating a writing method of a memory device according to an exemplary embodiment of the present disclosure. The writing method of FIG. 13 is an implementation example of the writing method of FIG. 9 and shows a writing method of a memory device when data previously written in the memory device 100 is set as a data pattern.

Referring to FIG. 13 , the memory device 100 receives a write command, a first address (or address signal), and data from the memory controller 200 (S410). In this case, the write command may be a normal write command. The memory device 100 may store the data in an internal buffer, for example, a pattern buffer ( 181 in FIG. 3 ) (S420), and write the data in a memory area corresponding to the first address (S430). In one embodiment, steps S410 and S420 may be performed a plurality of times to store a plurality of data in an internal buffer. In one embodiment, since the capacity of the internal buffer is limited, data received in the memory device 100 relatively late, that is, data received in a close period based on the present may be updated in the internal buffer.

Then, when the pattern write command and the second address are received (S440), the memory device 100 may generate a data pattern based on the data stored in the internal buffer (S450). The memory device 100 may select one of a plurality of data stored in an internal buffer and output the selected data as a data pattern in response to a pattern write command.

The memory device 100 may write the data pattern into a memory area corresponding to the second address (S460). The second address may indicate the same memory area as the first address. As another example, the second address may indicate a different memory area than the first address. For example, the second address may indicate a memory area adjacent to the first address.

14 is a flowchart illustrating an operating method of an electronic device to which a memory device according to an exemplary embodiment of the present disclosure is applied. The electronic device may include a memory device in which a write operation is performed according to the write method of FIG. 13 . The electronic device includes a host 300, a memory controller 200, and a memory device 100, and FIG. 14 shows a write operation among normal operations of the electronic device. In this embodiment, the memory controller 200 and the memory device 100 may each include a pattern buffer for storing data patterns therein, and the pattern buffer of the memory controller 200 is used as a first buffer, and the memory device ( 100) will be referred to as a second buffer.

Referring to FIG. 14 , first, the host 300 may make a data write request to the memory controller 200 (S510). The host 300 may transmit a write request signal, data to be written, and address signals to the memory controller 200 . When a write request is received from the host 300 (S510), the memory controller 200 may store the data received along with the data write request in the first buffer (S520). The memory controller 200 may transmit the normal write command NW, the address signal ADDR, and the data DATA to the memory device 100 (S530).

The memory device 100 stores data received from the memory controller 200 in a second buffer (S540) and writes the data into a memory area corresponding to the address signal ADDR (S550).

According to the above steps S510 to S550, data written in the memory device 100 may be set as a data pattern.

Then, when a data write request is received again from the host 300 (S560), the memory controller 200 compares the received data with data stored in the first buffer, that is, with a preset data pattern, and determines whether or not they match (S560). S570). If the data does not match, steps S520 to S550 may proceed. Data requested to be written from the host 300 may be written into the memory device 100 . At this time, the memory controller 200 may update the data pattern of the first buffer by storing the data received from the host 300 in the first buffer. In addition, the memory device 100 writes data received from the memory controller 200 into a new memory area corresponding to the address signal ADDR and stores the data in the second buffer, thereby storing data in the second buffer. Patterns can be updated. Updating the first buffer and the second buffer will be described later in detail with reference to FIG. 15 .

If the data match, the memory controller 200 provides the pattern write command PW and the address signal ADDR to the memory device 100 (S581). The memory device 100 may output the data pattern stored in the second buffer in response to the pattern write command PW (S582). In one embodiment, when a plurality of data patterns are stored in the second buffer, the memory device 100 may output one data pattern selected according to the pattern write command PW. The memory device 100 writes the data pattern into a memory area corresponding to the address signal ADDR (S583).

Data requested to be written into the memory device 100 may have temporal locality. For example, when one frame of image data is stored in the memory device 100 , the probability that the same data is continuously stored in the memory device 100 is high. Accordingly, the host 300 may successively request the memory controller 200 to write the same data. Accordingly, the memory controller 200 and the memory device 100 may store data transmitted/received from each other as data patterns in pattern buffers provided therein to write data. When writing the data is again requested from the host 300, the memory controller 200 provides a pattern writing command (PW) to the memory device 100 instead of transmitting the data to the memory device 100 again. , The memory device 100 may output a corresponding data pattern from the pattern buffer according to the pattern write command PW and write the corresponding data pattern into the memory cell array.

15A and 15B are diagrams illustrating an embodiment in which a memory controller and pattern buffers respectively provided in the memory device are updated in an electronic device according to an embodiment of the present disclosure. 15A and 15B illustrate embodiments of a method for updating a first pattern buffer and a second pattern buffer, which is performed in steps S520 and S540 in the flowchart of FIG. 14 .

Referring to FIG. 15A , the memory controller 200 may sequentially receive a plurality of data from the host 300 according to time. In this case, the received data may be the same data as one of the previously received data or new data different from the previously received data. For example, after the first data Data1 is received, the first data Data1 may be received again, or the second data Data2 different from the first data Data1 may be received. Alternatively, after the first data Data1 is received and new data are received thereafter, the first data Data1 may be received again.

The memory controller 200 may store the received data in a first pattern buffer PBUF1 provided therein. Then, the received data is provided to the memory device 100 . The memory device 100 may write the received data into the memory cell array and store it in the second pattern buffer PBUF2 provided therein.

When the new data received from the host 300 is the same as the previously received data, as described above, the memory controller 200 instead of providing the data to the memory device 100, sends a pattern write command to the memory device ( 200) can be provided. The pattern write command may include a signal for informing writing of a pattern and a signal for selecting one pattern data from among pattern data stored in the second pattern buffer PBUF2 .

For example, when first data Data1 is received along with a write request from the host 300, the memory controller 200 stores the first data Data1 in an internal first pattern buffer PBUF1, and 1 data Data1 may be provided to the memory device 100 . Then, when the first data Data1 is received from the host 300 again, a pattern write command is provided to the memory device 100 . Then, when second data Data2 different from the first data Data1 is received from the host 300, the second data Data2 is stored in the first pattern buffer PBUF1, and the second data Data2 is stored. may be provided to the memory device 100 . In this way, the memory controller 200 may store N pieces of new data in the first pattern buffer PBUF1. At this time, when the first pattern buffer PBUF1 includes N storage areas SR1 to SRN, there are no more areas to be stored in the first pattern buffer PBUF1.

When new data, that is, N+1th data DataN+1 different from the data stored in the first pattern buffer PBUF1 is received from the host 300, the memory controller 200 determines the first pattern buffer PBUF1. Among the data stored in ), data stored the longest, for example, the first data Data1 may be deleted, and the N+1th data DataN+1 may be stored in the first pattern buffer PBUF1. In this way, the memory controller 200 may update the data pattern of the first pattern buffer PBUF1 by deleting old data and storing new data in the first pattern buffer PBUF1.

As another embodiment, when new data, that is, N+1th data DataN+1 different from the data stored in the first pattern buffer PBUF1 is received from the host 300, the memory controller 200 Among the data stored in the 1st pattern buffer PBUF1, data that matches the data received the most recently may be deleted, and the N+1th data DataN+1 may be stored in the first pattern buffer PBUF1.

Referring to FIG. 15B , the memory controller 200 may store data in the first pattern buffer PBUF1 and store a matching order MN of the stored data. At this time, the matching order MN indicates the order most recently received from the host 300 among the data stored in the first pattern buffer PBUF1, and the lower the matching order MN, the more recently received from the host 300. can indicate that it has been For example, the matching order MN of data most recently written to the first pattern buffer PBUF1 or most recently matched data may be low. When the number of storage areas of the first pattern buffer PBUF1 is N, the matching order MN of the data most recently written to or most recently matched in the first pattern buffer PBUF1 is set to 1, and the oldest A matching order (MN) of matched data may be set to N. The matching order MN may be updated whenever data is received from the host 300 .

All data is stored in the storage space of the first pattern buffer PBUF1, new data, for example, N+1th data (DataN+1) is received, and the memory controller 200 uses the oldest matched data, that is, The data pattern of the first pattern buffer PUF1 is updated by deleting data whose matching sequence MN is N, that is, the N-1th data DataN, and storing the N+1th data DataN+1. can do.

Meanwhile, when data is received from the memory controller 200, the memory device 100 may store the received data in a corresponding memory cell area and may also store the received data in an internal second pattern buffer PBUF2. The memory device 100 may store received data in the second pattern buffer PBUF2 in substantially the same manner as the memory controller 200 . In one embodiment, the storage capacities of the first pattern buffer PBUF1 and the second pattern buffer PBUF2 may be the same, and the data storage order may be set to be the same. Data stored in the first pattern buffer PBUF1 and the second pattern buffer PBUF2 and the order of storing the data may be the same. Accordingly, the same data patterns are transmitted between the first pattern buffer PBUF1 of the memory controller 200 and the memory device 100 between the memory controller 200 and the memory device 100 without a separate command or an address signal designating a location in the pattern buffer. The second pattern buffer PBUF2 of the device 200 may be stored in substantially the same location or in the same order.

16 is a table showing an example of setting a write command according to an embodiment of the present disclosure. FIG. 16 is an example of setting a write command transmitted between a memory device and a memory controller to which the write method of FIG. 13 is applied, instructing to write previously written data into the memory cell array 110 as a data pattern. This is an extension example of the third pattern write command (PW3, see FIG. 6).

Referring to FIG. 16 , the third pattern writing command PW3 may be set according to signals received through some of the address pins CAx, CAy, CAz, CAj, CAk, and CAl among the addresses ??. A value received through the upper three address pins CAx, CAy, and CAz among the illustrated address pins CAx, CAy, CAz, CAj, CAk, and CAl, for example, '0 1 1' indicates one of the previous write data. Indicates a write command to select and write to the memory cell array, and among the address pins CAx, CAy, CAz, CAj, CAk, and CAl, the lower three address pins CAj, CAk, and CAl are assigned to the number of previous write data. Indicates whether to select previously written data. Referring to FIGS. 15A and 15B , the memory device 100 may store a plurality of previous write data in the second pattern buffer PBUF2 . The memory device 100 stores a plurality of patterns stored in the second pattern buffer PBUF2 based on a third pattern write command PW3 received through the illustrated address pins CAx, CAy, CAz, CAj, CAk, and CAl. One of the previous write data of can be selected. For example, the second pattern buffer PBUF2 may store 8 previous write data, based on values received through the three address pins CAj, CAk, and CAl of the memory device 100, 8 previous write data. One of the data may be selected and stored in a memory area corresponding to the address signal ADDR.

Meanwhile, in FIG. 16 , it has been described assuming that the second pattern buffer PBUF2 stores 8 pieces of previous write data, but this is only an embodiment, and the number of previous write data stored in the second pattern buffer PBUF2 is variable. It can be.

17 is a flowchart illustrating a writing method of a memory device according to an exemplary embodiment of the present disclosure. The writing method of FIG. 17 is an implementation example of the writing method of FIG. 9 and shows a writing method of a memory device when user setting data is set as a data pattern.

Referring to FIG. 17 , the memory device 100 may receive a pattern storage command and data from the memory controller 200 (S610). The pattern storage command may be a command instructing to store received data in an internal buffer rather than in the memory cell array 110 of the memory device 100 . The received data may be user setting data. For example, the user setting data may be data mainly stored in the memory device 100 in relation to an operation of an electronic device in which the memory device 100 is mounted. A host of the electronic device, for example, a host processor, analyzes data mainly stored in the memory device 100 and provides it to the memory device 100 as user setting data.

The memory device 100 may store the data, that is, user-set data, in an internal buffer in response to the pattern storage command (S620). In one embodiment, steps S610 and S620 may be performed a plurality of times to store a plurality of user setting data in an internal buffer.

Then, when a pattern write command and an address are received (S630), the memory device 100 may generate a data pattern based on user setting data stored in an internal buffer in response to the pattern write command (S640). In one embodiment, the memory device 100 may select one of a plurality of user-set data and output the selected data as a data pattern according to a pattern writing command.

The memory device 100 may write the data pattern, that is, user setting data, in a memory area corresponding to the address (S650).

18 is a flowchart illustrating an operating method of an electronic device to which a memory device according to an exemplary embodiment of the present disclosure is applied. The electronic device includes a host 300, a memory controller 200, and a memory device 100, and FIG. 18 shows a write operation among normal operations of the electronic device. In this embodiment, the memory controller 200 and the memory device 100 may each include a pattern buffer for storing data patterns therein, and the pattern buffer of the memory controller 200 is used as a first buffer, and the memory device ( 100) will be referred to as a second buffer.

Referring to FIG. 18 , the memory controller 200 may receive a data pattern storage request from the host 300 (S710). In one embodiment, when the host 300 transmits invalid address information along with a data write request and data, the memory controller 200 may interpret the write request as a data pattern storage request. The memory controller 200 may store the data received from the host 300 as a data pattern in the first buffer (S720). The stored data pattern may be referred to as a user-set data pattern. The memory controller 200 may transmit a pattern storage command (PS) and a data pattern (DPT), that is, a user-set data pattern to the memory device 100 (S730). The memory device 100 may store the user data pattern DPT in the second buffer in response to the pattern storage command PS (S740). Accordingly, a user-set data pattern may be set in the memory controller 200 and the memory device 100 .

Then, when a data writing request is received from the host 300 (S750), the memory controller 200 compares the received data with the data pattern stored in the first buffer and determines whether or not they match (S760). If the data match, the memory controller 200 may transmit the pattern write command PW and the address signal ADDR to the memory device 100 (S771). The memory device 100 may output the data pattern stored in the second buffer in response to the pattern write command PW (S772). In other words, the memory device 100 may output a user-set data pattern.

If the data do not match, the memory controller 200 may transmit the normal write command NW, the address signal ADDR, and the data DATA to the memory device 100 (S781).

The memory device 100 may write the data pattern or the received data in a memory area corresponding to the address signal ADDR (S782).

19 is a block diagram schematically illustrating a memory device according to an exemplary embodiment of the present disclosure. The memory device 100b of FIG. 19 is a modified example of the memory device 100 of FIG. 2 , and the above description with reference to FIG. 2 may also be applied to the memory device 100b of FIG. 19 .

Referring to FIG. 19 , the memory device 100b may include a plurality of banks. A bank can be defined as a set of memory cells that can be accessed simultaneously. Banks may be generally distinguished by address signals ADDR. Although not particularly shown, it can be distinguished by the received bank address signal. Different banks can function independently. For example, read and write operations may be independently performed on different banks.

19, one row decoder 140, one read/write circuit 150, and one column decoder 160 may correspond to one memory cell array 110. In this case, one memory cell array 110 may constitute one bank. However, it is not limited thereto, and two or more memory cell arrays may constitute one memory bank, and one row decoder 140 or one column decoder 160 may correspond to two or more memory cell arrays. .

Meanwhile, the data pattern provider 180 and the input/output buffer 170 may be shared by read/write circuits 150 of different banks. The data pattern provider 180 provides data patterns to the read/write circuits 150, and the input/output buffer 170 transmits data DATA output from the read/write circuits 150 to the outside, or Alternatively, when data DATA is received from the outside, the received data may be provided to the read/write circuit 150 .

In the memory device 100b according to an embodiment of the present disclosure, when a pattern write command is received from the outside, the memory device 100b converts data provided from the data pattern provider 180 into an address signal without receiving data from the outside. It is possible to write to the memory area corresponding to (ADDR). Read/write operations can be independently performed on different banks, and read/write operations can be performed simultaneously on different banks. At this time, since different banks share the input/output buffer 170 and the data pad DQ[m-1:0], even if read/write operations are performed simultaneously in different banks, one bank If using the input/output buffer 170 and the data pad DQ, if another bank wants to use the input/output buffer 170 and the data pad DQ, use the input/output buffer 170 and the data pad DQ You have to wait until the bank you are using is finished. Accordingly, read/write operations may be delayed. However, the memory device 100b according to an embodiment of the present disclosure does not use the input/output buffer 170 and the data pad DQ when a write operation is performed according to a pattern write command. Therefore, when a pattern write operation is performed on one bank, the input/output buffer 170 and the data pad DQ[m-1:0] can be used while another bank simultaneously performs a normal write operation or a read operation. there is. Accordingly, the operating speed of the memory device 100b may be improved.

20 is a block diagram illustrating a memory system according to an exemplary embodiment of the present disclosure.

Referring to FIG. 20 , a memory system 1000a may include a memory controller 200a and a memory device 100 . The memory controller 200 includes a data comparator 210, a pattern buffer 220, and a data pattern analyzer 230, and the memory device 100 includes a memory cell array 110, a read/write circuit 150 and a data pattern providing unit 180 . The memory system 100a of FIG. 20 is a modified example of the memory system 1000 of FIG. 1 , and contents described with reference to FIG. 1 may also be applied to the present embodiment. Therefore, redundant descriptions will be omitted.

The data pattern analyzer 230 of the memory controller 200a analyzes data received from the outside, for example, a host, to obtain frequently used data, that is, data frequently written to the memory device 100. can judge For example, the data pattern analyzer 230 may determine data for which the number of write requests from the host is equal to or greater than a preset threshold as frequently used data. The memory controller 200a may store frequently used data as a data pattern in the pattern buffer 220 and transmit it to the memory device 100 . The memory device 100 may store frequently used data received from the memory controller 200a in a pattern buffer (not shown) provided in the data pattern providing unit 180 . Accordingly, frequently used data may be set as a data pattern in the memory controller 200a and the memory device 100 . In one embodiment, the data pattern provider 180 may be a pattern buffer.

The data comparator 210 compares data requested to be written from the host with data patterns stored in the pattern buffer 220 and determines whether the requested data matches one of the data patterns. When the write-requested data matches one of the data patterns, the memory controller 200a does not transmit the data to the memory device 100 and sends the pattern write command and address signal ADDR to the memory device 100. can transmit The memory device 100 may select one of data patterns stored in the pattern buffer based on the pattern write command and write the selected data pattern into the memory cell array 110 .

In the memory system 1000a according to the present embodiment, the memory controller 200a determines frequently used data that is frequently written in the memory device 100 by analyzing data requested to be written, and the frequently used data By stipulating and using as a data pattern between the memory controller 200a and the memory device 100, the memory cell array ( 110), the frequently used data can be written.

21 is a block diagram illustrating an implementation example of a memory controller according to an exemplary embodiment of the present disclosure. FIG. 21 illustrates an implementation example of the memory controller 200a of the memory system 1000a of FIG. 20 .

Referring to FIG. 21 , the data pattern analyzer 230 analyzes data DATA received along with a write request from the host to determine frequently used data. In an embodiment, the data pattern analyzer 230 may determine data for which the number of write requests from the host is equal to or greater than a preset threshold value as frequently used data. In another embodiment, the data pattern analyzer 230 may determine data for which the number of write requests from the host is greater than or equal to the threshold value within a preset time period as frequently used data.

The data pattern analyzer 230 provides frequently used data to the pattern buffer 220, and the pattern buffer 220 may store frequently used data as a data pattern. A plurality of data patterns (Pattern 1 to Pattern m) may be stored in the pattern buffer 220 . The memory controller 200a may transmit data set as a data pattern to the memory device ( 100 of FIG. 20 ) together with the address signal ADDR and the second normal write command NW2 . When the second normal write NW2 is transmitted, the memory device 100 may store the data in a memory area corresponding to the address signal ADDR and an internal pattern buffer. Accordingly, the data may be set as a data pattern in the memory controller 200a and the memory device 100 .

If a write request is continuously received from the host, the data comparator 210 may compare the write requested data DATA with a plurality of data patterns (Pattern 1 to Pattern m) stored in the pattern buffer 220. . When the data DATA matches one of the plurality of data patterns Pattern 1 to Pattern m, the memory controller 200a may transmit the pattern write command PW and the address signal ADDR to the memory device 100. . If the data DATA does not match any of the plurality of data patterns Pattern 1 to Pattern m, the memory controller 200a sends the first normal write command NW1, the data DATA, and the address signal ADDR. may be transmitted to the memory device 100 . The memory device 100 may output one of data patterns stored in an internal pattern buffer based on the pattern write command PW, and write the output data into a memory area corresponding to the address signal ADDR. . Also, the memory device 100 may write the received data DATA into a memory area corresponding to the address signal ADDR based on the first normal write command NW1 .

22 is a table illustrating an example of setting a write command according to an embodiment of the present disclosure.

Referring to FIG. 22 , when a mode signal of '0 0 0' is received through the address pins CAx, CAy, and CAz, this indicates a first normal write command NW1. When a mode signal of '0 0 0' is received through the address pins CAx, CAy, and CAz, data may be transmitted from the memory controller 200a to the memory device 100 through the data pad DQ. The memory device 100 may write data received from the memory controller 200 into the memory cell array 110 in response to the first normal write command NW1 .

When a mode signal of '0 0 1' is received through the address pins CAx, CAy, and CAz, this indicates the second normal write command NW2. When a mode signal of '0 0 1' is received through the address pins CAx, CAy, and CAz, data may be transmitted from the memory controller 200a to the memory device 100 through the data pad DQ. The memory device 100 may write data received from the memory controller 200 into the memory cell array 110 and the pattern buffer in response to the first normal write command NW1 . Accordingly, the data pattern may be stored in the pattern buffer of the memory device 100 .

If the signal received through the upper one of the address pins CAx, CAy, and CAz is '0', this is a pattern write command to write buffer data, that is, data written in the pattern buffer to the memory cell array. Indicates the command (PW). When the pattern write command PW is received, there is no data transmission/reception between the memory controller 200a and the memory device 100, so the data pad DQ is not used. As described above with reference to FIGS. 20 and 21 , data written to the pattern buffer may be frequently used data. According to signals received through the lower two pins CAy and CAz among the address pins CAx, CAy, and CAz, one data pattern among data patterns stored in the pattern buffer may be selected and output.

In the above, the write command that can be transmitted to the memory device 100 of the memory system 1000a of FIG. 20 has been exemplarily described with reference to FIG. 22 . However, it is not limited thereto, and signals indicating the normal write command and the pattern write command may be set in various ways.

23 is a block diagram illustrating a memory system according to an exemplary embodiment of the present disclosure.

Referring to FIG. 23 , a memory system 1000c may include a memory controller 200c and a memory device 100c. The memory controller 200c may include a pattern buffer 220 , and the memory device 100c may include a memory cell array 110 , a data pattern provider 180 and a data comparator 185 . Although not shown, the memory controller 200c may further include a data comparison unit and a data pattern analysis unit.

As described above with reference to FIGS. 1 to 22 , the memory controller 200c and the memory device 100c stipulate data patterns in advance, and when data requested to be written from the host matches the data pattern, the memory controller 200c ) may transmit a preset pattern write command instead of transmitting the data to the memory device 100c, and the memory device 100c may write a data pattern into the memory cell array 110 in response to the pattern write command. there is.

Meanwhile, in the memory system 1000c of FIG. 23 , when the data read from the memory cell array 110 matches the data pattern, the memory device 100c instead of transmitting the read data to the memory controller 200c, set in advance. Pattern read signals, eg, matching signal RDM and pattern information BPIF, may be transmitted to the memory controller 200c. The memory controller 200c may transmit a data pattern to the outside, for example, a host, based on the received pattern read signals.

Specifically, when the memory controller 200c transmits the read command CMD and the address signal ADDR to the memory device 100c, the memory device 100c transmits the memory cell array 110 corresponding to the address signal ADDR. ) can read data from the memory area. The data comparison unit 185 compares the read data with the data pattern received from the data pattern providing unit 180, or accesses the data pattern providing unit 180 and compares the stored data pattern with the read data. . When the read data matches the data pattern, the data comparator 185 may generate a matching signal RDM indicating that the read data matches the data pattern.

The memory device 100c may transmit the matching signal RDM to the memory controller 200c. In addition, when the read data matches one of a plurality of data patterns, the memory device 100c converts information on the matched data pattern (eg, the position of the matched data pattern in the pattern buffer) into pattern information ( BPIF) to the memory controller 200c.

The memory controller 200c may provide data received from the memory device 100c to the host as a read signal. However, when the matching signal RDM is received from the memory device 100c, the memory device 100c does not transmit read data to the memory controller 200c. When the matching signal RDM is received, the memory controller 200c may transmit a preset data pattern to the host. In an embodiment, when a plurality of data patterns are stored in the pattern buffer 220, the memory controller 200c selects one of the plurality of data patterns based on pattern information BPIF received from the memory device 100c. and transmit the selected data pattern to the host.

As described above, in the memory system 1000c according to the present embodiment, when data read from the memory cell array 110 matches a preset data pattern, the memory controller 200c receives data from the memory device 100c. Without this, data patterns may be transmitted to the host as read data based on preset pattern read signals. Accordingly, since data transmission/reception does not occur between the memory controller 200c and the memory device 100c, power consumption of the memory system 1000c may be reduced. In addition, since data transfer time is reduced during reading, the operating speed of the memory system 1000c may be improved.

Hereinafter, detailed configurations and operations of the memory device 100c and the memory controller 200c will be described with reference to FIGS. 24 and 25 .

24 is a block diagram schematically illustrating a memory device according to an exemplary embodiment of the present disclosure. The memory device 100c of FIG. 24 may be applied to the memory system 1000c of FIG. 23 . 24 shows main configurations of a memory device in relation to a read operation, and the configurations of the memory device shown in FIG. 2 may be included in the memory device 100c of FIG. 24 .

Referring to FIG. 24 , the memory device 100c may include a memory cell array 110 , a read circuit 152 , an output buffer 172 , a data pattern provider 180 and a data comparator 185 .

The read circuit 152 may read data from a memory area of the memory cell array 110 corresponding to the address signal. The read data may be provided to the output buffer 172 and the data comparator 185 .

The output buffer 172 is a component of the input/output buffer 170 of FIG. 2 , and may transmit data DATA to the outside through the data pad DQ.

The data pattern provider 180 may output a preset data pattern. In one embodiment, the data pattern provider 180 may generate a preset data pattern. In another embodiment, the data pattern providing unit 180 may include a pattern buffer 181 storing a plurality of data patterns.

The data comparison unit 185 may compare the read data received from the read circuit 152 with the data pattern output from the data pattern providing unit 180 . Alternatively, the data comparator 185 may access the pattern buffer 185 to compare read data with a plurality of data patterns. The data comparator 185 may output a matching signal RDM. If the read data matches the data pattern, the data comparator 185 outputs a matching signal RDM of a first level, eg, logic high, and if the read data does not match the data pattern, the data comparator 185 ( 185) may output the matching signal RDM of the second level, for example, logic low. The matching signal RDM may be provided to the output buffer 172 and the memory controller ( 200c of FIG. 23 ).

If the read data does not match the data pattern, the output buffer 172 may output the read data to the memory controller 200c through the data pad DQ. However, when the read data matches the data pattern, the output of the output buffer 172 may be blocked. The output of the output buffer 172 may be blocked in response to the first level matching signal RDM. Accordingly, read data cannot be transmitted through the data pad DQ. When the read data matches one of the plurality of data patterns stored in the pattern buffer 181, the data pattern providing unit 180 provides pattern information (BPIF) indicating the position of the matched data pattern in the pattern buffer 181. can output The pattern information BPIF may be provided to the memory controller 200c.

25 is a schematic block diagram of a memory controller according to an exemplary embodiment of the present disclosure. The memory controller 200c of FIG. 25 may be applied to the memory system 1000c of FIG. 23 .

Referring to FIG. 25 , the memory controller 200c may include a pattern buffer 220, a data input buffer 9260, and a selector 290.

The memory controller 200c may receive data DATA and a matching signal RDM from the memory device 100c. The memory controller 200c may also receive pattern information BPIF from the memory device 100c.

The data input buffer 260 may receive data DATA from the memory device 100c. The received data DATA may pass through the selector 290 and be transmitted to the host as read data RDATA.

The pattern buffer 220 may store a plurality of pattern data (Pattern1 to Pattern m). The pattern buffer 220 may select and output one of a plurality of pattern data (Pattern1 to Pattern m) based on the pattern information (BPIF). The output pattern data may be transmitted to the host as read data RADAT through the selector 290 .

The selector 290 may output one of the data DATA provided from the data input buffer 260 and the data pattern provided from the pattern buffer 220 as read data RDATA based on the matching signal RDM. there is. The selector 290 outputs a data pattern in response to the matching signal RDM of the first level, and outputs data DATA provided from the input buffer 270 in response to the matching signal RDM of the second level. can do.

26 is a flowchart illustrating an operating method of an electronic device to which a memory device according to an embodiment of the present disclosure is applied. 26 illustrates a read operation among normal operations of an electronic device. The electronic device includes a host 300, a memory controller 200, and a memory device 100. The memory controller 200 includes the memory controller 200c described with reference to FIGS. 23 and 25, and the memory device 100 ) may include the memory device 100c described with reference to FIGS. 23 and 24 .

Referring to FIG. 26 , the memory device 100 and the memory controller 200 set data patterns (S811 and S812). The data pattern is data mutually stipulated between the memory device 100 and the memory controller 200 and may be commonly set in the memory controller 200 and the memory device 100 .

When a data read request is received from the host 300 (S820), the memory controller 200 transmits the read command RDCMD and the address signal ADDR to the memory device 100 (S830).

The memory device 100 may read data from a memory area corresponding to the address signal ADDR (S840). The memory device 100 may determine whether the read data matches the data pattern (S850). The memory device 100 may compare the read data with a preset data pattern and determine whether they match.

When the data is matched, the memory device 100 may transmit the matching signal RDM and the pattern information BPIF to the memory controller 200 (S861). When there are a plurality of preset data patterns, the memory controller 8610 selects one of the plurality of data patterns based on the pattern information (BPIF) (S870) and transmits the selected data pattern to the host 300 as read data. It can (S881).

If the data do not match, the memory device 100 transmits the read data to the memory controller 200, and the memory controller 200 transfers the data received from the memory device 100 to the host 300 as read data. It can be transmitted (S882).

27 is a block diagram illustrating a memory system according to an exemplary embodiment, and FIG. 28 is a timing diagram of input signals applied to ranks of the memory system.

Referring to FIG. 27 , a memory system 1000d may include a plurality of ranks 1100 and 1200 and a memory controller 200 . The plurality of ranks 1100 and 1200 may be mounted in one memory module. A rank may be defined as a memory device that simultaneously receives command and address signals and is selected according to the same chip select signal CS. For example, in a memory module, a rank may be defined as a set of DRAM chips selected according to the same chip selection signal CS. Ranks may be distinguished using a chip select signal CS provided to the memory module.

The first rank 1100 includes the first to fourth memory devices 101, 102, 103, and 104, and the second rank 1200 includes the fifth to eighth memory devices 105, 106, 107, and 108. can include At least one of the first to eighth memory devices 101 to 108 may be implemented as the memory devices 100 and 100a according to the exemplary embodiments described with reference to FIGS. 1 to 18 .

The memory devices 101 to 108 of the first rank 1100 and the second rank 1200 may simultaneously receive command/address signals C/A. At this time, the memory devices 101 to 104 of the first rank 1100 are selected by the first chip select signal CS0, and the memory devices 105 to 108 of the second rank 1200 are selected by the second chip It can be selected by the selection signal CS1. The memory devices 101 to 108 of the first rank 1100 and the second rank 1200 are each connected to the data bus 400 through a data pad DQ[m−1:0].

The first rank 1100 and the second rank 1200 share the data bus 400 . If the first rank 1100 is using the data bus 400, the second rank 1200 cannot use the data bus 400. For example, when data is to be written to the first rank 1100 and the second rank 1200, the memory controller 200 transmits a write command and data to the first rank 1100, and transmission of the data After waiting until completion, that is, until occupation of the data bus 400 of the first rank 1100 is completed, a write command and data may be transmitted to the second rank 1200 . Accordingly, the data transmission/reception delay time through the data bus 400 affects the operating speed of the memory system 1000a.

However, according to the method of operating a memory device and a memory system according to an embodiment of the present disclosure described with reference to FIGS. 1 to 26 , when a pattern write command is executed in the first rank 1100, the first rank 1100 does not receive data from the memory controller 200 and therefore does not use the data bus 400. Accordingly, the memory controller 200 may transmit a write command (pattern write command or normal write command) and data to the second rank 1200 immediately after transmitting the pattern write command to the first rank 1100 . The second rank 1100 may receive data through the data bus 400 . Similarly, the memory controller 200 transmits a read command to the second rank 1200 immediately after transmitting the pattern write command to the first rank 1100 and receives read data from the second rank 1200. can Accordingly, when the first rank 1100 executes a pattern write command, the second rank 1200 can directly execute a write or read command.

Referring to FIG. 28 , during a write operation, write commands such as a pattern write command and normal write commands PW and NW may be received in synchronization with the rising edge of the clock signal CLK. As shown, when the pattern write command PW is received, data is not received. The data Din may be received after a predetermined time after the normal write command NW is received, and the time at which the data Din is received may be longer than the time at which the command CMD is received.

As shown, the pattern write command PW may be received in the first rank 1100 (Ran0). In the first period T1 according to the pattern writing command PW, the time for receiving the data Din is not required. Therefore, after the pattern write command PW is received in the first rank 1100 in response to the rising edge (or clock) of the clock signal CLK, the second rank is synchronized with the immediately next rising edge (or next clock). A write command for (1200, Rank1) may be received. When the first rank 1100 executes a pattern write command, the second rank 1200 may immediately execute a normal write command. Accordingly, the operating speed of the memory system 1000d may be improved. In addition, when pattern writing is performed, data bus 400 is not used because there is no transmission and reception of data between the memory controller 200 and the memory device, so data bus utilization can be improved.

29A and 29B are block diagrams illustrating a memory controller and a memory module according to an exemplary embodiment of the present disclosure.

Referring to FIG. 29A , a memory system 2000A includes a memory module 2100A and a memory controller 2200A. The memory module 2100A may include a printed circuit board 2120A, a plurality of memory chips 2110A, and a connector 2130A. The plurality of memory chips 2110A may be coupled to upper and lower surfaces of the printed circuit board 2120A. The connector 2130A is electrically connected to the plurality of memory chips 2110A through conductive lines (not shown). Also, the connector 4230A may be connected to a slot of an external host. The memory module 2100A may be in the form of a dual in-line memory module (DIMM).

The plurality of memory chips 2110A may include volatile memories such as DRAM cells or non-volatile memory cells such as STT-MRAM cells. In this case, the memory chips 2110A may temporarily or temporarily store data of the computer system, such as an operating memory and a cache memory.

The plurality of memory chips 2110a may be arranged in two rows parallel to each other in the longitudinal direction of the printed circuit board 2120A. Memory chips 2110A in a first row relatively far from the connector 4230A constitute a first rank R0, and memory chips in a second row adjacent to the connector 4230A constitute a second rank R1. can

The first rank R0 and the second rank R1 may be activated by different selection signals.

The memory controller 2200A may perform an operation of queuing a command or outputting a command. A DRAM interface may be applied between the memory controller 2200A and the memory module 2100A in the memory system. According to the DRAM interface according to an embodiment of the present disclosure, the memory controller 2200A transmits a pattern write command and an address signal to the memory chip 21100A when data to be stored in the memory chip 21100A matches a preset data pattern. and may not transmit data. The memory chip 2110A may internally generate a data pattern in response to a pattern write command without receiving data and write the generated data pattern into the memory cell array. The memory chip 2110A includes a pattern buffer for storing data patterns, and may write one of the data patterns stored in the pattern buffer into the memory cell array in response to a pattern write command.

In the memory system 2000A of FIG. 29A , the memory controller 2200A is illustrated as being provided separately from the memory module 2100A, but the memory controller 2200A may be included in the memory module 2100A. The memory controller 2200A may be coupled to an upper or lower surface of the printed circuit board 2110A, and may communicate with the memory chips 2110A through conductive lines (not shown).

Meanwhile, as shown in FIG. 29B, the memory system 2000B includes a memory module 2100B and a memory controller 2200B, and the memory module 2100B includes one or more semiconductor chips each including a cell array, and cells. A buffer chip 2110B for managing memory operations for the array may be included.

The buffer chip 2120B may receive commands, address signals, and data from the memory controller 2200B, and may provide commands and data to a rank selected from ranks R0 and R1. The buffer chip 2120B may include a pattern buffer 2111B. When a pattern write command is received from the memory controller 2200B, the buffer chip 2120B outputs a data pattern corresponding to the pattern write command from the pattern buffer 2111B and includes it in a selected rank among the plurality of ranks R0 and R1. may be provided to the memory chips 2110B. When a normal write command is received from the memory controller 2200B, the buffer chip 2120B stores the data received from the memory controller 2200B in the memory chips 2110B included in the selected rank among the plurality of ranks R0 and R1. can provide

In the example of FIG. 29B , an example in which some of the functions of the memory controller are performed in an LRDIMM type memory module is illustrated, but embodiments of the present invention need not be limited thereto. For example, as a memory module in the form of an FBDIMM is applied, an Advanced Memory Buffer (AMB) chip may be mounted in the memory module as a management chip. In addition, other types of memory modules may be applied, and at least some of the functions of the above-described memory controller may be implemented in the memory module.

30 is a block diagram illustrating a stacked memory device including a plurality of semiconductor layers.

Referring to FIG. 30 , the memory device 3000 may include a plurality of semiconductor layers LA1 to LAn. Each of the semiconductor layers LA1 to LAn may be a memory chip including the memory cell array 1100 . Alternatively, some of the semiconductor layers LA1 to LAn may be a memory chip, and another part (or any one layer) may be a controller chip interfacing with the memory chip. In the example of FIG. 30 , it is assumed that the nth layer LAn is a controller chip.

The controller chip LAn communicates with the memory chips LA1 to LA n−1 and controls operation modes of the memory chips LA1 to LA n−1. The controller chip LAn may control various functions, characteristics, and modes using mode registers of the memory chips LA1 to LA n−1. Also, the controller chip LAn may perform an operation of queuing a command or outputting a command.

Also, the controller chip LAn may include a pattern buffer 3210 . When a pattern write command is received from a memory controller (not shown), the controller chip LAn outputs a data pattern corresponding to the pattern write command from the pattern buffer 3210 and provides it to the memory chips LA1 to LA n-1. can When a normal write command is received from the memory controller, the controller chip LAn may provide data received from the memory controller to the memory chips LA1 to LA n-1.

In the memory device 3000 , the plurality of semiconductor layers LA1 to LAn of the stacked structure may be interconnected through a through silicon via (TSV) 9300 .

31 is a block diagram illustrating a computer system according to an embodiment of the present disclosure.

The computer system 4000 may be a desktop computer, a notebook computer, a workstation, a hand health device, a wearable device, or the like. Referring to FIG. 21 , a computer system 4000 includes a processor 4100, a system controller 4200, and a memory system 4300. The computer system 4000 may further include a processor bus 4510, an expansion bus 4520, an input device 4410, an output device 4420, and a storage device 4430. The memory system 4300 may include at least one memory device 4320 and a memory controller 4310 . The memory controller 4310 may be included in the system controller 4200 .

Processor 4100 may execute a variety of computing systems, such as executing specific software to perform specific calculations or tasks. For example, the processor 4100 may be a microprocessor or central processing unit. The processor 4100 may be connected to the system controller 4200 through a processor bus 4510 including an address bus, a control bus, and/or a data bus. The system controller 4200 is coupled to an expansion bus 4520, such as a peripheral component interconnection (PCI) bus. Accordingly, the processor 4100 may transmit one or more input devices 4410 such as a keyboard or mouse through the system controller 4200, one or more output devices 4420 such as a printer or display device, or a hard disk drive, solid state drive, or It may control one or more storage devices 4430, such as a CD-ROM.

The memory controller 4310 may control the memory device 4320 to execute a command provided by the processor 4100 . The memory device 4320 may store data provided from the memory controller 4310 and provide the stored data to the memory controller 4310 . The memory device 4320 may include a plurality of memory chips, for example, a dynamic random access memory (DRAM), a static random access memory (SRAM), or a non-volatile memory chip. .

Meanwhile, according to an embodiment of the present disclosure, the memory controller 4310 writes a pattern without transmitting data to the memory device 4320 when write data provided along with a write command from the processor 4100 matches a preset data pattern. command can be sent. The memory device 4320 may store write data requested to be written from the processor 4100 by writing a preset data pattern into the memory cell array. Accordingly, since data transmission/reception between the memory controller 4310 and the memory device 4320 is reduced, power consumption of the computer system 4000 is reduced and the operating speed of the computer system 4000 can be improved. .

32 is a block diagram illustrating a computer system including a memory system according to an exemplary embodiment of the present disclosure. Referring to FIG. 32 , a computer system 5000 may include a central processing unit 5200 electrically connected to a system bus 5100, a modem 5300, a user interface 5400, and a memory system 5500. . The memory device 5520 may include volatile memory cells such as DRAM cells or non-volatile memory cells such as STT-MRAM cells.

The memory system 5500 may include a memory device 5520 and a memory controller 5510 . Data processed by the CPU 5200 or data input from the outside may be stored in the memory device 5520 . The memory device 5520 may be used as a storage for storing large amounts of data required for the computer system 5000 or a main memory for storing data requiring fast access, such as system data.

In the memory system 5500 according to an embodiment of the present disclosure, when data input from the central processing unit 5200 or the outside matches a preset data pattern, data transmission between the memory controller 5510 and the memory device 5520 occurs. / The above data can be stored in the memory device 5520 without reception. The memory controller 5510 transmits a pattern write command to write a preset data pattern to the memory device 5520 . The memory device 5520 may internally generate a data pattern in response to a pattern write command and store data input from the CPU 5200 or the outside by storing the generated data pattern. Since data transmission/reception between the memory controller 5510 and the memory device 5520 is reduced, power consumption of the computer system 5000 is reduced, and operating speed of the computer system 5000 can be improved.

Meanwhile, although not shown, the computer system 5000 may further include an application chipset, a camera image processor (CIS), an input/output device, and the like.

Although the present disclosure has been described with reference to the embodiments shown in the drawings, this is only exemplary, and those skilled in the art will understand that various modifications and equivalent other embodiments are possible therefrom. Therefore, the true technical scope of protection of the present disclosure should be determined by the technical spirit of the appended claims.

100, 100a, 100b: memory device
200, 200a: memory controller
180: data pattern providing unit
170: I/O buffer
1000: memory system

Claims (17)

a memory cell array including a first memory bank and a second memory bank, each of which is independently accessible;
a writing circuit that performs a pattern writing operation when receiving a pattern writing command and a first address from an external device, and performs a normal writing operation when receiving a normal writing command, a second address, and writing data;
a data pattern providing unit providing a selected data pattern to the writing circuit in response to the pattern writing command, wherein the selected data pattern is a data pattern to be written in the memory cell array; and
a data input buffer for receiving the write data from the external device and providing the write data to the write circuit during the normal write operation;
During the pattern write operation, the selected data pattern is written to the first memory bank designated by the first address, and the write data received from the external device during the normal write operation is designated by the second address. written to the second memory bank;
The memory device of claim 1 , wherein at least part of the normal write operation in the second memory bank is performed in parallel with the pattern write operation in the first memory bank. According to claim 1,
The memory device, characterized in that the memory device includes dynamic random access memory (DRAM). According to claim 2,
For the normal write operation, the write data is received through DQ pins of the memory device;
The memory device, characterized in that the write data is not received for the pattern write operation. According to claim 3,
The memory device according to claim 1 , wherein the write data is received after a predetermined delay from reception of the normal write command. The method of claim 4, wherein the data pattern providing unit,
A memory device comprising a pattern buffer for storing a plurality of data patterns, and generating the selected data pattern based on the plurality of data patterns stored in the pattern buffer. According to claim 5,
The DRAM receives write command related signals for performing the pattern write operation and the normal write operation;
The signals include a chip select signal (/CS), a row address strobe signal (/RAS), a column address strobe signal (/CAS) and a write enable signal (/WE), and the chip select signal logic levels of (/CS), the row address strobe signal (/RAS), the column address strobe signal (/CAS), and the write enable signal (/WE) are low, high, low, and low, respectively;
wherein the DRAM further receives a mode signal from the external device, and the mode signal identifies whether the received write command is the pattern write command or the normal write command. According to claim 6,
The memory device, characterized in that the mode signal identifies the selected data pattern of the plurality of data patterns. According to claim 7,
The memory device, characterized in that the mode signal is received through at least three address pins not used for transmission of address signals. According to claim 8,
The memory device, characterized in that the memory device further receives a pattern storage command together with buffer data, and the buffer data is stored in the pattern buffer as one of the plurality of data patterns. According to claim 9,
The plurality of data patterns include a user-defined data pattern and/or a data pattern frequently written to the memory device. According to claim 10,
The plurality of data patterns may include data patterns having all low logic levels and/or data patterns having all high logic levels. According to claim 10,
The pattern write command and the normal write command are received in synchronization with a first rising edge and a second rising edge of a clock signal, respectively, and the second rising edge of the clock signal follows immediately after the first rising edge. , a memory device. a pattern buffer for storing data patterns;
a receiving circuit for receiving a write request, address information and data from a host; and
A data comparison unit for comparing the data with the data pattern stored in the data pattern buffer;
Generates one of a pattern write command and a normal write command based on the comparison result of the comparison unit;
If the comparison result matches the data and the data pattern, transmits the pattern write command and the first address to a memory device;
If the comparison result is inconsistent between the data and the data pattern, transmit the normal write command, second address, and write data to the memory device;
The memory controller of claim 1 , wherein the pattern write command includes a mode signal indicating that the data pattern matches the data received from the host. delete According to claim 13,
The mode signal identifies a data pattern stored in the memory device in response to the pattern write command, and the data pattern stored in the memory device is identical to the data pattern that matches the data received from the host. , memory controller. 16. The method of claim 15, wherein the memory controller,
Characterized in that, the memory controller further transmits a pattern storage command together with the data pattern to store the data pattern in the memory device. 17. The method of claim 16,
The pattern write command and the normal write command are received in synchronization with a first rising edge and a second rising edge of a clock signal, respectively, and the second rising edge of the clock signal follows immediately after the first rising edge. , memory controller.

Images