KR102482700B1 - Method for testing semiconductor package - Google Patents

Abstract

An object of the present invention is to provide a semiconductor package test method capable of effectively inspecting operational performance of a semiconductor package having a narrow pitch and having a large number of signal buses, and at the same time improving productivity of the semiconductor package. The semiconductor package test method provides a first semiconductor package including a first semiconductor chip, wherein the first semiconductor chip has a first external terminal group arranged at a first pitch and a second pitch greater than the first pitch. An arranged second external terminal group is disposed on one surface, and a first test is performed on the first semiconductor package by contacting the first external terminal group and a first contactor, and the second external terminal group and the first contactor are contacted. and contacting two contactors to perform a second test on the first semiconductor package.

Description

Method for testing semiconductor package {Method for testing semiconductor package}

The present invention relates to a method for testing a semiconductor package, and more particularly, to a method for testing a semiconductor package in which a plurality of semiconductor chips are stacked and singulated.

A recent trend in the electronics industry is to manufacture lightweight, miniaturized, high-speed, multifunctional, and high-performance products at low prices. In addition, in order to improve the performance of integrated circuits, integrated circuits are being developed in three-dimensional structures such as multi-chip stacked packages.

For example, an integrated circuit having a three-dimensional structure in which a plurality of memory chips are stacked includes many signal buses for transmitting and receiving signals.

The problem to be solved by the present invention is to provide a semiconductor package test method capable of effectively inspecting the operating performance of a semiconductor package having a narrow pitch and a large number of signal buses, and at the same time improving the productivity of the semiconductor package test. will be.

The problems to be solved by the present invention are not limited to the above-mentioned problems, and other problems not mentioned will be clearly understood by those skilled in the art from the following description.

One aspect of a method for testing a semiconductor package of the present invention for solving the above problems is to provide a first semiconductor package including a first semiconductor chip, wherein the first semiconductor chip is arranged in a first pitch. A terminal group and a second external terminal group arranged at a second pitch greater than the first pitch are disposed on one surface, and contact the first external terminal group and a first contactor to form a first contact point for the first semiconductor package. A first test is performed, and a second test is performed on the first semiconductor package by contacting the second external terminal group and the second contactor.

Another aspect of the semiconductor package test method of the present invention for solving the above problems is to provide a plurality of semiconductor packages separated from each other and attached to a carrier, wherein each of the semiconductor packages has a micro bump group and a pad group on one surface. including the disposed first semiconductor chip, performing a first test on each semiconductor package by contacting a first contactor and a micro bump group included in each semiconductor package, and performing the first test; Then, rearranging at least some of the plurality of semiconductor packages on a first inspection stage to provide a first semiconductor package group, the pad group of each of the semiconductor packages included in the first semiconductor package group, and simultaneously performing a second test on each semiconductor package included in the first semiconductor package group by contacting the second contactor.

Another aspect of the semiconductor package test method of the present invention for solving the above problems is to provide a first semiconductor package including a first semiconductor chip, wherein the first semiconductor chip is a first micro bump group arranged in a first pitch. And, a first pad group arranged at a second pitch greater than the first pitch is disposed on one surface, and a second semiconductor package including a second semiconductor chip, wherein the second semiconductor chip has the first pitch An arrayed second micro bump group and a second pad group arrayed at the second pitch are disposed on one surface, the first semiconductor package and the second semiconductor package are rearranged on an inspection stage, and the first pad and simultaneously performing a first test on the first semiconductor package and the second semiconductor package by bringing the group and the second pad group into contact with the first contactor.

Other specific details of the invention are included in the detailed description and drawings.

1 is a diagram for explaining semiconductor packages used in a method for testing a semiconductor package according to some embodiments of the present invention.
2A and 2B are cross-sectional views illustrating the semiconductor package of FIG. 1 .
3A and 3B are views for explaining an external terminal group of the semiconductor package of FIG. 1 .
4 is a flowchart illustrating a method for testing a semiconductor package according to some embodiments of the present disclosure.
5 is a schematic diagram for explaining semiconductor package test equipment used in a semiconductor package test method according to some embodiments of the present invention.
6A and 6B are diagrams for explaining a contactor module included in the semiconductor package test equipment of FIG. 5 .
7 is a schematic diagram for explaining semiconductor package test equipment used in a semiconductor package test method according to some embodiments of the present invention.
8 is a schematic diagram for explaining semiconductor package test equipment used in a semiconductor package test method according to some embodiments of the present invention.
9A and 9B are diagrams for explaining a hybrid contactor module included in the semiconductor package test equipment of FIG. 8 .
10 is a schematic diagram for explaining semiconductor package test equipment used in a first test among semiconductor package test methods according to some embodiments of the present disclosure.
FIG. 11 is a schematic layout diagram of FIG. 10 .
12 is a schematic diagram for explaining semiconductor package test equipment used in a second test among semiconductor package test methods according to some embodiments of the present disclosure.
FIG. 13 is a schematic layout diagram of FIG. 12 .
14 is a schematic layout diagram of semiconductor package test equipment used for a second test among semiconductor package test methods according to some embodiments of the present invention.
15 is a schematic layout diagram of semiconductor package test equipment used for a second test among semiconductor package test methods according to some embodiments of the present invention.
16 is a schematic diagram for describing a socket that may be used for a second test among semiconductor package test methods according to some embodiments of the present disclosure.

A semiconductor package test method according to some embodiments of the present invention will be described using FIGS. 1 to 6B .

1 is a diagram for explaining semiconductor packages used in a method for testing a semiconductor package according to some embodiments of the present invention. 2A and 2B are cross-sectional views illustrating the semiconductor package of FIG. 1 . 3A and 3B are views for explaining an external terminal group of the semiconductor package of FIG. 1 . 4 is a flowchart illustrating a method for testing a semiconductor package according to some embodiments of the present disclosure. 5 is a schematic diagram for explaining semiconductor package test equipment used in a semiconductor package test method according to some embodiments of the present invention. 6A and 6B are diagrams for explaining a contactor module included in the semiconductor package test equipment of FIG. 5 .

Referring to FIGS. 1 to 3B , a first semiconductor package group 100 attached to a carrier 50 may be provided.

The first semiconductor package group 100 may include a plurality of semiconductor packages 110 separated from each other. That is, a plurality of semiconductor packages 110 separated from each other may be provided by being attached to the carrier 50 .

The carrier 50 may include a wafer ring 51 and an adhesive film 52 . The adhesive film 52 may fix the plurality of semiconductor packages 110 separated from each other to the wafer ring 51 .

The adhesive layer 52 may include, for example, a material that loses adhesive strength when irradiated with light.

For example, the plurality of semiconductor packages 110 may include a first semiconductor package 110_1 and a second semiconductor package 110_2 that are separated from each other. That is, the first semiconductor package 110_1 and the second semiconductor package 110_2 attached to the carrier 50 may be provided.

Each of the plurality of semiconductor packages 110 may include lower semiconductor chips 111_1 and 111_2 and upper semiconductor chips 112_1 and 112_2 . Since each of the plurality of semiconductor packages 110 is separated from each other, respective lower semiconductor chips 111_1 and 111_2 included in the plurality of semiconductor packages 110 are separated from each other.

The lower semiconductor chips 111_1 and 111_2 and the upper semiconductor chips 112_1 and 112_2 may include, for example, a silicon substrate. Alternatively, the lower semiconductor chips 111_1 and 111_2 and the upper semiconductor chips 112_1 and 112_2 may be made of another material, for example, silicon germanium, indium antimonide, lead tellurium compound, indium arsenide, indium phosphide, gallium arsenide, or gallium antimonide. can include

The lower semiconductor chips 111_1 and 111_2 may be, for example, logic chips. The lower semiconductor chips 111_1 and 111_2 may be designed in various ways in consideration of operations to be performed.

The upper semiconductor chips 112_1 and 112_2 may be, for example, memory chips. The upper semiconductor chips 112_1 and 112_2 may be, for example, non-volatile memory chips or volatile memory chips.

Specifically, when the memory chip is a volatile memory chip, the memory chip may include Dynamic Random-Access Memory (DRAM). When the memory chip is a non-volatile memory chip, the memory chip may be a flash memory chip. More specifically, the memory chip may be either a NAND flash memory chip or a NOR flash memory chip.

Meanwhile, the shape of the memory device according to the technical idea of the present invention is not limited thereto. In some embodiments of the present invention, a flash memory chip may include any one of phase-change random-access memory (PRAM), magneto-resistive random-access memory (MRAM), and resistive random-access memory (RRAM). .

The first semiconductor package 110_1 may include a first lower semiconductor chip 111_1 and one or more first upper semiconductor chips 112_1 stacked on the first lower semiconductor chip 111_1 . The first lower semiconductor chip 111_1 may include a first surface 111_1a and a second surface 111_1b facing each other.

The first lower semiconductor chip 111_1 may include a first inner external terminal group 113_1 and a first outer external terminal group 114_1 arranged on the first surface 111_1a of the first lower semiconductor chip. Descriptions of the first outer external terminal group 114_1 and the first inner external terminal group 113_1 will be described later.

One or more first upper semiconductor chips 112_1 may be stacked on the second surface 111_1b of the first lower semiconductor chip. At least a portion of the first upper semiconductor chip 112_1 may include the first through electrode 116_1.

The first through electrode 116_1 may include, for example, copper (Cu), aluminum (Al), or tungsten (W). A liner and a barrier layer may be further included between the first through electrode 116_1 and the semiconductor material that is the substrate of the first upper semiconductor chip 112_1 . The barrier layer may include, for example, Ta, TaN, Ti, TiN, Ru, Co, Ni, NiB, or WN. The liner may include, for example, silicon oxide having a low dielectric constant or silicon oxide doped with carbon.

A first connection terminal 116_1 may be formed between the first lower semiconductor chip 111_1 and the first upper semiconductor chip 112_1 and between the adjacent first upper semiconductor chip 112_1 . Although the first connection terminal 116_1 is shown in a ball shape, it is not limited thereto. Of course, the first connection terminal 116_1 may be a pillar bump type in which a pillar and a solder ball are combined.

The first molding material 118_1 may be formed on the second surface 111_1b of the first lower semiconductor chip. The first molding material 118_1 may cover the first upper semiconductor chip 112_1. The first molding material 118_1 may include, for example, an epoxy resin or a silicon hybrid material of two or more types.

The second semiconductor package 110_2 may include a second lower semiconductor chip 111_2 and one or more second upper semiconductor chips 112_2 stacked on the second lower semiconductor chip 111_2 . The second lower semiconductor chip 111_2 may include a first surface 111_2a and a second surface 111_2b facing each other.

The second lower semiconductor chip 111_2 may include a second inner external terminal group 113_2 and a second outer external terminal group 114_2 arranged on the first surface 111_2a of the second lower semiconductor chip. Descriptions of the second outer external terminal group 114_2 and the second inner external terminal group 113_2 will be described later.

One or more second upper semiconductor chips 112_2 may be stacked on the second surface 111_2b of the second lower semiconductor chip. At least a portion of the second upper semiconductor chip 112_2 may include the second through electrode 116_2.

A second connection terminal 116_2 may be formed between the second lower semiconductor chip 111_2 and the second upper semiconductor chip 112_2 and between the adjacent second upper semiconductor chip 112_2 .

The second molding material 118_2 may be formed on the second surface 111_2b of the second lower semiconductor chip. The second molding material 118_2 may cover the second upper semiconductor chip 112_2.

In FIGS. 2A and 2B , the number of the first upper semiconductor chip 112_1 and the second upper semiconductor chip 112_2 is illustrated as four, but is not limited thereto.

In addition, in FIGS. 2A and 2B , each of the first upper semiconductor chip 112_1 and each of the second upper semiconductor chip 112_2 is illustrated as including through electrodes 115_1 and 115_2 , but is not limited thereto. . The first upper semiconductor chip 112_1 and the second upper semiconductor chip 112_2 positioned at the top may not include the through electrodes 115_1 and 115_2 .

In addition, although the first molding material 118_1 and the second molding material 118_2 do not cover the upper surface of the first upper semiconductor chip 112_1 and the upper surface of the second upper semiconductor chip 112_2 located at the top, respectively, , but is not limited thereto.

In addition, although the through electrodes 115_1 and 115_2 included in the first upper semiconductor chip 112_1 and the second upper semiconductor chip 112_2 are illustrated as five, the number is not limited thereto.

For reference, FIGS. 2A and 2B illustrate only the stacked structures of the first semiconductor package 110_1 and the second semiconductor package 110_2 . However, it is apparent to those skilled in the art that each semiconductor package 110 may have the same or similar structure as the first semiconductor package 110_1 and the second semiconductor package 110_2.

3A and 3B , the first inner external terminal group 113_1 and the first outer external terminal group 114_1 included in the first semiconductor package 110_1 and the second semiconductor package 110_2 included in The second inner outer terminal group 113_2 and the second outer outer terminal group 114_2 will be described.

The first inner external terminal group 113_1 may be arranged on the first surface 111_1a of the first lower semiconductor chip. The first inner external terminal group 113_1 may be positioned in the center of the first surface 111_1a of the first lower semiconductor chip.

The first inner and outer terminal groups 113_1 may be arranged with a first pitch P1. The first pitch P1 may be smaller than 100 μm, for example.

The first outer external terminal group 114_1 may be arranged on the first surface 111_1a of the first lower semiconductor chip. The first outer external terminal group 114_1 may be positioned at an edge of the first surface 111_1a of the first lower semiconductor chip.

The first outer external terminal group 114_1 may be arranged with a second pitch P2. The first outer external terminal group 114_1 may be a design for test (DFT) based external terminal group.

The second inner external terminal group 113_2 may be arranged on the first surface 111_2a of the second lower semiconductor chip. The second inner external terminal group 113_2 may be positioned in the center of the first surface 111_2a of the second lower semiconductor chip.

The second inner and outer terminal groups 113_2 may be arranged with a first pitch P1.

The second outer external terminal group 114_2 may be arranged on the first surface 111_2a of the second lower semiconductor chip. The second outer external terminal group 114_2 may be positioned at an edge of the first surface 111_2a of the second lower semiconductor chip.

The second outer external terminal group 114_2 may be arranged with a second pitch P2. The second outer external terminal group 114_2 may be a DFT-based external terminal group.

Each of the first inner external terminal group 113_1 and the second inner external terminal group 113_2 may include, for example, a micro bump array. Each of the micro bumps may be, for example, a pillar bump type in which a pillar and a solder ball are combined, but are not limited thereto.

In FIGS. 3A and 3B , the first outer external terminal group 114_1 and the second outer external terminal group 114_2 are shown as pad arrays, but are not limited thereto. That is, of course, each of the first outer external terminal group 114_1 and the second outer external terminal group 114_2 may have a micro bump shape or a solder ball shape, for example.

In the semiconductor package test method according to some embodiments of the present invention, the first pitch P1 between the adjacent inner and outer terminal groups 113_1 and 113_2 is the second pitch P1 between the adjacent outer outer terminal groups 114_1 and 114_2. It is smaller than the pitch (P2).

In the semiconductor package test method according to some embodiments of the present invention, the package test of the first semiconductor package 110_1 and the second semiconductor package 110_2 using the first and second inner external terminal groups 113_1 and 113_2 is performed. This cannot be done using sockets.

In other words, after accommodating the first semiconductor package 110_1 and the second semiconductor package 110_2 in the socket, the inner and outer terminal groups 113_1 of the first semiconductor package 110_1 and the second semiconductor package 110_2, respectively, 113_2), the first pitch P1 must be sufficiently large to perform the package test.

However, the first pitch P1 of the first inner external terminal group 113_1 included in the first semiconductor package 110_1 and the second inner outer terminal group 113_2 included in the second semiconductor package 110_2 The first pitch P1 is very small. Accordingly, a package test using the first and second inner external terminal groups 113_1 and 113_2 cannot be performed by placing the first semiconductor package 110_1 and the second semiconductor package 110_2 in the socket.

Meanwhile, a package test of the first semiconductor package 110_1 using the first outer external terminal group 114_1 and a package test of the second semiconductor package 110_2 using the second outer external terminal group 114_2 are performed on the outer external terminal. Depending on the pitch of the groups 114_1 and 114_2, it may or may not be performed using a socket.

This is because the first outer external terminal group 114_1 and the second pitch P2 of the first outer external terminal group 114_1 may be changed according to a demand of a manufacturer of the semiconductor package or a user of the semiconductor package.

In the semiconductor package test method according to some embodiments of the present invention, each semiconductor package 110 has inner and outer terminal groups 113_1 and 113_2 and outer outer terminal groups 114_1 and 114_2 as described above formed on one surface. It does not contain a Printed Circuit Board. That is, each semiconductor package 110 may not have a plurality of semiconductor chips mounted on a printed circuit board including inner external terminal groups 113_1 and 113_2 and outer external terminal groups 114_1 and 114_2.

Meanwhile, each semiconductor package 110 may include a printed circuit board disposed between the lower semiconductor chip 111_1 and one or more upper semiconductor chips 112_1 and 112_2.

In the semiconductor package test method described with reference to FIGS. 1 to 6B , a package test of a first semiconductor package 110_1 using a first outer external terminal group 114_1 and a package test using a second outer external terminal group 114_2 It will be described that the package test of the second semiconductor package 110_2 cannot be performed using a socket.

For reference, FIGS. 3A and 3B show the first and second inner external terminal groups 113_1 and 113_2 of the first semiconductor package 110_1 and the second semiconductor package 110_2 and the first and second outer external terminals. Only the structures of the groups 114_1 and 114_2 are shown.

However, it is common in the art that each semiconductor package 110 includes an inner outer terminal group and an outer outer terminal group identical or similar to those of the first semiconductor package 110_1 and the second semiconductor package 110_2. It is self-evident to the technician of

A process of forming the first semiconductor package group 100 of FIG. 1 will be briefly described.

A semiconductor substrate including a plurality of lower semiconductor chips 111_1 and 111_2 that are not separated from each other is provided. At least one or more upper semiconductor chips 112_1 and 112_2 are stacked on each lower semiconductor chip.

Next, a molding material surrounding the laminate in which the upper semiconductor chips 112_1 and 112_2 are stacked is formed on the semiconductor substrate. Subsequently, the semiconductor substrate is diced to separate the lower semiconductor chips 111_1 and 111_2 included in the semiconductor substrate. In order to check whether the upper semiconductor chips 112_1 and 112_2 are well mounted on the lower semiconductor chips 111_1 and 111_2, the lower semiconductor chips 111_1 and 111_2 and the upper semiconductor chips 112_1 and 112_2 are subjected to dicing before dicing. Testing can be performed at the wafer level.

In FIG. 1 , since the first semiconductor package groups 100 separated from each other are formed through the dicing process, a separation width between adjacent semiconductor packages may vary. That is, the plurality of semiconductor packages 110 may not be arranged at equal intervals.

Each semiconductor package 110 may be, for example, a high bandwidth memory (HBM), but is not limited thereto.

First, a first semiconductor package test equipment 300 that can be used for the semiconductor package test described in FIG. 4 will be described with reference to FIG. 5 .

5 and 6 , the first semiconductor package test equipment 300 includes a first tester 310, a second tester 320, a first contactor module 315, and a second contactor module. 325 , a first inspection stage 340 , and a second inspection stage 350 .

The first semiconductor package test equipment 300 may include a first test area and a second test area. The first test area is an area where the first tester 310 and the first contactor module 315 are disposed, and the second test area is an area where the second tester 320 and the second contactor module 325 are disposed. can be

The first tester 310 performs a first test on the semiconductor package ( 110 in FIG. 1 ). Also, the second tester 320 performs a first test on the semiconductor package ( 110 in FIG. 1 ).

For example, a first test and a second test may be performed on the semiconductor package ( 110 in FIG. 1 ) using the first semiconductor package test equipment 300 , which is one piece of equipment.

The first test for the semiconductor package is, for example, an open/short test, a leakage current test, an operation current test, and a chip crack detection test. ), gross function tests, and the like.

The second test of the semiconductor package may be, for example, a function test of the semiconductor package. Through the function test, a specific memory pattern may be applied to a semiconductor package to test the operation of the memory cell, and operation and failure of the entire region of the memory cell may be determined.

The second test may include, for example, a cell & core operation test, a speed test, and a temperature test. The speed test may include a low-frequency test, a mid-frequency test, and a high-frequency test, and the temperature test may include a low-temperature test and a high-temperature test.

For example, the first test may be a test that takes several seconds to tens of seconds, and the second test may be a test that takes hundreds of seconds to thousands of seconds. Accordingly, the time during which the first test is performed is shorter than the time during which the second test is performed.

The first contactor module 315 may include a first contactor 315p used for the first test. The first contactor module 315 may be connected to the first tester 310 .

In FIG. 6A , the first contactor module 315 is illustrated as including one first contactor 315p, but is not limited thereto.

One package test area 110ta may be defined in the first contactor module 315 to correspond to the first contactor 315p.

The first contactor 315p may be located in the package test area 110ta. The first contactor 315p may be positioned to correspond to the inner and outer terminal groups 113_1 and 113_2 of the semiconductor package 110 .

The first contactor 315p may have, for example, a micro tip or needle shape, but is not limited thereto.

In FIG. 6B , the second contactor module 325 may include a second contactor 325p used for the second test. The second contactor module 325 may be connected to the second tester 320 .

The second contactor module 325 may include a plurality of second contactors 325p. A plurality of package test areas 110ta may be defined in the second contactor module 325 to correspond to the second contactor 325p.

Each second contactor 325p may be located within each package test area 110ta. Each of the second contactors 325p may be positioned to correspond to the outer terminal groups 114_1 and 114_2 of the semiconductor package.

The second contactor 325p may have, for example, a needle shape, but is not limited thereto.

The second test using the second contactor module 325 may be simultaneously performed on a plurality of semiconductor packages.

The first contactor 315p is disposed in the first test region of the first semiconductor package test equipment 300, and the second contactor 325p is disposed in the second test region of the first semiconductor package test equipment 300. It can be.

A semiconductor package for performing a first test may be positioned on the first inspection stage 340 . A semiconductor package for performing a second test may be positioned on the second inspection stage 350 .

Referring to FIGS. 1 , 4 and 5 , the first semiconductor package group 100 attached to the carrier 50 may be loaded into the first semiconductor package test equipment 300 .

To test each package included in the first semiconductor package group 100 , a plurality of semiconductor packages 110 may be provided.

The plurality of semiconductor packages 110 attached to the carrier 50 may be disposed on the first inspection stage 340 . For example, the first semiconductor package 110_1 and the second semiconductor package 110_2 may be disposed on the first inspection stage 340 .

Referring to FIGS. 1 and 3A to 6 , the first inner external terminal group 113_1 of the first semiconductor package 110_1 and the first contactor 315p are brought into contact so that the first semiconductor package 110_1 A first test may be performed (S200).

While contacting the first inner/outer terminal group 113_1 and the first contactor 315p, the first tester 310 may perform a first test.

Since the first inner/outer terminal group 113_1 may include a micro bump array, the first semiconductor package 110_1 is connected through contact between the micro bump array (or micro bump group) and the first contactor 315p. A first test may be performed for

As the first inspection stage 340 rotates, moves left and right, or moves up and down, the first inner/outer terminal group 113_1 and the first contactor 315p may be aligned and brought into contact with each other.

The first semiconductor package 110_1 after the first test may be moved to the second inspection stage 350 by the first transfer unit 330 .

Subsequently, a first test may be performed on the second semiconductor package 110_2 by contacting the second inner external terminal group 113_2 of the second semiconductor package 110_2 and the first contactor 315p (S200). ).

While contacting the second inner and outer terminal group 113_2 and the second contactor 325p, the first tester 310 may perform a first test.

As the first inspection stage 340 rotates, moves left and right, or moves up and down, the second inner/outer terminal group 113_2 and the first contactor 315p may be aligned and brought into contact with each other.

The first test of the first semiconductor package 110_1 may be performed in a separate step from the first test of the second semiconductor package 110_2 . In other words, the first test of the second semiconductor package 110_2 may be performed with a time difference from the first test of the first semiconductor package 110_1.

Since the first test is performed using the first and second inner external terminal groups 113_1 and 113_2, the first test may be performed without a socket accommodating the respective first and second semiconductor packages 110_1 and 110_2. there is. That is, the first test is a package test that does not use sockets.

A first test may be performed on each semiconductor package by contacting the inner and outer terminal groups included in each semiconductor package 110 with the first contactor 315p. When the micro bump group is included as the inner and outer terminal group, the micro bump group included in each semiconductor package ( 110 in FIG. 1 ) is brought into contact with the first contactor 315p to perform a first test on each semiconductor package. can be performed.

For example, the first test may be performed with one semiconductor package 110 .

Each semiconductor package 110 after the first test may be moved to the second inspection stage 350 by the first transfer means 330 .

In the semiconductor package test method described with reference to FIG. 5 , the first test may be performed while the first semiconductor package group 100 is attached to the carrier 50 .

Referring to FIGS. 5 and 6 , the first semiconductor package 110_1 and the second semiconductor package 110_2 on which the first test was performed may be rearranged on the second inspection stage 350 .

That is, at least a portion of the first semiconductor package group 100 on which the first test was performed may be rearranged on the second inspection stage 350 .

In other words, at least some of the plurality of semiconductor packages ( 110 in FIG. 1 ) provided as the carrier 50 may be rearranged on the second inspection stage 350 . At least some of the plurality of semiconductor packages ( 110 in FIG. 1 ) rearranged on the second inspection stage 350 may be packages on which the first test has been performed.

The second semiconductor package group 101 may be provided on the second inspection stage 350 by rearranging at least some of the plurality of semiconductor packages 110 , respectively, on the second inspection stage 350 .

The second semiconductor package group 101 on the second inspection stage 350 may be positioned to correspond to the second contactor 325p included in the second contactor module 325 .

That is, rearranging at least some of the plurality of semiconductor packages on which the first test is performed is performed on the second inspection stage 350 so that each semiconductor package ( 110 in FIG. 1 ) on which the first test is performed is used as a second contactor. (325p).

The second semiconductor package group 101 provided on the second inspection stage 350 includes the first semiconductor package 110_1 and the second semiconductor package 110_2 on which the first test is performed in separate steps. That is, the second semiconductor package group 101 may include at least two or more semiconductor packages 110 .

The second semiconductor package group 101 provided on the second inspection stage 350 may move under the second contactor module 325 connected to the second tester 320 . The second inspection stage 350 may be moved below the second contactor module 325 by the second moving unit 360 .

Referring to FIGS. 1 and 3A to 6 , the first inner external terminal group 113_1 of the first semiconductor package 110_1 and the second contactor 325p are in contact, and the second contactor 325p of the second semiconductor package 110_2 A second test may be simultaneously performed on the first semiconductor package 110_1 and the second semiconductor package by contacting the second inner external terminal group 113_2 and the second contactor 325p (S210).

While contacting the first outer external terminal group 114_1 and the second contactor 325p, and contacting the second outer external terminal group 114_2 and the second contactor 325p, the second tester 320 A second test can be performed.

Since the first outer external terminal group 114_1 and the second outer external terminal group 114_2 may each include a pad array, through contact between the pad array (or pad group) and the second contactor 325p, A second test for the first semiconductor package 110_1 and the second semiconductor package 110_2 may be simultaneously performed.

In the semiconductor package test method described with reference to FIG. 5 , the second test may be performed without a socket accommodating each of the first and second semiconductor packages 110_1 and 110_2 . That is, the second test may be a package test that does not use a socket.

The semiconductor packages 110 included in the second semiconductor package group 101 are brought into contact with the outer external terminal group of each semiconductor package 110 included in the second semiconductor package group 101 with the second contactor 325p. ) A second test may be performed.

The second test may be simultaneously performed on the semiconductor packages 110 included in the second semiconductor package group 101 .

Although not shown in FIG. 5 , the semiconductor packages 110 included in the second semiconductor package group 101 in which the second test was performed may be classified. For example, a semiconductor package that has passed the first test and the second test and a semiconductor package that has not passed may be separately placed on a tray or the like.

Effects obtained through the semiconductor package test method of the present invention will be described.

For example, it is assumed that the time for performing the first test is 10 seconds and the time for performing the second test is 1000 seconds.

If the first test and the second test are sequentially performed on one semiconductor package, the time required to test one semiconductor package may be 10 to 10 seconds. It takes about 100,000 seconds to test 100 semiconductor packages.

However, when the second test is performed on 100 semiconductor packages instead of one, only about 2000 seconds are required to test 100 semiconductor packages.

That is, since the second test, which requires a lot of time, is simultaneously performed on a plurality of semiconductor packages, the package test productivity can be improved.

In FIG. 5 , the second inspection stage 350 is illustrated as one, but is not limited thereto.

If there are two second inspection stages, the first test is performed on the other inspection stage while the second test on the second semiconductor package group 101 rearranged on one inspection stage is in progress. The semiconductor package may be rearranged. Through this, the test efficiency of the semiconductor package may be improved.

7 is a schematic diagram for explaining semiconductor package test equipment used in a semiconductor package test method according to some embodiments of the present invention. For convenience of description, the description will focus on points different from those described with reference to FIGS. 1 to 6B.

Referring to FIG. 7 , the carrier 50 to which the first semiconductor package group 100 is attached may be loaded onto the first support table 370 .

One semiconductor package 110 of the first semiconductor package group 100 placed on the first support table 370 may be separated from the carrier 50 .

The separated semiconductor package 110 may be moved onto the first inspection stage 340 by the first transfer unit 330 .

In the semiconductor package test method described with reference to FIG. 7 , the first test may be performed while the first semiconductor package group 100 is separated from the carrier 50 .

Since the first test is performed after the first semiconductor package group 100 is separated from the carrier 50, defects that may occur during the process of separating the semiconductor package 110 may be detected through the first test. Also, a low or high temperature test may be performed.

In FIG. 7 , the first test is illustrated as being performed on one semiconductor package 110, but is not limited thereto.

After the plurality of semiconductor packages 110 are moved onto the first inspection stage 340 by the first transfer means 330, a first test may be performed on the rearranged plurality of semiconductor packages 110. . In this case, the first contactor module 315 described in FIG. 6A may include a plurality of first contactors 315p.

However, since the first test uses an inner outer terminal group (113_1 and 113_2 in FIGS. 3A and 3B) having a small pitch and a large number of inner and outer terminals, the first contactor 315p and the inner outer terminal group ( 113_1, 113_2) may be difficult to align. Accordingly, when the first test is performed on a plurality of semiconductor packages 110 , the first test may be simultaneously performed on two to four semiconductor packages 110 .

8 is a schematic diagram for explaining semiconductor package test equipment used in a semiconductor package test method according to some embodiments of the present invention. 9A and 9B are diagrams for explaining a hybrid contactor module included in the semiconductor package test equipment of FIG. 8 . For convenience of description, the description will focus on points different from those described with reference to FIG. 7 .

Referring to FIGS. 8 to 9B , the first semiconductor package test equipment 300 may include a hybrid contactor module 316 and a hybrid tester 311 .

The hybrid contactor module 316 may be connected to the hybrid tester 311 .

The hybrid contactor module 316 may include a first contactor 315p used for a first test and a second contactor 325p used for a second test.

In the hybrid contactor module 316, the first contactor 315p and the second contactor 325p may be located in the package test area 110ta.

The first contactor 315p of the hybrid contactor module 316 may be used for the first test.

The second contactor 325p of the hybrid contactor module 316 may be used for the second test.

The hybrid tester 311 may simultaneously perform a first test and a second test on the semiconductor package 110 . The hybrid tester 311 may include a first tester performing a first test and a second tester performing a second test.

Meanwhile, the hybrid tester 311 may perform only the first test of the semiconductor package 110 or the second test of the semiconductor package as needed.

One semiconductor package 110 of the first semiconductor package group 100 placed on the first support table 370 may be separated from the carrier 50 . The separated semiconductor package 110 may be moved onto the first inspection stage 341 by the first transfer unit 330 .

The inner and outer terminal groups included in the semiconductor package 110 on the first inspection stage 341 are brought into contact with the first contactor 315p and the second contactor 325p to perform the first test and the second contactor 325p. 2 tests can be performed simultaneously.

FIG. 9A shows a hybrid contactor module 316 including one first contactor 315p and one second contactor 325p, and FIG. 9B shows a plurality of first contactors 315p and a plurality of second contactors 315p. A hybrid contactor module 316 including a rotor 325p is shown.

10 is a schematic diagram for explaining semiconductor package test equipment used in a first test among semiconductor package test methods according to some embodiments of the present disclosure. FIG. 11 is a schematic layout diagram of FIG. 10 . 12 is a schematic diagram for explaining semiconductor package test equipment used in a second test among semiconductor package test methods according to some embodiments of the present disclosure. FIG. 13 is a schematic layout diagram of FIG. 12 .

10 and 11 , the second semiconductor package test equipment 400 includes a first tester 310, a first contactor module 315, a third inspection stage 440, and a first discharge tray. (460).

The third inspection stage 440 may be a location where the semiconductor package 110 to be subjected to the first test is located.

The first discharge tray 460 may be an area to classify and contain the first semiconductor package group 100 in which the first test is performed.

12 and 13 , the third semiconductor package test equipment 500 includes a second tester 320, a fourth inspection stage 540, a fifth inspection stage 545, and a first loading tray ( 550), a second loading tray 555, a second discharge tray 560, and a third discharge tray 565.

The third semiconductor package test equipment 500 may include a first loading region 501 , a second loading region 502 , and a test region. The first loading area 501 may include a fourth inspection stage 540 , a first loading tray 550 , and a second discharge tray 560 . The second loading area 502 may include a fifth inspection stage 545 , a first loading tray 550 , and a second discharge tray 560 . The test area may include the second tester 320 .

The first loading tray 550 and the second loading tray 555 are either the first discharge tray 460 ejected from the second semiconductor package test equipment 400, or semiconductors contained in the first discharge tray 460. It may be an area accommodating packages.

10 and 11 , one semiconductor package 110 of the first semiconductor package group 100 placed on the second support table 450 may be separated from the carrier 50 . The separated semiconductor package 110 may be moved onto the third inspection stage 440 by the third transfer unit 430 .

A first test may be performed on the semiconductor package 110 placed on the third inspection stage 440 . According to the first test result, the semiconductor package 110 placed on the third inspection stage 440 may be moved to the first discharge tray 460 and classified.

Among the plurality of semiconductor packages 110 included in the first semiconductor package group 100 , semiconductor packages that are judged to be good products in the first test may be placed in some of the first discharge trays 460 .

That is, at least some of the plurality of semiconductor packages 110 put into the second semiconductor package test equipment 400 may be determined to be good products, and the semiconductor packages 110 determined to be good products are removed through the first discharge tray 460. 2 It may be tray-out from the semiconductor package test equipment 400 .

For convenience of description, the first semiconductor package 110_1 and the second semiconductor package 110_2 will be described as being judged to be good products in the first test.

Referring to FIGS. 12 and 13 , the semiconductor package 110 discharged from the second semiconductor package test equipment 400 through the first discharge tray 460 after being judged as a good product may be contained in the first loading tray 550 . there is.

The first loading tray 550 may contain the first semiconductor package 110_1 and the second semiconductor package 110_2.

The plurality of semiconductor packages 110 contained in the first loading tray 550 may be rearranged on the fourth inspection stage 540 by using the fourth moving unit 530 . Through this, the second semiconductor package group 101 may be provided on the fourth inspection stage 540 .

The second semiconductor package group 101 provided on the second inspection stage 350 may be moved below the second contactor module 325 in the test area by the fifth moving unit 570 . Subsequently, a second test may be performed on the semiconductor packages 110 included in the second semiconductor package group 101 .

While the second test of the second semiconductor package group 101 is being performed, the third semiconductor package group 102 may be provided on the fifth inspection stage 545 in the second loading region 502 . .

More specifically, the semiconductor package 110 discharged from the second semiconductor package test equipment 400 through the first discharge tray 460 after being judged as a good product may be contained in the second loading tray 555 .

The plurality of semiconductor packages 110 contained in the second loading tray 555 may be rearranged on the fifth inspection stage 545 by using the fourth moving means 530 . Through this, the third semiconductor package group 102 may be provided on the fifth inspection stage 545 .

The second semiconductor package group 101 on which the second test has been performed may be classified and contained in the second discharge tray 560 .

Similarly, the third semiconductor package group 102 on which the second test has been performed may be classified and contained in the third discharge tray 565 .

In the semiconductor package test method according to some embodiments of the present invention described with reference to FIGS. 10 to 13 , the first test is performed in the second semiconductor package test equipment 400 , and the second test is performed in the second semiconductor package test equipment 400 . It may be performed in the third semiconductor package test equipment 500 using the semiconductor package 110 discharged from the package test equipment 400 .

14 is a schematic layout diagram of semiconductor package test equipment used for a second test among semiconductor package test methods according to some embodiments of the present invention. For convenience of description, the description will focus on differences from those described with reference to FIGS. 10 to 13 .

Referring to FIG. 14 , the third semiconductor package test equipment 500 includes a second tester 320, a fourth inspection stage 540, a first loading tray 550, and a second discharge tray 560. can include

That is, the third semiconductor package test equipment 500 may include a test area including one loading area 501 and the second tester 320 .

15 is a schematic layout diagram of semiconductor package test equipment used for a second test among semiconductor package test methods according to some embodiments of the present invention. For convenience of description, the description will focus on differences from those described with reference to FIGS. 12 and 13 .

Referring to FIG. 15 , the carrier 50 to which the first semiconductor package group 100 is attached may be loaded onto the third support table 580 .

Each of the plurality of semiconductor packages 110 placed on the third support table 580 may be separated from the carrier 50 and sequentially moved onto the fourth inspection stage 540 .

The semiconductor package 110 moved onto the fourth inspection stage 540 may be rearranged on the fourth inspection stage 540 . For example, the first semiconductor package 110_1 and the second semiconductor package 110_2 may be rearranged on the fourth inspection stage 540 .

Through this, the second semiconductor package group 102 may be provided on the fourth inspection stage 540 .

A second test may be performed on the second semiconductor package group 102 provided on the fourth inspection stage 540 .

The semiconductor package test method described with reference to FIG. 15 may be a case in which only the second test is performed without performing the first test.

Since the second test is performed after the first semiconductor package group 100 is separated from the carrier 50, defects that may occur in the process of separating the semiconductor package 110 may be detected through the second test. .

16 is a schematic diagram for describing a socket that may be used for a second test among semiconductor package test methods according to some embodiments of the present disclosure.

Referring to FIG. 16 , each of the plurality of semiconductor packages 110 may be accommodated in the package seating portions 60s of the socket 60 .

A second test may be performed using a socket including a plurality of semiconductor packages 110 .

In the semiconductor package described with reference to FIG. 16, the outer external terminal groups (114_1 and 114_2 in FIGS. 3A and 3B) are arranged at a second pitch P2 large enough to allow the second test to be performed using a socket. There may be.

Also, the second test performed using the socket may include a configuration different from the semiconductor package test equipment described with reference to FIGS. 1 to 15 .

Although the embodiments of the present invention have been described with reference to the accompanying drawings, those skilled in the art can realize that the present invention can be implemented in other specific forms without changing the technical spirit or essential features. you will be able to understand Therefore, the embodiments described above should be understood as illustrative in all respects and not limiting.

100, 101, 102: semiconductor package group 110: semiconductor package
113_1, 113_2: micro bump group 114_1, 114_2: pad group
310, 320: tester 315, 325: contactor module
315p, 325p: contactors 300, 400, 500: test equipment

Claims (20)

A first semiconductor package including a first semiconductor chip is provided, wherein the first semiconductor chip includes first external terminal groups arranged at a first pitch and second external terminals arranged at a second pitch greater than the first pitch. The group is placed on one side,
A first test is performed on the first semiconductor package by contacting the first external terminal group and a first contactor;
and performing a second test on the first semiconductor package by contacting the second external terminal group and a second contactor,
The first test is performed using the first contactor including probes corresponding to the first external terminal group arranged at the first pitch,
The second test is performed for a longer time than the first test using the second contactor including probes corresponding to the second external terminal group arranged at the second pitch,
Another semiconductor package in which the first test is performed is provided while the second test is performed on the first semiconductor package. According to claim 1,
A second semiconductor package including a second semiconductor chip having a third external terminal group arranged with the first pitch and a fourth external terminal group arranged with the second pitch disposed on one surface,
performing the first test on the second semiconductor package by contacting the third external terminal group and a first contactor;
further comprising performing the second test on the second semiconductor package by contacting the fourth external terminal group and a second contactor;
The second test of the second semiconductor package is performed simultaneously with the second test of the first semiconductor package. According to claim 2,
The first test of the second semiconductor package and the first test of the first semiconductor package are not performed simultaneously. According to claim 2,
The semiconductor package inspection method of claim 1 , wherein the first semiconductor chip and the second semiconductor chip are separated from each other. According to claim 2,
and rearranging the first semiconductor package and the second semiconductor package on an inspection stage before performing the second test. According to claim 1,
The first test and the second test are performed using one semiconductor package inspection equipment,
The semiconductor package inspection apparatus includes a first test area where the first contactor is disposed and a second test area where the second contactor is disposed. According to claim 1,
The first test is performed in a first semiconductor package inspection equipment,
The second test is performed in a second semiconductor package inspection equipment using the first semiconductor package discharged from the first semiconductor package inspection equipment. According to claim 1,
The first external terminal group includes a micro bump array,
The first test is performed through contact between the first contactor and the micro bump array. According to claim 1,
The second external terminal group includes a pad array,
The second test of the first semiconductor package is performed through contact between the second contactor and the pad array. According to claim 1,
The first test is performed without a socket accommodating the first semiconductor package. Provide a plurality of semiconductor packages separated from each other and attached to a carrier, each semiconductor package including a micro bump group and a first semiconductor chip having a pad group disposed on one surface,
A first test is performed on each semiconductor package by contacting a first contactor with a micro bump group included in each semiconductor package;
After performing the first test, at least some of the plurality of semiconductor packages are rearranged on a first inspection stage to provide a first semiconductor package group;
Simultaneously performing a second test on each semiconductor package included in the first semiconductor package group by contacting the pad group and the second contactor of each semiconductor package included in the first semiconductor package group including,
The first test is performed using the first contactor including probes corresponding to the micro bump groups arranged in a first pitch,
The second test is performed for a longer time than the first test using the second contactor including probes corresponding to the pad groups arranged at a second pitch greater than the first pitch,
The semiconductor package inspection method of claim 1 , wherein another semiconductor package group in which the first test is performed is provided while the second test is performed on the first semiconductor package group. delete According to claim 11,
The first test and the second test are performed using one semiconductor package inspection device,
The semiconductor package inspection apparatus includes a first test area where the first contactor is disposed and a second test area where the second contactor is disposed. According to claim 11,
The first test is performed in a state in which each of the semiconductor packages is attached to the carrier. According to claim 11,
The first test is performed using a first semiconductor package test equipment, and the second test is performed using a second semiconductor package test equipment including the first test stage. According to claim 15,
Providing the first semiconductor package group
Discharging at least some of the plurality of semiconductor packages from the first semiconductor package inspection equipment through a tray;
and rearranging the semiconductor packages discharged through the tray on the first inspection stage. According to claim 16,
The second semiconductor package inspection equipment includes a test area and a loading area,
The semiconductor packages discharged through the tray are rearranged on the first inspection stage in the loading area;
In the test region, the second test is performed. According to claim 11,
The first test and the second test are performed without a socket accommodating each of the semiconductor packages. According to claim 11,
Wherein the first test is performed without a socket accommodating the semiconductor package, and the second test is performed using a socket accommodating the semiconductor package. A first semiconductor package including a first semiconductor chip is provided, wherein the first semiconductor chip includes a first micro bump group arranged at a first pitch and a first pad group arranged at a second pitch greater than the first pitch. Arranged on this one side,
A second semiconductor package including a second semiconductor chip is provided, wherein a second micro bump group arranged in the first pitch and a second pad group arranged in the second pitch are disposed on one surface of the second semiconductor chip. become,
rearranging the first semiconductor package and the second semiconductor package on an inspection stage;
simultaneously performing a first test on the first semiconductor package and the second semiconductor package by bringing the first pad group and the second pad group into contact with a first contactor;
The first test is performed using the first contactor including a probe corresponding to the second pad group,
The second test is performed for a shorter time than the first test using a second contactor including a probe corresponding to the first micro bump group,
A semiconductor package test method comprising: providing a third semiconductor package in which the second test is performed while the first test is performed on the first semiconductor package.

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