KR102477775B1 - Garbage collection device having subunit and memory system having the same - Google Patents

Abstract

A garbage collection device according to an embodiment of the present invention copies a first object based on a first response signal received from a memory device or generates a search value indicating whether the first object is referenced by a second object. If the copy search unit configured to output to the host determines that the first object is referenced by the second object, the host converts a bit count value including size information of the first object based on the second response signal received from the memory device to the host and a scan push unit configured to update metadata of the first object or push the first object to the stack memory based on the third response signal received from the memory device. .

Description

Garbage collection device having a subunit and a memory system including the same

The present invention relates to a garbage collection device and a memory system including the same, and more particularly, to a garbage collection device having sub units and a memory system including the same.

Since the storage capacity of the memory device is finite, objects allocated to the memory device must be reclaimed for allocation of other objects when use is completed. One of the techniques for managing memory is garbage collection (GC). Garbage collection is a technique that automatically detects and releases unused space among dynamically allocated memory spaces. Errors such as memory leaks and dangling pointers can be suppressed by garbage collection.

In general, garbage collection can be performed in software on a central processing unit (CPU). However, as the size of data input/output from a memory device has rapidly increased recently, overhead due to garbage collection on a CPU is increasing. Due to this overhead, there is a problem in that the throughput of the application is lowered and the latency is increased.

An object of the present invention is to provide a garbage collection device having a sub-unit for reducing overhead caused by garbage collection and a memory system including the same.

A garbage collection device according to an embodiment of the present invention copies a first object based on a first response signal received from a memory device, or a search value indicating whether the first object is referenced by a second object A copy search unit configured to output to a host, when it is determined that the first object is referenced by the second object, including size information of the first object based on a second response signal received from the memory device. Based on a bitmap count unit configured to output a bit count value to the host and a third response signal received from the memory device, update metadata of the first object or store the first object in a stack memory and a scan push unit configured to push.

In an exemplary embodiment, the memory device is configured to generate the first response signal in response to a first request signal, the copy search unit receives a first command from the host, and based on the first command A first request generator configured to output the first request signal to the memory device, a copy search module configured to generate a copy information signal or a search information signal based on the first response signal, based on the copy information signal, an address calculator configured to output an address corresponding to the copied first object to the memory device, determine whether the first object is referenced by the second object, and provide a first return signal including the search value and an object discriminator configured to output to the host.

In an exemplary embodiment, the memory device is configured to generate the second response signal in response to a second request signal, and if it is determined that the first object is referenced by the second object, the bitmap count unit a second request generator configured to receive a second command from the host and output the second request signal to the memory device based on the second command; A begin map module configured to generate a first count value corresponding to a begin map including a location where an object starts, and a location where the first object ends in the memory device based on the second response signal an end map module configured to generate a second count value corresponding to an end map corresponding to an end map, a subtractor configured to generate a third count value obtained by subtracting the second count value from the first count value, and the first count value Restoring the bitmap of the first object by adding the third count value to the count value, generating the bit count value by counting the number of bits having a specific value in the bitmap, and including the bit count value and a counter circuit configured to output a second return signal to the host.

In an exemplary embodiment, the memory device is configured to generate the third response signal in response to a third request signal, the scan push unit receives a third command from the host, and based on the third command A third request generator configured to output the third request signal to the memory device, a first case in which the first object is marked based on the third response signal, the first object not marked and the first object A type discriminator configured to determine one of a second case in which is included in the young generation and a third case in which the first object is not marked and the first object is included in the old generation; If it is determined as the first case, a metadata updater configured to update the metadata of the first object, and if it is determined as the second case or the third case, a push configured to push the first object to the stack memory. a stack module, and an object marker configured to mark the first object when it is determined as the third case.

In an exemplary embodiment, a host interface circuit connected to the host, the copy search unit, the bitmap count unit, and the scan push unit, and the memory device, the copy search unit, the bitmap count unit, and the scan push unit. A memory interface circuit coupled with the push unit is further included.

In an exemplary embodiment, the host interface circuitry is configured to receive at least one of first to third commands from the host, receive the first command from the main command queue, and send the copy search unit to the a first command queue configured to output a first command, a second command queue configured to receive the second command from the main command queue and output the second command to the bitmap count unit, Receive a third command queue configured to receive a third command and output the third command to the scan push unit, and receive a return value from at least one of the copy search unit, the bitmap count unit, and the scan push unit and a return queue configured to output the return value to the host.

In an exemplary embodiment, the memory interface circuit may include a metadata cache connected to at least one of the copy search unit, the bitmap count unit, and the scan push unit and configured to store the metadata of the first object; a bitmap cache connected to at least one of the bitmap count unit and the scan push unit and configured to store a bitmap corresponding to a memory space including the first object; and the metadata cache, the bitmap cache, and a translation lookaside buffer connected to the memory device.

A memory system according to an embodiment of the present invention includes a host configured to generate first to third commands, first to third response signals corresponding to the first to third commands, and first to third commands. A memory device having a memory space including two objects, and a memory controller including a garbage collection device, wherein the garbage collection device copies the first object based on the first response signal or a copy search unit configured to output to the host a search value indicating whether one object is referenced by the second object, if it is determined that the first object is referenced by the second object, based on the second response signal a bitmap count unit configured to output a bit count value including size information of the first object to the host, and updating metadata of the first object based on the third response signal; and a scan push unit configured to push the first object to the stack memory.

In an exemplary embodiment, the garbage collection device is formed on a logic layer, the memory device includes a first hybrid memory cube (HMC), and the first HMC is stacked on the logic layer in a first direction. It includes at least one first dynamic random access memory (DRAM) layer.

In an exemplary embodiment, the memory device further includes second to fourth HMCs, the host is spaced apart from the logic layer in a second direction perpendicular to the first direction, and the second HMC comprises the logic layer. The third HMC is spaced apart from the logic layer in a third direction perpendicular to a plane defined by the first and second directions, the third HMC is spaced apart from the logic layer in a direction opposite to the second direction, and the fourth HMC is It is spaced apart from the logic layer in a direction opposite to the third direction.

According to an embodiment of the present invention, a garbage collection device having a subunit for reducing overhead due to garbage collection and a memory system including the same are provided.

In addition, according to an embodiment of the present invention, a garbage collection device compatible with an object-oriented language (eg, Java), having an algorithm optimized for counting the size of objects, and implemented in a three-dimensional memory, including the same A memory system is provided.

1 is a block diagram showing a memory system according to an exemplary embodiment of the inventive concept.
2A is a diagram illustrating garbage collection according to an embodiment of the present invention.
FIG. 2B is a diagram illustrating the memory spaces of FIG. 2A by way of example.
3 is a block diagram showing a garbage collection apparatus according to an embodiment of the present invention by way of example.
FIG. 4 is an illustrative embodiment of the host interface circuit of FIG. 3 .
FIG. 5 is a block diagram exemplarily embodying the copy search unit of FIG. 3 .
FIG. 6A is a block diagram illustratively embodying the bitmap count unit of FIG. 3 .
FIG. 6B is a diagram illustrating a method of calculating the bit count value of FIG. 6A by way of example.
FIG. 7 is a block diagram exemplarily embodying the scan push unit of FIG. 3 .
FIG. 8 is a block diagram exemplarily embodying the memory interface circuit of FIG. 3 .
9 is a diagram showing a memory system having a 3D structure according to an exemplary embodiment of the present invention.
10 is a flowchart illustrating a method of performing minor garbage collection according to an exemplary embodiment of the present invention.
11 is a flowchart illustrating a method of performing major garbage collection according to an exemplary embodiment of the present invention.

Hereinafter, embodiments of the present invention will be described clearly and in detail to the extent that those skilled in the art can easily practice the present invention. Hereinafter, for convenience of description, similar components are represented using the same or similar reference numerals.

Modules in the following drawings or detailed description may be connected with other components other than those shown in the drawings or described in the detailed description. Connections between modules or components may be direct or non-direct, respectively. The connection between the modules or components may be a communication connection or a physical connection, respectively.

1 is a block diagram showing a memory system 10 according to an exemplary embodiment of the inventive concept. Referring to FIG. 1 , a memory system 10 may include a host 11 , a memory controller 12 , and a memory device 13 .

The host 11 may be connected to the memory controller 12 . The host 11 may output a command for controlling the operation of the memory controller 12 . The host 11 may receive data, a return value corresponding to a command, and the like from the memory controller 12 . For example, the host 11 may be a processor such as a central processing unit (CPU), a graphics processing unit (GPU), a digital signal processor (DSP), or the like.

The memory controller 12 may be connected to the host 11 and the memory device 13 . The memory controller 12 may process data stored in the memory device 13 based on a command received from the host 11 . For example, the memory controller 12 may read data stored in the memory device 13 or write data to the memory device 13 based on a command from the host 11 .

In an example embodiment, the memory controller 12 may include the garbage collection device 100 . The garbage collection device 100 may be a device that performs garbage collection (GC) or assists garbage collection performed by the host 11 . Garbage collection may be an operation of automatically detecting and freeing a space that is no longer used among dynamically allocated memory spaces. Errors such as memory leaks and dangling pointers can be suppressed by garbage collection. Garbage collection will be described later in more detail with reference to FIG. 2A. A more detailed description of the garbage collection apparatus 100 will be described later along with FIG. 3 .

The memory device 13 may be connected to the memory controller 12 . The memory device 13 may store data received from the memory controller 12 or output the stored data to the memory controller 12 . That is, the memory device 13 may be a device that stores data.

In an exemplary embodiment, the memory device 13 may be a volatile memory. For example, the memory device 13 may be Dynamic Random Access Memory (DRAM). Allocation and release of memory space for data in the memory device 13 may occur frequently. Memory management such as garbage collection may be required in the memory device 13 .

In an exemplary embodiment, the memory device 13 may be implemented based on a 3D stacking technique. For example, the memory device 13 may include a plurality of DRAM layers for storing data. A more detailed description of the memory device 13 implemented based on the 3D stacking technique will be described later along with FIG. 9 .

2A is a diagram illustrating garbage collection according to an embodiment of the present invention. Referring to FIGS. 1 and 2A , garbage collection performed in the memory system 10 is described as an example. Garbage collection may be an operation of automatically detecting and freeing a space that is no longer used among dynamically allocated memory spaces. A memory space may be referred to as an object. Whether memory space is used can be determined based on whether an object is referenced by another object. The object may include data to be stored in the memory device 13 of FIG. 1 .

According to an embodiment of the present invention, the memory system 10 may manage a memory space based on an object-oriented language. For example, unlike programming languages such as C and C++ languages in which users directly allocate and deallocate objects, objects are automatically managed in languages such as Java, Python, C#, and scala. An object oriented language may be used.

A space in which data is to be stored in the memory device 13 may be expressed as a plurality of memory spaces. For example, the memory device 13 may include a root set and a heap space. Heap space can contain young generation and old generation. The Young Generation may include an Eden space, a survival-to-space, and a survival-from space. The Old Generation may contain tenured spaces. A root set may be a set of root objects existing outside the heap space. The root object can access objects that exist in heap space.

Live objects are shown in white, and dead objects are shown in shade. A solid line arrow between a pair of objects may mean a reference relationship. A dotted line arrow between a pair of objects may indicate movement of the object.

Keeping an object alive can mean that memory space is being used. A living object can be an object that is directly or indirectly referenced from the root set. When an object dies, it can mean that the memory space is no longer used. A dead object can be an object that is not referenced from the root set.

For example, an object may be allocated to a memory space as needed, but data corresponding to the object may no longer be needed according to an application operation thereafter. Even objects that are no longer needed can occupy memory space until the allocated space is freed. The garbage collection apparatus 100 can increase the utilization rate of memory space by releasing unnecessary memory space.

The garbage collection apparatus 100 may traverse objects from the root set. Traversing may refer to an operation of sequentially finding objects referenced from at least one of root objects included in a root set. For example, the garbage collection apparatus 100 may serially find objects OJ5 , OJ4 , OJ3 , OJ2 , and OJ1 from the root set. Objects referenced directly from the root set may exist in Eden space. For example, an object OJ5 that is directly referenced from the root set may exist in the Eden space.

The garbage collection apparatus 100 may copy living objects. Copying can be duplication of an object in memory space within the zero generation. For example, the garbage collection apparatus 100 may copy the object OJ5 included in the Eden space to the survival-to-space. Object OJ5 may be a live object referenced from the root set. The garbage collection apparatus 100 may copy the object OJ2 included in the survival-from space to the survival-to space. Object OJ2 may be a living object referenced by objects OJ3, OJ4, OJ5 and a root set.

In an exemplary embodiment, a survival-to-space and a survival-from space may be interchanged. For example, if another garbage collection after the garbage collection shown as copying in FIG. 2A is performed, a living object in the survival-to-space may be copied to the survival-from space.

The garbage collection apparatus 100 may promote a living object after undergoing garbage collection exceeding a reference number of times within zero generation. Promoting can mean moving from a memory space in the young generation to a memory space in the old generation. For example, the garbage collection apparatus 100 copies an object OJ1 that lives longer than the object OJ2 (that is, lives even after being subjected to garbage collection exceeding a reference number of times) to the survival-to-space, in the old generation. can be promoted to a tenured space in

The garbage collection apparatus 100 may compact live objects in the tenured space. Compaction can be moving a live object to be adjacent to another live object within the old generation space. Fragmentation of memory space can be reduced by compaction. For example, the object OJc may be promoted to the tenured space and then become a dead object. That is, within the tenured space, the object OJc may be unnecessary. The garbage collection apparatus 100 may move the living object OJd to be adjacent to another living object OJb. That is, the garbage collection apparatus 100 may compact live objects within the tenured space.

On the other hand, in order to avoid the complexity of the drawing, arrows representing the reference relationships of the objects OJa, OJb, and OJd in the tenured space are omitted, but the living objects OJa, OJb, and OJd in the tenured space are separated from the root set. Reference may be made either directly or indirectly. On the other hand, dead objects OJc in the tenured space may not be referenced by the root set. After the garbage collection apparatus 100 performs a compaction operation, the dead object OJc may be deallocated.

In an exemplary embodiment, the garbage collection apparatus 100 may perform minor garbage collection. For example, minor garbage collection may be copying living objects within the zero generation to the survival-to-space and deallocating remaining objects. A more detailed description of the minor garbage collection will be described later along with FIG. 10 .

In an exemplary embodiment, the garbage collection apparatus 100 may perform a major garbage collection. For example, major garbage collection can mark live objects and compact objects within the old generation. Major garbage collection takes longer than minor garbage collection. A more detailed description of major garbage collection will be described later along with FIG. 11 .

FIG. 2B is a diagram illustrating the memory spaces of FIG. 2A by way of example. Referring to FIG. 2B , the memory space in FIG. 2A is exemplarily specified. For example, the space shown in FIG. 2B may conceptually show at least a portion of the heap space. Meanwhile, at least one of the root objects included in the root set of FIG. 2A may refer to an object existing in a heap space (eg, Eden space).

The memory space shown in FIG. 2B may include a zero generation and an old generation. The Young Generation may include an Eden space and a survival space. The survival space may include a first survival space and a second survival space. For example, the first survival space may be the survival-from space of FIG. 2A, and the second survival space may be the survival-to-space of FIG. 2A.

In an exemplary embodiment, the survival-from space and the survival-to space may be interchanged according to the number of times garbage collection is performed. For example, in the first garbage collection, the first survival space may be a survival-from space, and the second survival space may be a survival-to-space. In the second garbage collection after the first garbage collection, the first survival space may be a survival-to-space, and the second survival space may be a survival-from space.

The Old Generation may contain tenured spaces. Objects in the tenured space may be living objects after garbage collection exceeding the standard number of times. Objects that die after being moved into tenured space can be deallocated by major garbage collection.

3 is a block diagram showing a garbage collection apparatus 100 according to an exemplary embodiment of the present invention. Referring to FIG. 3 , the garbage collection device 100 may be connected to a host and a memory device. For example, the garbage collection device 100 may be included in the memory controller 12 of the memory system 10 of FIG. 1 .

The garbage collection device 100 may include a host interface circuit 110 , a copy search unit 120 , a bitmap count unit 130 , a scan push unit 140 , and a memory interface circuit 150 . The garbage collection device 100 may perform garbage collection on objects of a memory device under control of a host.

The host interface circuit 110 may be connected to the host, the copy search unit 120 , the bitmap count unit 130 , and the scan push unit 140 . The host interface circuit 110 transmits the first command CMD1 to the copy search unit 120 and the second command CMD2 to the bitmap count unit 130 under the control of the host, and scan A third command CMD3 may be transmitted to the push unit 140 . The host interface circuit 110 may output a return value corresponding to at least one of the first to third commands CMD1 to CMD3 to the host.

The copy search unit 120 may be connected to the host interface circuit 110 and the memory interface circuit 150 . The copy search unit 120 may output the first request signal RQ1 to the memory interface circuit 150 based on the first command CMD1 received through the host interface circuit 110 . The copy search unit 120 may receive the first response signal RP1 corresponding to the first request signal RQ1 from the memory interface circuit 150 .

The copy search unit 120 may perform a copy operation or a search operation based on the first response signal RP1. The copy operation may be generating an address of a memory space to be newly allocated for an object. The search operation may determine whether an object is referenced by another object, and output a return value indicating whether or not the object is referenced to the host.

The bitmap count unit 130 may be connected to the host interface circuit 110 and the memory interface circuit 150 . The bitmap count unit 130 may output the second request signal RQ2 to the memory interface circuit 150 based on the second command CMD2 received through the host interface circuit 110 . The bitmap count unit 130 may receive the second response signal RP2 corresponding to the second request signal RQ2 from the memory interface circuit 150 .

The bitmap count unit 130 may perform a bitmap count operation based on the second response signal RP2. The bitmap may be data expressing a memory space in a bit type. For example, in the bitmap, in the heap space, a memory space corresponding to a live object is represented by a first value (eg, '1'), and a memory space corresponding to a dead object or an unallocated memory space is second. It may be data expressed as a value of 2 (eg '0').

The bitmap count operation may be to obtain size information of a living object in a memory space corresponding to the bitmap and output a bit count value including the size information of the living object to the host. For example, the bit count value may be data of an integer type indicating the sum of the sizes of all living objects in the heap space.

In an example embodiment, the bitmap count operation may be performed for major garbage collection. For example, a bit count value obtained based on a bitmap count operation may be used to move living objects to a new memory area in a compaction operation.

The scan push unit 140 may be connected to the host interface circuit 110 and the memory interface circuit 150 . The scan push unit 140 may output the third request signal RQ3 to the memory interface circuit 150 based on the third command CMD3 received through the host interface circuit 110 . The scan push unit 140 may receive the third response signal RP3 corresponding to the third request signal RQ3 from the memory interface circuit 150 .

The scan push unit 140 may perform a scan operation and then a push operation based on the third response signal RP3. The scan operation may be to check whether a field of an object is marked. For example, whether an object is marked may indicate whether it is referenced by other objects (ie, alive). Pushing may be storing an object in a stack memory. The stack memory may be a memory space in which local variables and parameters related to function calls are stored.

In an exemplary embodiment, when minor garbage collection is performed, the scan push unit 140 may check whether an object is marked by referring to a field of the object. Once an object has been marked, the object's metadata can be updated. If the object is unmarked, it can be pushed onto the stack memory.

In an exemplary embodiment, when major garbage collection is performed, the scan push unit 140 may check whether an object is marked by referring to a field of the object. Once an object has been marked, the object's metadata can be updated. If the object is unmarked, we can refer to the bitmap to mark the live object, and push the newly marked object onto the stack memory.

The memory interface circuit 150 may be connected to the memory device, the copy search unit 120 , the bitmap count unit 130 , and the scan push unit 140 . The memory interface circuit 150 may transmit the first request signal RQ1 from the copy search unit 120 to the memory device. The memory interface circuit 150 may transmit a first response signal RP1 corresponding to the first request signal RQ1 from the memory device to the copy search unit 120 .

The memory interface circuit 150 may transmit the second request signal RQ2 from the bitmap count unit 130 to the memory device. The memory interface circuit 150 may transmit the second response signal RP2 corresponding to the second request signal RQ2 from the memory device to the bitmap count unit 130 .

The memory interface circuit 150 may transmit the third request signal RQ3 from the scan push unit 140 to the memory device. The memory interface circuit 150 may transmit a third response signal RP3 corresponding to the third request signal RQ3 from the memory device to the scan push unit 140 .

FIG. 4 is an illustrative embodiment of the host interface circuit 110 of FIG. 3 . Referring to FIG. 4 , the host interface circuit 110 includes a main command queue 111, a first command queue 112a, a second command queue 112b, a third command queue 112c, and a return queue 113. can include

The main command queue 111 may receive at least one of the first to third commands CMD1 to CMD3 from the host. The main command queue 111 may be connected to the first to third command queues 112a to 112c.

The first command queue 112a may output the first command CMD1 received from the main command queue 111 to the copy search unit 120 . The second command queue 112b may output the second command CMD2 received from the main command queue 111 to the bitmap count unit 130 . The third command queue 112c may output the third command CMD3 received from the main command queue 111 to the scan push unit 140 .

The return queue 113 may be connected to a host. The return queue 113 may be connected to at least one of the copy search unit 120 , the bitmap count unit 130 , and the scan push unit 140 . The return queue 113 may receive a return value from at least one of the copy search unit 120, the bitmap count unit 130, and the scan push unit 140, and may output the return value to the host. For example, the return value may be a value indicating whether an object output from the copy search unit 120 is referenced by another object. For example, the return value may be a bit count value including size information of a living object in the memory space output from the bitmap count unit 130 .

FIG. 5 is a block diagram exemplarily embodying the copy search unit 120 of FIG. 3 . Referring to FIG. 5 , the copy search unit 120 may include a first request generator 121 , a copy search module 122 , an address calculator 123 , and an object determiner 124 .

The first request generator 121 may receive the first command CMD1 from the host through the first command queue 112a. The first request generator 121 may output the first request signal RQ1 to the memory interface circuit 150 based on the first command CMD1 . The memory interface circuit 150 may transmit the first request signal RQ1 to the memory device. The memory device may output the first response signal RP1 to the memory interface circuit 150 in response to the first request signal RQ1.

The copy search module 122 may receive the first response signal RP1 from the memory device through the memory interface circuit 150 . The copy search module 122 may generate a copy information signal CPI or a search information signal SRI based on the first response signal RP1. The copy information signal CPI may include an object starting address before copying, an object starting address after copying, and object size information. The search information signal SRI may include an address where a range to perform a search operation starts and an address where the range ends.

The address calculator 123 may receive the copy information signal CPI from the copy search module 122 . The address calculator 123 may generate an address ADDc corresponding to the copied object based on the copy information signal CPI. The address calculator 123 may output the address ADDc corresponding to the copied object to the memory device through the memory interface circuit 150 .

The object determiner 124 may receive the search information signal SRI from the copy search module 122 . The object determiner 124 determines whether the object is referenced by another object based on the search information signal SRI, and sends a first return signal RET1 including the search value to the host through the return queue 113. can be printed out.

In an exemplary embodiment, the search value may be boolean data indicating whether an object is referenced by another object. For example, if an object is referenced by another object, the search value may have a first value (eg, '1' or 'true'). For example, if the object is not referenced by another object, the search value may have a second value (eg '0' or 'false').

FIG. 6A is a block diagram of an exemplary embodiment of the bitmap count unit 130 of FIG. 3 . Referring to FIG. 6A , the bitmap count unit 130 may include a second request generator 131, a draw map module 132, an end map module 133, a subtractor 134, and a counter circuit 135. can

The second request generator 131 may receive the second command CMD2 from the host through the second command queue 112b. The second request generator 131 may output the second request signal RQ2 to the memory interface circuit 150 based on the second command CMD2 . The memory interface circuit 150 may transmit the second request signal RQ2 to the memory device. The memory device may output the second response signal RP2 to the memory interface circuit 150 in response to the second request signal RQ2.

In an exemplary embodiment, the second response signal RP2 may include a bitmap. The bitmap may be data representing living objects in a memory space (eg, heap space) as a first value and dead objects or an unallocated memory space as a second value. More specifically, the bitmap divides the memory space into '8' byte sub-memory spaces, represents the sub-memory space to which living objects are allocated as '1', and the remaining sub-memory spaces to which objects are not allocated. It may represent the memory space as '0'.

The match map module 132 may receive the second response signal RP2 from the memory interface circuit 150 . The tied map module 132 may generate a tied map based on the second response signal RP2. The drawn map may include a starting location of a living object in a memory space (eg, a heap space) of a memory device. The tied map module 132 may generate a first count value CTV1 corresponding to the tied map.

The end map module 133 may receive the second response signal RP2 from the memory interface circuit 150 . The end map module 133 may generate an end map based on the second response signal RP2. The end map may include a location where a living object ends in a memory space (eg, heap space) of a memory device. The end map module 133 may generate a second count value CTV2 corresponding to the end map.

The subtractor 134 may receive the first count value CTV1 from the tied map module 132 . The subtractor 134 may receive the second count value CTV2 from the end map module 133 . The subtractor 134 may generate a third count value CTV3 by subtracting the second count value CTV2 from the first count value CTV1.

The counter circuit 135 may receive the first count value CTV1 from the tied map module 132 . The counter circuit 135 may receive the third count value CTV3 from the subtractor 134 . The counter circuit 135 may include an adder and a bit counter. The adder may restore the bitmap by adding the third count value CTV3 to the first count value CTV1. The bit counter may generate a bit count value by counting the number of bits having a first value (eg '1') in the restored bitmap. The counter circuit 135 may output the second return signal RET2 including the bit count value to the host through the return queue 113 .

FIG. 6B is a diagram illustrating a method of calculating the bit count value of FIG. 6A by way of example. Referring to FIG. 6B , a bitmap, a drawn map, an end map, a first count value (CTV1), a third count value (CTV3), an added value, and a bit count value are sequentially shown.

The bitmap displays a sub-memory space to which live objects are allocated as a first value (eg '1), and a sub-memory space to which dead objects are allocated or a sub-memory space to which no objects are allocated as a second value. It may be expressed as a value (for example, '0'). The drawn map may include information on a starting location of a living object in the bitmap. The first count value CTV1 may be a value expressing a drawn map in a number type. The end map may include information on the location where the living object ends in the bitmap. The second count value CTV2 may be a value expressing an end map as a number type. The third count value CTV3 may be a value represented by a number type obtained by subtracting the second count value CTV2 from the first count value CTV1.

The added value may be a value obtained by adding the third count value CTV3 from the first count value CTV1 by the adder of the counter circuit 135 of FIG. 6A. The added value may include substantially the same information as the bitmap. The bit count value may be a value obtained by counting the number of bits having a first value (eg, '1') when the added value is expressed as a series of bits. For example, when the bitmap is the bitmap shown in FIG. 6B, the bit count value may be '9'. As described above, the bit count value may include size information of an object living in a memory space corresponding to a bitmap.

FIG. 7 is a block diagram exemplarily embodying the scan push unit 140 of FIG. 3 . Referring to FIG. 7 , the scan push unit 140 includes a third request generator 141, a type determiner 142, an object marker 143, a push stack module 144, and a metadata updater 145. can do.

The third request generator 141 may receive the third command CMD3 from the host through the third command queue 112c. The third request generator 141 may output the third request signal RQ3 to the memory interface circuit 150 based on the third command CMD3. The memory interface circuit 150 may transmit the third request signal RQ3 to the memory device. The memory device may output the third response signal RP3 to the memory interface circuit 150 in response to the third request signal RQ3.

In an exemplary embodiment, the memory interface circuit 150 may output an electrical signal including a bitmap. The memory interface circuit 150 may output an electrical signal for marking an object of a memory device.

The type determiner 142 may receive the third response signal RP3 from the memory device through the memory interface circuit 150 . The type determiner 142 may determine the first to third cases based on the third response signal RP3.

The first case may be a case in which an object is marked. When an object is marked, it may mean that the corresponding object is marked as being referenced by another object (ie, the corresponding object is alive). The second case may be a case in which the object is not marked and minor garbage collection is performed. For example, in the second case, the object may be included in the zero generation. A third case may be a case in which an object is not marked and major garbage collection is performed. For example, in the third case, the object may be included in the old generation.

The metadata updater 145 may update metadata of the object when the type discriminator 142 determines that the object corresponding to the third response signal RP3 corresponds to the first case. In an exemplary embodiment, the metadata updater 145 may output a signal requesting storage of updated metadata to the memory interface circuit 150 . After that, the memory device may store the updated metadata.

When the type discriminator 142 determines that the object corresponding to the third response signal RP3 corresponds to the second case or the third case, the push stack module 144 stores the corresponding object in the stack memory. can push In an exemplary embodiment, the push stack module 144 may output a signal requesting object push to the memory interface circuit 150 . After that, the corresponding object may be pushed to the stack memory of the memory device.

The object marker 143 may mark the object when the type discriminator 142 determines that the object corresponding to the third response signal RP3 corresponds to the third case. For example, the object marker 143 may receive a bitmap from the memory interface circuit 150 and output a control signal to mark a field of a corresponding object to the memory interface circuit 150 . Then, the object marker 143 may activate the push stack module 144 to push the object corresponding to the third case to the stack memory. Accordingly, the push stack module 144 may push the object to the stack memory.

In an exemplary embodiment, the scan and push unit 140 may sequentially and repeatedly perform scan and push operations until all live objects in the memory space are marked.

As described above, according to an embodiment of the present invention, the scan push unit 140 may operate differently according to the first to third cases. More specifically, in the first case, the scan push unit 140 may update metadata of the marked object. In the second case, the scan push unit 140 may push an unmarked object in the minor garbage collection to the stack memory. And, in the third case, the scan push unit 140 may mark an unmarked object in major garbage collection and then push a newly marked object to the stack memory.

FIG. 8 is a block diagram exemplarily embodying the memory interface circuit 150 of FIG. 3 . Referring to FIG. 8 , the memory interface circuit 150 may include a memory access interface 151 and a translation lookaside buffer (TLB) 152 . The memory access interface 151 may include a metadata cache 151a and a bitmap cache 151b.

The metadata cache 151a may be connected to at least one of the copy search unit 120 , the bitmap count unit 130 , and the scan push unit 140 . The metadata cache 151a may store object metadata. In an exemplary embodiment, the metadata cache 151a may store a unit ID (Identification) and metadata requested by the corresponding unit ID as one set. The unit ID may be a code for distinguishing the copy search unit 120 , the bitmap count unit 130 , and the scan push unit 140 . For example, ID1 may refer to the copy search unit 120 , ID2 may refer to the bitmap count unit 130 , and ID3 may refer to the scan push unit 140 .

The bitmap cache 151b may be connected to at least one of the bitmap count unit 130 and the scan push unit 140 . The bitmap cache 151b may store a bitmap corresponding to a memory space including an object. Instead of directly accessing the memory space of the memory device, the bitmap may be quickly referred to during a bitmap count operation by separately providing the bitmap cache 151b for storing the bitmap. Also, when the object marker 143 of the scan push unit 140 marks a living object, the bitmap can be referred to more quickly.

The conversion lookaside buffer 152 may be connected to the memory access interface 151 and the memory device. Translation lookaside buffer 152 may be a cache memory used to accelerate translations between virtual memory addresses and physical addresses.

9 is a diagram showing a memory system 10 having a 3D structure according to an exemplary embodiment of the present invention. Referring to FIG. 9 , the memory system 10 may include a host 11, a logic layer, and at least one hybrid memory cube (HMC). In an exemplary embodiment, the memory system 10 may be implemented using a 3D stacking technique.

For better understanding of the present invention, the memory system 10 is illustrated as including first to fourth hybrid memory cubes HMC1 to HMC4, but the scope of the present invention is not limited thereto, and the memory system 10 The number of hybrid memory cubes included in can be increased or decreased. Since the host 11 is similar to the host 11 of FIG. 1, a detailed description thereof is omitted.

In FIG. 9 , first to third directions D1 to D3 are defined. The first direction D1 may be a direction connecting the host 11 and the logic layer. The second direction D2 may be perpendicular to the first direction D1. The third direction D3 may be a direction perpendicular to a plane defined by the first and second directions D1 and D2. For example, a plane defined by the first direction D1 and the second direction D2 may be parallel to the semiconductor substrate. The third direction D3 may be a direction in which DRAM layers are stacked.

The logic layer may be spaced apart from the host 11 in a first direction. The logic layer may be electrically connected to the host 11 . The logic layer may be a layer in which a memory controller is formed. For example, the memory controller 12 of FIG. 1 may be formed on a logic layer.

In an exemplary embodiment, the garbage collection device 100 may be formed on a logic layer. Since the garbage collection device 100 is located in the logic layer, compared to a general technique of performing garbage collection in software, internal memory bandwidth can be used and delay time of memory access can be reduced.

The first hybrid memory cube HMC1 may be stacked on the logic layer in the third direction. The first hybrid memory cube HMC1 may be electrically connected to the logic layer. The first hybrid memory cube HMC1 may include N DRAM layers stacked in the third direction. In this case, N is any natural number. Each of the N DRAM layers may include a memory cell storing data.

The second hybrid memory cube HMC2 may be spaced apart from the logic layer in a direction opposite to the second direction. The second hybrid memory cube HMC2 may be electrically connected to the logic layer. Although not shown in FIG. 9 to avoid drawing complexity, the second hybrid memory cube HMC2 may include a plurality of DRAM layers similarly to the first hybrid memory cube HMC1.

The third hybrid memory cube HMC3 may be spaced apart from the logic layer in the first direction. The third hybrid memory cube HMC3 may be electrically connected to the logic layer. Although not shown in FIG. 9 to avoid drawing complexity, the third hybrid memory cube HMC3 may include a plurality of DRAM layers like the first hybrid memory cube HMC1.

The fourth hybrid memory cube HMC4 may be spaced apart from the logic layer in the second direction. The fourth hybrid memory cube HMC4 may be electrically connected to the logic layer. Although not shown in FIG. 9 to avoid drawing complexity, the fourth hybrid memory cube HMC4 may include a plurality of DRAM layers like the first hybrid memory cube HMC1.

In an exemplary embodiment, the first to fourth hybrid memory cubes HMC1 to HMC4 may be included in the memory device 13 of FIG. 1 . Each of the first to fourth hybrid memory cubes HMC1 to HMC4 may be a device for storing data.

10 is a flowchart illustrating a method of performing minor garbage collection according to an exemplary embodiment of the present invention. Referring to FIG. 10 , a method of performing minor garbage collection is illustrated as an example. Minor garbage collection may be performed by the garbage collection apparatus 100 of FIG. 3 .

In step S110, the garbage collection device may pop an object from the stack memory. In step S120, the garbage collection device may determine whether the object is marked. For example, the garbage collection device may determine whether a field of the popped object is marked in step S110. If it is determined that it is marked, step S110 may be performed again. If it is determined that it is not marked, it may move to step S130.

In step S130, the garbage collection device may mark the object as alive, and then copy the object or promote the object. When an object is alive, it can mean that the object is referenced by another object. Whether to copy the object or promote the object may be determined according to whether the number of garbage collections that the corresponding object has undergone exceeds the reference number.

That is, if an object has lived for a long time, it can be promoted to be moved to the old generation, and if an object has not lived long enough, it can be copied from the survival-from space to the survival-to-two space within the young generation.

In step S140, the garbage collection device may determine whether the object is referenced by another object, and may push the referenced object to the stack memory. In an exemplary embodiment, steps S110 to S140 may be repeated until all objects in the stack memory have been processed.

11 is a flowchart illustrating a method of performing major garbage collection according to an exemplary embodiment of the present invention. Referring to FIG. 11 , a method of performing major garbage collection is illustrated as an example. Major garbage collection may be performed by the garbage collection apparatus 100 of FIG. 3 . Since steps S210, S220, and S240 are similar to steps S110, S120, and S140 of FIG. 10, detailed descriptions thereof are omitted.

In step S230, the garbage collection device may mark the object as alive. Step S230 may be performed when it is determined in step S220 that the object is not marked. Unlike step S130 of FIG. 10 , an operation of copying an object or promoting an object may be omitted in step S230 .

In step S250, the garbage collection device may compact living objects in the old generation. Compaction can be the sequential and contiguous reallocation of living objects in memory space. Size information of live objects may be needed to reallocate memory space. The garbage collection device may perform a compaction operation based on a bit count value obtained through a bitmap count operation.

The foregoing are specific embodiments for carrying out the present invention. The present invention will include not only the above-described embodiments, but also embodiments that can be simply or easily changed in design. In addition, the present invention will also include techniques that can be easily modified and practiced using the embodiments. Therefore, the scope of the present invention should not be limited to the above-described embodiments and should not be defined by the following claims as well as those equivalent to the claims of this invention.

10: memory system
11: host
12: memory controller
13: memory device
100: garbage collection device
110 host interface circuit
120: copy search unit
130: bitmap count unit
140: scan push unit
150: memory interface circuit

Claims (10)

a copy search unit configured to copy a first object or output a search value indicating whether the first object is referenced by a second object to a host based on a first response signal received from the memory device;
If it is determined that the first object is referenced by the second object, output a bit count value including size information of the first object to the host based on a second response signal received from the memory device bitmap count unit; and
and a scan push unit configured to update metadata of the first object or push the first object to a stack memory based on a third response signal received from the memory device. According to claim 1,
The memory device is configured to generate the first response signal in response to a first request signal;
The copy search unit:
a first request generator configured to receive a first command from the host and output the first request signal to the memory device based on the first command;
a copy search module configured to generate a copy information signal or a search information signal based on the first response signal;
an address calculator configured to output an address corresponding to the copied first object to the memory device based on the copy information signal; and
and an object discriminator configured to determine whether the first object is referenced by the second object and output a first return signal including the search value to the host. According to claim 1,
the memory device is configured to generate the second response signal in response to a second request signal;
If it is determined that the first object is referenced by the second object, the bitmap count unit:
a second request generator configured to receive a second command from the host and output the second request signal to the memory device based on the second command;
a begin map module configured to generate a first count value corresponding to a begin map including a starting position of the first object in the memory device based on the second response signal;
an end map module configured to generate a second count value corresponding to an end map including an end position of the first object in the memory device based on the second response signal;
a subtractor configured to generate a third count value by subtracting the second count value from the first count value; and
Restoring the bitmap of the first object by adding the third count value to the first count value, counting the number of bits having a specific value in the bitmap to generate the bit count value, and generating the bit count value and a counter circuit configured to output a second return signal including a value to the host. According to claim 1,
The memory device is configured to generate the third response signal in response to a third request signal;
The scan push unit:
a third request generator configured to receive a third command from the host and output the third request signal to the memory device based on the third command;
Based on the third response signal, a first case in which the first object is marked, a second case in which the first object is not marked and the first object is included in a young generation, and the first a type determiner configured to determine one of third cases in which the object is not marked and the first object is included in an old generation;
a metadata updater configured to update the metadata of the first object when the first case is determined;
a push stack module configured to push the first object to the stack memory when the second case or the third case is determined; and
and an object marker configured to mark the first object when it is determined as the third case. According to claim 1,
a host interface circuit connected to the host, the copy search unit, the bitmap count unit, and the scan push unit; and
The garbage collection device further includes a memory interface circuit connected to the memory device, the copy search unit, the bitmap count unit, and the scan push unit. According to claim 5,
The host interface circuitry:
a main command queue configured to receive at least one of first to third commands from the host;
a first command queue configured to receive the first command from the main command queue and output the first command to the copy search unit;
a second command queue configured to receive the second command from the main command queue and output the second command to the bitmap count unit;
a third command queue configured to receive the third command from the main command queue and output the third command to the scan push unit; and
and a return queue configured to receive a return value from at least one of the copy search unit, the bitmap count unit, and the scan push unit, and to output the return value to the host. According to claim 5,
The memory interface circuit is:
a metadata cache connected to at least one of the copy search unit, the bitmap count unit, and the scan push unit and configured to store the metadata of the first object;
a bitmap cache connected to at least one of the bitmap count unit and the scan push unit and configured to store a bitmap corresponding to a memory space including the first object; and
A garbage collection device including a translation lookaside buffer connected to the metadata cache, the bitmap cache, and the memory device. a host configured to generate first to third commands;
a memory device configured to generate first to third response signals corresponding to the first to third commands and having a memory space including first and second objects; and
A memory controller comprising a garbage collection device;
The garbage collection device:
a copy search unit configured to copy the first object or output a search value indicating whether the first object is referred to by the second object to the host, based on the first response signal;
a bitmap count unit configured to output a bit count value including size information of the first object to the host, based on the second response signal, when it is determined that the first object is referenced by the second object; and
and a scan push unit configured to update metadata of the first object or push the first object to a stack memory based on the third response signal. According to claim 8,
The garbage collection device is formed on a logic layer,
The memory device includes a first hybrid memory cube (HMC), and the first HMC includes at least one first dynamic random access memory (DRAM) layer stacked on the logic layer in a first direction. . According to claim 9,
The memory device further includes second to fourth HMCs,
The host is spaced apart from the logic layer in a second direction perpendicular to the first direction,
The second HMC is spaced apart from the logic layer in a third direction perpendicular to a plane defined by the first and second directions;
The third HMC is spaced apart from the logic layer in a direction opposite to the second direction;
The fourth HMC is spaced apart from the logic layer in a direction opposite to the third direction.

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