KR102474575B1 - An image sensor, and an image processing system including the image sensor - Google Patents

Abstract

An image sensor according to the present invention includes a pixel array including a plurality of pixels generating pixel signals corresponding to a plurality of row lines; a row driver outputting a plurality of control signals for controlling operations of the plurality of pixels; a plurality of analog-to-digital converters for analog-to-digital conversion of pixel signals output from the plurality of pixels through a plurality of column lines to output digital pixel signals; and a timing generator generating line control signals for controlling output of pixel signals corresponding to the plurality of row lines.

Description

An image sensor, and an image processing system including the image sensor

Embodiments according to the concept of the present invention relate to an image sensor and an image processing system including the image sensor, and more particularly, an image sensor capable of improving performance of an image sensor operating in a rolling shutter method. , and an image processing system including the image sensor.

An image sensor is a device that converts an optical image into an electrical signal. The image sensor is used in a digital camera or other image processing device. The image sensor includes a plurality of pixels.

A mechanical shutter method and an electrical shutter method are largely used to adjust an exposure time that determines the amount of photocharge that is the basis of the electrical signal.

First, the mechanical shutter method is a method of physically blocking light incident to the pixels using a mechanical device.

Second, the electrical shutter method is mainly used in a CMOS image sensor (Complementary Metal-Oxide Semiconductor Image Sensor; CIS), and electrically controls an integration time at which the photocharges are generated and accumulated.

The electrical shutter method includes a rolling shutter method and a global shutter method. The rolling shutter method controls the accumulation time differently for each row of the pixel array, and the global shutter method controls the accumulation time equally for all rows of the pixel array.

At this time, since the rolling shutter method causes image distortion due to different accumulation times for each row, improvement is required.

A technical problem to be achieved by the present invention is to provide an image sensor capable of reducing image distortion caused by a rolling shutter method, and an image processing system including the image sensor.

An image sensor according to an embodiment of the present invention includes a pixel array including a plurality of pixels generating pixel signals corresponding to a plurality of row lines; a row driver outputting a plurality of control signals for controlling operations of the plurality of pixels; a plurality of analog-to-digital converters for analog-to-digital conversion of pixel signals output from the plurality of pixels through a plurality of column lines to output digital pixel signals; and a timing generator configured to generate a line control signal for controlling output of pixel signals corresponding to the plurality of row lines, wherein the timing generator generates signals from one row line or one or more row lines among the plurality of row lines. The line control signal is output to the row driver so that pixel signals according to a predetermined pixel unit are output in parallel.

According to an embodiment, each of the plurality of analog-to-digital converters may include a correlated double sampling (CDS) block performing correlated double sampling on pixel signals output from the plurality of pixels through the plurality of column lines; and a databus (DBS) block that converts each of the correlated double-sampled signals into digital pixel signals and outputs a plurality of digital pixel signals according to the conversion result, wherein the image sensor corresponds to the plurality of column lines. A channel conversion unit for converting the number of channels to be used is further included.

According to an embodiment, the image sensor stores the plurality of digital pixel signals output in parallel from the DBS block through the channels converted by the channel conversion unit in a frame memory, and stores the plurality of digital pixel signals stored therein. It further includes a frame controller that outputs sequentially.

According to an embodiment, the channel converting unit converts the number of N (N is an integer greater than 4) channels corresponding to the plurality of column lines to L (L is an integer smaller than N) channels corresponding to the input ports of the frame controller. convert to number

According to an embodiment, the frame controller receives the plurality of digital pixel signals output through the L channels, stores them in the frame memory, and converts the stored plurality of digital pixel signals to M (M is an integer less than or equal to L). ) through channels.

The timing generator may control the plurality of row lines to output the pixel signals from the pixel array at first time intervals, and the frame controller may output the stored digital pixel signals from the frame memory. Output at intervals of 2 points.

In some embodiments, the first viewpoint interval is shorter than the second viewpoint interval.

According to an embodiment, the frame controller may include a compression device configured to compress the plurality of digital pixel signals output from the DBS block and output the compressed digital pixel signals to the frame memory; and a decompression device decompressing and outputting signals stored in the frame memory.

According to an embodiment, the image sensor may further include an image correction block configured to perform correction on image data corresponding to the digital pixel signals output from the frame controller and output corrected image data. The analog-to-digital converter includes the N analog-to-digital converters, and the image correction block includes the M image correction circuits.

According to an embodiment, the frame memory is a volatile memory including static random access memory (SRAM) or dynamic random access memory (DRAM), and the frame controller manages a storage area of the frame memory.

According to an embodiment, the image sensor may include an encoder configured to encode the plurality of digital pixel signals output from the DBS block and output encoded data to the frame controller; and a decoder that decodes the encoded data transmitted from the frame controller and outputs decoded data.

According to an embodiment, the frame memory is implemented in a first chip, and the pixel array and the plurality of analog-to-digital converters are implemented in a second chip stacked on the first chip.

An image processing system according to an embodiment of the present invention includes an image sensor; and a digital signal processor controlling an operation of the image sensor, wherein the image sensor comprises: a pixel array including a plurality of pixels generating pixel signals corresponding to a plurality of row lines; a row driver outputting a plurality of control signals for controlling operations of the plurality of pixels; a plurality of analog-to-digital converters for analog-to-digital conversion of pixel signals output from the plurality of pixels through a plurality of column lines to output digital pixel signals; and a timing generator configured to generate a line control signal for controlling output of pixel signals corresponding to the plurality of row lines, wherein the timing generator generates signals from one row line or one or more row lines among the plurality of row lines. The line control signal is output to the row driver so that pixel signals according to a predetermined pixel unit are output in parallel.

According to an embodiment, each of the plurality of analog-to-digital converters may include a correlated double sampling (CDS) block performing correlated double sampling on pixel signals output from the plurality of pixels through the plurality of column lines; and a databus (DBS) block that converts each of the correlated double-sampled signals into digital pixel signals and outputs a plurality of digital pixel signals according to the conversion result, wherein the image sensor corresponds to the plurality of column lines. and a channel converter for converting the number of N (N is an integer greater than or equal to 4) channels to the number of L (L is an integer smaller than N) channels.

According to an embodiment, the image sensor sequentially stores the plurality of digital pixel signals output in parallel through the L channels from the DBS block through the channels converted by the channel conversion unit in a frame memory, and a frame controller sequentially outputting the stored plurality of digital pixel signals through M (M is an integer less than or equal to L) channels.

The timing generator may control the plurality of row lines to output the pixel signals from the pixel array at first time intervals, and the frame controller may output the stored digital pixel signals from the frame memory. It outputs at two viewpoint intervals, and the first viewpoint interval is shorter than the second viewpoint interval.

According to an embodiment, the frame controller may include a compression device configured to compress the plurality of digital pixel signals output from the DBS block and output the compressed digital pixel signals to the frame memory; and a decompression device decompressing and outputting signals stored in the frame memory.

According to an embodiment, the frame memory is implemented in a first chip, and the pixel array and the analog-to-digital converter are implemented in a second chip stacked on the first chip.

An image sensor according to an embodiment of the present invention includes a pixel array including a plurality of pixels generating pixel signals corresponding to a plurality of row lines; a plurality of analog-to-digital converters for analog-to-digital conversion of pixel signals output from the plurality of pixels through a plurality of column lines to output digital pixel signals; and generating a line control signal for controlling the plurality of row lines such that pixel signals according to predetermined pixel units are output in parallel from one row line or one or more row lines of the plurality of row lines to the plurality of analog-to-digital converters. It includes a timing generator that

According to an embodiment, the image sensor further includes an image correction block configured to perform correction on image data corresponding to the digital pixel signals output in parallel from the plurality of analog-to-digital converters and output corrected image data. The image correction block includes a plurality of image correction circuits corresponding to the plurality of analog-to-digital converters.

According to an image sensor according to an embodiment of the present invention and an image processing system including the image sensor, a rolling shutter effect can be reduced by reading out pixel signals at high speed.

In addition, according to the image sensor and the image processing system including the image sensor according to an embodiment of the present invention, power consumption can be reduced by performing frame rate conversion to reduce a rolling shutter effect.

1 shows a block diagram of an image processing system according to an embodiment of the present invention.
FIG. 2A is a conceptual diagram of an image sensor shown in FIG. 1 having a stack structure according to an embodiment of the present invention.
FIG. 2B is a conceptual diagram of an image sensor shown in FIG. 1 having a stack structure according to another embodiment of the present invention.
FIG. 2C is a conceptual diagram of an image sensor shown in FIG. 1 having a stack structure according to another embodiment of the present invention.
FIG. 2D is a conceptual diagram of an image sensor shown in FIG. 1 having a stack structure according to another embodiment of the present invention.
FIG. 3A is a diagram illustrating an embodiment of the image sensor shown in FIG. 1 .
FIG. 3B is a diagram illustrating another embodiment of the image sensor shown in FIG. 1 .
4 is a timing diagram for explaining an operation of an image sensor according to a comparative example of the present invention.
5 is a timing diagram for explaining an operation of an image sensor according to an embodiment of the present invention.
FIG. 6 is a diagram illustrating another embodiment of the image sensor shown in FIG. 1 .
FIG. 7 is a block diagram illustrating an embodiment of an electronic system including the image sensor shown in FIG. 1 .
FIG. 8 is a block diagram illustrating another embodiment of an electronic system including the image sensor shown in FIG. 1 .

Specific structural or functional descriptions of the embodiments according to the concept of the present invention disclosed in the present specification or application are only exemplified for the purpose of explaining the embodiment according to the concept of the present invention, and the implementation according to the concept of the present invention Examples may be embodied in many forms and should not be construed as limited to the embodiments described in this specification or application.

Embodiments according to the concept of the present invention may be applied with various changes and may have various forms, so specific embodiments are illustrated in the drawings and described in detail in the present specification or application. However, this is not intended to limit the embodiments according to the concept of the present invention to a specific disclosed form, and should be understood to include all modifications, equivalents, or substitutes included in the spirit and technical scope of the present invention.

Terms such as first and/or second may be used to describe various components, but the components should not be limited by the terms. The above terms are only for the purpose of distinguishing one component from another component, e.g., without departing from the scope of rights according to the concept of the present invention, a first component may be termed a second component, and similarly The second component may also be referred to as the first component.

It is understood that when an element is referred to as being "connected" or "connected" to another element, it may be directly connected or connected to the other element, but other elements may exist in the middle. It should be. On the other hand, when an element is referred to as “directly connected” or “directly connected” to another element, it should be understood that no other element exists in the middle. Other expressions describing the relationship between elements, such as "between" and "directly between" or "adjacent to" and "directly adjacent to", etc., should be interpreted similarly.

Terms used in this specification are only used to describe specific embodiments, and are not intended to limit the present invention. Singular expressions include plural expressions unless the context clearly dictates otherwise. In this specification, terms such as "comprise" or "having" are intended to designate that the described feature, number, step, operation, component, part, or combination thereof exists, but one or more other features or numbers However, it should be understood that it does not preclude the presence or addition of steps, operations, components, parts, or combinations thereof.

Unless defined otherwise, all terms used herein, including technical or scientific terms, have the same meaning as commonly understood by one of ordinary skill in the art to which the present invention belongs. Terms such as those defined in commonly used dictionaries should be interpreted as having a meaning consistent with the meaning in the context of the related art, and unless explicitly defined in this specification, it should not be interpreted in an ideal or excessively formal meaning. don't

Hereinafter, the present invention will be described in detail by describing preferred embodiments of the present invention with reference to the accompanying drawings.

1 shows a block diagram of an image processing system according to an embodiment of the present invention.

Referring to FIG. 1 , an image processing system 10 is a portable electronic device such as a digital camera, a mobile phone, a smart phone, a tablet personal computer (PC), a personal digital assistant (PDA), and an enterprise digital device (EDA). assistant, digital still camera, digital video camera, portable multimedia player (PMP), mobile internet device (MID) or wearable computer. have. Also, the image processing system 10 may be implemented as a front camera, a rear camera, or a black box camera of a vehicle.

The image processing system 10 includes an optical lens 103, a CMOS image sensor 100, a digital signal processor (DSP) 200, and a display 300. Each component 100 and 200 may be implemented as a chip.

The CMOS image sensor 100 may generate image data IDATA for the subject 101 input (or captured) through the optical lens 103 .

The CMOS image sensor 100 includes an active pixel (or active pixel sensor (APS)) block 110, a row driver 120, an analog-to-digital converter (ADC) block 130, and a channel Conversion unit 137, frame controller 140, frame memory 145, timing generator 150, ramp signal generator 160, image correction block 170, output interface 180 and control register block 190 can include

The active pixel block 110 includes a plurality of pixels generating pixel signals corresponding to a plurality of row lines. Active pixel block 110 may be referred to as a pixel array. Each of the plurality of pixels may accumulate photocharges generated according to incident light and generate a pixel signal corresponding to the accumulated photocharges.

The plurality of pixels may be arranged in a matrix form. Each of the plurality of pixels may include a photoelectric conversion element and a plurality of transistors for processing photocharges output from the photoelectric conversion element. Each of the plurality of pixels may output a corresponding pixel signal to a column line. For example, the photoelectric conversion element may be implemented as a photo diode, a photo transistor, a photogate, or a pinned photo diode.

The row driver 120 may transmit a plurality of control signals for controlling the operation of each of the plurality of pixels to the active pixel block 110 based on the line control signal LCS received from the timing generator 150. .

The analog-to-digital converter block 130 may include a correlated double sampling (CDS) block 133 and a databus (DBS) block 135 .

The CDS block 133 performs correlated double sampling on pixel signals output from each of a plurality of column lines included in the active pixel block 110 . The DBS block 135 converts each of the correlated double sampled pixel signals output from the CDS block 133 into a digital pixel signal and outputs a plurality of digital pixel signals generated according to the conversion result.

The channel conversion unit 137 may convert the number of channels corresponding to a plurality of column lines. Digital pixel signals output from the DBS block 135 may be output to the frame controller 140 through channels whose number of channels is converted.

The frame controller 140 includes a frame memory 145 and may manage a storage area of the frame memory 145 . The frame controller 140 may input data to the frame memory 145 or output data from the frame memory 145 .

For example, the frame controller 140 may control the frame memory 145 so that input data is not written only to a specific area of the frame memory 145 .

In this case, the frame memory 145 may be implemented as a volatile memory such as static random access memory (SRAM), but is not limited thereto. The frame memory 145 may be a volatile memory or a part of non-volatile memory. The volatile memory may be dynamic random access memory (DRAM), thyristor RAM (T-RAM), zero capacitor RAM (Z-RAM), or twin transistor RAM (TTRAM). The nonvolatile memory may be a flash memory, a magnetic RAM (MRAM), a phase change RAM (PRAM), or a resistive memory.

The frame controller 140 may sequentially store a plurality of digital pixel signals output from the DBS block 135 in the frame memory 145 and sequentially output the stored digital pixel signals.

A more detailed operation of the frame controller 140 will be described later with reference to FIGS. 3A and 5 .

The timing generator 150 controls operations of the row driver 120, the CDS block 133, the DBS block 135, and the ramp signal generator 160 under the control of the control register block 190. The control register block 190 controls operations of the timing generator 150, the ramp signal generator 160, and the output interface 180 under the control of the DSP 200.

The timing generator 150 may generate line control signals LCS for controlling output of pixel signals corresponding to a plurality of row lines.

According to an embodiment, the timing generator 150 transmits a line control signal (to the row driver 120 so that pixel signals according to a predetermined pixel unit are output in parallel from one row line or one or more row lines among a plurality of row lines). LCS) can be output.

The image correction block 170 may perform color tone correction, picture quality correction, or size adjustment on image data corresponding to a plurality of digital pixel signals output from the frame controller 140 and output corrected image data.

The output interface 180 transmits the image data IDATA output from the image correction block 170 to the DSP 200 .

The DSP 200 includes an image signal processor 210, a sensor controller 220, and an interface 230.

The image signal processor 210 controls the sensor controller 220 which controls the control register block 190 and the interface 230 . According to an embodiment, each of the image sensor 100 and the DSP 200 may be implemented as a chip, and may be implemented as a single package, for example, a multi-chip package. According to another embodiment, each of the image sensor 100 and the image signal processor 210 may be implemented as a chip and implemented as a single package, for example, a multi-chip package. According to another embodiment, the image sensor 100 and the image signal processor 210 may be implemented as a single chip.

The image signal processor 210 processes (or processes) the image data IDATA transmitted from the output interface 180 to make it look good to humans, and transmits the processed (or processed) image data to the interface 230 .

The sensor controller 220 generates various control signals for controlling the control register block 190 under the control of the image signal processor 210 .

The interface 230 transmits image data processed by the image signal processor 210 to the display 300 .

The display 300 displays image data output from the interface 230 . For example, the display 300 may be implemented as a thin film transistor-liquid crystal display (TFT-LCD), a light emitting diode (LED) display, an organic LED (OLED) display, or an active-matrix OLED (AMOLED) display.

2A is a conceptual diagram of an image sensor shown in FIG. 1 having a stack structure according to an embodiment of the present invention, and FIG. 2B is a conceptual diagram of an image sensor shown in FIG. 1 having a stack structure according to another embodiment of the present invention. 2C shows a conceptual diagram of the image sensor shown in FIG. 1 having a stack structure according to another embodiment of the present invention, and FIG. 2D shows a conceptual diagram of the image sensor shown in FIG. It shows a conceptual diagram of the image sensor shown in

Referring to FIGS. 1 to 2A , an image sensor 100 - 1 is an example of the image sensor 100 shown in FIG. 1 .

The image sensor 100-1 includes a first chip 50-1, a second chip 50-2 stacked on the first chip 50-1, and a first chip 50-1. It may include a plurality of signal transmission lines SL for transmitting pixel signals between the second chips 50-2.

The DBS block 135 and the frame memory 145 may be implemented (or formed) in the first chip 50-1. Each component 150, 160, 170, 180, and 190 may be implemented (or formed) in the first chip 50-1.

The active pixel block 110 and the CDS block 133 may be implemented (or formed) in the second chip 50 - 2 . The row driver 120 may be implemented (or formed) in the second chip 50-2.

The plurality of signal transmission lines SL may transmit signals output from the CDS block 133 to the DBS block 135.

Referring to FIGS. 1 to 2B , an image sensor 100 - 2 is another embodiment of the image sensor 100 shown in FIG. 1 .

The image sensor 100-2 includes a first chip 50-1, a second chip 50-2 stacked on the first chip 50-1, and the first chip 50-1 and the second chip. It may include a plurality of signal transmission lines SL for transmitting pixel signals between (50-2).

According to another embodiment, only the active pixel block 110 is implemented in the second chip 50-2, and the CDS block 133, the DBS block 135, and the frame memory 145 are implemented in the first chip 50-1. ) can be implemented. The plurality of signal transmission lines SL may transmit signals output from the active pixel block 110 to the CDS block 133 .

Referring to FIGS. 1 to 2C , an image sensor 100 - 3 is another embodiment of the image sensor 100 shown in FIG. 1 .

The image sensor 100-3 includes a first chip 50-1, a second chip 50-2 stacked on the first chip 50-1, and the first chip 50-1 and the second chip. It may include a plurality of first signal transmission lines SL1 and a plurality of second signal transmission lines SL2 for transmitting pixel signals between 50 - 2 .

According to another embodiment, the frame memory 145, the first DBS block 135-1 and the second DBS block 135-2 are implemented in the first chip 50-1, and the active pixel block 110 ), the first CDS block 133-1 and the second CDS block 133-2 may be implemented in the second chip 50-2.

The plurality of first signal transmission lines SL1 transmits the signals output from the first CDS block 133-1 to the first DBS block 135-1, and the plurality of second signal transmission lines SL2 may transmit signals output from the second CDS block 133-2 to the second DBS block 135-2.

Referring to FIGS. 1 to 2D , an image sensor 100 - 4 is another embodiment of the image sensor 100 shown in FIG. 1 .

In the image sensor 100-4 according to another embodiment, a first CDS block 133-1, a first DBS block 135-1, a frame memory 145, and a second DBS block 135-2 ) and the second CDS block 133-2 may be implemented in the first chip 50-1, and only the active pixel block 110 may be implemented in the second chip 50-2.

The plurality of first signal transmission lines SL1 transmits signals output from the active pixel block 110 to the first CDS block 133-1, and the plurality of second signal transmission lines SL2 transmits the signals output from the active pixel block 110 to the active pixel block 133-1. Signals output from the block 110 may be transmitted to the second CDS block 133-2.

In the case of the image sensors 100-3 and 100-4 shown in FIGS. 2C to 2D, under the control of the row driver 120, corresponding to the pixels included in the first area of the active pixel block 110 Pixel signals may be output to the first CDS block 133-1, and pixel signals corresponding to pixels included in the second area excluding the first area may be output to the second CDS block 133-2.

FIG. 3A is a diagram illustrating an embodiment of the image sensor shown in FIG. 1 . FIG. 3B is a diagram illustrating another embodiment of the image sensor shown in FIG. 1 . In FIGS. 3A and 3B , only some components of the image sensor 100 shown in FIG. 1 are described as examples.

1 to 3A, the CDS block 133 may include a plurality of CDS circuits (CDS 1 to CDS N), and the DBS block 135 may include a plurality of DBS circuits (Databus 1 to Databus N). can That is, the CDS block 133 and the DBS block 135 are configured to include a plurality of CDS circuits (CDS 1 to CDS N) and a plurality of DBS circuits (Databus 1 to Databus N) corresponding to each of the plurality of column lines. It can be.

One CDS circuit and DBS circuit may be an analog-to-digital converter, and a plurality of CDS circuits and a plurality of DBS circuits may be an analog-to-digital converter block 130 .

The image correction block 170 may include a plurality of image correction circuits (Image Correction 1 to Image Correction M).

Based on the line control signal LCS output from the timing generator 150, pixel signals according to a predetermined pixel unit are transmitted from one row line or more than one row line of the active pixel block 110 to the CDS block 133. can be output in parallel.

In this case, pixel signals according to a predetermined pixel unit may be values for pixels corresponding to one row line or one or more row lines. Pixel signals may be output in parallel to the CDS block 133 through N (N is an integer of 4 or more) channels corresponding to the plurality of column lines of the active pixel block 110 .

The CDS block 133 may perform correlated double sampling on pixel signals, and the DBS block 135 may convert the correlated double sampled signals into digital pixel signals and output the converted digital pixel signals.

The channel converter 137 may convert the number of N channels corresponding to the plurality of column lines into the number of channels corresponding to an input port of the frame controller 140 .

The channel converter 137 may output digital pixel signals received in predetermined pixel units through N channels to the frame controller 140 through grouped L (L is an integer smaller than N) channels CH_L. have. The channel conversion unit 137 may be implemented to include a plurality of multiplexers (not shown), but is not limited thereto.

The frame controller 140 may sequentially store digital pixel signals output from the channel converter 137 through the L channels CH_L in the frame memory 145 . The frame controller 140 may sequentially output the digital pixel signals stored in the frame memory 145 through M (M is an integer less than or equal to L) channels.

That is, the frame controller 140 may receive and store pixel signals in units of L pixels, and output pixel signals in units of M pixels.

At this time, the frame controller 140 compresses a plurality of digital pixel signals output from the channel converter 137 and compresses the signals stored in the frame memory 145 and a compression device (not shown) for outputting the compressed signals to the frame memory 145. It may further include a decompression device (not shown) for decompressing and outputting.

The image correction block 170 may perform correction on image data corresponding to digital pixel signals output in parallel from the frame controller 140 and output corrected image data.

To this end, as shown in FIG. 3A , the image correction block 170 may include M circuits.

That is, the output interface 180 outputs pixel signals in units of L pixels output from the active pixel block 110 through the N channels to the ISP 210 through the M channels.

According to another embodiment, the image sensor 100-1a may further include an encoder and a decoder, and an example of the image sensor 100-1b for this is shown in FIG. 3B.

Referring to FIG. 3B , the encoder 20 may encode digital pixel signals output from the channel converter 137 and output encoded data to the frame controller 140 .

The frame controller 140 may sequentially store encoded data in the frame memory 145 and sequentially output the stored encoded data.

The decoder 30 may perform decoding on the encoded data output from the frame controller 140 and output the decoded data to the image correction block 170 .

4 is a timing diagram for explaining an operation of an image sensor according to a comparative example of the present invention. 5 is a timing diagram for explaining an operation of an image sensor according to an embodiment of the present invention.

Referring to FIG. 4 , each of the lines Line 1 to Line n performs an operation in which pixel signals read out from the active pixel block 110 are output to the ISP 210 through the output interface 180. indicate

As the image sensor operates in a rolling shutter method, pixel signals corresponding to the respective lines (Line 1 to Line n) are sequentially read out at different points in time (t1 to tn) and converted into analog signals during a predetermined period (Tcout). - It is digitally converted and output.

That is, due to a temporal difference between the respective viewpoints t1 to tn, a rolling shutter effect may occur and distortion may occur in the output image.

On the other hand, referring to FIGS. 3A and 5 , each of the lines Line 1 to Line n provides pixel signals corresponding to one row line or predetermined pixels corresponding to one or more row lines in the active pixel block 110 . Indicates an operation output by the output interface 180 from

Taking the first line Line 1 as an example, a pixel corresponds to photocharges accumulated in the photodiodes included in the active pixel block 110 from the first time T1 to the time before the first period Tc. Signals are generated, and the generated pixel signals may be read out.

During the first period Tc, analog-to-digital conversion is performed on the pixel signals by the CDS block 133 and the DBS block 135, and the converted digital pixel signals are output to the frame controller 140. have.

At a second time point Tout1 after the second period Td, the frame controller 140 outputs a digital pixel signal, and the image correction block 170 corrects image data corresponding to the digital pixel signal to perform correction. image data can be output.

At this time, the second period Td is a period indicating the time from when the digital pixel signals are stored in the frame memory 145 to before they are output to the image correction block 170, and is read by the active pixel block 110. It may depend on the ratio between the out rate and the rate output by the output interface 180. That is, since the number of input ports and the number of output ports of the frame controller 140 are different, the second period Td may vary depending on the number of channels corresponding to the input port and the number of channels corresponding to the output port of the frame controller 140. can

The above operation may be repeatedly performed with respect to the second line (Line 2) to the n-th line (Line n).

For this operation, the timing generator 150 may output the line control signal LCS to the row driver 120 so that the pixel signals are read out from the active pixel block 110 at the first time interval T1 to Tn. have.

During the first period Tc, the analog-to-digital converter block 130 performs analog-to-digital conversion on read-out pixel signals to output digital pixel signals, and the frame controller 140 receives the digital pixel signals. and can be sequentially stored in the frame memory 145.

After the second period Td, the frame controller 140 may sequentially output the digital pixel signals to the image correction block 170 at second time intervals Tout1 to Toutn.

In this case, the first viewpoint interval T1 to Tn may be shorter than the second viewpoint interval Tout1 to Toutn.

Pixel signals read out corresponding to the respective lines (Line 1 to Line n) are converted in parallel by the analog-to-digital converter block 130 and then transmitted to the frame memory 145 in parallel, apart from this operation. Digital pixel signals stored in the frame memory 145 may be sequentially output to the output interface 180 . For this reason, the second period Td corresponding to each of the lines Line 1 to Line n may have different times.

That is, since the first viewpoint intervals T1 to Tn in the embodiment shown in FIG. 5 are shorter than the viewpoint intervals t1 to tn in the comparative example shown in FIG. 4 , the output operation to the output interface 180 Since the pixel signals are quickly read out regardless of , distortion of the output image can be minimized.

Accordingly, a frame rate before pixel signals are stored in the frame memory 145 may be higher than a frame rate after pixel signals are output from the frame memory 145 .

FIG. 6 is a diagram illustrating another embodiment of the image sensor shown in FIG. 1 . In FIG. 6 , only some components of the image sensor 100 shown in FIG. 1 are described as an example.

1 and 6 , an image sensor 100-2 according to another embodiment, unlike the image sensor 100-1a shown in FIG. 3A, excludes the frame controller 140 and the frame memory 145. components may be included.

Based on the line control signal LCS output from the timing generator 150, pixel signals corresponding to a predetermined pixel unit from one row line or one or more row lines of the active pixel block 110 correspond to a plurality of column lines. may be output in parallel to the CDS block 133 through N (N is an integer of 4 or more) channels.

The CDS block 133 may perform correlated double sampling on pixel signals, and the DBS block 135 may convert the correlated double sampled signals into digital pixel signals and output the converted digital pixel signals.

The channel conversion unit 137 may output digital pixel signals received in predetermined pixel units through N channels to the image correction block 170' through L (L is an integer smaller than N) channels.

The image correction block 170' may perform correction on image data corresponding to digital pixel signals output in parallel through L channels from the channel converter 137 and output corrected image data.

The output interface 180' outputs pixel signals in units of L pixels output from the active pixel block 110 through the N channels to the ISP 210 through the L channels.

Therefore, in the image processing system 10, when the external ISP 210 is configured to have M (M is an integer smaller than L) number of channels, the image sensors 100-1a and 100-1a shown in FIGS. 3A and 3B 1b), and when the external ISP 210 is configured to have L (L is an integer greater than M) number of channels, it may be implemented to include the image sensor 100-2 shown in FIG. 6. can

FIG. 7 is a block diagram illustrating an embodiment of an electronic system including the image sensor shown in FIG. 1 .

Referring to FIGS. 1 and 7 , an electronic system 800 is a data processing device capable of using or supporting a mobile industry processor interface (MIPI) interface, such as a mobile phone, personal digital assistants (PDA), or portable multimedia player (PMP). , IPTV (internet protocol television) or smart phone (smart phone) can be implemented.

The electronic system 800 includes an image sensor 100 , an application processor 810 , and a display 850 .

A camera serial interface (CSI) host 812 implemented in the application processor 810 may perform serial communication with the CSI device 841 of the image sensor 100 through a camera serial interface. In this case, for example, the CSI host 812 may include an optical deserializer (DES), and the CSI device 841 may include an optical serializer (SER).

The DSI host 811 implemented in the application processor 810 may perform serial communication with the DSI device 851 of the display 850 through a display serial interface (DSI). In this case, for example, the DSI host 811 may include an optical serializer (SER), and the DSI device 851 may include an optical deserializer (DES).

According to embodiments, the electronic system 800 may further include an RF chip 860 capable of communicating with the application processor 810 . A PHY (PHYsical channel) 813 included in the application processor 810 and a PHY 861 included in the RF chip 860 may exchange data according to MIPI DigRF.

According to an embodiment, the electronic system 800 includes a GPS 820, a storage 870, a microphone (MIC) 880, a dynamic random access memory (DRAM) 885, and a speaker 890. can include more. The electronic system 800 may communicate using world interoperability for microwave access (Wimax) 891, wireless LAN (WLAN) 893, and/or ultra wideband (UWB) 895.

FIG. 8 is a block diagram illustrating another embodiment of an electronic system including the image sensor shown in FIG. 1 .

Referring to FIGS. 1 and 8 , an electronic system 900 may include an image sensor 100 , a processor 910 , a memory 920 , a display unit 930 and an interface 940 .

The processor 910 may control the operation of the image sensor 100 . For example, the processor 910 may generate image data by processing a pixel signal output from the image sensor 100 .

The memory 920 may store a program for controlling the operation of the image sensor 100 and image data generated by the processor 910 . The processor 910 may execute a program stored in the memory 920 . For example, the memory 920 may be implemented as volatile memory or non-volatile memory.

The display unit 930 may display the image data output from the processor 910 or the memory 920 . For example, the display unit 930 may be a liquid crystal display (LCD), an LED display, an OLED display, an active matrix organic light emitting diodes (AMOLED) display, or a flexible display.

The interface 940 may be implemented as an interface for inputting/outputting image data. According to embodiments, the interface 940 may be implemented as a wireless interface.

The present invention can also be implemented as computer readable codes on a computer readable recording medium. A computer-readable recording medium includes all types of recording devices that store data that can be read by a computer system.

Examples of computer-readable recording media include ROM, RAM, CD-ROM, magnetic tape, floppy disk, and optical data storage devices.

In addition, the computer-readable recording medium is distributed in computer systems connected through a network, so that computer-readable codes can be stored and executed in a distributed manner. In addition, functional programs, codes, and code segments for implementing the present invention can be easily inferred by programmers in the art to which the present invention belongs.

Although the present invention has been described with reference to an embodiment shown in the drawings, this is only exemplary, and those skilled in the art will understand that various modifications and equivalent other embodiments are possible therefrom. Therefore, the true technical protection scope of the present invention should be determined by the technical spirit of the attached claims.

10; image processing system
100; CMOS image sensor
110; pixel array
120; low driver
130; analog digital converter
140; frame controller
145; frame memory
150; timing generator
160; lamp signal generator
170; image correction block
180; output interface
190; control register block

Claims (10)

a pixel array including a plurality of pixels generating pixel signals corresponding to a plurality of row lines;
a row driver outputting a plurality of control signals for controlling operations of the plurality of pixels;
A plurality of analog-to-digital converters performing analog-to-digital conversion, each of the analog-to-digital converters performing correlated double sampling on the pixel signals output from the pixels through a plurality of column lines. a plurality of analog-to-digital converters including a sampling block and a data bus block respectively converting and outputting the pixel signals digitized in the correlated double sampling block;
a timing generator configured to generate line control signals for controlling output of pixel signals corresponding to the plurality of row lines; and
a frame controller for storing the digitized pixel signals output in parallel from the data bus block in a frame memory and sequentially outputting the stored digitized pixel signals;
The timing generator outputs the line control signal to the row driver so that pixel signals according to predetermined pixel units are output in parallel from one row line or one or more row lines of the plurality of row lines;
A time delay between the digitized pixel signals stored in the frame memory and the stored digitized pixel signals that are sequentially output depends on the output rate of the pixel signal from the pixel array and the stored digitized pixel signal. An image sensor based on a ratio of sequential output speeds or based on the number of input ports of the frame controller and the number of output ports of the frame controller. According to claim 1,
The image sensor may further include a channel converter configured to convert the number of channels corresponding to the plurality of column lines. According to claim 2,
The frame memory is a volatile memory including static random access memory (SRAM) or dynamic random access memory (DRAM), and the frame controller manages a storage area of the frame memory. The method of claim 3, wherein the channel conversion unit,
An image sensor that converts the number of N (N is an integer greater than or equal to 4) channels corresponding to the plurality of column lines into the number of L (L is an integer less than N) channels corresponding to the input ports of the frame controller. The method of claim 4, wherein the frame controller,
An image sensor configured to receive the plurality of digital pixel signals output through the L channels, store the plurality of digital pixel signals in the frame memory, and output the stored plurality of digital pixel signals through M (M is an integer less than or equal to L) channels. delete The method of claim 3, wherein the frame controller,
a compression device for compressing the plurality of digital pixel signals output from the data bus block and outputting the compressed signals to the frame memory; and
An image sensor comprising a decompression device for decompressing and outputting signals stored in the frame memory. The method of claim 5, wherein the image sensor,
An image correction block configured to perform correction on image data corresponding to the digital pixel signals output from the frame controller and output corrected image data;
The plurality of analog-to-digital converters include the N analog-to-digital converters, and the image correction block includes the M image correction circuits. The method of claim 4, wherein the image sensor,
an encoder for encoding the plurality of digital pixel signals output from the data bus block and outputting encoded data to the frame controller; and
and a decoder configured to decode the encoded data transmitted from the frame controller and output decoded data. According to claim 3,
The image sensor of claim 1 , wherein the frame memory is implemented in a first chip, and the pixel array and the plurality of analog-to-digital converters are implemented in a second chip stacked on the first chip.

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