KR102459985B1 - Error Reduction Techniques for Content Addresable Memory based Binary Neural Network Accelerator - Google Patents

Abstract

Proposed is an error correction technique of a content-addressable memory-based BNN accelerator. The content-addressable memory-based BNN accelerator proposed in the present invention comprises: a first reference match line (ML) that compares a plurality of mismatched additional CAM cells to a single reference ML; and a second reference ML that compares a plurality of additional matching CAM cells to the single reference ML, wherein an XNOR-popcount operation is optionally performed through the plurality of additional CAM cells, the first reference ML, and the second reference ML to reduce calculation errors. Therefore, the present invention is capable of reducing a probability of the error.

Description

Error Reduction Techniques for Content Addressable Memory based Binary Neural Network Accelerator

The present invention relates to a method and apparatus for error correction of a content addressable memory-based BNN accelerator.

Binarized Neural Network (BNN) has received a lot of attention in lightweight neural networks because weights and activations are limited to two values that are advantageous in terms of hardware by reducing the amount of data [1], [2]. However, existing computing systems employing separate processing units and data storage elements still require a lot of power and performance overhead due to data transfer between the processing elements and memory.

Therefore, there is a need for new BNN accelerators to perform high performance and robust multiplicative accumulators that operate directly within the memory circuit.

[1] Y. H. Chen et al. 2017. Eyeriss: An Energy-Efficient Reconfigurable Accelerator for Deep Convolutional Neural Networks. IEEE JSSC, 52, 1, (2017), 127-138. [2] S. Han et al. 2016. EIE: Efficient Inference Engine on Compressed Deep Neural Network. (2016). arXiv:1602.01528. [3] M. Courbariaux et al. 2016. Binarized Neural Networks: Training Deep Neural Networks with Weights and Activations Constrained to +1 or -1. (2016). arXiv:1602.02830. [4] M. Rastegari et al. 2016. XNOR-Net: ImageNet Classification Using Binary Convolutional Neural Networks. In 2016 Computer Vision, 525-542. [5] W. Tang et al. 2017. Wang, “How to Train a Compact Binary Neural Network with High Accuracy?. in 2017 AAAI, 2625- 2631. [6] D. Miyashita et al. 2017. A Neuromorphic Chip Optimized for Deep Learning and CMOS Technology With Time-Domain Analog and Digital Mixed-Signal Processing," IEEE JSSC. 52, 10, (2017), 2679-2689 [7] K. Pagiamtzis et al. 2006. Content-Addressable Memory (CAM) Circuits and Architectures: A Tutorial and Survey. IEEE JSSC, (2006). 41, 3, 712-727. [8] W. Choi, K. Jeong, K. Choi, K. Lee, and J. Park, "Content addressable memory based binarized neural network accelerator using time-domain signal processing," in ACM/IEEE Design Automation Conference (DAC ), 2018. [9] H. Yonekawa et al. 2017. On-Chip Memory Based Binarized Convolutional Deep Neural Network Applying Batch Normalization Free Technique on an FPGA. in 2017 IPDPSW, 98-105.

The technical problem to be achieved by the present invention is to efficiently perform a convolution operation by utilizing a fully parallel search operation to reduce the hardware error probability, and to reduce the memory size and complexity of the convolution operation using binary data. To provide a content addressable memory)-based BNN accelerator and an operating method thereof. Through the proposed CAM-based BNN accelerator, we want to reduce the probability of hardware error and deterioration of operational reliability due to process change during ML (Match Line) sensing operation.

In one aspect, the content addressable memory-based BNN accelerator proposed in the present invention compares a plurality of mismatched additional CAM cells with a single reference ML (Match Line) and a plurality of matching additional CAM cells. and a second criterion ML for comparison with a single criterion ML, and selectively performs an XNOR-popcount operation through the plurality of additional CAM cells, the first criterion ML and the second criterion ML in order to reduce an operation error.

The first criterion ML and the second criterion ML are connected by an ML switch to make an input feature map (iFMAP) connection, and additional read and write operations are performed to rearrange the iFMAP pairs in the case of down-filter sliding. carry out

The plurality of additional CAM cells can replace the convolution operation of BNN with a CAM array without additional digital logic circuits by performing XNOR-popcount operation on the CAM array including the plurality of additional CAM cells, and the hardware error rate due to process changes An XNOR-popcount operation is performed followed by an SRAM read operation with an additional clock cycle to reduce the

The plurality of additional CAM cells utilize parallel ML operations of a CAM array comprising the plurality of additional CAM cells to enable data processing.

In another aspect, the error correction method of the content addressable memory-based BNN accelerator proposed in the present invention comprises the steps of comparing a plurality of additional CAM cells mismatched through a first reference ML (Match Line) with a single reference ML; , comparing a plurality of additional CAM cells matched via a second criterion ML to a single criterion ML and XNOR-popcount via the plurality of additional CAM cells, the first criterion ML and the second criterion ML to reduce computational errors. and selectively performing the operation.

Through the CAM (Content Addressable Memory)-based BNN accelerator and its operating method according to embodiments of the present invention, the convolution operation is efficiently performed by utilizing a fully parallel search operation for reducing the hardware error probability, and the binarized data is used This reduces the memory size and complexity of the convolution operation. Through the proposed CAM-based BNN accelerator, it is possible to reduce the deterioration of operational reliability and the probability of hardware errors due to process changes during ML (Match Line) sensing operation.

1 is a diagram illustrating a BNN arithmetic truth table according to an embodiment of the present invention.
2 is a diagram for explaining BNN activation and XNOR-popcount according to an embodiment of the present invention.
3 is a diagram for explaining a CAM memory-based XNOR operation according to an embodiment of the present invention.
4 is a diagram illustrating a circuit of a CAM memory-based BNN accelerator according to an embodiment of the present invention.
5 is a diagram for explaining an ML connection using an ML switch according to an embodiment of the present invention.
6 is a diagram for explaining a multi-reference sensing method according to an embodiment of the present invention.
7 is a flowchart illustrating an error correction method of a CAM memory-based BNN accelerator according to an embodiment of the present invention.
8 is a diagram comparing the error correction result of the prior art with the CAM memory-based BNN accelerator according to an embodiment of the present invention.

Binarized Neural Network (BNN) is one of the most efficient neural networks for low-cost convolutional computations. In such a BNN, it is possible to reduce the memory size and the complexity of the convolution operation by using the binarized data.

Content Addressable Memory (CAM)-based BNN accelerators can efficiently perform convolution operations by utilizing fully parallel search operations in CAM. However, one of the major problems with CAM-based BNN hardware is that the operational reliability is severely degraded due to process changes during ML (Match Line) sensing operation.

Therefore, the present invention proposes a new CAM array design that can reduce the hardware error probability. The proposed CAM-based accelerator achieves a 62% reduction in XNOR-popcount operation, and the decrease in classification accuracy of the Fashion-MNIST dataset is reduced from 2.33% to 1.26%. Hereinafter, an embodiment of the present invention will be described in detail with reference to the accompanying drawings.

1 is a diagram illustrating a BNN arithmetic truth table according to an embodiment of the present invention.

Fig. 1(a) shows the truth table of the multiplication operation of BNN based on the binarized bits of +1 and -1 [3]. However, for simplified BNN hardware implementations, we prefer to process the binarized bits of 1 or 0 instead of using -1 [4], [5]. When -1 is converted to 0, the truth table for the multiplication operation is changed as shown in FIG. 1(b), and the XNOR gate can also perform the same operation.

2 is a diagram for explaining BNN activation and XNOR-popcount according to an embodiment of the present invention.

In the BNN of FIG. 2(a), the post-accumulate signum function may be mapped to a bit count operation using a comparator of n/2 (half the cumulative size) threshold as shown in FIG. 2(b).

3 is a diagram for explaining a CAM memory-based XNOR operation according to an embodiment of the present invention.

CAM compares the input search data with the stored data and returns the address of the matching location. Figure 3 shows a CAM cell composed of a 6T SRAM and two-stack NMOS transistors on both sides [6], [7].

The ML sensing operation of the CAM array can be described as follows. Prior to the ML pre-charge phase, the search-line (SL) pair is disabled to ground to prevent unintentional ML discharge. In the ML pre-charge phase, all MLs in the array are pre-charged to supply voltage. When the SL pair is set as search data, a two-stack NMOS transistor compares the search data with the stored data.

As shown in the truth table of FIG. 3 , when the search data does not match the stored data, a pull-down path is formed to discharge the ML node. On the other hand, if the search data and the stored data do not match, the two stacked NMOS transistors are turned off and the current path from ML to ground is lost [8].

4 is a diagram illustrating a circuit of a CAM memory-based BNN accelerator according to an embodiment of the present invention.

The proposed CAM memory-based BNN accelerator includes a first reference ML (Match Line) (ML _REF0 ) and a second reference ML (ML _REF1 ).

The first reference ML compares a plurality of mismatched additional CAM cells to a single reference ML. The second criterion ML compares the matching plurality of additional CAM cells to the single criterion ML. Thereafter, the XNOR-popcount operation may be selectively performed through the plurality of additional CAM cells, the first reference ML, and the second reference ML in order to reduce an operation error.

In the BNN Multiply Accumulate (MAC) operation according to an embodiment of the present invention, an input X is mapped to a storage node of a CAM cell, and a search line node is determined by a Weight input.

Considering the majority rule, the XNOR-popcount operation can be performed by comparing the discharge delay of the evaluated ML and the reference ML [4], [8]. As shown in FIG. 4 , the filter weight is connected to the SL and the input feature map (iFMAP) is stored in the CAM array and can be used for the XNOR-popcount operation.

For example, the XNOR operation is performed by comparing iFMAP and weights in the CAM cell. Since the ML discharge delay depends on the number of mismatched CAM cells, the voltage of the ML is compared with the reference ML through the sensing amplifier to determine whether it is mainly '1' or mainly '0'. An ML switch (ML_Switch) located between Bank 1 and Bank 2 is used for filter sliding.

5 is a diagram for explaining an ML connection using an ML switch according to an embodiment of the present invention.

The ML switch located between Bank 1 and Bank 2 is used for filter sliding. First, as shown in Fig. 5(a), the XNOR-popcount operation is simultaneously performed on four MLs. In the next right filter sliding, the ML connections have to be reconfigured by the ML switches to make the necessary iFMAP connections. Otherwise, in case of down-filter sliding, additional read and write operations are required to rearrange the appropriate iFMAP pairs. By performing the XNOR-popcount operation on the modified CAM array, the powerful convolution operation of BNN can be replaced with a CAM array without additional digital logic circuitry. Additionally, parallel ML operations on CAM arrays can be utilized to enable high data throughput in CAM-based BNN accelerators.

However, the main disadvantage of the CAM-based BNN accelerator [8] is that the reliability of the XNOR-popcount operation is severely affected by process changes, resulting in large sensing errors. This requires improving the computational reliability of the XNOR-popcount operation in case of small mismatch differences.

The present invention proposes a new design technique that can reduce arithmetic errors by selectively performing an additional logic-based XNOR-popcount operation. The XNOR-popcount operation error is based on the fact that it mainly occurs when the evaluated ML and the reference ML are small. This is because, when the mismatch difference is small, the ML sensing reliability is not affected by the process change as the ML discharge rate is close.

According to an embodiment of the present invention, a new sensing method using multiple criteria as shown in FIG. 4 is proposed to solve the ML sensing reliability problem. The two separate criteria are determined as follows. In one reference ML(REF0), the three additional CAM cells that are mismatched have a faster discharge rate compared to the conventional single reference scheme. On the other hand, in the other reference ML(REF1), three additional CAM cells are matched, and the discharge rate is slower than that of the existing reference method.

6 is a diagram for explaining a multi-reference sensing method according to an embodiment of the present invention.

Reference ML(REF0) and reference ML(REF1) are the case of 5-bit mismatch and 3-bit mismatch, respectively. If there is no mismatch input, ML is not discharged, so that the evaluated ML voltage is higher than the voltages of the reference ML(REF0) and the reference ML(REF1). Therefore, the error probability of the XNOR-popcount operation is almost zero.

Similarly, the evaluated ML of all mismatched inputs discharges much faster than the reference ML(REF0) and reference ML(REF1), so in this case the XNOR-popcount operation can have high reliability. On the other hand, in the case of a 4-bit mismatch, since the mismatch difference is small, the reliability of the XNOR-popcount operation is low. If the ML discharge rate lies between the two criteria, it is desirable to manually perform a digital logic-based XNOR-popcount operation to achieve high classification accuracy.

Therefore, the method proposed in the present invention performs a digital logic-based XNOR-popcount operation followed by an SRAM read operation with an additional clock cycle in order to mitigate the hardware error rate due to process change.

7 is a flowchart illustrating an error correction method of a CAM memory-based BNN accelerator according to an embodiment of the present invention.

The error correction method of the proposed CAM memory-based BNN accelerator compares a plurality of additional CAM cells that are mismatched through a first reference ML (Match Line) with a single reference ML (710), and is matched through a second reference ML Comparing a plurality of additional CAM cells with a single reference ML ( 720 ) and selectively performing an XNOR-popcount operation through the plurality of additional CAM cells, a first reference ML and a second reference ML to reduce computational errors step 730 .

In step 710 , a plurality of additional CAM cells mismatched via a first reference Match Line (ML) are compared to a single reference ML.

In step 720 , a plurality of additional CAM cells matched via the second reference ML are compared to a single reference ML.

In step 730, an XNOR-popcount operation is selectively performed through the plurality of additional CAM cells, the first reference ML and the second reference ML in order to reduce the operation error.

According to an embodiment of the present invention, the first criterion ML and the second criterion ML are connected by an ML switch to make an input feature map (iFMAP) connection, and rearrange the iFMAP pair in the case of down-filter sliding to perform additional read and write operations.

By performing the XNOR-popcount operation on the CAM array including a plurality of additional CAM cells according to an embodiment of the present invention, the convolution operation of the BNN can be replaced with a CAM array without an additional digital logic circuit. In the present invention, an XNOR-popcount operation followed by an SRAM read operation can be performed with an additional clock cycle to reduce a hardware error rate due to a process change. Additionally, parallel ML operations in a CAM array containing a plurality of additional CAM cells can be utilized to enable data processing.

8 is a diagram comparing the error correction result of the prior art with the CAM memory-based BNN accelerator according to an embodiment of the present invention.

To verify the efficiency of the CAM-based BNN accelerator according to an embodiment of the present invention, a second convolutional layer of the LeNet-5 model was implemented using commercial 28nm CMOS technology. Five banks (150 cells per ML) were implemented in a CAM array architecture to perform HSPICE simulations.

Fig. 8(a) shows the relationship between the mismatch difference between the reference ML and the evaluated ML and the error probability of the XNOR-popcount operation in a single criterion-based CAM array.

As described above, when the absolute value of the mismatch difference increases, the operation failure rate decreases. The proposed CAM array (Prop.) shows a much lower operation failure rate than the single reference method (1Ref.) as shown in FIG.

Table 1 is a table comparing the error probability and classification accuracy of the BNN accelerator.

<Table 1>

As shown in Table 1, when applying the ML sensing error probabilities to the original XNOR-popcount results, 7.51% of the overall output activations for the Fashion MNIST test images are inverted, which degrades the top 1 accuracy by 2.33% in LeNet-5. On the other hand, the proposed memory architecture can only achieve 2.88% of XNOR-popcount operation errors, which represents a 62% reduction in hardware errors. This leads to a 1.26% reduction in classification accuracy compared to the top 1 accuracy. In addition, the proposed BNN accelerator can achieve a 51.72% reduced computational cycle for the input image compared to the conventional XNOR-popcount computation shown in [9].

As such, the present invention proposes a new reliability improvement technique for a fast and powerful CAM-based BNN accelerator. The huge convolution operation of BNN can be replaced by XNOR-popcount operation on the modified CAM array. Parallel convolution operation can be performed with a fully parallel search of the CAM array, which improves computational performance by more than 50%. In addition, the proposed sensing scheme with multiple criteria can improve the Fashion MNIST classification accuracy by more than 1% by alleviating the XNOR-popcount error probability problem.

The device described above may be implemented as a hardware component, a software component, and/or a combination of the hardware component and the software component. For example, devices and components described in the embodiments may include, for example, a processor, a controller, an arithmetic logic unit (ALU), a digital signal processor, a microcomputer, a field programmable array (FPA), It may be implemented using one or more general purpose or special purpose computers, such as a programmable logic unit (PLU), microprocessor, or any other device capable of executing and responding to instructions. The processing device may execute an operating system (OS) and one or more software applications running on the operating system. The processing device may also access, store, manipulate, process, and generate data in response to execution of the software. For convenience of understanding, although one processing device is sometimes described as being used, one of ordinary skill in the art will recognize that the processing device includes a plurality of processing elements and/or a plurality of types of processing elements. It can be seen that may include For example, the processing device may include a plurality of processors or one processor and one controller. Other processing configurations are also possible, such as parallel processors.

The software may comprise a computer program, code, instructions, or a combination of one or more thereof, which configures a processing device to operate as desired or is independently or collectively processed You can command the device. The software and/or data may be any kind of machine, component, physical device, virtual equipment, computer storage medium or device, to be interpreted by or to provide instructions or data to the processing device. may be embodied in The software may be distributed over networked computer systems and stored or executed in a distributed manner. Software and data may be stored in one or more computer-readable recording media.

The method according to the embodiment may be implemented in the form of program instructions that can be executed through various computer means and recorded in a computer-readable medium. The computer-readable medium may include program instructions, data files, data structures, etc. alone or in combination. The program instructions recorded on the medium may be specially designed and configured for the embodiment, or may be known and available to those skilled in the art of computer software. Examples of the computer-readable recording medium include magnetic media such as hard disks, floppy disks and magnetic tapes, optical media such as CD-ROMs and DVDs, and magnetic such as floppy disks. - includes magneto-optical media, and hardware devices specially configured to store and execute program instructions, such as ROM, RAM, flash memory, and the like. Examples of program instructions include not only machine language codes such as those generated by a compiler, but also high-level language codes that can be executed by a computer using an interpreter or the like.

As described above, although the embodiments have been described with reference to the limited embodiments and drawings, various modifications and variations are possible by those skilled in the art from the above description. For example, the described techniques are performed in a different order than the described method, and/or the described components of the system, structure, apparatus, circuit, etc. are combined or combined in a different form than the described method, or other components Or substituted or substituted by equivalents may achieve an appropriate result.

Therefore, other implementations, other embodiments, and equivalents to the claims are also within the scope of the following claims.

Claims (8)

a first reference ML (Match Line) comparing a plurality of additional mismatched CAM cells to a single reference ML; and
A second criterion ML comparing a plurality of additional CAM cells that match to a single criterion ML.
including,
Selectively perform XNOR-popcount operation through the plurality of additional CAM cells, the first reference ML and the second reference ML to reduce the operation error,
The first reference ML and the second reference ML are:
connected by ML switches to make an input feature map (iFMAP) connection,
In case of downward filter sliding, additional read and write operations are performed to rearrange the iFMAP pairs.
BNN accelerator. delete According to claim 1,
The plurality of additional CAM cells,
By performing the XNOR-popcount operation on the CAM array including the plurality of additional CAM cells, the convolution operation of BNN can be replaced with a CAM array without additional digital logic circuits,
To reduce the hardware error rate due to process variations, an XNOR-popcount operation is performed followed by an SRAM read operation with an additional clock cycle.
BNN accelerator. 4. The method of claim 3,
The plurality of additional CAM cells,
Utilizing parallel ML operations of a CAM array comprising the plurality of additional CAM cells to enable data processing.
BNN accelerator. comparing a plurality of additional CAM cells mismatched via a first reference Match Line (ML) to a single reference ML;
comparing a plurality of additional CAM cells matched via the second criterion ML to a single criterion ML; and
Selectively performing an XNOR-popcount operation through the plurality of additional CAM cells, a first reference ML and a second reference ML to reduce an operation error;
including,
Selectively performing an XNOR-popcount operation through the plurality of additional CAM cells, a first reference ML and a second reference ML in order to reduce the operation error,
The first reference ML and the second reference ML are connected by an ML switch to make an input feature map (iFMAP) connection, and additional read and write operations are performed to rearrange the iFMAP pairs in the case of down-filter sliding. performing
Error correction method of BNN accelerator. delete 6. The method of claim 5,
Selectively performing an XNOR-popcount operation through the plurality of additional CAM cells, a first reference ML and a second reference ML in order to reduce the operation error,
By performing the XNOR-popcount operation on the CAM array including the plurality of additional CAM cells, the convolution operation of BNN can be replaced with a CAM array without additional digital logic circuits,
To reduce the hardware error rate due to process variations, an XNOR-popcount operation is performed followed by an SRAM read operation with an additional clock cycle.
Error correction method of BNN accelerator. 8. The method of claim 7,
Utilizing parallel ML operations of a CAM array comprising the plurality of additional CAM cells to enable data processing.
Error correction method of BNN accelerator.

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