KR102458919B1 - Memory System controlling an operation performance and Operating Method thereof - Google Patents

Abstract

Disclosed are a memory controller performing adaptive power control, a memory system including the same, and a method for operating the memory system. The method for operating the memory system according to an embodiment of the present invention comprises the steps of: transmitting information on maximum power consumable in the memory system to a host; receiving, from the host, table information including a plurality of entries, wherein each entry includes information on a battery stage associated with the remaining amount of a battery of the electronic device equipped with the memory system and information on maximum consumable power corresponding thereto; receiving battery information from the host; and controlling power so that the power consumed by the memory system does not exceed the maximum power corresponding to the maximum consumable power information according to the maximum consumable power information of the entry corresponding to the received information on the battery. The memory system controls the power consumed by at least some components among a plurality of components and controls the power for the components differently based on the operation pattern of the memory system. The power can be adaptively managed on the remaining amount of the battery in the electronic device.

Description

A memory controller performing adaptive power control, a memory system including the same, and an operating method of the memory system

The present disclosure relates to a memory controller, a memory system including the same, and more particularly, to a memory controller for performing power control and a memory system including the same.

The memory system can be broadly classified into a volatile memory system and a nonvolatile memory system. The nonvolatile memory retains stored data even when power is cut off, whereas in the volatile memory, data is deleted when power is cut off. Non-volatile memory may include read only memory (ROM), magnetic disk, optical disk, flash memory and resistive random access memory (RRAM), phase-change memory (PRAM) and magnetic random access memory (MRAM). A solid state drive (SSD) including a nonvolatile memory is used in many electronic devices as a memory system.

A portable electronic device such as a mobile device may supply power to various internal devices using a battery, and since the capacity of the battery is limited, power consumption needs to be optimally managed. However, when the power provided to the memory system is reduced, the performance of the memory system may be deteriorated, and in this case, there is a problem that the overall performance of the electronic device may be deteriorated.

An object of the present disclosure is to provide a memory controller capable of efficiently managing power of a memory system employed in an electronic device, and a memory system including the same.

In order to achieve the above object, a method of operating a memory system according to an embodiment of the present disclosure includes transmitting information on maximum power consumable in the memory system to a host, including a plurality of entries from the host, Each entry includes: receiving table information including a battery level related to a remaining battery level of an electronic device employing the memory system and maximum power consumption information corresponding thereto; receiving battery information from the host; adjusting power so that the power consumed in the memory system does not exceed the maximum power corresponding to the maximum power consumption information according to the maximum power consumption information of an entry corresponding to the battery information, wherein the memory system includes a plurality of It is characterized in that the power consumed by at least some of the components is adjusted, and the power of the components is differently adjusted based on the operation pattern of the memory system.

On the other hand, the method of operating a memory system according to another embodiment of the present disclosure includes the steps of receiving information on maximum device power consumption to be consumed in the memory system from a host, and based on the received information on maximum power consumption of the device, Calculating component maximum power consumption information to be consumed by one or more components provided in a memory system, and storing the device maximum power consumption information and the component maximum power consumption information as table information; and detecting a power consumed by the memory system, and when the detected power exceeds the device maximum power consumption information, reducing power consumed by the memory system.

Meanwhile, the memory controller according to an embodiment of the present disclosure includes a plurality of entries from a CPU core and a host that control a memory operation for the memory device, and each entry is based on the remaining battery level of an electronic device employing the memory system. a storage circuit for storing table information including a related battery stage and maximum power consumption information corresponding thereto; transmit maximum power information, receive battery information corresponding to a first entry among the entries from the host, and the power consumed in the memory system corresponds to the maximum power consumption information of the first entry set by the host It is characterized in that the power is adjusted so as not to exceed the maximum power.

According to the memory controller of the present disclosure and a memory system including the same, since power adjustment is performed based on maximum power information from the host, the power of the memory system can be managed under the leadership of the host, and accordingly, the remaining battery level of the electronic device Accordingly, there is an effect of adaptively managing power.

In addition, according to the memory controller of the present disclosure and a memory system including the same, in controlling the power of the memory system, it is possible to control the power through various elements based on the operation pattern for each component, so that the power consumption of the memory system is reduced. There is an effect that can minimize the performance degradation in the reduction.

1 is a block diagram illustrating a data processing system including a memory system according to an exemplary embodiment of the present disclosure.
FIG. 2 is a block diagram illustrating an implementation example of the memory controller of FIG. 1 .
3 is a block diagram illustrating an example in which the memory system of FIG. 1 is implemented with an SSD.
4 is a block diagram illustrating an implementation example of a memory controller according to an exemplary embodiment of the present disclosure.
5 is a diagram illustrating an operation example of an electronic device including a memory system according to an exemplary embodiment of the present disclosure.
6 is a diagram illustrating table information according to an exemplary embodiment of the present disclosure.
7 is a block diagram illustrating an example of a power control operation of a memory controller according to an exemplary embodiment of the present disclosure.
8 is a waveform diagram illustrating an example of an operation of the memory controller of FIG. 7 .
9 is a flowchart illustrating a method of operating a memory system according to an exemplary embodiment of the present disclosure.
10 is a diagram illustrating an operation example of an electronic device including a memory system according to another exemplary embodiment of the present disclosure.
11 is a block diagram illustrating an example of a power control operation of the memory controller in the embodiment shown in FIG. 10 .
12 is a block diagram illustrating an implementation example of a memory controller according to an exemplary embodiment of the present disclosure.
13 is a flowchart illustrating an operating method of an electronic device employing a memory system according to another exemplary embodiment of the present disclosure.
14 is a flowchart illustrating a method of operating a memory system according to another exemplary embodiment of the present disclosure.
15 is a flowchart illustrating a method of operating a memory system according to another exemplary embodiment of the present disclosure.
16 is a diagram illustrating an example of communication between a host and a memory system through various types of commands.
17 is a perspective view illustrating a memory block included in a memory system according to an embodiment of the present disclosure;
18 is a block diagram illustrating a data processing system including a memory system according to embodiments of the present disclosure.

Hereinafter, embodiments of the present disclosure will be described in detail with reference to the accompanying drawings.

1 is a block diagram illustrating an electronic device including a memory system according to an exemplary embodiment of the present disclosure. In the following embodiments, the electronic device is referred to as a data processing system in that it performs processing such as data access by including the memory system according to embodiments of the present disclosure.

1 , the data processing system 10 may include a host 100 and a memory system 200 . The data processing system 10 may be implemented as, for example, a personal computer (PC), a data server, a network-coupled storage, an Internet of Things (IoT) device, or a portable electronic device. Portable electronic devices include laptop computers, mobile phones, smart phones, tablet PCs, personal digital assistants (PDAs), enterprise digital assistants (EDAs), digital still cameras, digital video cameras, audio devices, PMPs (portable multimedia players), PNDs. (personal navigation device), an MP3 player, a handheld game console, an e-book, a wearable device, and the like.

The host 100 may include an application processor (AP) or a System-On-Chip (SoC), and the memory system 200 includes a Universal Serial Bus (USB), a multimedia card (MMC), and an embedded embedded MMC (eMMC). MMC), PCI (peripheral component interconnection), PCI-E (PCI-express), ATA (Advanced Technology Attachment), Serial-ATA, Parallel-ATA, SCSI (small computer small interface), ESDI (enhanced small disk interface), It may communicate with the host 100 through various interfaces such as Integrated Drive Electronics (IDE), Firewire, Universal Flash Storage (UFS), and Nonvolatile Memory express (NVMe).

The memory system 200 may include a nonvolatile memory device, for example, a NAND flash memory, a vertical NAND flash memory, a NOR flash memory, and a resistive random RAM (RAM). Access memory), phase-change memory (Phase-Change Memory), magnetoresistance memory (magnetoresistive random access memory), such as non-volatile memory may include. The memory system 200 may be implemented as a memory card such as eMMC, SD, Micro SD, Universal Flash Storage (UFS), etc. or a solid state drive (SSD) including a nonvolatile memory system, hereinafter referred to as the memory system 200 . In describing the configuration and operation, it is assumed that the memory system 200 is an SSD including a plurality of flash memory chips. Also, the memory system 200 may be referred to as a storage device in terms of storing information.

The host 100 may include the application processor 110 , and may include various intelligent properties (IPs). As the IP, the host 100 may include a memory device driver 111 for controlling the memory system 200 . The host 100 may communicate with the memory system 200 to transmit various information, such as a request for a memory operation, and receive a response thereto.

Meanwhile, the memory system 200 may include a memory controller 210 and a memory device 220 . The memory controller 210 may receive requests related to a memory operation from the host 100 , generate a command/address and a clock signal, and provide the generated command/address and clock signals to the memory device 220 . The memory device 220 may store write data in the memory cell array or provide read data to the memory memory controller 210 in response to a command/address.

According to an exemplary embodiment of the present disclosure, various types of information are used between the host 100 and the memory system 200 using an In-Band Command and/or a Side-Band Command. can be transmitted and received. For example, the memory system 200 may operate according to various performances while consuming power, and may host information (eg, maximum power information MAX_PWR) related to the maximum power that the memory system 200 can consume. (100) can be transmitted. Also, the host 100 may receive the maximum power information MAX_PWR, generate table information Info_Table based thereon, and transmit it to the memory system 200 .

As an example, the host 100 receives the maximum power information MAX_PWR at the beginning of the operation of the data processing system 10 (or at the time of system booting) and transfers the table information Info_table to the memory system 200 based on the maximum power information MAX_PWR. may be transmitted, and the memory system 200 may store the received table information Info_table therein. Alternatively, the maximum power information MAX_PWR and the table information Info_table may be transmitted/received between the host 100 and the memory system 200 during a runtime operation of the data processing system 10 .

The data processing system 10 may include a battery 11 , and the host 100 and the memory system 200 may receive power PWR from the battery 11 . In an exemplary embodiment, the host ( 100) may generate table information (Info_table) including entries for a plurality of battery stages. The table information Info_table may include various information, and as an example, the remaining amount of the battery may be classified into a plurality of stages (hereinafter, referred to as battery stages), and each entry corresponds to the battery stage in memory. Information related to the maximum power to be consumed in the system 200 (hereinafter, referred to as maximum power consumption information) and information related to average power (hereinafter, referred to as average power consumption information) may be included.

The host 100 may periodically detect the remaining amount of the battery 11 and transmit battery information Info_BAT according to the detection result to the memory system 200 . Each battery level may include information of a predetermined remaining battery level range, and as the battery information Info_BAT corresponds to the remaining battery level, any one battery level to which the battery information Info_BAT belongs may be determined. Alternatively, each battery stage may be stage information corresponding to the remaining battery capacity, and the battery information Info_BAT may indicate any one of the plurality of battery stages described above.

The memory system 200 checks the table information Info_table based on the received battery information Info_BAT, and based on the entry corresponding to the battery information Info_BAT, the maximum power consumed in the memory system 200 and / Or you can adjust the average power. For example, an adjustment operation may be performed so that the maximum power and/or average power consumed in the memory system 200 decreases as the remaining amount of the battery 11 decreases.

The memory system 200 may correspond to a device and may include a plurality of components. As an example, a unit that individually consumes power in the memory system 200 may be defined as a component, and each of the memory controller 210 and the memory device 220 may correspond to a component. In addition, various components provided in each of the memory controller 210 and the memory device 220 may correspond to a component, for example, a CPU core and a volatile memory (eg, DRAM) provided in the memory controller 210 and , each of the flash memory chips included in the memory device 220 may correspond to a component.

The memory system 200 may adjust power consumption according to various methods based on the table information Info_table. As an example, the memory system 200 may adjust the average power consumption and the maximum power consumption of the memory system 200 by adjusting the power of at least some of the plurality of components. As an example, the memory controller 210 may provide a clock signal having a predetermined frequency to the memory device 220 and control access operations to a plurality of flash memory chips included in the memory device 220 . In controlling the power consumption of the memory system 200, various operating characteristics of the components (eg, CPU core performance, clock signal frequency, number of simultaneously accessed flash memory chips, etc.) may be adjusted. .

FIG. 2 is a block diagram illustrating an embodiment of the memory controller 210 of FIG. 1 .

1 and 2 , the memory controller 210 may include a CPU core 211 , a memory 212 storing table information Info_Table, and a power controller 213 . The CPU core 211 may control the overall operation of the memory controller 210 and may perform a control operation according to a request from the host 100 . Also, based on the control of the CPU core 211 , the memory controller 210 includes various signals for controlling memory operations, such as a command CMD, an address ADD, data DATA, a clock signal CLK, and a chip. The selection signal Sel_chip may be transmitted to the memory device 220 . Also, although not shown in FIG. 2 , the above-described maximum power information MAX_PWR may be stored in the memory 212 or another storage area and provided to the host 100 .

The power controller 213 may generate a control signal (not shown) for controlling power consumption of the memory system 200 based on information stored in the table information Info_table. The memory controller 210 may include internal components that generate the above-described command CMD, address ADD, clock signal CLK, chip select signal Sel_chip, and the like, and each of the internal components provides power An operation characteristic related to power consumption may be changed based on the control of the controller 213 . Also, the CPU core 211 may adjust core performance based on the control of the power controller 213 .

Meanwhile, in the embodiment shown in FIG. 2 , an example in which the power controller 213 generates various control signals for controlling power consumption based on the control of the CPU core 211 is illustrated, but embodiments of the present disclosure are not limited thereto. no need. In another exemplary embodiment, the table information Info_Table may be referenced by the CPU core 211 , and various components in the memory controller 210 in relation to power consumption adjustment based on the control of the CPU core 211 . may be controlled.

3 is a block diagram illustrating an example in which the memory system of FIG. 1 is implemented with an SSD. As shown in FIG. 3 , the SSD 300 as a memory system may include a plurality of flash memory chips 310 , an SSD controller 320 , and a power supply 330 . The power supply 330 may receive power PWR_B from a battery in the electronic device in which the SSD 300 is employed, and may provide internal power to various components in the SSD 300 .

The SSD controller 320 may control the flash memory chips 310 in response to a signal SIG received from the host through the first port PT1 , and provide power PWR_B through the second port PT2 . can be input. The SSD controller 320 may be connected to the flash memory chips 310 through a plurality of channels CH1 to CHM.

The SSD controller 320 may include a memory 321 and a power controller 322 for storing table information Info_table according to the above-described embodiment. Although not shown in FIG. 3 , the SSD controller 320 may further include a CPU core, transmits the maximum power information according to the above-described embodiment to the host, and includes a battery level and corresponding power consumption information from the host. You can receive table information.

After storing table information therein, the SSD controller 320 may periodically or aperiodically receive battery information from the host. Also, based on the received battery information and table information Info_table, the SSD controller 320 may control the power supply 330 to adjust internal power provided from the power supply 330 . In addition, based on the received battery information and table information (Info_table), the SSD controller 320 adjusts the frequency of a clock signal used in the SSD 300 or changes the number of flash memory chips 310 simultaneously accessed. Various types of power control operations may be performed.

4 is a block diagram illustrating an implementation example of a memory controller according to an exemplary embodiment of the present disclosure.

4 , the memory controller 400 may include a CPU core 410 , a host interface 420 , and a memory interface 430 . As described above, the CPU core 410 may control the overall operation of the memory controller 400 , and the host interface 420 may use a predetermined protocol, for example, Serial ATA (SATA), Serial Attached SCSI (SAS). ), NVMe (NVM Express), USB (Universal Serial Bus), UFS transport protocols, etc. Also, the memory interface 430 may communicate with the memory device to control a memory operation.

Meanwhile, according to embodiments of the present disclosure, the memory controller 400 stores the first memory 440 storing table information Info_table, the power controller 450, and setting information Info_set related to operations of various components. It may further include a second memory 460 to store, a clock generator 470 and a command/address generator 480 . Each of the first/second memories 440 and 460 may include various types of memory (eg, volatile memory), and may include, for example, memories such as DRAM, SRAM, and registers. Also, although it is illustrated that table information (Info_table) and setting information (Info_set) are stored in separate memories in FIG. 4 , the information may be described as being stored in the same memory.

The power controller 450 is configured to control power consumption of a memory system employing the memory controller 400 based on the battery information Info_BAT provided from the host and the table information Info_table stored in the first memory 440 . The information may be stored in the second memory 460 as setting information Info_set. The CPU core 410 may control power consumption by adjusting the operating characteristics of various components included in the memory system based on the setting information Info_set stored in the second memory 460 , and may control the power consumption corresponding to the battery information Info_BAT. Power consumption may be controlled so as not to exceed the maximum consumed power and average consumed power at the entry.

In an exemplary embodiment, the clock generator 470 may generate a clock signal provided to components in the memory controller 400 or a clock signal provided to the memory device, and may generate battery information ( Info_BAT), the frequency of the clock signal may be changed. As an example, consumption of maximum power and/or average power may be increased by increasing the frequency of the clock signal, and consumption of maximum power and/or average power may be decreased by decreasing the frequency of the clock signal. . In addition, the command/address generator 480 may generate a command/address (CMD/ADD) for controlling access of flash memory chips of the memory device, and by changing the number of simultaneously accessed flash memory chips, the maximum power and /or the consumption of average power may be adjusted.

5 is a diagram illustrating an operation example of an electronic device including a memory system according to an exemplary embodiment of the present disclosure.

As shown in FIG. 5 , when the electronic device is initially driven, the SSD as a memory system may provide information related to the maximum power consumption as a host. In addition, according to an exemplary embodiment, the SSD can adjust power by itself in a plurality of steps, and as an example, when the SSD can consume power by adjusting the power in N steps (N is an integer greater than or equal to 2), N steps It is possible to provide step information indicating

The host may generate table information based on the maximum power information and step information provided from the SSD and provide it to the SSD. The host may create entries based on the number of power stages that the SSD can adjust, and in an exemplary embodiment, the number of power stages may correspond to the number of entries. Each entry may include maximum consumed power information (MAX) and average consumed power information (AVG) corresponding to the battery stage, and the SSD may store table information in its internal memory.

Thereafter, as the memory system operates normally, various memory operations may be performed, and the host may periodically or aperiodically provide battery information related to the remaining battery amount to the SSD. As an example, battery information corresponding to step A indicating that the remaining amount of the battery is relatively high may be provided to the SSD. The SSD may perform an internal power setting operation based on the received battery information and table information stored therein. For example, when the remaining amount of the battery is relatively large, internal power setting may be performed to increase power consumption in the SSD, and accordingly, in response to receiving a first normal read/write (RD/WR) request from the host, A memory operation may be performed with high power (or high performance).

The SSD may provide a first request response to a first normal read/write (RD/WR) request from the host to the host, and the first normal read/write (RD/WR) operation is performed with high power (or, It can provide a request response with a relatively small latency as it is performed with high performance).

Thereafter, battery information corresponding to step B indicating that the remaining amount of the battery is relatively low may be provided to the SSD, and the SSD may perform an internal power setting operation based on the received battery information and table information stored therein. . For example, when the remaining amount of the battery is relatively low, internal power setting may be performed to reduce power consumption in the SSD, and accordingly, in response to receiving a second normal read/write (RD/WR) request from the host, A memory operation may be performed with low power (or low performance). The SSD may provide a second request response to a second normal read/write (RD/WR) request from the host to the host, and the second normal read/write (RD/WR) operation is performed with low power (or, As it is performed with low performance), it is possible to provide a request response with a relatively large latency.

6 is a diagram illustrating table information according to an exemplary embodiment of the present disclosure.

Referring to FIG. 6 , the memory system may adjust power consumption in ten steps, and based on this, the host may provide table information including a plurality of entries (eg, ten entries) to the memory system. have. In the embodiments of the present disclosure, it has been described that the number of power stages adjustable by the memory system is equal to the number of entries in the table information, but embodiments of the present disclosure are not limited thereto. For example, the table information may be implemented so that the number of entries of the table information is less than or more than the number of adjustable power stages in the memory system.

The table information may include a plurality of battery stages as entries based on the remaining amount of the battery in the electronic device. For example, when the remaining amount of the battery is 90 to 100%, the battery stage includes the information of step 1, When the remaining capacity of the battery is 80 to 90%, the battery stage may include the information from step 2, and similarly, when the remaining capacity of the battery is 0 to 10%, the battery stage may include the information from step 10. can

In addition, information related to the maximum consumed power and/or the average consumed power corresponding to each battery stage may be included in the table information, and in the embodiment shown in FIG. 6 , the maximum consumed power information and the average consumed power corresponding to each stage A case in which all information is included in table information is exemplified. For example, assuming that the value of the maximum power that can be consumed by the memory system (or the maximum power information provided by the memory system to the host) is Pm, the maximum power consumption corresponding to step 1 corresponds to Pm - M1 . can do. Also, assuming that the maximum value of average power consumption that can be consumed by the memory system during a predetermined period is Pa, the average power consumption corresponding to step 1 may correspond to Pa - A1. In this case, each of M1 and A1 may have a value of 0 or a relatively small positive value compared to other steps.

Meanwhile, in the case of step 2, the remaining battery power is smaller than that of step 1, and accordingly, the maximum power consumption corresponding to step 2 may correspond to Pm - M2, and the average power consumption may correspond to Pa - A2, and M2 is M1 larger than A2, and A2 may be larger than A1. Similarly, in the case of step 10, the remaining battery power is the smallest compared to other steps, and accordingly, the maximum power consumption corresponding to step 10 is Pm - M10, and the average power consumption may correspond to Pa - A10, M10 may have a greater value than M1 to M9, and A10 may have a greater value than A1 to A9.

7 is a block diagram illustrating an example of a power control operation of a memory controller according to an exemplary embodiment of the present disclosure.

First, as shown in FIG. 7A , the memory system may provide maximum power information MAX_PWR to the host at the initial stage of operation of the memory system, and also provide step information related to the power adjustment step. can do. The host HOST may generate table information Info_table based on the maximum power information MAX_PWR and the step information provided from the memory system.

Meanwhile, as shown in FIG. 7B , the host HOST provides the generated table information Info_table to the memory system, and the memory controller of the memory system transmits the table information Info_table to its internal memory. can be stored in Assuming that the memory system shown in FIGS. 7A to 7C is the memory controller in the above-described embodiment, the control logic shown in FIGS. may correspond to a CPU core of

In an exemplary embodiment, the table information Info_table may be implemented in various ways. For example, as described above, the table information Info_table may include a plurality of entries, and each entry may include power information corresponding to a battery level. Also, the memory system may include various types of components, and the table information Info_table may be generated for each of at least some of the components. For example, table information related to power consumed by the CPU (or CPU core), table information related to power consumed by a NAND memory (NAND) as a flash memory chip, and DRAM as a volatile memory that may be included in the memory system Table information related to power consumption may be included in table information (Info_table) from the host.

Thereafter, as shown in FIG. 7C , the host HOST may periodically or aperiodically provide the battery information Info_BAT to the memory system. The memory system may adjust power consumed by the memory system based on the battery information Info_BAT and the table information Info_table. Although it is illustrated that the control logic refers to the table information Info_table in FIG. 7C , various embodiments of the present disclosure are possible, for example, a power controller provided in the memory controller according to the above-described embodiments. Table information (Info_table) may be referred to based on control (not shown), and power consumption may also be adjusted.

Also, in an exemplary embodiment, in FIG. 7C , power consumption is controlled by adjusting the frequency of a clock signal, and the memory controller may include a clock controller. A control operation may be performed so that power is consumed based on the average power and the maximum power according to an entry in the table information Info_table corresponding to the battery information Info_BAT from the host. For example, the clock controller may adjust and output the frequency of the input clock CLK_I based on the control of the control logic. As an example, the frequency of the clock signal used in the memory controller, NAND, and DRAM as a component in the memory system is adjusted. and, through this, power consumption of the entire memory system can be controlled.

8 is a waveform diagram illustrating an example of an operation of the memory controller of FIG. 7 .

As shown in FIG. 8 , the host provides various requests or commands Req(CMD) to the memory system and, as an example, provides battery information Info_BAT to the memory system, and the memory system provides internal power based thereon. A setting operation (SET PWR) may be performed. When the battery information Info_BAT indicates that the remaining amount of the battery is relatively high, the memory system performs a setting operation so that the power consumed by the memory system has a relatively high power HIGH PWR based on entries in the table information. can do.

As relatively high power is consumed by the memory system, signals are transmitted and received with short latency between the host and the memory system. For example, read data after a relatively short latency in response to a read request from the host may be provided as a host. In addition, the clock signal CLK used in the memory system has a relatively high frequency, and when the memory system includes a plurality of NANDs, a relatively large number of NANDs (eg, 8 NANDs) are simultaneously accessed. can be

Thereafter, when the battery information Info_BAT provided from the host indicates that the remaining amount of the battery is relatively low, the memory system may perform an internal power setting operation SET PWR based thereon. A setting operation may be performed so that the consumed power has a relatively low power (LOW PWR). Accordingly, signals are transmitted and received with a long latency between the host and the memory system, and, for example, read data may be provided to the host after a relatively long latency in response to a read request from the host. In addition, the clock signal CLK used in the memory system has a relatively low frequency, and a relatively small number of NANDs (eg, four NANDs) can be simultaneously accessed in the memory system.

After that, the remaining battery power may increase due to charging of the electronic device to which the memory system is employed, and for example, when the battery information Info_BAT provided from the host indicates that the remaining battery power corresponds to an intermediate level, the memory system Based on this, the internal power setting operation SET PWR may be performed, and as an example, the setting operation may be performed so that power consumed by the memory system has a relatively medium power MIDDLE PWR. Accordingly, signals are transmitted and received with a medium latency between the host and the memory system, and, for example, read data may be provided to the host after a medium latency in response to a read request from the host. In addition, the clock signal CLK used in the memory system has an intermediate frequency, and the number of NANDs simultaneously accessed in the memory system is between 4 and 8 NANDs (eg, 6 NANDs) described above. can be accessed simultaneously.

9 is a flowchart illustrating a method of operating a memory system according to an exemplary embodiment of the present disclosure. In FIG. 9 , a case in which power consumption is controlled by adjusting operating characteristics of various components in the memory system is exemplified. In addition, although the maximum/average power consumed in the memory system is reduced according to the remaining amount of battery, FIG. 9 exemplifies a case in which performance degradation of the memory system is minimized.

As an example, the memory system may store table information provided from the host and may receive battery information having information related to the remaining battery amount from the host ( S11 ). In the following operation example, as the stage of the received battery information is lower than the current stage, the case where the maximum power and/or the average power consumed by the memory system is reduced is exemplified.

The memory system may perform memory operations such as read and write based on a request from the host, and may determine an operation pattern of the current memory system (S12). For example, an operation pattern may be determined whether a currently frequently performed memory operation corresponds to a read operation or a write operation, or whether a random write operation is frequently performed or a sequential write operation is performed in a write operation. Whether or not it is frequently performed may be determined.

As an example, it is determined whether the current operation pattern corresponds to the write pattern (S13), and when the operation pattern corresponds to the read pattern (NO), power consumption may be reduced by lowering the core performance (S14). For example, maintaining the clock frequency in a read operation of the memory system may prevent performance degradation thereof, and accordingly factors other than the clock frequency (eg, core performance) may be selected as factors for reducing power consumption. . Alternatively, according to various embodiments, even when the frequency of the clock signal is reduced, the power setting operation may be performed in the read operation so that the amount of decrease in the frequency of the clock signal is smaller than that in the write operation.

Meanwhile, when the current operation pattern corresponds to the recording pattern (YES), it may be determined whether the recording operation corresponds to the random recording pattern (S15). If the write operation corresponds to the sequential write pattern (NO), the core performance of the CPU core of the memory system may be an important factor in the performance of the memory system, and thus the core performance may be maintained ( S16 ). Meanwhile, in this case, settings for other factors may be performed to reduce power consumption, and as an example, a setting operation for reducing the frequency of a clock signal (or lowering clock performance) may be performed in FIG. 9 . have. In addition, in step S16 , the core performance may be maintained, or the degree of lowering of the core performance may be small compared to other operations (eg, a read operation, a sequential write operation, etc.).

On the other hand, when the current write operation corresponds to a random write pattern (YES), as data is randomly written to a plurality of NANDs, the number of NANDs accessed in parallel among the plurality of NANDs is an important factor in the performance of the memory system. , and thus the number of NANDs accessed in parallel may be maintained (S16). Meanwhile, in this case, settings for other factors may be performed to reduce power consumption, and as an example, a case in which the frequency of the clock signal is reduced is illustrated in FIG. 9 .

Hereinafter, an operation example of a memory system according to another embodiment of the present disclosure will be described. 10 is a diagram illustrating an operation example of an electronic device including a memory system according to another exemplary embodiment of the present disclosure.

Referring to FIG. 10 , when the electronic device is initially driven, the host may transmit information (eg, maximum power consumption information) related to the maximum power that the memory system (eg, SSD) can consume. For example, an electronic device may require different performance of devices (eg, a memory system) provided therein depending on the type thereof, and thus, in order for the memory system to operate with high performance, the maximum value having a relatively high value While power consumption information may be transmitted, maximum power consumption information having a relatively low value may be transmitted to the memory system in order to allow the memory system to operate with relatively low performance.

The memory system may set the maximum power consumption for various components therein based on the maximum power consumption information from the host. For example, the maximum power consumption of the memory system (device) may be set, and the maximum power consumption of components such as a memory controller, NAND, and DRAM provided in the memory system may be set. In an exemplary embodiment, the memory system may set the maximum power consumption of each of a plurality of components within the range of the maximum power consumption of the device, and may vary the performance of the memory controller provided in the memory system, the size of DRAM, the number of NANDs, etc. It may be possible to set the maximum power consumption of the components based on the factors.

The host may transmit a first normal read/write request to the memory system, and the memory system may perform a memory operation according to the request and transmit a first request response to the host. Also, the memory system may periodically or aperiodically detect power (device power) consumed by the memory system, and determine whether the detected device power exceeds the maximum consumed power provided by the host. As a result of the determination, when the currently consumed device power exceeds the maximum consumed power, an internal power setting operation for reducing the power consumed in the memory system may be performed.

The host may transmit a second normal read/write request to the memory system, and the memory system may perform a memory operation according to the request and transmit a second request response to the host. In this case, since power consumption in the memory system is reduced according to the internal power setting operation, the memory system may perform a memory operation according to the reduced power and generate a second request response. For example, the second request response may be transmitted with a relatively long latency compared to the above-described first request response.

Thereafter, when it is determined based on the power detection and comparison of the memory system that the consumed device power does not exceed the maximum consumed power, an internal power setting operation for increasing the power consumption in the memory system again may be performed. . Thereafter, the host may transmit a third normal read/write request to the memory system, and the memory system may perform a memory operation according to the request and transmit a third request response to the host. In this case, since power consumption in the memory system is increased according to the internal power setting operation as compared to before, the memory system may perform a memory operation according to the increased power and generate a third request response. For example, the third request response may be transmitted with a relatively short latency compared to the above-described second request response.

11 is a block diagram illustrating an example of a power control operation of the memory controller in the embodiment shown in FIG. 10 .

As shown in (a) of FIG. 11 , according to an embodiment of the present disclosure, the memory system does not transmit separate maximum power information to the host HOST, and the maximum power usable by the memory system from the host HOST Power consumption information (MAX_PWR_M) may be received. Assuming that the memory system shown in FIGS. 11A to 11C is a memory controller, each component in the memory system uses the maximum power consumption information MAX_PWR_M from the host HOST based on the control logic. A value of the maximum available power consumption may be calculated, and in the example of FIG. 11 , a case in which the value of the maximum power consumption available in the memory controller, NAND, and DRAM is calculated is exemplified. In addition, the maximum power consumption information MAX_PWR_M from the host HOST and the maximum power consumption information of each component calculated in the memory system may be stored in the memory system.

Meanwhile, as shown in FIG. 11B , the memory system may further include a power management integrated circuit (PMIC) and a power detector, and the PMIC may check power used in the memory system. In an exemplary embodiment, the PMIC may provide power used by each component, and the power detector may detect a value of power provided from the PMIC and provide it to the control logic.

Based on the control of the control logic, it may be determined whether the power consumed by the memory system exceeds the maximum power consumption information MAX_PWR_M provided from the host HOST. According to an exemplary embodiment, the control logic is configured to generate power based on whether the power consumed by the memory system (eg, the device) exceeds the maximum consumed power information MAX_PWR_M based on the power consumed by the components of the memory system. control operation can be performed. Alternatively, according to another embodiment, the control logic may perform a power adjustment operation based on whether the power consumed by each component of the memory system exceeds the maximum consumed power of each component calculated in the above-described memory system. have.

Thereafter, as illustrated in FIG. 11C , power consumed by the memory system may be adjusted based on the control of the control logic. As an example, in FIG. 11C , a case in which power consumption is adjusted by adjusting the frequency of a clock signal provided to each component is exemplified, and the sum of power consumed by the components of the memory system is the maximum power consumption information. A clock control operation may be performed so as not to exceed (MAX_PWR_M). Alternatively, in various embodiments, a clock control operation may be performed so that power consumed by each component does not exceed the maximum power consumption for each component calculated in the memory system.

12 is a block diagram illustrating an implementation example of a memory controller according to an exemplary embodiment of the present disclosure.

12 , the memory controller 500 may include a component power calculator 510 , a storage circuit 520 , a power detector 530 , and a power controller 540 . The component power calculator 510 receives the maximum power consumption information (MAX_PWR_M) from the host and the information (Info_C) related to various components provided in the memory system, and calculates the maximum power consumption information for each component based on the received information (Info_C). In this case, the maximum power consumption information MAX_PWR_M from the host and the maximum power consumption information of each component may be provided to the storage circuit 520 in the form of table information.

Meanwhile, the power detector 530 may detect power provided from the PMIC (eg, power PWR provided to each component) and provide the detection result to the power controller 540 as power information Info_P. The power controller 540 determines the components in the memory system based on the power information Info_P from the power detector 530 and the table information from the storage circuit 520 (eg, the component maximum power information Info_CP). A control operation for adjusting the consumed power may be performed, and as an example, various control operations such as a clock frequency change, a core performance change, and a change in the number of concurrently accessed NAND may be performed as in the above-described embodiments. will be. In addition, in the embodiment of FIG. 12 , the power controller 540 may be implemented separately from the CPU core, or may correspond to or include a CPU core.

13 is a flowchart illustrating an operating method of an electronic device employing a memory system according to another exemplary embodiment of the present disclosure. In FIG. 13 , the memory system may be operated with low performance or high performance according to a program (eg, an application) executed in the electronic device, and maximum power consumption information related to the memory system is changed during runtime based on the type of application. case is exemplified.

As an example, the host may execute the first application ( S21 ), and the host may determine the performance required by the memory system according to the execution of the first application, and based on this, information on maximum power consumption of the memory system can be set. The host may transmit the maximum power consumption information having the first value to the memory system, and the memory system may receive the maximum power consumption information having the first value and store it ( S22 ).

The memory system may set the maximum power consumption for various components included in the memory system based on the maximum power consumption information having the first value set for the memory system as a device, and the maximum power consumption information of the device and The maximum power consumption information of the components may be stored as table information (S23). Also, the memory system may perform a normal read/write operation in a state that does not exceed the maximum power consumption based on the maximum power consumption information having the first value from the host ( S24 ). In addition, according to the above-described embodiments, the memory system may detect power consumption, and when the consumed power exceeds the maximum power consumption information from the host, it may itself perform a control operation to reduce the power consumption. have.

Meanwhile, the host may execute a second application as another application ( S25 ), and the second application may require different performance of the memory system compared to the first application. The host may set the maximum power consumption information for the memory system according to the execution of the second application, and the memory system may receive the maximum power consumption information having the second value from the host and store it (S26).

The memory system may set the maximum power consumption for various components included in the memory system based on the maximum power consumption information having the second value set for the memory system as a device, and accordingly, the maximum consumption of the components. Power information can be changed (S27). The memory system may perform a normal read/write operation in a state that does not exceed the maximum power consumption based on the maximum power consumption information having the second value from the host ( S28 ). As an example, when the second value is greater than the first value, the memory system may operate with relatively high performance compared to when the first application is executed.

14 is a flowchart illustrating a method of operating a memory system according to another exemplary embodiment of the present disclosure.

Referring to FIG. 14 , the host may transmit the maximum power consumption information to the memory system, and as an example, the maximum power consumption information (first maximum power consumption information) in the idle period among various periods related to the memory operation of the memory system. and the maximum power consumption information (second maximum power consumption information) in the active period, and the memory system may receive the first maximum power consumption information and the second maximum power consumption information from the host and store them (S31) .

The memory system may set the maximum power consumption of the device based on the maximum power consumption information provided from the host, and may also set the maximum power consumption for each component ( S32 ). That is, the memory system may set the maximum power consumption for each component in the idle period and the maximum power consumption for each component in the active period. Preferably, the maximum power consumed by each component in the active period is the idle period. It can be set to be larger than the maximum power consumed in .

When the memory system is not accessed for a certain period or the access frequency is low, the memory system may enter an idle period ( S33 ), and the memory system may be driven in the idle period based on the first maximum power consumption information. (S34). The memory system may perform a power adjustment operation with reference to table information including maximum power information of components corresponding to the idle period, for example, the memory system may deactivate a clock signal provided to some components in the idle period, etc. The overall device power consumption can be reduced through the power adjustment operation.

Thereafter, the memory system may enter an active period (S35), and the memory system may be driven based on the second maximum power consumption information in the active period (S36). The memory system may perform a power control operation with reference to table information including information on maximum power consumption of components corresponding to the active period. For example, the memory system may activate a clock signal provided to the components in the active period. The adjustment operation may increase overall device power consumption.

15 is a flowchart illustrating a method of operating a memory system according to another exemplary embodiment of the present disclosure. 15 exemplifies a case in which power consumption is controlled by adjusting operating characteristics of various components in the memory system of the embodiment shown in FIG. 10 .

Referring to FIG. 15 , the memory system may set the maximum power consumption of the device based on the maximum power consumption information provided from the host, and may also set the maximum power consumption for each component ( S41 ). Also, the memory system may periodically or aperiodically detect device power consumed by the memory system (S42), and determine whether the consumed device power exceeds the maximum consumed power (S43). If the consumed device power does not exceed the maximum power, a separate power adjustment operation may not be performed.

On the other hand, when the device power exceeds the maximum power consumption, a power adjustment operation may be performed to adjust the power consumed by at least some components included in the memory system, and as an example, determination of various operation patterns A power adjustment operation for minimizing the degree of degradation of memory performance may be performed based on . As an example, according to the above-described embodiment, it is determined whether the current operation pattern of the memory system corresponds to the write pattern (S44), and when the operation pattern corresponds to the read pattern (NO), power is consumed by lowering the core performance may be decreased (S45).

On the other hand, if the current operation pattern corresponds to the recording pattern (YES), it may be determined whether the recording operation corresponds to the random recording pattern (S46), and if the recording operation corresponds to the sequential recording pattern (NO), the core While performance is maintained, power consumption may be reduced through other factors (S47). As an example, a setting operation of reducing the frequency of a clock signal in the memory system (or lowering clock performance) may be performed. In addition, when the current write operation corresponds to a random write pattern (YES), the number of NANDs accessed in parallel is maintained, but power consumption can be reduced through other factors, and as an example, the frequency of the clock signal is reduced. A setting operation may be performed (S48).

16 is a diagram illustrating an example of communication between a host and a memory system through various types of commands. In FIG. 16, an In-Band Command and a Side-Band Command are exemplified as various types of commands, and an SSD is exemplified as a memory system.

Referring to FIG. 16 , the data processing system 600 includes a host 610 and an SSD 620 , and various channels are disposed between the host 610 and the SSD 620 , and an in-band command is an example. Multiple channels for communication and one or more channels for side-band command communication may be deployed. According to the above-described embodiments, the SSD 620 may transmit the maximum power information MAX_PWR to the host 610 , and the host 610 may transmit the table information Info_table to the SSD 620 .

Various types of memory operations such as data write/read operations for the SSD 620 may be performed through the above-described in-band command communication, and various types of information according to embodiments of the present disclosure are transmitted through the above-described in-band command communication. can be transmitted through Various types of commands may be defined between the host 610 and the SSD 620 , and as an example, various types of information according to embodiments of the present disclosure are provided through a Set Feature command defined in a nonvolatile memory express (NVMe) interface. Transmission can be controlled.

Alternatively, in an exemplary embodiment of the present disclosure, various pieces of information may be transmitted through side-band command communication, as an example, transmitted through UART (Universal asynchronous receiver/transmitter) communication, or I2C (Inter-Integrated Circuit) communication It may be transmitted through various methods such as

17 is a perspective view illustrating a memory block included in a memory system according to an embodiment of the present disclosure; FIG. 17 illustrates a case in which any one of a plurality of memory blocks included in a cell array included in the memory device 220 of FIG. 1 is implemented as a 3D NAND (VNAND).

Referring to FIG. 17 , the memory block BLKa is formed in the vertical direction VD with respect to the substrate SUB. The substrate SUB has a first conductivity type (eg, p-type) and extends along the second horizontal direction HD2 on the substrate SUB. In an embodiment, the common source line CLS doped with impurities of the second conductivity type (eg, n-type) may be provided to the substrate SUB. In an embodiment, the substrate SUB may be implemented with polysilicon, and a plate-type common source line CSL may be disposed on the substrate SUB. On the substrate SUB, a plurality of insulating layers IL extending along the second horizontal direction HD2 are sequentially provided along the vertical direction VD, and the plurality of insulating layers IL are disposed in the vertical direction VD. ) along a certain distance. For example, the plurality of insulating layers IL may include an insulating material such as silicon oxide.

A plurality of pillars P are provided on the substrate SUB, which are sequentially disposed along the first horizontal direction HD1 and penetrate the plurality of insulating layers IL along the vertical direction VD. do. For example, the plurality of pillars P may pass through the plurality of insulating layers IL to make contact with the substrate SUB. Specifically, the surface layer S of each pillar P may include the first type silicon material and function as a channel region. Accordingly, in some embodiments, the pillar P may be referred to as a channel structure or a vertical channel structure. Meanwhile, the inner layer I of each pillar P may include an insulating material such as silicon oxide or an air gap.

A charge storage layer (CS) is provided along the exposed surfaces of the insulating layers IL, the pillars P, and the substrate SUB. The charge storage layer CS may include a gate insulating layer (also referred to as a 'tunneling insulating layer'), a charge trapping layer, and a blocking insulating layer. For example, the charge storage layer CS may have an oxide-nitride-oxide (ONO) structure. In addition, on the exposed surface of the charge storage layer CS, a gate electrode GE, such as a ground selection line GSL, a string selection line SSL, and the word lines WL1 to WL8, is provided.

Drain contacts or drains DR are provided on the plurality of pillars P, respectively. For example, the drains DR may include a silicon material doped with impurities having a second conductivity type. Bit lines BL1 to BL3 extending in the first horizontal direction HD1 and spaced apart by a specific distance along the second horizontal direction HD2 are provided on the drains DR.

18 is a block diagram illustrating a data processing system including a memory system according to embodiments of the present disclosure. As an electronic device, in a data processing system 700 such as a mobile device or a desktop computer, the memory system of the present disclosure shown in FIGS. 1 to 17 may be provided as the storage system 750 .

The data processing system 700 may further include a host 710 including an application processor and the like, a RAM 720 , a user interface 730 , and a device driver 740 , each of which includes a bus 760 . may be electrically connected to, and the storage system 750 may be connected to the device driver 740 . The host 710 may control the overall operation of the data processing system 700 and may perform processing corresponding to a user's command input through the user interface 730 . The RAM 720 may serve as a data memory of the host 710 , and the host 710 may write or read user data to or from the storage system 750 through the device driver 740 . Also, in FIG. 18 , the device driver 740 for controlling the operation and management of the storage system 750 is illustrated as being provided outside the host 710 , but the device driver 740 is provided inside the host 710 . it could be

Exemplary embodiments have been disclosed in the drawings and specification as described above. Although the embodiments have been described using specific terms in the present specification, these are used only for the purpose of explaining the technical idea of the present disclosure and not used to limit the meaning or the scope of the present disclosure described in the claims. . Therefore, it will be understood by those skilled in the art that various modifications and equivalent other embodiments are possible therefrom. Accordingly, the true technical protection scope of the present disclosure should be defined by the technical spirit of the appended claims.

Claims (20)

A method of operating a memory system, comprising:
transmitting information on maximum power consumable in the memory system to a host when the electronic device employing the memory system is initially driven;
receiving, from the host, table information including a plurality of entries, each entry including a battery level related to a remaining battery level of an electronic device employing the memory system and maximum power consumption information corresponding thereto;
receiving battery information from the host; and
adjusting power so that the power consumed in the memory system does not exceed the maximum power corresponding to the maximum power consumption information according to the maximum power consumption information of the entry corresponding to the received battery information;
The memory system includes a plurality of components, wherein the plurality of components include a CPU core and a plurality of flash memory chips,
The table information includes information calculated based on the maximum power information transmitted to the host,
The memory system adjusts the power by adjusting at least one of a clock frequency of the memory system, performance of the CPU core, and the number of simultaneously accessed flash memory chips, and controls the power of the components based on an operation pattern of the memory system. A method of operating a memory system, characterized in that differently adjusting the power for the . According to claim 1,
the memory system further transmits step information indicating an adjustable power consumption level in the memory system to the host;
The method of operating a memory system, characterized in that the number of entries included in the received table information corresponds to the number of adjustable power consumption steps in the memory system. According to claim 1,
The table information further includes information indicating average power consumed in the memory system in response to the battery stage,
The adjusting of the power comprises adjusting the power so that the power consumed by the memory system does not exceed an average power corresponding to the battery stage. delete According to claim 1,
The plurality of components further include a volatile memory,
The method of operating a memory system, wherein the table information includes table information for each of the components. 6. The method of claim 5,
The adjusting of the power comprises adjusting the power consumed by at least some of the components by referring to table information for each of the components. According to claim 1,
The operating method of the memory system, characterized in that the power is adjusted so that the power consumed in the memory system is reduced as the battery stage corresponding to the received battery information is lower than the current battery stage. The method of claim 1,
When the operation pattern of the memory system corresponds to a read operation, the clock frequency of the memory system is maintained the same when power consumed by the memory system is reduced. According to claim 1,
When the operation pattern of the memory system corresponds to a random write pattern, the number of simultaneously accessed flash memory chips is maintained the same in reducing power consumed by the memory system. . According to claim 1,
When the operation pattern of the memory system corresponds to the sequential write pattern, the performance of the CPU core is maintained the same in reducing power consumed by the memory system. A method of operating a memory system including a memory controller and a memory device, the method comprising:
receiving device maximum power consumption information to be consumed in the memory system from a host at an initial stage of operation of a system employing the memory system;
calculating component maximum power consumption information to be consumed by one or more components included in the memory system based on the received device maximum power consumption information;
storing the device maximum power consumption information and the component maximum power consumption information as table information;
detecting power consumed in the memory system; and
reducing power consumed by the memory system based on determining an operation pattern of the memory system when the detected power exceeds the device maximum power consumption information;
the memory controller includes a volatile memory, the memory device includes a plurality of flash memory chips, and the components include at least two of the memory controller, the volatile memory, and the flash memory chips;
The operating method of the memory system, characterized in that the power consumed by the components is differently adjusted according to the determination of the operation pattern of the memory system. delete 12. The method of claim 11,
The reducing of the power comprises reducing a frequency of a clock signal provided to at least one of the memory controller, the volatile memory, and the flash memory chips. 12. The method of claim 11,
The method of operating a memory system, characterized in that the reducing of the power includes adjusting the power so that the power simultaneously consumed by the components does not exceed the maximum consumed power information. 12. The method of claim 11,
When the operation pattern of the memory system corresponds to a read operation, the clock frequency of the memory system is maintained the same when power consumed by the memory system is reduced. 12. The method of claim 11,
When the operation pattern of the memory system corresponds to a random write pattern, the number of simultaneously accessed flash memory chips is maintained the same in reducing power consumed by the memory system. . 12. The method of claim 11,
The memory controller further comprises a CPU core,
When the operation pattern of the memory system corresponds to a sequential write pattern, the performance of the CPU core is maintained the same in reducing power consumed by the memory system. A memory controller, wherein the memory controller communicates with a host and a memory device including a plurality of flash memory chips, respectively;
a CPU core for controlling a memory operation for the memory device; and
Table information received from the host and including a plurality of entries, each entry including a battery level related to a remaining battery amount of an electronic device to which a memory system including the memory controller is employed, and maximum power consumption information corresponding thereto and a storage circuit for storing,
The memory controller is configured to transmit, to the host, information on maximum power consumable in the memory system in relation to generation of the table information when the electronic device employing the memory system is initially driven, and from the host to a first one of the entries Receive battery information corresponding to an entry, and set a clock frequency of the memory system such that power consumed in the memory system does not exceed a maximum power corresponding to the maximum power consumption information of the first entry set by the host, the CPU Adjusting the power by adjusting at least one of the performance of the core and the number of concurrently accessed flash memory chips,
The received table information includes information calculated based on the maximum power information transmitted to the host. 19. The method of claim 18,
The table information is received through communication according to an in-band command of the memory system, or is received through communication according to a side-band command of a UART (Universal asynchronous receiver/transmitter) or I2C (Inter-Integrated Circuit). memory controller. 19. The method of claim 18,
wherein the memory controller selectively receives the battery information from the host when the battery level is changed due to a change in the remaining amount of the battery.

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