KR102457807B1 - Semiconductor chip with a plurality of pads - Google Patents

Abstract

A semiconductor chip including a plurality of input/output units according to an embodiment of the present invention may include a plurality of additional pads and a plurality of pads. The plurality of additional pads may be disposed along the first row or the second row on the surface of the semiconductor chip, and the plurality of pads may be disposed along the surface of the semiconductor chip. The plurality of additional pads may include a first additional pad to which a ground voltage is input or a second additional pad to which a power voltage is input, and the plurality of pads include a first pad to which a ground voltage is input, and a second additional pad to which a power voltage is input. It may include a pad or a third pad to which a signal is input or output. The first additional pad or the second additional pad may be disposed on an input/output unit in which a third pad is disposed among the plurality of input/output units.

Description

A semiconductor chip including a plurality of pads

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor chip, and more particularly, to an arrangement of pads of a semiconductor chip mounted by a flip-chip method.

In general, a semiconductor chip may be mounted on a package substrate by a wire bonding method or a flip chip method. When the semiconductor chip is mounted by the flip-chip method, the semiconductor chip may include a plurality of pads for receiving power or for transmitting and receiving signals. These pads may be disposed on a semiconductor chip.

However, it is very important to sufficiently supply power to the semiconductor chip in order to prevent an increase in simultaneous switching noise (SSN) of the signal in the process of transmitting and receiving the signal. However, if the number of pads to which power is supplied is increased to sufficiently supply power to the semiconductor chip, this may result in an increase in the chip size. On the other hand, if you reduce the number of pads to which power is supplied, this may result in an increase in SSN. Therefore, it is very important to efficiently arrange the pads to supply sufficient power to the semiconductor chip without increasing the size of the semiconductor chip.

The technical idea of the present invention provides a method of arranging pads of a semiconductor chip that enables stable power supply.

The technical idea of the present invention provides a method of arranging pads of a semiconductor chip capable of reducing a chip size.

In a semiconductor chip according to an embodiment of the present invention, a plurality of additional pads are disposed along a first row or a second row on a surface of the semiconductor chip, and the plurality of additional pads are first additional pads to which a ground voltage is input. or a second additional pad to which a power voltage is input, and a plurality of pads disposed on a surface of the semiconductor chip, wherein the plurality of pads include a first pad to which the ground voltage is input, and a first pad to which the power voltage is input. an input/output unit in which the third pad is disposed among the plurality of input/output units, wherein the first additional pad or the second additional pad includes a second pad to be used, or a third pad to which a signal is input or output. may be placed on the

For example, a first conductive ring may be disposed inside the semiconductor chip under the first additional pad, and the first additional pad and the first conductive ring may be electrically connected. In addition, the first pad may be electrically connected to the first conductive ring.

For example, a second conductive ring may be disposed inside the semiconductor chip under the second additional pad, and the second additional pad and the second conductive ring may be electrically connected to each other. In addition, the second pad may be electrically connected to the second conductive ring.

For example, the semiconductor chip may further include an input/output buffer disposed inside the semiconductor chip at a lower end of an input/output unit in which a third pad is disposed among the input/output units to receive the signal.

For example, the semiconductor chip may be connected to the first additional pad or a first bump region connected to the first pad through a first conductive line, and the second additional pad or the second pad through a second conductive line. It may further include a second bump region connected to and a third bump region connected to the third pad through a third conductive line.

For example, the semiconductor chip may be mounted on a package substrate by a flip-chip method.

A semiconductor chip including a plurality of input/output units according to an embodiment of the present invention includes a plurality of pads disposed on a surface of the semiconductor chip, wherein the plurality of pads are disposed along a first row and receive a ground voltage. a first pad, a second pad disposed along the second row and to which a power supply voltage is input, or a third pad disposed along the third row and to which a signal is input or output, and disposed on a surface of the semiconductor chip a plurality of additional pads to be used, wherein the plurality of additional pads include a first additional pad to which the ground voltage is input or a second additional pad to which the power voltage is input, wherein the first additional pad includes the plurality of additional pads. Among the input/output units, the second pad may be disposed on an input/output unit, and the second additional pad may be disposed on an input/output unit on which the first pad is disposed among the plurality of input/output units.

For example, a first conductive ring may be disposed inside the semiconductor chip under the first pad, and the first pad and the first conductive ring may be electrically connected to each other. In addition, the first additional pad may be electrically connected to the first conductive ring.

For example, a second conductive ring may be disposed inside the semiconductor chip under the second pad, and the second pad and the second conductive ring may be electrically connected to each other. In addition, the second additional pad may be electrically connected to the second conductive ring.

For example, the semiconductor chip may further include an input/output buffer disposed inside the semiconductor chip at a lower end of an input/output unit in which a third pad is disposed among the input/output units to receive the signal.

For example, the semiconductor chip may be connected to the first additional pad or a first bump region connected to the first pad through a first conductive line, and the second additional pad or the second pad through a second conductive line. It may further include a second bump region connected to and a third bump region connected to the third pad through a third conductive line.

According to an embodiment of the present invention, it is possible to provide a method of arranging pads of a semiconductor chip that enables stable power supply.

According to an embodiment of the present invention, a method of arranging pads of a semiconductor chip capable of reducing a chip size may be provided.

1 is a plan view of a semiconductor chip according to an embodiment of the present invention.
FIG. 2 is a diagram schematically illustrating an enlarged area of FIG. 1 .
3 is a plan view illustrating a part of a semiconductor chip according to an embodiment of the present invention.
4A is a cross-sectional view taken along line A-A' of FIG. 3 .
4B is a cross-sectional view taken along line B-B' of FIG. 3 .
4C is a cross-sectional view taken along line C-C' of FIG. 3 .
5A is a cross-sectional view taken along line D-D' of FIG. 3 .
5B is a cross-sectional view taken along line E-E' of FIG. 3 .
5C is a cross-sectional view taken along line F-F' of FIG. 3 .
5D is a cross-sectional view taken along line G-G' of FIG. 3 .
6 is a view showing a part of FIG. 3 three-dimensionally by combining FIGS. 4A to 5D.
7 is a diagram schematically illustrating a part of a semiconductor chip according to another embodiment of the present invention.
8 is a plan view illustrating a part of a semiconductor chip according to an embodiment of the present invention.
9A is a cross-sectional view taken along line A-A' of FIG. 8 .
9B is a cross-sectional view taken along line B-B' of FIG. 8 .
9C is a cross-sectional view taken along line C-C' of FIG. 8 .
10A is a cross-sectional view taken along line D-D' of FIG. 8 .
10B is a cross-sectional view taken along line E-E' of FIG. 8 .
10C is a cross-sectional view taken along line F-F' of FIG. 8 .
11 is a view showing a part of FIG. 8 three-dimensionally by combining FIGS. 9A to 10C.
12 is a diagram schematically illustrating a part of a semiconductor chip according to another embodiment of the present invention.
13 is a plan view illustrating a part of a semiconductor chip according to an embodiment of the present invention.
14A is a cross-sectional view taken along line A-A' of FIG. 13 .
14B is a cross-sectional view taken along line B-B' of FIG. 13 .
14C is a cross-sectional view taken along line C-C' of FIG. 13 .
15A is a cross-sectional view taken along line D-D' of FIG. 13 .
15B is a cross-sectional view taken along line E-E' of FIG. 13 .
15C is a cross-sectional view taken along line F-F' of FIG. 13 .
FIG. 16 is a three-dimensional view of a part of FIG. 13 by combining FIGS. 14A to 15C .

It is to be understood that both the foregoing general description and the following detailed description are exemplary, and it is to be considered that an additional description of the claimed invention is provided. Reference signs are indicated in detail in preferred embodiments of the present invention, examples of which are indicated in the reference drawings. Wherever possible, the same reference numbers are used in the description and drawings to refer to the same or like parts.

When an element or layer is referred to as being “connected”, “coupled to,” or “adjacent to” another element or layer, it refers to being directly connected to, coupled to, or adjacent to the other element or layer. may mean, or may mean indirectly connected, coupled, or adjacent to another element or layer interposed therebetween. As used herein, the term “and/or” shall include one or more possible combinations of the listed elements.

Although terms such as "first", "second", etc. may be used herein to describe various elements, these elements are not limited by these terms. These terms may only be used to distinguish one component from others. Accordingly, terms such as a first component, a section, and a layer used in this specification may be used as a second component, a section, a layer, etc. without departing from the spirit of the present invention.

The terminology described herein is used only for the purpose of describing specific embodiments, and is not limited thereto. A term such as “a” is to be understood to include plural forms unless explicitly indicated otherwise. Terms such as “comprising” or “consisting of” specify the presence of a described feature, step, operation, component, and/or component, and include additional one or more features, steps, operations, components, components, and /or do not exclude the existence of their group.

Hereinafter, embodiments of the present invention will be described with reference to the accompanying drawings so that those of ordinary skill in the art to which the present invention pertains can easily implement the technical idea of the present invention.

1 is a plan view of a semiconductor chip 100 according to an embodiment of the present invention. The semiconductor chip 100 may be mounted on a package substrate or another semiconductor chip by a flip-chip method. A plurality of pads may be provided on one surface of the semiconductor chip 100 , and the plurality of pads may include first pads 112 to which a ground voltage is supplied, second pads 122 to which a power voltage is supplied, and a signal to receive a signal. It may include input or output third pads 132 . For example, a signal input/output through the third pads 132 may be a data signal or a control signal for controlling the semiconductor chip 100 .

The first pads 112 may be connected to the at least one first bump region 140_1 through the first conductive lines 110 . Although one first bump region 140_1 is illustrated in the drawing, a plurality of first bump regions not shown may be further provided. The second pads 122 may be connected to the at least one second bump region 140_2 through the second conductive lines 120 . Although one second bump region 140_2 is illustrated in the drawing, a plurality of second bump regions not shown may be further provided. The third pads 132 may be connected to the at least one third bump region 140_3 through the third conductive lines 130 . Although one third bump region 140_3 is illustrated in the drawing, a plurality of third bump regions not shown may be further provided.

A first bump (not shown) may be connected to the first bump region 140_1 . For example, the first bump (not shown) connects the semiconductor chip 100 to another semiconductor chip (not shown) or a package substrate (not shown) attached by the flip-chip method to the semiconductor chip 100 . can That is, the ground voltage provided through the first bump region 140_1 may be transferred to the first pads 112 through the first conductive lines 110 .

A second bump (not shown) may be connected to the second bump region 140_2 . For example, the second bump (not shown) connects the semiconductor chip 100 to another semiconductor chip (not shown) or a package substrate (not shown) attached by the flip-chip method to the semiconductor chip 100 . can That is, the power voltage provided through the second bump region 140_2 may be transferred to the second pads 122 through the second conductive lines 120 .

A third bump (not shown) may be connected to the third bump region 140_3 . For example, the third bump (not shown) connects the semiconductor chip 100 to another semiconductor chip (not shown) or a package substrate (not shown) attached by the flip-chip method to the semiconductor chip 100 . can That is, the power voltage provided through the third bump region 140_3 may be transferred to the third pads 132 through the third conductive lines 130 .

The connection relationship between the bump regions 140_1 to 140_3 and the conductive lines 110 to 130 illustrated in the drawings is exemplary and is not limited as illustrated in the drawings. In addition, a detailed arrangement method of the first pads 112 to the third pads 132 according to an embodiment of the present invention will be described in detail with reference to the drawings below.

FIG. 2 is a diagram schematically illustrating an enlarged area of FIG. 1 . For simplicity of description, conductive lines connecting the bump regions 140_1 to 140_3 and the pads 112 to 132 are omitted in this figure. Instead, ring-type conductive rings 116 and 126 disposed inside the semiconductor chip 100 are shown.

Referring to FIG. 2 , the semiconductor chip 100 may include a plurality of input/output units. Illustratively, 13 input/output units are shown in the drawing. Each input/output unit may include at least one pad. For example, the first input/output unit I/O unit_1 is illustrated as including one second pad 122 and one third pad 132 . In particular, the input/output unit including the third pad 132 to which a signal is input or output among I/O units further includes an input/output buffer (not shown) inside the semiconductor chip 100 at the lower end thereof. can do. In addition, the ground voltage supplied through the first pads 112 and 112A and the power voltage supplied through the second pads 122 and 122A are supplied to the input/output buffer (not shown), so that the signal SSN (simultaneous switching) is supplied. noise) can be prevented from increasing.

The first pads 112 may be disposed along a third row Row3 parallel to the second direction D2 . However, some of the first pads 112 may be disposed along the first row Row1 parallel to the second direction D2 , which is illustrated as the first additional pad 112A. The second pads 122 may also be disposed along a third row Row3 parallel to the second direction D2 . However, some of the second pads 122 may be disposed in a second row Row2 parallel to the second direction D2 , which is illustrated as a second additional second pad 122A. The third pads 132 may be disposed along the third row Row3 .

Although the drawing shows that the first pad 112 , the second pad 122 , and the third pad 132 are arranged in the same row, they are not necessarily arranged in the same row. However, it is sufficient if the first pad 112 , the first additional pad 112A, the second pad 122 , and the second additional pad 122A are respectively arranged in different rows.

The first conductive ring 116 may be disposed inside the semiconductor chip 100 under the first row Row1 . That is, the first conductive ring 116 may extend along the first row Row1 . Although only a portion of the first conductive ring 116 is illustrated because only a portion of the semiconductor chip 100 is illustrated in the drawing, the first conductive ring 116 may be disposed to form a closed curve inside the semiconductor chip 100 . . The first conductive ring 116 may be connected to the first pad 112 and the first additional pad 112A through internal wirings (not shown).

The second conductive ring 126 may be disposed inside the semiconductor chip 100 under the second row Row2 . That is, the second conductive ring 126 may extend along the second row Row2 . Similarly, although only a portion of the second conductive ring 126 is illustrated, the second conductive ring 126 may be disposed to form a closed curve inside the semiconductor chip 100 . The second conductive ring 126 may be connected to the second pad 122 and the second additional pad 122A through internal wirings (not shown).

According to an embodiment of the present invention, the input/output unit including the third pad 132 that receives a signal from the outside may include the first pad 112 and/or the second pad 122 . In this case, the first pad 112 and the second pad 122 may be disposed in a row different from that of the third pad 132 . That is, at least two or more pads may be provided in one input/output unit, and in this case, the at least two pads may be disposed along the first direction D1. However, in order to prevent a short circuit that may occur between the two conductive rings 116 and 126 connected to the pads, the direction in which at least two pads disposed in one input/output unit are disposed is exactly the first direction D1 . may not match. According to this arrangement method, instead of having a separate input/output unit for supplying a ground voltage and a power supply voltage, one additional pad 112A and/or a second addition to the input/output unit on which the third pad 132 is already disposed A pad 122A may be disposed. As a result, the ground voltage and the power voltage can be stably supplied to the input/output unit without reducing the pads to which the ground voltage and the power voltage are supplied, and the chip size can be reduced.

3 is a plan view illustrating a part of the semiconductor chip 100 according to an embodiment of the present invention. 4A is a cross-sectional view taken along line A-A' of FIG. 3 . 4B is a cross-sectional view taken along line B-B' of FIG. 3 . 4C is a cross-sectional view taken along line C-C' of FIG. 3 . 5A is a cross-sectional view taken along line D-D' of FIG. 3 . 5B is a cross-sectional view taken along line E-E' of FIG. 3 . 5C is a cross-sectional view taken along line F-F' of FIG. 3 . 5D is a cross-sectional view taken along line G-G' of FIG. 3 .

3 to 5D , the first pads 112 may be disposed along the first row Row1 . In addition, a first conductive ring 116 may be disposed inside the semiconductor chip 100 under the first additional pads 112A. The first additional pads 112A may be connected to the first conductive ring 116 through the first additional internal wirings 114A. A depth at which the first conductive ring 116 is disposed in the semiconductor chip 100 may be h1. At this time, as shown in the drawing, the first additional pads 112A and the first conductive ring 116 may be connected to have the shortest distance. That is, the length at which each of the first additional pads 112A is connected to the first conductive ring 116 may be h1.

The second additional pads 122A may be disposed along the second row Row2 . In addition, a second conductive ring 126 may be disposed inside the semiconductor chip 100 under the second additional pads 122A. The second additional pads 122A may be connected to the second conductive ring 126 through the second additional internal wirings 124A. A depth at which the second conductive ring 126 is disposed in the semiconductor chip 100 may be h1. In this case, as shown in the drawing, the second additional pads 122A and the second conductive ring 126 may be connected to have the shortest distance. That is, the length at which each of the second additional pads 122A is connected to the second conductive ring 126 may be h2. For example, the lengths of h1 and h2 may be the same, but may be different from each other.

The third pads 132 may be disposed along the third row Row3 . The third internal wirings 134 may connect the third pads 132 to a logic circuit (not shown), and a signal input through the third pads 132 may be applied to the third internal wirings 134 . may be transmitted to a logic circuit (not shown) through Although the drawings show that the third internal wirings 134 penetrate the semiconductor chip 100 , this is for the sake of simplicity of description, and the third internal wirings 134 are disposed inside the semiconductor chip 100 . connected to a logic circuit (not shown).

The first pad 112 and the second pad 122 may be disposed along the third row Row3 . The first internal wiring 114 may connect the first pad 112 to the first conductive ring 116 . However, in order to prevent a short circuit that may occur between the first internal wiring 114 and the second conductive ring 126 , the first internal wiring 114 is arranged in a 'U' shape as shown in the drawings. can be In addition, the second internal wiring 124 may connect the second pad 122 to the second conductive ring 126 . Similarly, in order to prevent a short circuit that may occur between the second inner wiring 124 and the first conductive ring 116, the second inner wiring 124 is arranged in a 'U' shape as shown in the drawings. can be

6 is a view showing a part of FIG. 3 three-dimensionally by combining FIGS. 4A to 5D.

Referring to FIG. 6 , the first additional pad 112A is disposed along the first row Row1 , and the first conductive ring 116 is disposed inside the semiconductor chip 100 under the first additional pad 112A. it can be seen that In addition, the first additional pad 112A and the first conductive ring 116 are connected by the first additional internal wiring 114A to have the shortest distance. In addition, the first pad 112 is disposed along the third row Row3 . It can be seen that the first pad 112 is connected to the first conductive ring 116 by the first internal wiring 114 having a 'U' shape. This is to prevent a short circuit that may occur between the first conductive ring 116 and the second conductive ring 126 , so the shape of the first internal wiring 114 is not limited to the 'U' shape, and prevents a short circuit. It can take many different forms.

Also, it can be seen that the second additional pads 122A are disposed along the second row Row2 , and the second conductive ring 126 is disposed inside the semiconductor chip 100 under the second additional pad 122A. have. In addition, the second additional pad 122A and the second conductive ring 126 are connected by the second additional internal wiring 124A to have the shortest distance. In addition, the second pad 122 is disposed along the third row Row3 . It can be seen that the second pad 122 is connected to the second conductive ring 126 by the second internal wiring 124 having a 'U' shape. Similarly, since this is to prevent a short circuit that may occur between the first conductive ring 116 and the second conductive ring 126 , the shape of the second internal wiring 124 is not limited to a 'U' shape, and the short circuit Various forms can be taken to prevent

Summarizing the above-described configuration, the first pad 112 and the first additional pad 112A disposed in the first row Row1 and the third row Row3 are connected to the first conductive ring 116, The second pad 122 and the second additional pad 122S disposed in the second row Row2 and the third row Row3 may be connected to the second conductive ring 126 . The first conductive ring 116 and the second conductive ring 126 may be connected to an electrostatic discharge circuit (ESD) circuit (not shown) disposed inside the semiconductor chip 100 . The ESD circuit (not shown) is connected to a logic circuit (not shown) disposed inside the semiconductor chip 100 to stably supply power to the logic circuit (not shown). In addition, the third pads 132 may be connected to a logic circuit (not shown) disposed inside the semiconductor chip 100 through third internal wirings 134 .

According to this arrangement method, instead of having a separate input/output unit for supplying the ground voltage and the power voltage, the first additional pad 112A and/or the second input/output unit in which the third pad 132 is already disposed. Additional pads 122A may be disposed. In this case, the first additional pad 112A and/or the second additional pad 122A are disposed in the first row Row1 or the second row Row2 of the input/output unit in which the third pad 132 is disposed. Accordingly, since the ground voltage and the power voltage can be sufficiently supplied without reducing the number of pads for supplying the ground voltage and the power voltage, the SSN of the signal input through the third pad 132 can be reduced. In addition, since there is no need to provide a separate input/output unit for supplying the ground voltage and the power voltage, the chip size can be reduced.

7 is a diagram schematically illustrating a part of a semiconductor chip according to another embodiment of the present invention. As described above, a ground voltage may be supplied through the first pads 212 , a power voltage may be supplied through the second pads 222 , and signals may be provided through the third pads 232 . have. For simplicity of description, conductive lines connecting the bump regions 240_1 to 240_3 and the pads 212 to 232 are omitted in this figure. Instead, ring-type conductive rings 216 and 226 disposed inside the semiconductor chip are shown.

Referring to the drawings, a semiconductor chip may include a plurality of input/output units (I/O units). Illustratively, 13 input/output units are shown in the drawing. Each input/output unit may include at least one pad. For example, the fifth input/output unit I/O unit_5 is illustrated as including one first additional pad 212A and one second pad 222 . In particular, the input/output unit including the third pad 232 to which a signal is input or output among the input/output units may further include an input/output buffer (not shown) inside the semiconductor chip at the lower end thereof. .

The first pads 212 may be disposed along a first row Row1 parallel to the second direction D2 . The second pads 222 may be disposed along a second row Row2 parallel to the second direction D2 . The third pads 232 may be disposed along a third row Row3 parallel to the second direction D2 . However, some of the first pads 212 may be disposed along the third row Row3 , which is a row in which the third pads 232 are disposed, which is illustrated as the first additional pad 212A. However, the first additional pad 212A is not necessarily arranged in the third row Row3 , and the first additional pad 212A is arranged in a row other than the first row Row1 and the second row Row2 . it is enough

The first conductive ring 216 may be disposed inside the semiconductor chip at the lower end of the first row Row1 . That is, the first conductive ring 216 may extend along the first row Row1 . Although only a portion of the first conductive ring 216 is illustrated because only a portion of the semiconductor chip is illustrated in the drawing, the first conductive ring 216 may be disposed to form a closed curve inside the semiconductor chip. The first conductive ring 216 may be connected to the first pads 212 through internal wirings (not shown).

The second conductive ring 226 may be disposed inside the semiconductor chip under the second row Row2 . That is, the second conductive ring 226 may extend along the second row Row2 . Similarly, although only a portion of the second conductive ring 226 is illustrated, the second conductive ring 226 may be disposed to form a closed curve inside the semiconductor chip. The second conductive ring 226 may be connected to the second pads 222 through internal wirings (not shown).

According to the present embodiment, instead of providing a separate input/output unit to include the pads receiving the ground voltage, the pad receiving the ground voltage may be disposed in the input/output unit in which the pad receiving the power voltage is disposed. For example, referring to FIG. 7 , the first additional pad 212A is disposed in a fifth input/output unit I/O Unit_5 separately provided to receive a power voltage. In this case, instead of disposing the pad in a separate input/output unit to receive the ground voltage, the first additional pad 212A may be disposed in the fifth input/output unit I/O Unit_5 . As described above, by simultaneously disposing the first additional pad 212A and the second pad 222 in one input/output unit, the SSN of a signal input through the third pad 232 can be reduced. In addition, the size of the semiconductor chip can be reduced.

8 is a plan view illustrating a part of a semiconductor chip according to an embodiment of the present invention. 9A is a cross-sectional view taken along line A-A' of FIG. 8 . 9B is a cross-sectional view taken along line B-B' of FIG. 8 . 9C is a cross-sectional view taken along line C-C' of FIG. 8 . 10A is a cross-sectional view taken along line D-D' of FIG. 8 . 10B is a cross-sectional view taken along line E-E' of FIG. 8 . 10C is a cross-sectional view taken along line F-F' of FIG. 8 .

8 to 10C , the first pads 212 may be disposed along the first row Row1 . In addition, a first conductive ring 216 may be disposed inside the semiconductor chip 200 under the first pads 212 . The first pads 212 may be connected to the first conductive ring 216 through the first internal wirings 214 . A depth at which the first conductive ring 216 is disposed in the semiconductor chip may be h1. At this time, as shown in the drawing, the first pads 212 and the first conductive ring 216 may be connected to have the shortest distance. That is, the length at which each of the first pads 212 is connected to the first conductive ring 216 may be h1.

Some of the first pads 212 may be disposed in the third row Row3 , which is denoted as the first additional pad 212A. The first additional internal wiring 214A may connect the first additional pad 212A to the first conductive ring 216 . The first additional internal wiring 214A may be arranged in a 'U' shape as shown in the drawing.

The second pads 222 may be disposed along the second row Row2 . In addition, a second conductive ring 226 may be disposed inside the semiconductor chip 200 under the second pads 222 . The second pads 222 may be connected to the second conductive ring 226 through second internal wirings 224 . A depth at which the second conductive ring 226 is disposed in the semiconductor chip 200 may be h2. At this time, as shown in the drawing, the second pads 222 and the second conductive ring 226 may be connected to have the shortest distance. That is, the length at which each of the second pads 122 is connected to the second conductive ring 126 may be h2. The lengths of h1 and h2 may be the same, but may be different from each other.

The third pads 232 may be disposed along the third row Row3 . The third internal wirings (not shown) may connect the third pads 232 to a logic circuit (not shown), and a signal input through the third pads 232 may be transmitted through the third internal wirings (not shown). time) through a logic circuit (not shown).

11 is a view showing a part of FIG. 8 three-dimensionally by combining FIGS. 9A to 10C.

Referring to FIG. 11 , the first pad 212 is disposed along the first row Row1 , and the first conductive ring 216 is disposed inside the semiconductor chip 200 under the first pad 212 . The first pad 212 and the first conductive ring 216 are connected by the first internal wiring 214 to have the shortest distance. In addition, the first additional pad 212A is disposed along the third row Row3 . It can be seen that the first additional pad 212A is connected to the first conductive ring 216 by the first additional internal wiring 214A having a 'U' shape. The shape of the first additional internal wiring 214A is not limited to the 'U' shape and may take various forms.

The second pads 222 are disposed along the second row Row2 , and the second conductive ring 226 is disposed inside the semiconductor chip 200 under the second pad 222 . In addition, the second pad 122 and the second conductive ring 226 are connected by the second internal wiring 224 to have the shortest distance.

In addition, third pads 232 are disposed along the third row Row3 , and the third pads 232 may be connected to a logic circuit (not shown) through third internal wirings 234 .

Summarizing the above configuration, the first pad 212 and the first additional pad 212A disposed in the first row Row1 and the third row Row3 are connected to the first conductive ring 216, The second pad 222 disposed in the second row Row2 may be connected to the second conductive ring 226 . The first conductive ring 216 and the second conductive ring 226 may be connected to an ESD circuit (not shown) disposed inside the semiconductor chip 200 . The ESD circuit (not shown) is connected to a logic circuit (not shown) disposed inside the semiconductor chip 200 to stably supply power to the logic circuit (not shown). In addition, the third pads 232 may be connected to a logic circuit (not shown) disposed inside the semiconductor chip 200 through third internal wirings 234 .

According to this arrangement method, instead of having a separate input/output unit for supplying the ground voltage, the input/output unit (eg, I/O Unit_5) in which the second pad 222 for supplying the power supply voltage is already arranged. A first additional pad 212A may be disposed on the . That is, since the power supply voltage can be sufficiently supplied without a separate input/output unit for supplying the ground voltage, the SSN of the signal input through the third pad 232 can be reduced. In addition, since there is no need to provide a separate input/output unit for supplying the ground voltage and the power voltage, the chip size can be reduced.

12 is a diagram schematically illustrating a part of a semiconductor chip according to another embodiment of the present invention. As described above, a ground voltage may be supplied through the first pads 312 , a power voltage may be supplied through the second pads 322 , and signals may be provided through the third pads 332 . have. For simplicity of description, conductive lines connecting the bump regions 340_1 to 340_3 and the pads 312 to 332 are omitted in this figure. Instead, ring-type conductive rings 316 and 326 disposed inside the semiconductor chip are shown.

Referring to the drawings, a semiconductor chip may include a plurality of input/output units (I/O units). Each input/output unit may include at least one pad. For example, the fifth input/output unit I/O unit_5 is illustrated as including one first pad 312 and one second pad 322A. In particular, the input/output unit including the third pad 332 to which a signal is input or output among the input/output units may further include an input/output buffer (not shown) in the lower semiconductor chip. .

The first pads 312 may be disposed along a first row Row1 parallel to the second direction D2 . The second pads 322 may be disposed along a second row Row2 parallel to the second direction D2 . However, some of the second pads 322 may be disposed along the third row Row3 , which is a row in which the third pads 332 are disposed, which is illustrated as the second additional pad 322A. The third pads 332 may be disposed along a third row Row3 parallel to the second direction D2 . However, the second additional pad 322A is not necessarily arranged in the third row Row3 , and the second additional pad 322A is arranged in a row other than the first row Row1 and the second row Row2 . it is enough

The first conductive ring 316 may be disposed inside the semiconductor chip at the bottom of the first row Row1 . That is, the first conductive ring 316 may extend along the first row Row1 . Although only a portion of the first conductive ring 316 is illustrated because only a portion of the semiconductor chip is illustrated in the drawing, the first conductive ring 316 may be disposed to form a closed curve inside the semiconductor chip. The first conductive ring 316 may be connected to the first pads 312 through internal wirings (not shown).

The second conductive ring 326 may be disposed inside the semiconductor chip at the bottom of the second row Row2 . That is, the second conductive ring 326 may extend along the second row Row2 . Similarly, although only a portion of the second conductive ring 326 is illustrated, the second conductive ring 326 may be disposed to form a closed curve inside the semiconductor chip. The second conductive ring 326 may be connected to the second pads 322 through internal wirings (not shown).

According to the present embodiment, instead of providing a separate input/output unit to include the pads receiving the power voltage, the pad receiving the power voltage may be disposed in the input/output unit in which the pad receiving the ground voltage is disposed. For example, referring to FIG. 12 , the second additional pad 322A is disposed in the fifth input/output unit I/O Unit_5 separately provided to receive the ground voltage. That is, instead of providing a separate input/output unit for receiving the power voltage, the second additional pad 322A may be disposed in the fifth input/output unit I/O Unit_5 in which the pad for receiving the ground voltage is disposed. have. As described above, by simultaneously disposing the first pad 312 and the second additional pad 322A in one input/output unit, the SSN of a signal input through the third pad 332 can be reduced. In addition, the size of the semiconductor chip can be reduced.

13 is a plan view illustrating a part of a semiconductor chip according to an embodiment of the present invention. 14A is a cross-sectional view taken along line A-A' of FIG. 13 . 14B is a cross-sectional view taken along line B-B' of FIG. 13 . 15A is a cross-sectional view taken along line C-C' of FIG. 13 . 16A is a cross-sectional view taken along line D-D' of FIG. 13 . FIG. 16B is a cross-sectional view taken along line E-E' of FIG. 13 . 16C is a cross-sectional view taken along line F-F' of FIG. 13 .

13 to 15C , the first pads 312 may be disposed along the first row Row1 . In addition, a first conductive ring 316 may be disposed inside the semiconductor chip 300 under the first pads 312 . The first pads 312 may be connected to the first conductive ring 316 through the first internal wirings 314 . A depth at which the first conductive ring 316 is disposed in the semiconductor chip may be h1. At this time, as shown in the drawing, the first pads 312 and the first conductive ring 316 may be connected to have the shortest distance. That is, the length at which each of the first pads 312 is connected to the first conductive ring 316 may be h1.

The second pads 322 may be disposed along the second row Row2 . In addition, a second conductive ring 326 may be disposed inside the semiconductor chip 300 under the second pads 322 . The second pads 322 may be connected to the second conductive ring 326 through second internal wirings 324 . A depth at which the second conductive ring 326 is disposed in the semiconductor chip 300 may be h2. In this case, as shown in the drawing, the second pads 322 and the second conductive ring 326 may be connected to have the shortest distance. That is, the length at which each of the second pads 322 is connected to the second conductive ring 326 may be h2.

In this case, some of the second pads 322 may be disposed in the third row Row3 , which is indicated as the second additional pad 322A. The second additional internal wiring 324A may connect the second additional pad 322A to the second conductive ring 326 . The second additional internal wiring 324A may be arranged in an 'L' shape as shown in the drawing.

The third pads 332 may be disposed along the third row Row3 . The third internal wirings (not shown) may connect the third pads 332 to a logic circuit (not shown), and a signal input through the third pads 332 may be transmitted through the third internal wirings (not shown). time) through a logic circuit (not shown).

FIG. 16 is a three-dimensional view of a part of FIG. 13 by combining FIGS. 14A to 15C .

Referring to FIG. 16 , first pads 312 are disposed along a first row Row1 , and a first conductive ring 316 is disposed inside the semiconductor chip 300 under the first pads 312 . became The first pad 312 and the first conductive ring 316 are connected by the first internal wiring 314 to have the shortest distance.

Second pads 322 are disposed along the second row Row2 , and a second conductive ring 326 is disposed inside the semiconductor chip 300 under the second pad 322 . In addition, the second pad 322 and the second conductive ring 326 are connected by the second internal wiring 324 to have the shortest distance. In addition, the second additional pad 322A is disposed along the third row Row3 . It can be seen that the second additional pad 322A is connected to the second conductive ring 326 by a second additional internal wiring 324A having an 'L' shape. The shape of the second additional internal wiring 324A is not limited to the 'L' shape and may take various forms.

In addition, third pads 332 are disposed along the third row Row3 , and the third pads 332 may be connected to a logic circuit (not shown) through third internal wirings 334 .

Taking the above-described configuration together, the first pad 312 disposed in the first row Row1 is connected to the first conductive ring 316 , and the second additional pad 322A disposed in the third row Row3 . ) may be connected to the second conductive ring 326 . The first conductive ring 316 and the second conductive ring 326 may be connected to an ESD circuit (not shown) disposed inside the semiconductor chip 300 . The ESD circuit (not shown) is connected to a logic circuit (not shown) disposed inside the semiconductor chip 300 to stably supply power to the logic circuit (not shown). In addition, the third pads 332 may be connected to a logic circuit (not shown) disposed inside the semiconductor chip 300 by third internal wirings 334 .

According to this arrangement method, instead of having a separate input/output unit for supplying the power voltage, the first pad 312 for supplying the ground voltage is disposed on the input/output unit (eg, I/O Unit_5). A second additional pad 322A may be disposed. That is, since the power supply voltage can be sufficiently supplied without a separate input/output unit for supplying the power supply voltage, the SSN of the signal input through the third pad 232 can be reduced. In addition, since there is no need to provide a separate input/output unit for supplying the ground voltage and the power voltage, the chip size can be reduced.

It will be apparent to those skilled in the art that the structure of the present invention can be variously modified or changed without departing from the scope or spirit of the present invention. In view of the foregoing, it is contemplated that the present invention includes such modifications and variations of the present invention provided that they fall within the scope of the following claims and their equivalents.

100: semiconductor chip
110: first conductive line
112: first pad
114: first internal wiring
116: first conductive ring
120: second conductive line
122: second pad
124: second internal wiring
126: second conductive ring
130: third conductive line
132: third pad
134: third internal wiring
140_1~140_3: bump area

Claims (10)

For a semiconductor chip:
first to fourth bump regions provided on a surface of the semiconductor chip;
first to fourth conductive lines provided on the surface and connected to the first to fourth bump regions, respectively; and
Comprising a first conductive ring and a second conductive ring provided inside the semiconductor chip,
one end of the first conductive line and the first conductive ring are electrically connected to each other through a first internal interconnection line provided in a first row of the surface;
one end of the second conductive line and the second conductive ring are electrically connected to each other through a second internal interconnection line provided in a second row of the surface;
one end of the third conductive line and the first conductive ring are electrically connected to each other through a third internal interconnection line provided in a third row of the surface;
One end of the fourth conductive line and the second conductive ring are electrically connected to each other through a fourth internal interconnection line provided in the third row of the surface. The method of claim 1,
a ground voltage is applied to the first bump region and the third bump region;
A semiconductor chip to which a power voltage is applied to the second bump region and the fourth bump region. The method of claim 1,
a fifth bump region provided on the surface; and
a fifth conductive line provided on the surface and connected to the fifth bump region;
One end of the fifth conductive line is electrically connected to an input/output unit provided in the semiconductor chip through a fifth internal interconnection line provided on the surface,
and one end of the fifth conductive line is provided in a row different from the first row and the second row. 4. The method of claim 3,
wherein the row is the third row. 4. The method of claim 3,
A semiconductor chip through which a signal is received or transmitted through the fifth bump region. The method of claim 1,
the first internal interconnection line is provided to have a first minimum distance between the first conductive line and the first conductive ring;
and the second internal interconnection line is provided to have a second minimum distance between the second conductive line and the second conductive ring. 7. The method of claim 6,
a third internal interconnection line is provided such that it does not have the first minimum distance between the first conductive line and the first conductive ring;
and the fourth internal interconnection line is provided so as not to have the second minimum distance between the fourth conductive line and the second conductive ring. For a semiconductor chip:
first to fourth bump regions provided on a surface of the semiconductor chip;
first to fourth conductive lines provided on the surface and respectively connected to the first to fourth bump regions;
a first conductive ring and a second conductive ring provided inside the semiconductor chip;
a first internal interconnection line provided in a first row of the surface and electrically connecting one end of the first conductive line and the first conductive ring;
a second internal interconnection line provided in a second row of the surface and electrically connecting one end of the second conductive line and the second conductive ring;
a third internal interconnection line provided in a third row of the surface and electrically connecting one end of the third conductive line and the first conductive ring; and
and a fourth internal interconnection line provided on the third row of the surface and electrically connecting one end of the fourth conductive line and the second conductive ring. delete 9. The method of claim 8,
a ground voltage is applied to the first bump region and the third bump region;
A semiconductor chip to which a power voltage is applied to the second bump region and the fourth bump region.

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