KR102456653B1 - Method for packaging ⅲ-ⅴ compound semiconductor and ⅲ-ⅴ compound semiconductor package using the same - Google Patents

Abstract

The present disclosure relates to a semiconductor package, specifically, to a III-V group compound semiconductor package, and more specifically, to a gallium nitride semiconductor package and a packaging method for manufacturing the same. More specifically, the semiconductor packaging method of the present disclosure includes: a first step of forming a via hole in a substrate; a second step of performing a process of forming a metal thin film pattern on the upper surface of the substrate, forming a seed layer on the inner surface of the via hole, and a process of bonding a first material layer to the lower surface of the substrate, and then filling the via hole with a conductive metal material; a third step of performing heat treatment to increase adhesion between the seed layer and the substrate; a fourth step of forming or bonding a second material layer on the substrate, wherein a semiconductor die is inserted into the second material layer; and a fifth step of forming a stacked package structure electrically connected to the semiconductor die on the second material layer. High integration and high reliability can be achieved at the same time.

Description

III-V compound semiconductor packaging method, and group III-V compound semiconductor package manufactured using the same

The present disclosure relates to a semiconductor structure, specifically to a process for manufacturing a compound semiconductor package, and more specifically to a process for manufacturing a III-V compound semiconductor package. The present disclosure relates to suppressing a self-heating effect generated inside a III-V compound semiconductor device (die) or MMIC (monolithic microwave IC) device and reducing parasitic losses. This is to secure the high efficiency, high output, and high reliability of the III-V compound semiconductor package.

Specific embodiments are a process of forming a via hole in a diamond wafer, which is manufactured by wafer unit of polycrystalline diamond having excellent thermal conductivity, and filling the via hole with copper, a diamond power semiconductor or MMIC device package using the same. It relates to a process optimized for application in manufacturing.

The following terms are widely used in the technical field of the present invention, and their definitions will be useful in interpreting this specification. A 'wide band-gap semiconductor technology' may be used to refer to a technology for manufacturing an electronic device and an optoelectronic device based on a wide band-gap semiconductor.

'Single-crystalline (monocrystalline) or polycrystalline (polycrystalline) material, wafer, or layer' is used to refer to a material, wafer, or layer formed of one or several crystals, i.e., generally having translational symmetry. can be The term 'layer' refers to a material disposed in a continuous or discontinuous manner over at least a portion of its underlying surface. Also, the term "layer" does not necessarily mean that the material on which it is disposed has a constant thickness. The disposed material may have either a constant thickness or a varying thickness.

Moreover, any “layer” referred to herein may refer to a single layer or a plurality of layers, unless the context dictates otherwise. This term is commonly used in reference to crystal growth and is essential for most semiconductors. Real semiconductors have some defects, but their defect density is low enough to explain the electronic and optical properties of these materials, assuming translational symmetry.

Polycrystalline material may be used to refer to a material that is composed of more than one number of crystals or is composed of crystals having various orientations, and amorphous (amorphous) material is used to refer to a material that has no actual or apparent crystalline form. can be used

Synthetic diamond may be used to refer to artificial diamond produced by any of the methods known in the art, which methods include high temperature and high pressure techniques and chemical vapor deposition (CVD). including but not limited to. 'Diamond wafer' or 'diamond substrate' are terms used interchangeably, e.g., such a diamond wafer may include a commercial polycrystalline diamond wafer having a given diameter (e.g., 4 inches or more than 100 mm) will be understood by those skilled in the art.

Bonding or bonding may be used to refer to a technique that brings two surfaces, typically semiconductor surfaces, into close proximity to each other and tightly adhered. Bonding can be accomplished by using chemical bonding or adhesives. This process is widely used in the field of semiconductor technology.

In addition to broadcasting systems and other communication systems, the rapid expansion of the mobile communication market and the increase in user demand have resulted in a need for faster and more data transmission in the mobile communication system. For this purpose, a high-power amplification device with a broadband characteristic of several hundred MHz is required. High output power of semiconductor devices and stable operation at high temperatures, i.e., high voltage, high efficiency and high reliability in the field of power devices, especially in fields such as power systems, satellites, eco-friendly energy products, automotive sensors, etc., as well as in the defense industry. I need this.

In response to these requirements, III-V compound semiconductor devices such as gallium nitride (GaN) devices have a high breakdown voltage and a wide energy band gap (3.4 eV in the case of gallium nitride), which is advantageous for the output of high power. , has a high carrier concentration and high electron mobility, showing a high electric field saturation rate, while having low carrier scattering, which is advantageous for high-speed switching (that is, high-frequency operation), and has the advantage of stably operating even at a relatively high temperature. are receiving

However, the gallium nitride (GaN) device has a maximum output power that is 10 times higher than that of a conventional silicon (Si)-based LDMOS device and 8 times higher than that of a GaAs device. Only a power density of about 7 W to 8 W/mm corresponding to 20% of the performance is being implemented. In the case of a power semiconductor device using a gallium nitride material, for example, a 2-dimensional electron gas (2DEG) layer showing rapid electron mobility is formed inside the material by an AlGaN/GaN heterojunction structure, so that electrons are rapidly transferred This is because, although moving from the source side to the drain side, high heat is generated due to the collision of electrons due to the electric field concentrated at the gate edge (edge) portion of the drain side.

Conventionally, as a way to solve this heat generation problem, a phenomenon in which electrons are saturated at the corners is alleviated to some extent by introducing a field plate structure in the gate region and the source region, but there is still a limit.

In addition, as another method to solve the heat problem, a buffer and a substrate having high thermal conductivity and high insulation are required to function as a heat spreader. Due to the characteristics of sapphire, silicon, and silicon carbide materials are used.

Considering the use of various materials as a heat sink, the thermal conductivity of sapphire is 20 ~ 25 W/m K, the thermal conductivity of Si (silicon) is about 149 W/m K, and the thermal conductivity of gallium nitride is about 160 W/ m·K, and CPC (Cu/Mo ₇₀ Cu/Cu) has a thermal conductivity of about 300 W/m·K, and CMC (Cu/Mo/Cu) Since it has a thermal conductivity of about 250 W/m·K, and CuW (W ₈₅ Cu ₁₅ ) only has a thermal conductivity of about 220 W/m·K, a method using a SiC (silicon carbide) substrate (eg, US registered Patent No. 9,111,750), but there is a limit of up to 4 inches in the growth of silicon carbide wafers, and the thermal conductivity is only about 390 to 450 W/m·K, so there is still a limit in its heat dissipation performance.

Therefore, recent efforts have been made to improve the heat dissipation characteristics by using a diamond wafer having a thermal conductivity of 1200 to 2000 W/m·K. For this reason, there is a problem of low bonding strength during polishing of the surface or heterojunction with other metals, and it is necessary to solve the problem.

The present disclosure improves the heat dissipation characteristics of group III-V compound semiconductors by using diamond with the highest thermal conductivity, but reduces parasitic components by reducing the distance between the source and ground, and promotes heat dissipation while promoting dissipation of diamond-metal heterogeneity To present a method for manufacturing a compound semiconductor device package that can overcome the problems in the prior art that occur during bonding and can configure a three-dimensional stacked package at a lower process temperature to achieve high integration and high reliability at the same time The purpose.

The characteristic configuration of the present invention for achieving the object of the present invention as described above and for realizing the characteristic effects of the present invention to be described later is as follows.

According to an aspect of the present disclosure there is provided a semiconductor packaging method, the method comprising: a first step of forming a via hole in a substrate; Forming a metal thin film pattern on the upper surface of the substrate, forming a seed layer on the inner surface of the via hole, bonding a first material layer to the lower surface of the substrate, and then forming the via with a conductive metal material a second step of performing a hole filling process; a third step of performing heat treatment to increase adhesion between the seed layer and the substrate; a fourth step of forming or bonding a second material layer on the substrate, wherein a semiconductor die is inserted into the second material layer; and a fifth step of forming a stacked package structure electrically connected to the semiconductor die on the second material layer.

Preferably, the first step comprises: forming the via hole in the substrate using a microwave laser; cleaning the surface of the substrate; and immersing the cleaned surface in a strong acid solution to remove the residue adhering to the surface. Here, the cleaning may be ultrasonic cleaning.

More preferably, the cleaned surface is immersed in a strong acid solution at 200° C. for 1 hour, so that the residue including the graphite phase adhering to the surface can be removed.

Advantageously, the first step is a microwave laser in a spiral shape in a first radial direction that is a direction from the periphery of the via hole toward the center or a direction from the center of the via hole outward, and a first rotational direction that is clockwise or counterclockwise. A first laser processing step of irradiating the substrate in the vertical direction; And a second laser processing step of irradiating the microwave laser in a vertical direction of the substrate in a spiral shape of a second radial direction opposite to the first radiation direction, and a second rotation direction opposite to the first rotation direction. includes

In an embodiment, the substrate is a diamond substrate, and the conductive metal material is copper (Cu). In this embodiment, the seed layer may include titanium (Ti), tungsten (W), or chromium (Cr) as the first bonding material.

In the embodiment, titanium, tungsten, or chromium of the first bonding material may react with carbon of the diamond substrate to form metal carbide by the heat treatment of the third step.

Preferably, the second step comprises: forming a pattern with a dry film or a photosensitizer on the upper surface of the substrate of the substrate; depositing the titanium, tungsten or chromium as the first bonding material on an upper surface of the diamond substrate and an inner surface of a via hole; depositing gold (Au), silver (Ag), or copper (Cu) as a second bonding material on the first bonding material; and removing the dry film or the photosensitizer to remove the first bonding material and the second bonding material deposited on the dry film or the photosensitizer, thereby forming a metal thin film pattern including the first bonding material and the second bonding material. forming a lift-off step.

Here, the deposition may be performed by a magnetron sputtering device, the first bonding material may be deposited to a thickness of 300 to 500 angstroms, and the second bonding material may be deposited to a thickness of 500 to 1000 angstroms.

More preferably, the second step may include, after the lift-off step, bonding the first material layer to the lower surface of the substrate; and a copper filling step of filling the via hole with copper, which is the conductive metal material. Here, the first material layer may be a first silicon layer, and the first bonding material and the second bonding material may be sequentially deposited on a surface to be bonded to the lower surface of the substrate.

Even more preferably, the second step further includes, after the copper filling step, a polishing step of removing the overfilled copper on the upper surface of the substrate.

In an embodiment, a diffusion barrier layer may be interposed between the first bonding material and the second bonding material.

Advantageously, the fourth step may include bonding a second silicon (Si) layer, which is the second material layer, on the substrate; removing a portion of the silicon material included in the second silicon layer to form a groove penetrating a portion of the second silicon layer; and seating the semiconductor die in the groove and directly bonding the semiconductor die onto the metal thin film pattern of the substrate. Here, the direct bonding may be by heat or compression.

More advantageously, the semiconductor die is a semiconductor die of a III-V compound, and the III-V compound may be gallium nitride (GaN).

Preferably, the fourth step comprises: directly bonding the semiconductor die onto the metal thin film pattern of the substrate; and forming a ceramic layer, which is the second material layer, surrounding a portion of the height of the semiconductor die on the substrate by inkjet printing using ceramic ink.

Advantageously, the fifth step is achieved using inkjet printing using ceramic inks and metal inks.

Preferably, the method further includes, after the fifth step, a sixth step of dicing the substrate to separate a unit chip, and packaging the unit chip to manufacture an individual semiconductor package.

According to another aspect of the present disclosure, there is provided a semiconductor chip, the semiconductor chip comprising: a substrate having a via hole formed therein; a seed layer formed on an inner surface of the via hole; a conductive metal material filled in the via hole over the seed layer; a metal thin film pattern formed on the upper surface of the substrate and including a portion conducting the conductive metal material; a second material layer formed on the metal thin film pattern and having a semiconductor die inserted therein; and a stacked package structure formed on the second material layer to be electrically connected to the semiconductor die.

Preferably, the semiconductor chip includes a metal carbide between the seed layer and the substrate.

Advantageously, no other conductive material is interposed between the metal thin film pattern and the semiconductor die.

According to the compound semiconductor packaging method of the present disclosure, on the basis of a sandwich structure using a diamond wafer and a silicon wafer, a wiring including a compound power semiconductor (transistor) die, a passive element, and an electrode are integrated into one package, thereby forming a conventional power transistor There is an effect of reducing the size of the package compared to the

In addition, according to the semiconductor packaging method of the present disclosure, a wafer made of a diamond material having excellent heat dissipation characteristics is used and copper-filled via holes are processed to reduce parasitic components to improve RF characteristics while effectively dissipating heat to a transistor. It has the advantage of increasing the durability of

In addition, according to the semiconductor packaging method of the present disclosure, since a semiconductor device die such as a power device can be bonded by heat or compression without eutectic bonding, the reliability of the transistor is improved.

In particular, according to the present disclosure, unlike the prior art, the input/output matching circuit, electrode wiring, and passive elements can all be formed of various dielectric and metal parts using inkjet printing of ceramic ink and metal (eg, silver) ink. The structure is suitable for manufacturing packaging, and the reliability of the transistor is ensured because the sintering process of ink is performed at a low temperature, while additional substrates and passive elements are not required when implementing a separate impedance matching and bias circuit. There is a beneficial effect in downsizing the overall product using the compound semiconductor package and reducing the development cost thereof.

Embodiments will be described with reference to the accompanying drawings to show the semiconductor package structure shown in the present disclosure for understanding the present disclosure, which are only non-limiting examples, and common knowledge in the technical field to which the present disclosure belongs It goes without saying that other drawings may be obtained based on these drawings for a person having (hereinafter referred to as "a person skilled in the art") without additional efforts to reach another invention.
1 is a flowchart illustrating main steps of a semiconductor packaging method according to the present disclosure.
2 is a diagram conceptually illustrating a method of forming a via hole in a substrate in an embodiment of a semiconductor packaging method according to the present disclosure.
3 is a diagram exemplarily illustrating an alignment via that can be used for alignment between a first material layer and/or a second material layer and a substrate in a semiconductor packaging method according to the present disclosure.
4 is an SEM photograph taken in a state in which the surface of the substrate is laser-processed in the first step of the semiconductor packaging method according to the present disclosure and the surface is cleaned.
5 is a plan view of the substrate conceptually illustrating each process belonging to the second step of the semiconductor packaging method according to the present disclosure.
6 is a cross-sectional side view of the substrate conceptually illustrating a process in which a conductive material is filled in a via hole in an embodiment of a semiconductor packaging method according to the present disclosure.
7 is an exemplary photograph taken in a bottom-up manner in which copper is filled in a via hole formed in a substrate in an embodiment of the semiconductor packaging method according to the present disclosure.
8A and 8B are conceptual views exemplarily illustrating two different embodiments of the fourth step of the semiconductor packaging method according to the present disclosure.
9A is a side cross-sectional view illustrating a packaging structure of a gallium nitride power semiconductor formed using stacked vertical wiring in a fifth step of the semiconductor packaging method according to the present disclosure.
9B is a side cross-sectional view illustrating a stacked packaging structure using a via hole formed in a diamond substrate in a fifth step of the semiconductor packaging method according to the present disclosure.
10 is a diagram conceptually illustrating a method in which inkjet printing is performed in parallel on a plurality of unit chips included in a substrate using a plurality of inkjet nozzles in an embodiment of the semiconductor packaging method of the present disclosure.
11 is a diagram conceptually illustrating a sixth step of separating a unit chip by dicing a substrate in the semiconductor packaging method of the present disclosure.

All prior publications cited in this disclosure are incorporated by reference in their entirety as if they were all set forth in this disclosure. Unless defined otherwise, all terms used herein, including technical or scientific terms, have the same meaning as commonly understood by one of ordinary skill in the art. Terms such as those defined in a commonly used dictionary should be interpreted as having a meaning consistent with the meaning in the context of the related art, and should not be interpreted in an ideal or excessively formal meaning unless explicitly defined in the present specification. does not

The detailed description set forth below with respect to the construction principle of the processes and the semiconductor package according to the present disclosure is a specific implementation in which the present invention may be practiced in order to clarify the objectives, technical solutions and advantages of the present disclosure appearing in the present disclosure. Reference is made to the accompanying drawings, which show examples by way of example. In the description with reference to the accompanying drawings, the same components are assigned the same reference numerals regardless of the reference numerals, and the overlapping description thereof will be omitted. It will be understood that the structure of the substrate and the semiconductor package according to the present disclosure does not have a length ratio as shown in the drawings, and the dimensions of each part in the drawings are only shown for illustrative purposes without limiting the scope of the present invention. will be. For example, dimensions of some of the elements shown in the drawings are provided to aid understanding of various embodiments. In addition, the description and drawings are not meant to be in the order in which they are described. Skilled artisans will appreciate that acts and/or steps described or depicted in a particular order may not require special limitations on that order.

Therefore, specific structural or functional descriptions of the embodiments are disclosed for the purpose of illustration only, and may be changed and implemented in various forms.

And although terms such as first or second may be used to describe various elements, these terms should be interpreted only for the purpose of distinguishing one element from other elements. For example, a first component may be termed a second component, and similarly, a second component may also be termed a first component.

When a component is referred to as being “connected” to another component, it may be directly connected or connected to the other component, but it should be understood that another component may exist in between. Also, when it is mentioned that a certain element is 'on' or 'above' another element, it will be understood that the other element may be 'immediately on', but another element may be present in the middle.

The singular expression includes the plural expression and vice versa, unless the context clearly dictates otherwise.

In the present disclosure, the expression "disposed on" or the expression "disposed on" and "disposed between" means, unless otherwise specified, the expressions disposed to be in direct contact with each other or interposed therebetween. It means that it is so arranged indirectly through other components. Moreover, "on" and "on" merely indicate the relative positions between the components, since they may look different depending on the viewpoint of the observer. In addition, "formed on (on)" has a broad meaning, and the fact that a component is formed on another component does not always mean direct physical contact of any component with the other component.

Moreover, the invention encompasses all possible combinations of the embodiments indicated herein. It should be understood that various embodiments of the present invention are different but need not be mutually exclusive. For example, certain shapes, structures, and characteristics described herein may be implemented in other embodiments without departing from the spirit and scope of the invention in relation to one embodiment. That is, the embodiments of the present invention are described with reference to specific drawings of ideal embodiments of the present invention, but should not be construed as being limited to a specific shape as shown, and various modifications may be included. The shapes shown in the drawings are conceptually presented, and are not intended to limit the scope of the present invention by limiting the precise shape of the structure or area. For example, areas shown in the drawings as rectangles, squares, etc. can often be tapered, curved, or rounded.

It should be understood that the location or arrangement of individual components within each disclosed embodiment may be changed without departing from the spirit and scope of the present invention. Accordingly, the detailed description set forth below is not intended to be taken in a limiting sense, and the scope of the present invention, if properly described, is limited only by the appended claims, along with all scope equivalents to those claimed.

In addition, in describing the present invention, if it is determined that the detailed description of the related known configuration or function relates to materials, processes, etc. well known to those skilled in the art of the semiconductor technology, and may obscure the gist of the present invention, it is excessively Detailed description will be omitted.

1 is a flowchart illustrating main steps of a semiconductor packaging method according to the present disclosure.

Referring to FIG. 1 , the semiconductor packaging method of the present disclosure includes a first step ( S100 ) of forming a via hole in a substrate.

Here, the substrate may be a diamond substrate. Further, the diamond substrate may be a polycrystalline diamond substrate formed by chemical vapor deposition (CVD). For example, the thickness of the substrate may be less than 1000 μm, but is not limited thereto.

In the first step (S100) for processing the substrate, a laser may be used. In an embodiment, the first step (S100) is performed using a microwave pulse laser, for example, a nanosecond laser or a picosecond laser. and forming the via hole in the substrate (S120). The diameter of the via hole may be 250 μm to 350 μm.

This is because, when the substrate is a diamond substrate, it is extremely difficult to process by a wafer dicing equipment generally used to cut a wafer due to the bonding force between carbons of diamond.

However, when irradiating a laser onto a substrate using a microwave laser light source, the energy density inside the substrate rapidly increases due to the strong energy of the laser and the surface temperature increases, causing the material to move in the heat affect zone (HAZ). By melting, vaporizing, and solidifying, the surface of the substrate and the inside of the via hole are contaminated. In particular, in the case of a diamond substrate, carbon bonds of diamond are deformed by heat to generate a graphite phase.

2 is a diagram conceptually illustrating a via hole formation method for solving such a problem.

Referring to FIG. 2 , in the step of forming the via hole ( S120 ), the microwave laser is used in a spiral trajectory having a first radial direction and a clockwise first rotation direction from the outside of the via hole 120 toward the center. A first processing step (S122) of irradiating in a direction perpendicular to the plane of the substrate 100, a second radial direction opposite to the first radial direction, and a direction opposite to the first rotational direction (in this example, half A second processing step (S124) of irradiating the microwave laser in a direction perpendicular to the plane of the substrate 100 in a spiral-shaped locus having a second rotational direction (clockwise) may be performed.

In general, the laser irradiation of the spiral trajectory may be performed by controlling a stage (not shown) on which the substrate is mounted while the laser light source is fixed.

Of course, alternative combinations are possible, such as when the first radial direction is a direction from the center of the via hole to the outside, and when the first rotation direction is a counterclockwise direction.

If the via hole is formed using a microwave pulse laser as in the present disclosure, there is an advantage in that the low specific heat of the diamond substrate can be maintained.

3 is a diagram exemplarily illustrating an alignment via that can be used for alignment between a first material layer and/or a second material layer and a substrate in a semiconductor packaging method according to the present disclosure.

Referring to FIG. 3 , in step S120 , the alignment via 190 that can be used for alignment with a first material layer and/or a second material layer to be described later as well as a via hole 120 for energizing the upper and lower sides of the substrate. ) can also be formed together.

In addition, in order to minimize the negative effect of the laser, the first step ( S100 ) in this embodiment, after the formation of the via hole ( S120 ), is the step of cleaning the surface of the substrate ( S140 ; not shown), and the cleaned and removing the residue adhering to the surface by immersing the surface in a strong acid solution (S160; not shown).

The cleaning (S140) may be, for example, cleaning by ultrasonic waves, and the cleaned surface is immersed in a strong acid solution at a predetermined temperature for a predetermined time at a predetermined temperature, for example, for 1 hour at 200°C in the step (S160). Residues including the graphite phase adhering to the surface can be removed. The residue here may include a graphite phase produced by laser processing as described above.

4 is an SEM photograph taken in a state in which the surface of the substrate is laser-processed in the first step of the semiconductor packaging method according to the present disclosure and the surface is cleaned.

Referring again to FIG. 1 , after the first step ( S100 ), the semiconductor packaging method of the present disclosure includes a process of forming a metal thin film pattern on the upper surface of the substrate, and a seed layer on the inner surface of the via hole. ) and, after bonding the first material layer to the lower surface of the substrate, a second step (S200) of performing a process of filling the via hole with a conductive metal material.

Here, the conductive metal material may be copper (Cu). In addition, the seed layer may include titanium (Ti), tungsten (W), or chromium (Cr) as the first bonding material.

5 is a plan view of the substrate conceptually illustrating each process belonging to the second step of the semiconductor packaging method according to the present disclosure.

Referring to FIG. 5 , in an embodiment, in the second step (S200), a pattern is formed using a dry film or a photosensitizer 130 on the upper surface of the substrate 100 through which the via hole is formed in the first step (S100) (patterning). ) including a step (S210).

The second step (S200) in this embodiment is the step (S220) of depositing the titanium, tungsten or chromium as the first bonding material on the upper surface of the diamond substrate and the inner surface of the via hole after the step (S210). include more

Deposition in step (S220) may be made by a magnetron stuffer equipment. In addition, the first bonding material may be deposited to a thickness of 300 to 500 angstroms.

Copper is generally not easy to bond to a diamond substrate. Specifically, due to the strong bonding force between carbon atoms constituting diamond, diamond shows low adhesion to metal materials, while the thermal expansion coefficient of diamond is 1.18×10 ^-6 m/(mK) and that of copper is 18× Since it is 10 ^-6 m/(mK), there is a difference of about 18 times from each other, so the copper metal inside the via hole is easily desorbed according to the change in temperature. In order to prevent this, in the present disclosure, the adhesion between the diamond material and the metal material is improved by using the first bonding material of the seed layer. tightly coupled

Subsequently, the second step ( S200 ) of this embodiment further includes a step ( S240 ) of depositing gold (Au), silver (Ag), or copper (Cu) as a second bonding material on the first bonding material. The first bonding material has good bonding strength with diamond, but has low thermal conductivity, electrical conductivity, and metal-to-metal bonding properties, so that the second bonding material may be further used to compensate for this.

For example, the second bonding material may be deposited to a thickness of 500 to 1000 angstroms.

Optionally, the step S230 of inserting platinum (Pt) or nickel (Ni) to function as a diffusion barrier layer between the first bonding material and the second bonding material is performed between the steps S220 and S240. more can be done.

In the second step (S200) of this embodiment, after the second bonding material is deposited (S240), the dry film or the photosensitive agent 130 is removed to obtain the first bonding material deposited on the dry film or the photosensitive agent and the The method further includes a lift-off step (S250) of forming the metal thin film pattern 140 including the first bonding material and the second bonding material by removing the second bonding material.

6 is a cross-sectional side view of the substrate conceptually illustrating a process in which a conductive material is filled in a via hole in an embodiment of a semiconductor packaging method according to the present disclosure.

Referring to FIG. 6 , following the lift-off step ( S250 ), the first material layer 200 , for example, the first material layer 200 , which functions as a dummy, to fill the through-holes with a conductive material, for example, copper metal, 1 The silicon layer may be directly bonded to the substrate (S260), and the conductive material, for example, copper, may be charged (S270) from the lower portion 122a of the via hole through electroplating (S270). As mentioned above, in order to minimize parasitic inductance, ^it is necessary to fill the via hole using a metal having excellent electrical conductivity. It has a low advantage.

In this case, the aforementioned alignment via 190 may be used for alignment for bonding between the first material layer and the substrate.

Here, the first material layer is a first material layer as in steps S220 and S240, so as to facilitate bonding to constitute a sandwich structure sandwiched between the first material layer and the second material layer, as will be described later. The first bonding material and the second bonding material may be sequentially deposited on the upper surface of the material layer, that is, the surface 240 to be bonded to the lower surface of the substrate. For example, the combination of metal thin films deposited on the upper surface of the first material layer may include a combination of titanium and gold (Ti/Au), and a combination of chromium and gold (Cr/Au).

In addition, the electrolytic plating may be performed by immersing the substrate in a plating solution and applying a pulse voltage to fill the inside of the via with copper metal.

Conventionally, when a via hole passing through a substrate is plated with copper, when a flat DC voltage is applied by putting the substrate in a plating solution, the copper metal is first rapidly reduced at the via hole entrance on the upper and lower surfaces of the substrate so that the inside of the via hole is completely filled with copper. Previously, the inlet of the via hole could be blocked, and a process for removing it was additionally required, and there was a disadvantage in that uniformity was lowered due to the occurrence of non-uniform voids inside the via hole.

In the present disclosure, the clogging of the via hole entrance during electroplating as described above is solved by applying a pulse voltage alternating between a positive voltage and a negative voltage. That is, since the accumulation of copper metal and the etching reaction are alternately repeated at the entrance of the via hole by the pulse voltage, the clogging of the entrance of the via hole can be solved.

In addition, a leveler may be further added to the plating solution in order to facilitate filling of the copper metal upward from a position close to the first material layer by electroplating. A process in which copper metal is reduced from the plating solution and filled from bottom to top, which is a position close to the first material layer, may be referred to as a bottom-up method.

7 is an exemplary photograph taken in which copper is filled in a bottom-up method inside a via hole formed in a substrate in an embodiment of the semiconductor packaging method according to the present disclosure, wherein the copper metal is completely filled without a void inside the via hole. The filling is shown.

After the above-described copper filling step ( S270 ), the second step ( S200 ) is performed in order to increase the flatness of the copper metal at the entrance of the via hole, for example, the copper 122b overfilled on the upper surface of the substrate, for example, beyond the thickness of the substrate. A polishing step (S280) of removing the protruding copper may be further included.

The polishing may be performed using polishing equipment. For example, polishing the upper surface of the substrate 100 is performed on the substrate (polishing pad) with polishing equipment, for example, a polishing pad made of polyurethane. 100), by using a slurry containing an abrasive having a size of several hundred nm, by rotating the polishing pad at high speed so that a mechanical reaction and a chemical reaction occur, it can be performed in a way to reduce the surface roughness. have.

Conventionally, in order to improve RF characteristics in RF wave or millimeter wave devices, a method of minimizing the distance between the source and ground is generally used through a backgrinding process and a source via forming process for the back side of the substrate. As in the present disclosure, when a via hole filled with a conductive material, particularly, copper (Cu) is formed as in the embodiment of the present disclosure, the distance between the semiconductor die and the ground is further reduced to reduce parasitic components. Thermal conductivity is also improved.

In particular, in order to reduce the distance between a point where heat is generated inside the semiconductor die and the ground, the via hole 120 may be formed to be placed under a channel region close to the source region of the semiconductor die.

Continuingly, referring to FIG. 1 , after the second step ( S200 ), the semiconductor packaging method of the present disclosure further includes a third step ( S300 ) of performing heat treatment to increase adhesion between the seed layer and the substrate. include

The third step (S300) is a heat treatment step including annealing to increase adhesion and thermal conductivity between the diamond material and the metal material of the substrate, argon (Ar), nitrogen (N ₂ ), hydrogen (H ₂ ) It may be carried out for at least 30 minutes at a temperature of 400 ℃ to 700 ℃ in an atmosphere containing at least one.

More specifically, in the third step (S300), by performing heat treatment at 400 ° C. to 600 ° C. for 1 hour in a hydrogen gas atmosphere, titanium, tungsten, and chromium metals are respectively reacted with carbon to form titanium carbide, tungsten carbide, and chromium carbide. can be

In the case of titanium and chromium, excluding tungsten, when combined with carbon, not only adhesive strength but also thermal conductivity was improved. For example, titanium's low thermal conductivity of 15 W/m K As a result, it was improved to 110 W/m·K of titanium carbide, showing an effect of improving thermal conductivity more than 7 times.

Referring to FIG. 1 , after the third step ( S300 ), in the semiconductor packaging method of the present disclosure, a second material layer is formed or bonded on the substrate, and a semiconductor die is inserted into the second material layer. A fourth step (S400) is further included. A so-called 'sandwich structure' is formed in which the substrate is sandwiched between the first material layer and the second material layer by the fourth step.

In the fourth step, a second silicon layer or a ceramic layer, which is a second material layer, is formed on the upper surface of the substrate 100 that has undergone the third step, wherein a semiconductor die, such as a III-V compound semiconductor die, more specifically gallium nitride ( A GaN) semiconductor die is embedded or embedded in its second material layer.

8A and 8B are conceptual views exemplarily illustrating two different embodiments of the fourth step of the semiconductor packaging method according to the present disclosure. FIG. 8A illustrates a process in which a sandwich structure is formed using the second silicon layer, and FIG. 8B illustrates a process in which a sandwich structure is formed using a low-temperature sintered ceramic ink.

Referring first to FIG. 8A , in the fourth step ( S400 ) of an embodiment of the semiconductor packaging method of the present disclosure, a sandwich structure is formed by bonding a second silicon (Si) layer 300a, which is the second material layer, on the substrate. to form (S410a).

Before the second silicon layer 300a is bonded to the upper surface of the substrate 100 ( S410a ), the first bonding material and the second bonding material are sequentially deposited on the surface to be bonded to form the metal thin film layer 340a . can be The combination of the metal thin film layer 340a formed on the second silicon layer may be, for example, titanium and gold (Ti/Au), or chromium and gold (Cr/Au).

When the second silicon layer 300a is attached to the substrate in a direct bonding method, the second silicon layer 300a may have a thin thickness of 80 to 100 μm in consideration of the thickness of the semiconductor die 400 to be described later.

In this embodiment, after the sandwich structure is formed (S410a), a portion of the silicon material included in the second silicon layer 300a is removed to form a groove 350a penetrating a portion of the second silicon layer (S420a) do. For example, dry etching may be used to remove the silicon material, and during etching, the metal thin film pattern 140 formed on the upper portion of the substrate may function as a metal mask protecting the lower portion.

When the groove 350a is formed ( S420a ), the semiconductor die 400 is seated in the groove 350a and directly bonded to the metal thin film pattern 140 of the substrate 100 ( S430a ).

Here, direct bonding may be achieved by heat or compression, and since conventional eutectic bonding or soldering is not used, a thermal resistance component such as thermal barrier resistance (TBR) may be reduced.

Meanwhile, referring to FIG. 8B , in the fourth step ( S400 ) of another embodiment of the semiconductor packaging method of the present disclosure, first, the semiconductor die 400 is directly bonded on the metal thin film pattern 140 of the substrate 100 ( S430b ). )do. Direct bonding may be performed by heat or compression as in the embodiment of FIG. 8A described above.

After that (S430b), a ceramic layer 300b which is an insulating second material layer surrounding a part of the height of the semiconductor die is formed on the substrate by inkjet printing using a low-temperature sintered ceramic ink (S440b; S442b to S444b). In this embodiment, semiconductor packaging using direct bonding or low temperature sintering inkjet printing technology (for example, disclosed in Korean Patent Application Laid-Open No. 10-2010-0127011) without using expensive organic thin film deposition equipment It can process and manufacture the necessary substrates. In step S440b, the ceramic layer can be formed by spraying the low-temperature sintered ceramic ink with inkjet (S442b) and then sintering at a low temperature of 300 ° C. or less (S444b). The problem of damage can be improved.

Low-temperature sintered ceramic ink is made of ceramic (Al ₂ O ₃ ) powder with a dispersion solution in the form of ink.

The volume of an exemplary ceramic ink droplet is 150 to 180 picoliter, and the pitch between the ink droplets is 50 to 100 micrometers, and a drop-on-demand (DOD) printing method, which is a conventional inkjet printing method, may be applied. have. It is well known that DOD printing is implemented by an actuator including a piezoelectric element. Preferably, the inkjet printing used in the present disclosure can be performed by jet jetting ink droplets having a volume smaller than 180 picoliters at intervals smaller than 50 micrometers.

The ceramic ink contains not only ceramic (Al ₂ O ₃ ) particles but also other components such as AlN, BN, and BaTiO ₃ , so that characteristics of the ceramic dielectric produced by the ceramic ink can be controlled.

When ceramic ink is used, the volatile solvent material, which is a binder contained in the ink, is vaporized at 50 ° C. to 100 ° C., the ceramic ink is cured first, the shape of the ceramic film is fixed, and then completely at a lower temperature of 250 ° C. Since sintering is performed, there is an advantage in that reliability is improved. In particular, compared to the conventional semiconductor packaging process usually performed at a temperature of about 300 ° C, when using a ceramic ink and a metal ink to be described later, the primary curing by vaporization of the solvent material is made at 50 ° C. to 100 ° C. , secondary complete sintering is performed at 250 degrees Celsius, so there is an advantage that can solve the problem due to heat.

In order to enable this low-temperature sintering, it is preferable that the filling rate of the ceramic particles shown in Equation 1 below is 68% or more, and the size of the ceramic particles is 20 nanometers to 1 micrometer.

In particular, in order to increase the density of the film formed by the ceramic ink, it is advantageous for the ceramic particles to have different sizes rather than uniform sizes.

For example, when ceramic powder having a particle size of 50 nm to 1 μm is used for the inkjet printing, the density of ceramic particles per unit area can be increased, so that a ceramic layer having a high filling rate can be realized.

In addition, by varying the mixing ratio of AlN, Al ₂ O ₃ , Si ₃ N ₄ , and BaTiO ₃ contained in the ceramic powder, the ceramic layer can be implemented as a material with different insulation properties for each layer, and semiconductor devices according to RF or millimeter wave bands There is an advantage that a ceramic layer that functions as an insulating film can be configured differently depending on the characteristics of the .

As a substrate manufactured up to the fourth step (S400), when a CVD diamond substrate is used, the CVD diamond has a thermal conductivity four times higher than that of other materials used as a heat sink, for example, copper (Cu) and CPC. This helps to secure the efficiency and reliability of the device by quickly dissipating the heat generated by the gallium nitride power semiconductor die operating at high output and high voltage to the outside. In addition, the metal thin film pattern and the semiconductor die are electrically directly connected without intervening other conductive materials, so that the copper-filled via hole is also the source via of the semiconductor die (shown by reference numeral 'S' in FIGS. 9A and 9B ). Since the distance between the source via and the ground is minimized by being electrically connected to the bar, the generation of a parasitic component is suppressed, the efficiency of the power semiconductor device operating in the RF or millimeter frequency region can be greatly improved.

Continuing to refer to FIG. 1 , after the fourth step ( S400 ), the semiconductor packaging method of the present disclosure includes a fifth step ( S500 ) of forming a stacked package structure electrically connected to the semiconductor die on the second material layer ( S500 ). further includes

The fifth step ( S500 ) may be performed by inkjet printing using ceramic ink and metal ink. Inkjet printing can be applied not only to the aforementioned ceramic ink, but also to metal ink containing nano-scale metal particles, for example, silver nano ink. can also be formed.

Here, the metal particles contained in the metal ink may include a component of silver (Ag) or copper (Cu). As an example, characteristics such as filling rate and viscosity of silver ink containing silver nanoparticles depend on the content ratio of silver nanoparticles contained in the silver ink, glycerol as a solvent, and polyvinylpyrrolidone affecting dispersion characteristics. can be adjusted.

Considering the limitation in that commonly used semiconductor processing equipment is manufactured for a wafer size of up to 4 inches, in the fifth step (S500), the formation of the stacked package structure on the sandwich structure formed on the wafer substrate is performed by inkjet printing. This can be done by the bar, such inkjet printing is for the simplification of the process and reduction of cost.

Since the implementation of input and output matching circuits was essential in the packaging of conventional RF power semiconductor devices, matching devices (resistors, inductors, capacitors), insulated PCBs for matching, and single layer capacitors (SLCs) in addition to the semiconductor die In order to dissipate the heat generated by the high-output power semiconductor die itself, as well as parasitic components generated from elements such as bonding wires, solder a copper metal with high thermal conductivity under the power semiconductor die or use Ag paste was bonded using , and due to such a thick (more than 20 micrometers) adhesive material, there was a significant thermal resistance component at the interface between the power semiconductor die and copper.

According to such a conventional packaging, a signal loss occurs due to a parasitic component and a thermal resistance component, which deteriorates the performance of the power semiconductor device, and the heat generated inside cannot be effectively dissipated, thereby causing damage to the semiconductor device, etc. Operational reliability There was a problem with this lowering.

9A is a side cross-sectional view illustrating an exemplary first packaging structure 500a of a gallium nitride power semiconductor formed using stacked vertical wiring in a fifth step of a semiconductor packaging method according to the present disclosure.

Referring to FIG. 9A , the fifth step (S500) is a single-layer molding (S520; not shown) using a low-temperature sintered ceramic and/or a metal ink in a substrate unit of a sandwich structure according to the present disclosure and a low-temperature sintered ceramic formed in a single layer; / or repeating the low-temperature sintering of the metal ink (S540; not shown).

As shown in FIG. 9A , the wiring connected to each of the gate terminal G and the drain terminal D in the fifth step S500 may be formed by applying a metal ink such as silver nano ink, and the metal ink and A ceramic material 510 having a high Q value and a low dielectric constant may be used together, and passive components for input and output impedance matching, such as resistors, capacitors 522a and inductors 524a, are made of ceramic and metal inks. In addition, by forming the vertical electrode wiring 520a instead of wire bonding, signal loss due to parasitic components generated inside can be reduced, and packaging in a flip-chip structure is possible through the bump 526a, thereby reducing the size of the semiconductor package. can be reduced

In the case of a compound power semiconductor package, a single layer capacitor (SLC) or a dielectric having a metal pattern for internal impedance matching is generally mounted together in the semiconductor package, and the metal wires inside the semiconductor package are mainly used to transmit external input/output signals. It is used to supply an over-bias voltage. In order not to obscure the essence of the present invention, a more detailed description of the elements and wirings formed by the ceramic ink and the metal ink will be omitted.

Meanwhile, referring to the second packaging structure 500b illustrated in FIG. 9B , it is possible to optimize the wiring lengths of the input/output signal, the bias voltage, and the ground by using the via hole 120 formed according to the present disclosure. It is easy to implement and reduce parasitic components, and after polishing the first material layer 200 , particularly the first silicon layer under the substrate 100 , and then applying a patterning process, an electrode pad is manufactured and then the unit chip is diced. When the 600 is directly attached to the PCB, the bonding material used in the conventional packaging method can not be used, so the TBR of the heterogeneous matching interface between the unit chip 600 and the PCB can be reduced, thereby further promoting heat dissipation. .

10 conceptually illustrates a method in which inkjet printing is performed in parallel on a plurality of unit chips 600 included in a substrate using a plurality of inkjet nozzles 700 in an embodiment of the semiconductor packaging method of the present disclosure. the drawing shown.

Inkjet printing technology has the advantages of low equipment cost and simple process, but has a limitation in that productivity is lowered due to its slow speed. In order to overcome this limitation, the inkjet printing in the fourth step ( S400 ) and the fifth step ( S500 ) may be performed in parallel on a plurality of unit chips included in the substrate using a plurality of inkjet nozzles 700 . possible, as exemplified in FIG. 10 .

11 is a diagram conceptually illustrating a sixth step ( S600 ) of separating a unit chip by dicing a substrate in the semiconductor packaging method of the present disclosure.

1 and 11 , after the fifth step ( S500 ), in the semiconductor packaging method of the present disclosure, a unit chip is separated by dicing the substrate, and an individual semiconductor is packaged by packaging the unit chip. A sixth step (S600) of manufacturing the package may be further included.

For example, the substrate 100 completed through the fifth step (S500) can be diced after removing the lower surface, that is, the first material layer by a back-side etching or polishing process, at this time Since dicing relates to a diamond material, mechanical cutting is difficult, and it is preferably performed using a microwave laser.

The microwave laser has a wavelength of 532 nm and a pulse width of 180 ns, and can be irradiated with a fast repetition rate of 6 kHz at low energy. However, those skilled in the art will understand that the wavelength, pulse width, and repetition rate of the microwave laser are not limited to these specific values.

By optimizing the size, pulse period, and applied energy of the microwave laser beam, the line width of the laser is limited to 70 μm to 100 μm, thereby minimizing the processing step and error of dicing.

The separated unit chip, for example, may be directly bonded to a printed circuit board or mounted in a predetermined housing, and may be sealed with a lid (lid) using epoxy.

The semiconductor packaging method and the semiconductor package according to the present disclosure described so far use a diamond material having excellent thermal conductivity as a substrate to replace the conventionally used copper or aluminum material to obtain an improved heat dissipation effect. In addition to the advantages that can be achieved, it is possible to improve the durability, reliability, output and efficiency of diamond-based semiconductors, especially III-V compound semiconductor packages, by proposing the parameters of process equipment optimized for manufacturing semiconductor packages using diamond materials. It works. In particular, the efficiency and operational stability of III-V compound semiconductor package chips requiring high performance are significantly improved by overcoming the limitations of the prior art in processing via holes for diamond substrates, copper filling, and diamond-metal dissimilar material bonding. There are advantages to doing.

Although the present invention has been described only in some selected embodiments above, those skilled in the art can easily understand the concept based on the present disclosure, and the concept as a design basis for modified structures for carrying out some purposes of the present invention will be able to easily use

The foregoing examples merely illustrate several possible embodiments of various aspects of the present disclosure, with equivalent modifications made by others skilled in the art upon reading and understanding this specification and the accompanying drawings. Waters and/or corrections will occur. In addition, although particular features of this disclosure may have been described and/or illustrated for only one of several embodiments, such features may be present in one or more other embodiments of any given application or other embodiments that may be desirable and advantageous for that particular application. It can be combined with features. Also, to the extent that the words "comprising", "comprises", "comprising", "having", "having", or variations thereof, are used in the specification and/or claims, such terms shall mean " It is intended to be inclusive in a manner analogous to the term "comprising".

100: substrate
120: via hole
130: dry film or photosensitizer
140: metal thin film pattern
190: vias for alignment
200: first material layer
240: a metal thin film formed on the first material layer
300: second material layer
300a: second silicon layer
340a: a metal thin film formed on the second silicon layer
350a: home
400: semiconductor die
300b: ceramic layer
500a: first packaging structure
510: ceramic material
520a: vertical electrode wiring
522a, 522b: capacitors
524a, 524b: inductors
526a: bump
500b: second packaging structure
600: unit chip
700: multiple inkjet nozzles
G: gate terminal
S: source terminal
D: drain terminal

Claims (19)

A first step of forming a via hole (via hole) in the substrate (S100);
Forming a metal thin film pattern on the upper surface of the substrate, forming a seed layer on the inner surface of the via hole, bonding a first material layer to the lower surface of the substrate, and then forming the via with a conductive metal material a second step of performing a hole filling process (S200);
a third step (S300) of performing heat treatment to increase adhesion between the seed layer and the substrate;
a fourth step (S400) of forming or bonding a second material layer on the substrate, wherein a semiconductor die is inserted into the second material layer; and
A fifth step of forming a stacked package structure electrically connected to the semiconductor die on the second material layer (S500)
A semiconductor packaging method comprising: According to claim 1,
The first step is
forming the via hole in the substrate using a microwave laser (S120);
cleaning the surface of the substrate (S140); and
Removing the residue adhering to the surface by immersing the cleaned surface in a strong acid solution (S160)
A semiconductor packaging method comprising: According to claim 1,
The substrate is a diamond substrate, and the conductive metal material is copper (Cu). 4. The method of claim 3,
wherein the seed layer comprises titanium (Ti), tungsten (W) or chromium (Cr) as a first bonding material. 5. The method of claim 4,
Titanium, tungsten or chromium of the first bonding material reacts with carbon of the diamond substrate by the heat treatment of the third step (S300). 5. The method of claim 4,
The second step is
forming a pattern (patterning) with a dry film or a photosensitive agent on the upper surface of the substrate (S210);
depositing the titanium, tungsten, or chromium as the first bonding material on the upper surface of the diamond substrate and the inner surface of the via hole (S220);
depositing gold (Au), silver (Ag), or copper (Cu) as a second bonding material on the first bonding material ( S240 ); and
A metal thin film pattern including the first bonding material and the second bonding material is formed by removing the dry film or the photosensitizer to remove the first bonding material and the second bonding material deposited on the dry film or the photosensitizer a lift-off step (S250)
A semiconductor packaging method comprising: 7. The method of claim 6,
The second step is
After the lift-off step (S250),
bonding a first material layer to the lower surface of the substrate (S260); and
A copper filling step of filling the via hole with copper, which is the conductive metal material (S270)
Further comprising a, semiconductor packaging method. 8. The method of claim 7,
The second step is
After the copper charging step (S270),
The method further comprising a polishing step (S280) of removing overfilled copper on the upper surface of the substrate. 7. The method of claim 6,
Between step S220 and step S240,
The method further comprising the step of forming a diffusion barrier layer on the first bonding material (S230), the semiconductor packaging method. 8. The method of claim 7,
In the first material layer, the first bonding material and the second bonding material are sequentially deposited on a surface to be bonded to the lower surface of the substrate. 7. The method of claim 6,
The fourth step is
bonding a second silicon (Si) layer, which is the second material layer, on the substrate (S410a);
forming a groove penetrating a portion of the second silicon layer by removing a portion of the silicon material included in the second silicon layer (S420a); and
Seating the semiconductor die in the groove and directly bonding the metal thin film pattern on the substrate (S430a)
A semiconductor packaging method comprising: 7. The method of claim 6,
The fourth step is
directly bonding the semiconductor die onto the metal thin film pattern of the substrate (S430b); and
Forming a ceramic layer, which is the second material layer, surrounding a part of the height of the semiconductor die on the substrate by inkjet printing using ceramic ink (S440b)
A semiconductor packaging method comprising: According to claim 1,
The fifth step is
A semiconductor packaging method comprising inkjet printing using ceramic ink and metal ink. 14. The method of claim 13,
The inkjet printing is performed in parallel on a plurality of unit chips included in the substrate using a plurality of inkjet nozzles. According to claim 1,
After the fifth step,
A sixth step (S600) of dicing the substrate to separate unit chips, and packaging the unit chips to manufacture individual semiconductor packages (S600)
Further comprising a, semiconductor packaging method. According to claim 1,
wherein the semiconductor die is a semiconductor die of a III-V compound. 17. The method of claim 16,
The III-V compound is gallium nitride (GaN), a semiconductor packaging method. According to claim 1,
wherein the first material layer is a first silicon (Si) layer. a substrate having via holes formed thereon;
a seed layer formed on an inner surface of the via hole;
a conductive metal material filled in the via hole over the seed layer;
a metal thin film pattern formed on the upper surface of the substrate and including a portion conducting the conductive metal material;
a second material layer formed on the metal thin film pattern and having a semiconductor die inserted therein; and
A stacked package structure formed on the second material layer to be electrically connected to the semiconductor die
A semiconductor chip comprising:
A semiconductor chip comprising a metal carbide between the seed layer and the substrate, and no other conductive material is interposed between the metal thin film pattern and the semiconductor die.

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