KR102451480B1 - Access detecting device - Google Patents

Abstract

An apparatus for detecting access of a word line in order to prevent distortion of data due to a row hammering phenomenon is provided.
An access detection apparatus according to an embodiment of the present invention includes: an access detection capacitor connected to a word line connected to a memory cell; and a controller configured to sense the voltage of the access detection capacitor and generate a flag when the voltage of the access detection capacitor is equal to or greater than a reference value.

Description

Access detection device {ACCESS DETECTING DEVICE}

The present invention relates to an access detection apparatus, and more particularly to an access detection apparatus capable of detecting access of a word line.

In a semiconductor device, a memory cell in which data is stored is implemented as a capacitor. Accordingly, when a specific word line is selected, the transistor connected to the word line is turned on, and the potential of the cell corresponding to the word line is output to the bit line.

The potential of these memory cells gradually decreases over time. That is, a capacitor used as a memory cell in a semiconductor device discharges its own charge over time, and thus data is lost. This is a fatal disadvantage for a memory device used to read and write data. Therefore, in order to ensure data reliability, all devices using a semiconductor device must perform a refresh operation for recovering the charge of the memory cell.

An object of the present invention is to provide an access detection apparatus for detecting access of a word line in order to determine a memory cell on which a refresh operation is to be performed.

An access detection apparatus according to an embodiment of the present invention includes an access detection capacitor connected to a word line connected to a memory cell, and sensing a voltage of the access detection capacitor, if the voltage of the access detection capacitor is equal to or greater than a reference value A control unit for generating a flag is included.

The access detection apparatus according to an embodiment of the present invention includes an access detection capacitor connected to a plurality of word lines, detects a voltage of the access detection capacitor, and sets a flag if the voltage of the access detection capacitor is greater than or equal to a reference value. control unit for generating

An access detection apparatus according to an embodiment of the present invention includes a first access detection capacitor connected to a first word line group including a plurality of word lines, and sensing a voltage of the first access detection capacitor, A first control unit generating a first flag when the voltage of the first access detection capacitor is equal to or greater than a first reference value, and a second word line including a plurality of word lines different from a plurality of word lines belonging to the first word line group a second access detection capacitor connected to the group; and a second controller configured to sense a voltage of the second access detection capacitor and generate a second flag if the voltage of the second access detection capacitor is equal to or greater than a second reference value; include

According to the access detection apparatus according to an embodiment of the present invention, it is possible to accurately detect the degree of access of a word line while minimizing an increase in the area of the apparatus. Accordingly, it is possible to prevent data distortion by performing refresh on a word line corresponding to a memory cell in which data may be deteriorated.

1 is a block diagram of a cell of a semiconductor device;
2 is a block diagram of a semiconductor device including an access detection apparatus according to an embodiment of the present invention;
Figure 3 is a detailed configuration diagram of the control unit of Figure 2;
Figure 4 is another detailed configuration diagram of the control unit of Figure 2;
5 is a block diagram of a semiconductor device including an access detection apparatus according to another embodiment of the present invention;
6 is a block diagram of a semiconductor device including an access detection apparatus according to another embodiment of the present invention;
7 is a block diagram of a system including an access detection apparatus according to another embodiment of the present invention;

Hereinafter, a preferred embodiment of the present invention will be described with reference to the drawings.

1 is a block diagram of a cell of a semiconductor device.

In FIG. 1, the word line WL<n> corresponds to a word line with a large number of activations, and the word line WL<n-1> and the word line WL<n+1> are disposed adjacent to the word line WL<n>, respectively. Corresponds to a word line, that is, a word line adjacent to a word line having a large number of activations. At the intersection of the word lines WL<n-1>, WL<n>, WL<n+1> and the bit lines BL<0>, BL<1>, a memory cell including a cell capacitor and a cell transistor is formed. have.

1, when word line WL<n> is activated or deactivated, between word line WL<n> and word line WL<n-1> and between word line WL<n> and word line WL<n+1> As the voltage on word line WL<n-1> and word line WL<n+1> rises or falls due to the coupling phenomenon that occurs, the voltage connected to word line WL<n-1> and word line WL<n+1> It also affects the amount of charge on the cell capacitor. Thus, word line WL<n-1> and the cell connected to word line WL<n+1> when word line WL<n> is activated frequently, causing word line WL<n> to toggle between enabled and disabled states. Data of the memory cell may be deteriorated because the amount of electric charge stored in the cell capacitor included in the memory cell is changed.

In addition, electromagnetic waves generated while the word line toggles an active state and an inactive state cause data to be corrupted by introducing electrons into or outflowing electrons from the cell capacitor of a memory cell connected to an adjacent word line.

As described above, a phenomenon in which data of a memory cell connected to a corresponding row or a neighboring row is damaged due to a high number of activations is called row hammering and is also called a word line disturbance phenomenon.

In order to prevent such row hammering, it is possible to provide a counter for each word line and additionally perform a refresh operation on a word line that is activated more than a preset number of times.

However, in this case, since a counter must be provided corresponding to each word line, it occupies a large area. In addition, since the method of including the counter does not directly detect whether the data of the memory cell is deteriorated, but only indirectly estimates whether the data of the memory cell is deteriorated from the value counted by the external address, the result may be inaccurate.

2 is a block diagram of a semiconductor device including an access detection apparatus according to an embodiment of the present invention.

Referring to FIG. 2 , a semiconductor device according to an embodiment of the present invention includes an access detection apparatus 100 and a memory cell 200 , and the access detection apparatus 100 includes an access detection capacitor C_DET and a controller 300 . includes

As described with reference to FIG. 1 , the memory cell 200 includes a cell capacitor C_CELL in which data is stored and a cell transistor TR_CELL. Cell transistor TR_CELL is coupled to word line WL. Cell capacitor C_CELL is connected to bit line BL through a cell transistor TR_CELL.

When an active signal is applied to the word line WL and the potential of the word line WL is boosted to a predetermined potential, for example, VPP, the cell transistor TR_CELL is enabled. Accordingly, when a read command is input, data stored in the cell capacitor C_CELL is transferred to and outputted to the bit line BL, and when a write command is input, data input through the bit line BL is transferred to the cell capacitor C_CELL. is saved

The access detection capacitor C_DET is located between the word line WL and the ground voltage. Accordingly, when the word line WL is enabled with VPP, VPP is also applied to the access detection capacitor C_DET to charge the access detection capacitor C_DET. Each time the word line WL is accessed, an electric charge is charged in the access detection capacitor C_DET, so that the potential of the access detection capacitor C_DET is proportional to the number of accesses of the word line WL.

The control unit 300 is connected to the access detection capacitor C_DET, detects the potential of the access detection capacitor C_DET, and outputs the result as a low hammering flag signal RH_FLAG.

Also, after enabling the low hammering flag signal RH_FLAG, the controller 300 may discharge charges charged in the access detection capacitor C_DET. For example, although not shown in FIG. 2, a switch is provided at both ends of the access detection capacitor C_DET, and the control unit 300 turns on the switch when the low hammering flag signal RH_FLAG is enabled. Charged charges can be discharged.

Hereinafter, a specific example of the control unit 300 will be described with reference to FIGS. 3 and 4 .

3 is a detailed configuration diagram of the control unit 300 of FIG. 2 .

The control unit 300 of FIG. 3 includes a switching unit 310 , a sensing unit 320 , and a comparison unit 330 .

The switching unit 310 connects or disconnects the access detection capacitor C_DET and the sensing unit 320 . For example, the switching unit 310 may be configured to be controlled by the word line enable signal WL_EN.

Specifically, when the word line enable signal WL_EN is enabled, the switch 310 is turned off. Accordingly, the capacitor C_DET for access detection is charged. In this case, since the access detection capacitor C_DET is not connected to the sensing unit 320 , the sensing unit 320 does not sense the voltage of the access detection capacitor C_DET.

Also, when the word line enable signal WL_EN is disabled, the switch 310 is turned on. Accordingly, the access detection capacitor C_DET and the sensing unit 320 are connected, and the potential of the access detection capacitor C_DET is transmitted to the sensing unit 320 .

That is, in the present embodiment, the switching unit 310 is controlled according to a value obtained by inverting the word line enable signal WL_EN. Accordingly, it is possible to prevent the access detection capacitor C_DET from being charged while sensing the access detection capacitor C_DET.

Also, the switching unit 310 may be configured to be controlled by other control signals capable of adjusting timing, rather than the word line enable signal. As described above, if the switching unit 310 is controlled according to the inverted value of the word line enable signal WL_EN, the switching unit 310 is connected to the sensing unit 320 whenever the word line is enabled. Accordingly, the sensing unit 320 detects the potential of the access detection capacitor C_DET whenever the word line is enabled. In this case, even though the potential of the access detection capacitor C_DET does not reach the reference value, unnecessary power may be wasted due to frequent sensing.

Accordingly, the control unit 300 may generate a control signal for turning on the switching unit 310 at a predetermined cycle. At this time, in order to detect the potential of the access detection capacitor C_DET while the access detection capacitor C_DET is not charged, the control signal for turning on the switching unit 310 is activated only while the word line enable signal WL_EN is disabled. can be enabled. That is, the control signal for turning on the switching unit 310 may be generated in consideration of both a predetermined period and the word line enable signal WL_EN.

When the sensing unit 320 is connected to the access detection capacitor C_DET by the switching unit 310 , the sensing unit 320 senses the potential V_C_DET of the access detection capacitor C_DET and outputs to the comparator 330 . do.

The comparison unit 330 compares the potential V_C_DET of the access detection capacitor C_DET with a preset value V_REF. Then, when the potential V_C_DET of the access detection capacitor C_DET is greater than the preset value V_REF, the low hammering flag signal RH_FLAG indicating whether low hammering occurs is enabled.

Although the subsequent process is not shown in the drawings, when the low hammering flag signal RH_FLAG is enabled, the data distortion due to the row hammering can be prevented by performing refreshing on the word line WL in which the row hammering flag signal RH_FLAG is enabled. .

FIG. 4 is another detailed configuration diagram of the control unit 300 of FIG. 2 .

The control unit 300 ′ of FIG. 4 includes a switching unit 310 , a sensing unit 320 , an analog-to-digital conversion unit 340 , and a comparison unit 330 ′.

Since the switching unit 310 and the sensing unit 320 are the same as the switching unit 310 and the sensing unit 320 of FIG. 3 , a description thereof will be omitted.

The analog-to-digital conversion unit 340 outputs a value V_C_DET' obtained by digitizing the potential V_C_DET of the access detection capacitor C_DET output from the sensing unit 320 by a predetermined number of bits.

The comparator 330' compares the potential V_C_DET' of the digitized access detection capacitor C_DET with a preset digitized value V_REF', so that the potential V_C_DET' of the digitized access detection capacitor C_DET is higher than the preset digitized value V_REF'. If it is large, the row hammering flag signal RH_FLAG indicating whether row hammering has occurred is activated.

Thereafter, as in FIG. 3 , when the row hammering flag signal RH_FLAG is activated, the word line WL in which the low hammering flag signal RH_FLAG is activated is refreshed, thereby preventing data distortion due to row hammering.

According to the semiconductor device having such a structure, by adding a capacitor C_DET for access detection having a simple structure instead of providing a counter for each word line WL, it is possible to directly detect whether the number of accesses of the word line WL exceeds the quoting limit. Accordingly, it is possible to prevent data distortion due to row hammering by performing refresh on the word line WL exceeding the quoting limit.

5 is a block diagram of a semiconductor device including an access detection apparatus according to another embodiment of the present invention.

The semiconductor device of FIG. 5 includes a plurality of word lines WL, memory cells CELL respectively connected to the word lines WL, and access detection devices 100_0 to 100_N connected to the word lines WL.

One access detection device 100_0 to 100_N is provided for every four word lines WL (word line group). Each of the access detection apparatuses 100_0 to 100_N includes an access detection capacitor (C_DET_0 to C_DET_N) and a control unit 300_0 to 300_N respectively connected to the access detection capacitor (C_DET_0 to C_DET_N).

In other words, unlike the access detection apparatus 100 of FIG. 2 connected for one word line WL, each of the access detection apparatuses 100_0 to 100_N of FIG. 5 is connected to four word lines (word line groups). is connected to

According to the semiconductor device of FIG. 5 having such a configuration, when at least one of the four word lines (word line groups) to which the access detection capacitors C_DET_0 to C_DET_N are connected is enabled, the access detection capacitors C_DET_0 to C_DET_N are charged .

The controllers 300_0 to 300_N sense potentials of the corresponding access detection capacitors C_DET_0 to C_DET_N. Then, when the potential is greater than a predetermined reference value, the group row hammering flag signals RH_FLAG_0 to RH_FLAG_N are enabled.

In this case, since four word lines (word line groups) are connected to each of the access detection capacitors C_DET_0 to C_DET_N, the charging speed may be faster than in the embodiment of FIG. 2 . Therefore, compared to the embodiment of FIG. 2 , the period for sensing the potentials of the access detection capacitors C_DET_0 to C_DET_N may be lengthened, or the reference value for enabling the group row hammering flag signals RH_FLAG_0 to RH_FLAG_N may be set higher. Alternatively, a period or a reference value may be set lower than in the embodiment of FIG. 2 .

Thereafter, although not shown in the drawing, when the group row hammering flag signals RH_FLAG_0 to RH_FLAG_N are enabled, refresh is performed on all four word lines connected to the access detection devices 100_0 to 100_N in which the row hammering flag signals RH_FLAG_0 to RH_FLAG_N are enabled. carry out

Then, the control unit 300_0 to 300_N discharges the access detection capacitors C_DET_0 to C_DET_N to prepare the access detection capacitors C_DET_0 to C_DET_N to be charged during the next cycle.

According to the semiconductor device of this embodiment, since only one access detection capacitor is provided for a plurality of word lines, it is impossible to know exactly which word line is in danger of low hammering, and in fact, data distortion due to low hammering The refresh may also be performed on a word line that is less likely to occur.

However, row hammering occurs between adjacent word lines. Accordingly, it may be more efficient to perform the refresh on a plurality of adjacent word lines together, rather than detecting the access level for each word line and performing the refresh. In addition, since only one access detection capacitor is provided for a plurality of word lines, the area required for installing the capacitor and the control unit can be reduced.

In the present embodiment, it has been described that four word lines connected to each access detection device 100_0 to 100_N are connected. However, this is only an example, and the number of word lines connected to each access detection device 100_0 to 100_N may be variously set.

In this case, as the number of word lines connected to each access detection device 100_0 to 100_N increases, the installation area of the capacitor and the controller decreases. However, since the refresh is performed even for a word line that is less likely to cause row hammering, the refresh execution time increases, thereby reducing efficiency. Accordingly, the number of word lines connected to each access detection device 100_0 to 100_N should be set to an appropriate value in consideration of an installation area and product efficiency.

In addition, different reference values for generating the group row hammering flag signals RH_FLAG_0 to RH_FLAG_N in the controllers 300_0 to 300_N in each of the access detection devices 100_0 to 100_N may be set differently. For example, if there is a high probability of low hammering in a group due to the characteristics of the device during testing, the reference value for generating the low hammering flag signal for the group may be set low.

6 is a block diagram of a semiconductor device including an access detection apparatus according to another embodiment of the present invention.

The semiconductor device of FIG. 6 includes a plurality of word lines WL, memory cells CELL respectively connected to the word lines WL, and access detection devices 100_0' to 100_N' connected to the plurality of word lines WL.

Each of the access detection devices 100_0' to 100_N' has access detection capacitors C_DET_0' to C_DET_N' connected to a plurality of word lines WL (word line group), and a control unit connected to the access detection capacitors C_DET_0' to C_DET_N', respectively. (300_0'~300_N'). Specifically, the access detection apparatus 100_0' is connected to k word lines (first word line group), and the access detection apparatus 100_1' is connected to m word lines (second word line group), and , the access detection apparatus 100_N' is connected to n word lines (N+1th word line group).

In other words, unlike each of the access detecting devices 100_0 to 100_N of the semiconductor device of FIG. 5 is connected to the same number of word lines, each of the access detecting devices 100_0' to 100_N' of the semiconductor device of FIG. 6 is , connected to a different number of word lines.

Accordingly, the number of word lines WL connected to the access detection devices 100_0' to 100_N' can be flexibly set in consideration of the area of the device, the range in which row hammering occurs, and the reduction in device efficiency due to refresh. .

In this case, the reference values for generating the group row hammering flag signals RH_FLAG_0' to RH_FLAG_N' in the control units 300_0' to 300_N' in each of the access detection devices 100_0' to 100_N' may be set differently. For example, the reference value may be set to be proportional to the size of each group Group_0' to Group_N'.

Although not shown in the drawings, the number of word lines to which the access detection device is connected may be partially made the same and some may be different.

The number of word lines to which the access detecting device is connected and the reference value used in the access detecting device are not limited to the above, and may be set in various ways.

7 is a block diagram of a semiconductor system including an access detection apparatus according to another embodiment of the present invention.

7 , the semiconductor system may include a host 3 and a semiconductor device 1 , and the semiconductor device 1 may include a memory controller 20 and a memory 10 .

The host 3 may transmit a request and data to the memory controller 20 to access the memory 10 . The host 3 may transmit data to the memory controller 20 to store the data in the memory 10 . Also, the host 3 may receive data output from the memory 10 through the memory controller 20 . The memory controller 20 may control the memory 10 to perform a write or read operation by providing data information, address information, memory setting information, a write request, a read request, etc. to the memory 10 in response to the request. . The memory controller 20 may relay communication between the host 3 and the memory 10 . The memory controller 20 receives a request and data from the host 3 and controls the operation of the memory 10 with data DQ, data strobe DQS, command CMD, and a memory address signal ADD. and a clock signal CLK may be generated and provided to the memory 10 . Also, the memory controller 20 may provide the data DQ and the data strobe DQS output from the memory 10 to the host 3 .

The above-described access detection apparatus 100 may be included in the memory 10 . Accordingly, when the memory address signal ADD is input from the memory controller 20 and a corresponding word line is enabled, the access detection capacitor in the access detection apparatus 100 connected to the corresponding word line is charged. When the number of accesses of the word line increases and the charge amount of the access detection capacitor increases, and accordingly, when the potential of the access detection capacitor becomes equal to or greater than a predetermined reference value, the access detection apparatus 100 enables the low hammering flag signal. . Accordingly, refresh is performed on the word line.

Although the access detection apparatus 100 is illustrated as being included in the memory 10 in FIG. 7 , the access detection capacitor may be located in the memory 10 , and the control unit may be located in the memory controller 20 .

In FIG. 7 , the host 3 and the memory controller 20 are physically separated, but the memory controller 20 is a central processing unit (CPU), an application processor (AP), and a graphic processing unit of the host 3 . It may be included (embedded) in a processor such as (GPU) or implemented as a single chip together with these processors in the form of an SoC (System On Chip).

The memory 10 includes at least one access detection device 100 , and includes a command CMD, a memory address signal ADD, data DQ, a data strobe DQS, and a clock signal from the memory controller 20 . CLK) and the like, and a data reception operation may be performed based on the signals.

The memory 10 may include a plurality of memory banks, and may store the data DQ in a specific area among the banks of the memory based on the memory address signal ADD. Also, the memory 10 may perform a data transmission operation based on the command CMD received from the memory controller 20 , the memory address signal ADD, the data strobe DQS, and the like. The memory may transmit data stored in a specific region of the memory bank to the memory controller 20 based on the memory address signal ADD, the data DQ, and the data strobe DQS.

It is common in the technical field to which the present invention pertains that the present invention described above is not limited to the above-described embodiments and the accompanying drawings, and various substitutions, modifications and changes are possible within the scope without departing from the technical spirit of the present invention. It will be clear to those who have the knowledge of

Claims (20)

a capacitor for access detection coupled to the word line coupled to the memory cell; and
a control unit sensing a voltage of the access detection capacitor and generating a flag when the voltage of the access detection capacitor is equal to or greater than a reference value;
including,
The access detection capacitor is charged when the word line is enabled. ◈Claim 2 was abandoned when paying the registration fee.◈ The method of claim 1,
The control unit is
a sensing unit sensing a voltage of the access detection capacitor; and
a comparator for generating the flag when the voltage of the access detection capacitor is equal to or greater than a reference value;
Access detection device comprising a. ◈Claim 3 was abandoned when paying the registration fee.◈ According to claim 2, wherein the control unit,
A switching unit connecting or disconnecting the access detection capacitor and the sensing unit based on a word line enable signal enabling the word line
Access detection apparatus further comprising a. ◈Claim 4 was abandoned when paying the registration fee.◈ 4. The method of claim 3,
and the switching unit separates the access detection capacitor from the sensing unit when the word line enable signal is enabled. ◈Claim 5 was abandoned when paying the registration fee.◈ 4. The method of claim 3,
and the switching unit connects the access detection capacitor and the sensing unit when the word line enable signal is disabled. ◈Claim 6 was abandoned when paying the registration fee.◈ 6. The method of claim 5,
and the sensing unit detects a potential of the access detection capacitor when the word line enable signal is disabled. ◈Claim 7 was abandoned when paying the registration fee.◈ According to claim 2, wherein the control unit,
An analog-to-digital converter that digitizes the voltage of the capacitor for access detection output from the sensing unit into a predetermined number of bits
additionally provided,
and the comparison unit compares the voltage of a predetermined number of bits output from the analog-digital conversion unit with a reference value expressed by the predetermined number of bits. delete delete delete delete delete delete delete delete delete delete delete delete delete

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