KR102450890B1 - Non-Volatile Memory circuit - Google Patents

Abstract

The present invention relates to a non-volatile memory circuit, which detects a change in an external power supply voltage VCC to control the enabled number of VPP charge pump circuits to pump maximum VPP in a wide voltage range of 2.5V to 5.5V even when VCC increases It is possible to reduce the ripple voltage by suppressing the current.
To this end, the present invention includes a non-volatile memory cell array in which a plurality of non-volatile memory cells are arranged, and a pumping voltage generator circuit that detects a change in an external power supply voltage VCC and controls the enabled number of VPP charge pumps according to the VCC voltage. Thus, it is possible to suppress the VPP pumping current according to the VCC voltage fluctuation and reduce the ripple voltage.

Description

Non-Volatile Memory circuit

The present invention relates to a non-volatile memory (NVM) circuit using a vertical PIP (Polysilicon-Insulator-Polysilicon) capacitor, and more particularly, to an external power applied to a non-volatile memory using a vertical PIP capacitor. By detecting the VCC voltage, which is the voltage, and controlling the number of enabled charge pump circuits, even if the VCC voltage increases, the VPP pumping current is suppressed to a maximum of 474.6 [㎂] in the wide VCC voltage range of 2.5V to 5.5V, thereby reducing the voltage of the VPP charge pump. The present invention relates to a nonvolatile memory circuit in which the ripple voltage can be reduced to within 3% of a target voltage, for example, when the target voltage is 7.5V, the ripple voltage can be reduced to within 0.19V.

In general, in MCU (Micro Controller Unit), etc., high-speed read operation of 40 [ns] or less is possible and EEPROM (Electrically Erasable Programmable Read-Only Memory) or flash with high-speed write operation characteristics to reduce tester time. Non-volatile memory such as memory IP (Intellectual Property) is required, and semiconductor chips used in applications such as wireless charger and USB type-C require EEPROM memory IP for MCU.

FG devices, which are floating gates (hereinafter referred to as FGs) with a storage layer for storing electric charges, are frequently used in EEPROM cells. In particular, 2T (Two Transitor) FG EEPROM cells with excellent performance and power consumption characteristics are mainly used. It is used a lot. Meanwhile, a double poly EEPROM cell using a split gate EEPROM cell, which is a 2T FG EEPROM cell, has been announced, which is erased and programmed by Fowler-Nordheim (FN). Although the tunneling method is a coupling capacitor of the EEPROM cell, it is a double poly EEPROM cell structure of a vertical PIP capacitor, so the cell size in the 110nm manufacturing process is as small as 0.97 [㎛ ² ]. For reference, below, it is stated in advance that all of the values are in the 110nm manufacturing process. Like the double poly EEPROM cell, the single poly EEPROM cell performs FN tunneling erase and program operations using a positive pumping voltage VPP and a negative pumping voltage VNN. Meanwhile, VPP and VNN voltages are applied to the P-Well (hereinafter referred to as PW) forming the coupling capacitor of the cell in which the program operation is performed and the PW forming the tunnel gate_sense (TG_SENSE) transistor, respectively, and the erase operation is performed. Since VNN and VPP voltages must be applied to PW forming the cell coupling capacitor and PW forming the TG_SENSE transistor, respectively, the coupling capacitor and the TG_SENSE transistor in the deep N-Well (DNW) of the single poly EEPROM cell array The PW has to be separated from each other so that the cell size is as large as 33 [㎛ ² ]. Meanwhile, in order to reduce the cell size of a single poly EEPROM, it is necessary to form devices in the same PW. A single poly EEPROM cell that forms a device within the same PW uses a lateral MIP (Metal-Insulator-Polysilicon) capacitor while programming the FG EEPROM cell using the CHEI (Channel Hot Electron Injection) method. Bias PW to GND. In order to maintain the coupling ratio at 0.815, the cell size is also large at 7.37 [㎛ ² ] because the area occupied by the lateral MIP capacitor is large. An MTP cell with a merged MOS capacitor has been proposed, which uses a Band-To-Band Tunneling (BTBT) method for erasing and a Hot Carrier Injection (HCI) method for programming, but PW is biased to GND. Although there is an advantage of reducing the cell size by eliminating the need for a separate PW in the PW, there is a limit to reducing the cell size when a merged MOS capacitor is to be formed in the PW.

On the other hand, MTP memory IP required for applications such as USB type-C requires that the power supply voltage VCC be operated in a wide range of 2.5V to 5.5V. However, while the pumping current of the VPP charge pump circuit is the lowest when the VCC voltage is the minimum of 2.5V, the ripple voltage is rather large when the VCC voltage is 5.5V. If the programming of a 32-bit memory cell array requires a VPP pumping current of 320 [㎂] or more, the ripple voltage of the conventional VPP charge pump appears too high from a VCC of 5.5V to 0.85V in the simulation. Therefore, in order to guarantee durability and retention characteristics in a wide voltage range of 2.5V to 5.5V, it is necessary to suppress the ripple voltage of the VPP charge pump circuit within 3% if possible.

KR 10-2082147 B1 2020.02.21. registration

Accordingly, the present invention has been devised to solve the above problems, and the technical problem to be solved by the present invention is to detect the applied power voltage VCC and to determine the number of enabled and operating among the plurality of charge pump circuits. The goal is to provide a nonvolatile memory circuit that can reduce the ripple voltage by suppressing the maximum VPP pumping current in a wide VCC voltage range of 2.5V to 5.5V even when VCC is high by implementing a controlling pumping voltage generator circuit.

One embodiment of the present invention for achieving the above object is a cell array in which non-volatile memory cells are arranged; A pumping voltage generator circuit including a plurality of charge pump circuits and a power supply voltage detector sensing a change in the supplied power voltage, wherein the power voltage detector detects a change in the external power supply voltage, It is a nonvolatile memory circuit configured to control the number of enabled and operated charge pump circuits, and to suppress the VPP pumping current and reduce the ripple voltage according to the VCC voltage.

In the present invention, the nonvolatile memory cell array may be formed by arranging MTP cells constituting a coupling capacitor as a vertical PIP capacitor.

According to the present invention, VPP in a wide VCC voltage range of 2.5V to 5.5V even when VCC increases by detecting the VCC voltage, which is an external power supply applied to the nonvolatile memory cell, and controlling the number of enabled VPP charge pump circuits. By suppressing the pumping current to a maximum of 474.6 [㎂], the ripple voltage of the VPP charge pump can be reduced within 3% (0.19V) of the target voltage (7.5V).

1 is an equivalent circuit diagram of an MTP cell using a vertical PIP capacitor exemplifying an example of a nonvolatile memory circuit proposed in the present invention.
2 is a block diagram illustrating a configuration of a pumping voltage generator circuit applicable to a nonvolatile memory circuit according to the present invention.
3 is a block circuit diagram of a DC-DC converter using a charge pumping method used for a VPP boosting voltage in the present invention.
4 is a detailed circuit diagram of a unit charge pump used in the 4-stage VPP charge pump circuit of FIG. 3 .
5 is a waveform diagram illustrating a simulation result of a four-phase charge pumping operation.
6 is a detailed circuit diagram of the VCC detection circuit of FIG.
7 is a graph illustrating the result of comparing the ripple voltage for each VCC of the VPP charge pump circuit proposed in the present invention with the existing VPP charge pump circuit under the simulated conditions of Temp.=25° C. and typical model parameters.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, the configuration and operation of a non-volatile memory circuit according to a preferred embodiment of the present invention and the effects thereof will be described in detail with reference to the accompanying drawings.

The terms or words used in the present specification and claims are not to be construed as limited in their ordinary or dictionary meanings, and on the principle that the inventor can appropriately define the concept of the term in order to best describe his invention. It should be interpreted as meaning and concept consistent with the technical idea of the present invention. Therefore, it is understood that since the embodiments described in this specification and the configurations shown in the drawings are only the most preferred embodiment of the present invention, there may be various equivalents and modifications that can be substituted for them at the time of the present application. shall.

2 is an equivalent circuit diagram of an MTP cell exemplifying an example of a non-volatile memory circuit according to the present invention. A non-volatile memory cell array to which the present invention can be applied is a vertical PIP capacitor and an MTP constituting a coupling capacitor. Multi-Time Programmable (MTP) cells may be arranged, and in the present invention, a case in which MTP cells constituting a coupling capacitor are arranged as a non-volatile memory cell array as an example in a vertical PIP capacitor. decide to do

As illustrated in FIG. 2, the MTP cell using the vertical PIP capacitor constitutes a coupling capacitor with a vertical PIP (Poly-Insulator-Poly) capacitor having a large capacitance per unit area, and the MTP cell array has a coupling capacitor. MTP cells with a reduced area occupied are arranged. In this MTP cell, a vertical PIP capacitor (C1) which is a coupling capacitor having one terminal connected to a control gate of 5V, an erase gate oxide capacitor (C2), a floating gate is connected to the other terminal of the coupling capacitor, and one terminal is connected to the other terminal of the coupling capacitor. It consists of a floating gate MOS transistor MN1 connected to the bit line BL and the other terminal connected to a select transistor, and a select transistor MN2 for reducing off-leakage current in the bit line BL during over-erasing. .

In the MTP cell, the control gate (CG), select gate (SG), and source line (SL) signals are routed in the row direction, and the bit line (BL) and erase gate (EG) signals are routed in the column direction. In addition, the floating gate MOS transistor MN1 and the select transistor MN2 used in the MTP cell and the pwell of the erase gate n+ junction are shared.

Table 1 below illustrates bias conditions for each operation mode of the MTP cell.

[Table 1]

As can be seen from Table 1, the erase mode uses a page erase method in which one page corresponding to a 1024-bit cell connected to one row is erased at once in order to reduce the erase time. When biasing voltages of -7.5V, 0V, 0V, 0V, 7.5V and 0V to CG, SG, SL, BL, EG, and PW of cells connected to the selected page row in page erase mode, respectively, As electrons in the floating gates FG of all cells connected to the row are erased by the erase gate node, the threshold voltage VTE of the floating gate MOS transistor MN1 of the erased cells becomes about -0.5V. On the other hand, in program mode, programs are performed by 32 bits, and when voltages of 5V, 2.5V, 0V, 7.5V, 0V and 0V are biased to CG, SG, SL, BL, EG, and PW, respectively, the cell selected by HCI As electrons are injected into the floating gate of , the threshold voltage VTP of the floating gate MOS transistor MN1 of the programmed cell becomes about 4V. On the other hand, in the read mode, when the voltages of 1.5V, 5V, 0V, 0V and 0V are biased to CG, SG, SL, EG, and PW, respectively, and the BL voltage is precharged to VDD-V _T , the BL of the erased cell is close to 0V. On the other hand, the BL of the programmed cell remains at VDD-V _T .

2 is a block diagram of a pumping voltage generator circuit applicable to a non-volatile memory circuit according to the present invention, preferably an MTP memory. and a pumping voltage generator circuit 10 for detecting and controlling the number of turned-on VPP charge pumps of the VPP charge pump circuit according to the VCC voltage to regulate the maximum pumping current of the VPP charge pump circuit, wherein the VPP pumping according to the VCC voltage It is configured to reduce the ripple voltage of the VPP charge pump to within 3% (0.19V) of the target voltage (7.5v) by suppressing the current. This pumping voltage generator circuit 10 may be configured to include a VPP charge pump circuit 11 , a VCC detector circuit 12 , a VPP level detector 13 , a ring oscillator 14 , and a VPP precharging circuit 15 . can

The VPP charge pump circuit 11 applies the bias voltage of the MTP cell for each operation mode to the P-well forming the coupling capacitor of the MTP cell and the P-well forming the tunnel gate_sense (TG_SENSE) transistor. do. This VPP charge pump circuit 11 may consist of N M-stage VPP charge pumps. Here, N is determined by the N oscillation signals OSC[N-1:0] output from the ring oscillator, and M is the number of units in which the unit charge pumps are cascaded, that is, for example, a unit as illustrated in FIG. 5 to be described later. It is determined by how many cascades of charge pumps are connected. Preferably eight four-stage charge pumps.

The VCC detector circuit 12 detects the VCC voltage, which is an external power supply, and controls each unit charge pump of the VPP charge pump circuit 11 according to the VCC voltage.

The VPP level detector 13 detects the level of the positive pumping voltage VPP during a program operation or an erase operation, and the VPP level detector 13 divides the VPP voltage by 1/5, the voltage VPP_DIV and VREF_VPP( =1.5V) and when the VPP voltage is lower than 7.5V, VDD is provided to the ring oscillator 14 as an enable (OSC_EN) signal to operate the ring oscillator 14, thereby causing N M-stage VPP charges Boost the VPP voltage by pumping in the pump circuit.

The ring oscillator 14 generates and outputs the OSC_A signal and the OSC_B signal having a phase difference of 90 degrees to the VPP charge pump circuit 11 .

The VPP precharging circuit 15 is connected to the VPP charge pump circuit 11 .

Table 2 below illustrates the main features of 512Kb MTP memory IP.

[Table 2]

As can be seen from Table 2, the voltage used in the 512Kb MTP memory IP uses dual power of VCC and VDD (=1.5V), and the VCC voltage has a wide operating voltage range of 2.5V to 5.5V. have The normal operation modes are read mode, page erase mode, and program mode. Write-verify-read mode is erase-verify-read and program-verify-read mode. There is a program-verify-read mode. The MTP cell array may consist of 512 rows x 1,024 columns, and read, page erase, and program operations are performed in units of 32 bits, 1 Kbit, and 32 bits, respectively. On the other hand, the erase time, program time, and read access time are 20 [ms], 20 [㎲] and 40 [ns], respectively.

Table 3 below exemplifies the voltage source output voltage and circuit types of the DC-DC converter for each operation mode.

[Table 3]

Referring to Tables 2 and 3, in order to supply the cell bias voltage for each operation mode of Table 1, as illustrated in Table 3, VRD (Read Voltage) as a voltage regulator, VCP and VEVR (Erase-Verify) using a voltage follower circuit -Read Voltage), VPP(Boosted Voltage), V5V(5VPower), VPVR(Program-Verify-Read Voltage) as positive charge pump circuit, VNN(Negative Voltage) and VNNL(Lower VNN) generating circuit as negative charge pump circuit need.

Also, as can be seen from Table 2, a voltage of 7.5V is required for the BL selected in the program mode, and a voltage of 7.5V is required for all EG nodes in the page erase mode as well. However, the 7.5V voltage is higher than the external voltage source, VCC, and in order to program a 32-bit cell in the HCI method, a driving current of 160 [㎂] or more is required considering the current of 5 [㎂] per cell.

The DC-DC converter for the VPP boosting voltage, which is a voltage higher than the VCC voltage, can use the PWM (Pulse Width Modulation) method and the charge pumping method, but when the required driving current is as small as 320 [㎂] considering the design margin Since the charge pumping method can be designed with a small layout area, the VPP charge pump circuit of the charge pumping method as illustrated in FIG. 4 is used in the present invention.

3 is a block circuit diagram of a DC-DC converter using a charge pumping method used for VPP boosting voltage in the present invention. As illustrated in FIG. 4, a ring oscillator includes eight oscillation signals OSC[7:0]. ], and a 2-phase cross-coupled unit charge pump circuit is used to reduce the peak current of the VCC supply voltage source during charge pumping to lower electromagnetic interference (EMI) characteristics. However, although the ring oscillator used in FIG. 4 has a long oscillation period and can output 8 OSCs[7:0], the pumping current of the VPP charge pump used for MTP IP is 320[㎂] or more in consideration of the design margin. In the case of designing with VCC=5.5V, FF (Fast NMOS, Fast PMOS) model parameters, and Temp.=-40℃, the oscillation period is as short as 15.7ns, so it is not possible to create 8 OSC output signals and a 90 degree phase difference OSC_T and OSC_B signals can be created and designed, and each OSC_T and OSC_B signal is connected to a 4-stage VPP charge pump circuit, respectively. The unit charge pump used in this 4-stage VPP charge pump circuit is illustrated in the detailed circuit diagram of FIG. 5, and the simulation result of the 4-phase charge pumping operation is illustrated in the waveform diagram in FIG.

As illustrated in FIG. 4 , each unit charge pump of the 4-stage VPP charge pump includes an NMOS charge transfer switch (MN1, MN2), a cross-coupled PMOS charge transfer switch (MP1, MP2). , body potential biasing circuits (MP3, MP4, MP5, MP6), gate boosting circuits (MN3, MN4, MC0, MC3) and pumping capacitors (MC1, MC2). Here, the pumping capacitor uses an isolated NMOS transistor of 5V, and the four clock signals (CLK0, CLK1, CLK2, CLK3) are non-overlap clock signals and are switched to VCC voltage. Since this unit charge pumping circuit is a two-phase charge pumping circuit in which charge pumping occurs once at the rising edge of CLK1 and CLK2 during one cycle, if OSC_T and OSC_B with a 90 degree phase difference each have a 4-stage charge When the pump circuit is driven, as can be seen from the waveform diagram of FIG. 5, it operates as a four-phase charge pump that pumps charges four times during one cycle oscillation. However, when a 4-phase 4-stage VPP charge pump is used, the pumping current of the VPP charge pump must be designed to satisfy the pumping current of 320 [㎂] when the VCC voltage is the minimum of 2.5V. If it is designed to satisfy the pumping current of 320[㎂] at the VCC of 2.5V, the ripple voltage is 0.85V as a result of SPICE simulation because it is supplied too high as 1.9[mA] at the VCC of 5.5V. Therefore, the VPP ripple voltage appears large when the VCC voltage is 5.5V.

6 is a detailed circuit diagram of the VCC detection circuit 12 of FIG. 3 . The VCC detector circuit 12 may be implemented using a Flash A/D converter having six outputs, and the VCC voltage, which is an external power supply, is A driving signal is provided to eight 4-stage VPP charge pump circuits according to the VCC voltage compared to each preset reference voltage. Here, the VCC detector circuit 12 applies driving signals to each of the three charge pumps except for the top charge pump among the four four-stage VPP charge pump circuits disposed above and below according to the VCC detection result, respectively. to provide.

Table 4 below exemplifies the number of VPP charge pumps that are turned on according to the VCC detection result of the VCC detection circuit 12 .

[Table 4]

As can be seen from Table 4, in the VPP voltage generator circuit 10 of the nonvolatile memory circuit according to the present invention, the VCC voltage detected by the VCC detection circuit 12 is 8 up to 2.4V, 7 at 2.5V, Only 6 4-stage VPP charge pumps up to 2.6V, 5 up to 2.9V, 4 up to 3.3V, 3 up to 4.1V, and two up to 5.5V are set to turn on. In the case of using such a VCC detection circuit, in the pumping voltage generator circuit 10 according to the present invention, as illustrated in FIG. 3 , the number of charge pumps that are turned on among the eight 4-stage VPP charge pump circuits 11 is VCC It can be controlled according to the detection result.

Table 5 below compares the pumping current of the 4-stage charge pump for each VCC, the number of turned on charge pumps, and the total VPP pumping current measured under simulated conditions of Temp.=25℃ and typical model parameters.

[Table 5]

As can be seen from Table 5 above, the pumping current of the 4-stage VPP charge pump increases as VCC increases, whereas as VCC increases, the ON pumping current is regulated so that the total VPP pumping current satisfies 320 [㎂] or more. And even if VCC was increased, the total VPP pumping current could be suppressed to a maximum of 474.6 [㎂].

7 is a graph illustrating the result of comparing the ripple voltage for each VCC of the VPP charge pump circuit proposed in the present invention with the existing VPP charge pump circuit under the simulated conditions of Temp.=25° C. and typical model parameters. As shown in the figure, in the case of the VPP charge pump circuit 11 using the VCC detection circuit 12 of the present invention, the maximum VPP pumping current can be suppressed to 474.6 [㎂] by controlling the number of 4-stage VPP charge pumps that are turned on. Therefore, it can be seen that the VPP ripple voltage shows good ripple voltage characteristics of about 0.19V, which is lower than 0.85V of the conventional VPP charge pump circuit, as illustrated in the figure.

According to the present invention configured as described above, it is possible to implement an MTP cell using a vertical PIP capacitor as a coupling capacitor using the Hynix 110nm process, and the erase operation is performed between FG and EG instead of FN tunneling between FG and PW. Since the FN tunneling of the FN tunneling and the CHEI implantation method are used for the program operation, the MTP cell size can be reduced to 1.09 [㎛ ² ] by sharing the PW (=0V) of the MTP cell array.

And in the 512Kb MTP IP implemented using the MTP cell, it is possible to control the number of VPP charge pumps that are turned on by using the VCC detector circuit. The pumping current can be suppressed to a maximum of 474.6 [㎂], and the VPP pumping current can be suppressed by using a circuit that controls the number of VPP charge pumps that are turned on. V) can be reduced to within

10: pumping voltage generator circuit 11: charge pumping circuit
12: power supply voltage detector 13: level detector
14: ring oscillator 15: precharging circuit

Claims (6)

a memory cell array in which non-volatile memory cells are arranged; and
A plurality of charge pump circuits, and a pumping voltage generator circuit including a power supply voltage detector sensing a change in the supplied power supply voltage; and
The power supply voltage detector detects a change in the power supply voltage, and controls the number of enabled and operated among the plurality of charge pump circuits,
The pumping voltage generator circuit comprises:
a VPP charge pump circuit 11 for applying a VPP voltage to a pwell forming a coupling capacitor of each memory cell of the memory cell array and a pwell forming a tunnel gate_sense transistor;
a VCC detector circuit 12 for detecting a voltage VCC that is an external power supply;
a VPP level detector 13 for detecting the level of the positive pumping voltage VPP during a program operation or an erase operation;
a ring oscillator 14 for generating and outputting an OSC_T signal and an OSC_B signal having a phase difference of 90 degrees to the VPP charge pump circuit 11; and
and a VPP precharging circuit (15) connected to the VPP charge pump circuit (11). delete According to claim 1, wherein the VPP charge pump circuit (11),
It consists of N M-stage VPP charge pumps, where N is determined by the number of oscillating signals OSC[N-1:0] of the ring oscillator and M is determined by the number of cascaded stages of unit charge pumps. Characterized by a non-volatile memory circuit. 4. The method of claim 3, wherein each unit charge pump of the M-stage VPP charge pump comprises:
NMOS charge transfer switches (MN1, MN2), cross-coupled PMOS charge transfer switches (MP1, MP2), body potential biasing circuits (MP3, MP4, MP5, MP6), N0 and N3 A non-volatile memory circuit comprising a gate boosting circuit (MN3, MN4, MC0, MC3) and a pumping capacitor (MC1, MC2) that switch nodes between VIN and VIN+VCC. delete The non-volatile memory circuit according to claim 1, wherein, depending on the enable operation, a ripple voltage of the charge pump can be reduced to 3% or less of a target voltage.

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