KR102448124B1 - 가상 주소들을 사용하여 액세스된 캐시 - Google Patents

가상 주소들을 사용하여 액세스된 캐시 Download PDF

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KR102448124B1
KR102448124B1 KR1020177020817A KR20177020817A KR102448124B1 KR 102448124 B1 KR102448124 B1 KR 102448124B1 KR 1020177020817 A KR1020177020817 A KR 1020177020817A KR 20177020817 A KR20177020817 A KR 20177020817A KR 102448124 B1 KR102448124 B1 KR 102448124B1
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address
virtual
virtual address
cache
memory
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KR20170100003A (ko
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구린다 에스. 소히
홍일 윤
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위스콘신 얼럼나이 리서어치 화운데이션
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    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/10—Address translation
    • G06F12/1009—Address translation using page tables, e.g. page table structures
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0893—Caches characterised by their organisation or structure
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0602—Interfaces specially adapted for storage systems specifically adapted to achieve a particular effect
    • G06F3/061—Improving I/O performance
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0628—Interfaces specially adapted for storage systems making use of a particular technique
    • G06F3/0638—Organizing or formatting or addressing of data
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0628—Interfaces specially adapted for storage systems making use of a particular technique
    • G06F3/0662—Virtualisation aspects
    • G06F3/0664—Virtualisation aspects at device level, e.g. emulation of a storage device or system
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0668—Interfaces specially adapted for storage systems adopting a particular infrastructure
    • G06F3/0671—In-line storage system
    • G06F3/0673—Single storage device
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/10—Providing a specific technical effect
    • G06F2212/1016—Performance improvement
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/50—Control mechanisms for virtual memory, cache or TLB
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/60—Details of cache memory
    • G06F2212/608—Details relating to cache mapping
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/68—Details of translation look-aside buffer [TLB]

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Human Computer Interaction (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
KR1020177020817A 2014-12-26 2015-12-10 가상 주소들을 사용하여 액세스된 캐시 Active KR102448124B1 (ko)

Applications Claiming Priority (7)

Application Number Priority Date Filing Date Title
US201462096962P 2014-12-26 2014-12-26
US62/096,962 2014-12-26
US201462097342P 2014-12-29 2014-12-29
US62/097,342 2014-12-29
US14/867,926 2015-09-28
US14/867,926 US10089240B2 (en) 2014-12-26 2015-09-28 Cache accessed using virtual addresses
PCT/US2015/064955 WO2016105961A1 (en) 2014-12-26 2015-12-10 Cache accessed using virtual addresses

Publications (2)

Publication Number Publication Date
KR20170100003A KR20170100003A (ko) 2017-09-01
KR102448124B1 true KR102448124B1 (ko) 2022-09-28

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Country Status (6)

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US (1) US10089240B2 (enExample)
EP (1) EP3238074B1 (enExample)
JP (1) JP6696987B2 (enExample)
KR (1) KR102448124B1 (enExample)
CN (1) CN107111455B (enExample)
WO (1) WO2016105961A1 (enExample)

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US9772943B1 (en) * 2016-04-01 2017-09-26 Cavium, Inc. Managing synonyms in virtual-address caches
US20180173637A1 (en) * 2016-12-21 2018-06-21 Intel Corporation Efficient memory aware cache management
US10606762B2 (en) 2017-06-16 2020-03-31 International Business Machines Corporation Sharing virtual and real translations in a virtual cache
US10698836B2 (en) 2017-06-16 2020-06-30 International Business Machines Corporation Translation support for a virtual cache
US10831664B2 (en) 2017-06-16 2020-11-10 International Business Machines Corporation Cache structure using a logical directory
US10402337B2 (en) 2017-08-03 2019-09-03 Micron Technology, Inc. Cache filter
US10324846B2 (en) 2017-09-21 2019-06-18 International Business Machines Corporation Bits register for synonyms in a memory system
US10572256B2 (en) 2017-10-06 2020-02-25 International Business Machines Corporation Handling effective address synonyms in a load-store unit that operates without address translation
US10606590B2 (en) 2017-10-06 2020-03-31 International Business Machines Corporation Effective address based load store unit in out of order processors
US10394558B2 (en) 2017-10-06 2019-08-27 International Business Machines Corporation Executing load-store operations without address translation hardware per load-store unit port
US10606591B2 (en) 2017-10-06 2020-03-31 International Business Machines Corporation Handling effective address synonyms in a load-store unit that operates without address translation
US10417002B2 (en) 2017-10-06 2019-09-17 International Business Machines Corporation Hazard detection of out-of-order execution of load and store instructions in processors without using real addresses
US10534616B2 (en) 2017-10-06 2020-01-14 International Business Machines Corporation Load-hit-load detection in an out-of-order processor
GB2579534B (en) * 2017-10-06 2020-12-16 Ibm Load-store unit with partitioned reorder queues with single CAM port
US11175924B2 (en) * 2017-10-06 2021-11-16 International Business Machines Corporation Load-store unit with partitioned reorder queues with single cam port
US11392508B2 (en) * 2017-11-29 2022-07-19 Advanced Micro Devices, Inc. Lightweight address translation for page migration and duplication
GB2570691B (en) * 2018-02-02 2020-09-09 Advanced Risc Mach Ltd Controlling guard tag checking in memory accesses
CN111124945B (zh) * 2018-10-30 2023-09-22 伊姆西Ip控股有限责任公司 用于提供高速缓存服务的方法、设备和计算机可读介质
US11010067B2 (en) 2018-12-28 2021-05-18 Intel Corporation Defense against speculative side-channel analysis of a computer system
CN112579170B (zh) * 2020-12-10 2022-11-08 海光信息技术股份有限公司 一种用于减少虚拟地址计算的处理器及其方法
US11461247B1 (en) * 2021-07-19 2022-10-04 Arm Limited Granule protection information compression
US12105634B2 (en) 2021-09-27 2024-10-01 Ati Technologies Ulc Translation lookaside buffer entry allocation system and method
CN113934655B (zh) * 2021-12-17 2022-03-11 北京微核芯科技有限公司 解决高速缓冲存储器地址二义性问题的方法和装置
CN119719018A (zh) * 2024-11-15 2025-03-28 北京航空航天大学 面向多类神经网络协同场景的张量感知片上缓存系统

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EP3238074A4 (en) 2018-08-08
JP2018504694A (ja) 2018-02-15
US10089240B2 (en) 2018-10-02
EP3238074A1 (en) 2017-11-01
EP3238074B1 (en) 2019-11-27
CN107111455A (zh) 2017-08-29
KR20170100003A (ko) 2017-09-01
JP6696987B2 (ja) 2020-05-20
WO2016105961A1 (en) 2016-06-30
CN107111455B (zh) 2020-08-21
US20160188486A1 (en) 2016-06-30

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