KR102446121B1 - Memory controlling device and memory system including the same - Google Patents

Abstract

A memory system is provided that includes a memory subsystem and a memory controller. The memory subsystem includes a plurality of first memory modules implemented as a phase change memory and a second memory module implemented as a memory having a write speed faster than that of the phase change memory. The memory controller generates a non-blocking code from the plurality of sub data in which the original data is divided, writes the non-blocking code to the second memory module, writes the plurality of sub data to the plurality of first memory modules, respectively, and requests a read At the time, original data is reconstructed from some of the plurality of sub data read from the first memory module among the plurality of first memory modules and the non-blocking code read from the second memory module under a predetermined condition.

Description

MEMORY CONTROLLING DEVICE AND MEMORY SYSTEM INCLUDING THE SAME

The present invention relates to a memory control device and a memory system including the same.

A next-generation semiconductor memory is being developed in line with the trend of higher performance and lower power consumption of semiconductor memory. Among these next-generation semiconductor memories, there is a phase-change memory (PCM) using a phase-change material, particularly a phase-change random access memory (PRAM). The phase change memory uses a phase change material that switches between a crystalline state and an amorphous state, and stores data based on a difference in resistivity between the crystalline state and the amorphous state.

In such a phase change memory, there is a problem in that it takes more time to write data that needs to change the state of the phase change material than when data is read through the current state of the phase change material.

SUMMARY OF THE INVENTION An object of the present invention is to provide a memory system and a memory control device using a phase change memory capable of increasing response speed.

According to an embodiment of the present invention, a memory subsystem including a plurality of first memory modules implemented as a phase change memory and a second memory module implemented as a memory having a write speed faster than that of the phase change memory, and the plurality of first memory modules There is provided a memory system including a first memory module and a memory controller connected to the second memory module through a plurality of channels. The memory controller generates a non-blocking code from a plurality of sub data in which original data is divided, writes the non-blocking code to the second memory module, and writes the plurality of sub data to the plurality of first memory modules, respectively write, and receive the original data from some of the plurality of sub data read from some of the plurality of first memory modules and the non-blocking code read from the second memory module under a predetermined condition at the time of a read request reconstruct

The memory controller may include a cache for storing data corresponding to the write request in response to a write request from a central processing unit (CPU).

When the raw data is stored in the cache, the memory controller is configured to, when migrating the raw data stored in the cache to the memory subsystem, write the non-blocking code to the second memory module, and Each of the sub data may be written to the plurality of first memory modules.

The plurality of sub data may include first sub data and second sub data. In this case, when writing the plurality of sub data to the plurality of first memory modules, respectively, the memory controller writes the first sub data to a corresponding first memory module among the plurality of first memory modules, After writing of the sub data is completed, the second sub data may be written to a corresponding first memory module among the plurality of first memory modules.

After the writing of the plurality of sub-data to the plurality of first memory modules is completed, the memory controller may remove the original data from the cache.

When writing the first sub data to the corresponding first memory module, the memory controller may write the non-blocking code to the second memory module.

If a cache hit occurs on the raw data while migrating the raw data to the memory subsystem, the memory controller may stop the migration of the raw data.

The memory cell array of each first memory module may be divided into a plurality of partitions. In this case, the predetermined condition may include a condition that a write operation is in progress in a partition in which some other sub data among the plurality of sub data is stored.

The predetermined condition may further include a condition in which a cache miss occurs with respect to the read request of the original data.

The cache may be implemented as a non-volatile memory.

The memory system may be main memory used by the CPU of the computing device.

According to another embodiment of the present invention, a plurality of memory subsystems are provided in a memory subsystem including a first memory module and a second memory module implemented as a phase change memory, and a third memory module implemented as a memory having a write speed faster than that of the phase change memory. A memory control device connected through a channel of The memory control device includes a cache and a memory controller. The cache stores data corresponding to the write request according to the write request from the CPU. The memory controller divides the original data stored in the cache into a plurality of sub data including first sub data and second sub data, generates a non-blocking code from the plurality of sub data, and performs migration of the first sub data. write sub data to the first memory module, write the second sub data to the second memory module, write the non-blocking code to the third memory module, and write the non-blocking code to the third memory module The original data is reconstructed from the first sub data read from the first memory module and the non-blocking code read from the third memory module without reading the second sub data from the second memory module.

The memory controller writes any one of the first and second sub data to a corresponding one of the first and second memory modules, and after writing of the one sub data is completed, the first and second sub data The other sub data among the two sub data may be written to a corresponding memory module among the first and second memory modules.

After the first and second sub-data are written to the first and second memory modules, the memory controller may remove the raw data from the cache.

When writing the one sub-data to the corresponding memory module, the memory controller may write the non-blocking code to the third memory module.

When a cache hit occurs with respect to the raw data during the migration, the memory controller may stop the migration of the raw data.

The memory cell array of the second memory module may be divided into a plurality of partitions. In this case, the predetermined condition may include a condition that a write operation is in progress in the partition in which the second sub data is stored.

The predetermined condition may further include a condition in which a cache miss occurs with respect to the read request of the original data.

The cache may be implemented as a non-volatile memory.

According to another embodiment of the present invention, there is provided a memory system including the memory control device and the memory subsystem.

According to an embodiment of the present invention, a long write delay in the phase change memory can be hidden, and data of a read request can be provided without blocking the read request. According to another embodiment, memory continuity may be provided without a logging mechanism for storing log data.

1 is a schematic block diagram of a computing device according to an embodiment of the present invention.
2 is a diagram schematically illustrating one memory cell in a PRAM.
FIG. 3 is a diagram illustrating a current applied to the memory cell shown in FIG. 2 .
FIG. 4 is a diagram illustrating a temperature change when the current shown in FIG. 3 is applied to the memory cell shown in FIG. 2 .
5 is a schematic block diagram of a PRAM module in a PRAM-based accelerator according to an embodiment of the present invention.
6 is a view for explaining an example of a method of partitioning a memory cell array in a PRAM according to an embodiment of the present invention.
7 is a diagram for explaining an example of a partition in a PRAM according to an embodiment of the present invention.
8 is a schematic block diagram of a memory system according to an embodiment of the present invention.
9 is a schematic block diagram of a memory system according to another embodiment of the present invention.
10 is a flowchart illustrating an operation of a cache control module in a memory controller according to an embodiment of the present invention.
11 is a flowchart illustrating an operation of a migration module in a memory controller according to an embodiment of the present invention.
12 is a diagram for explaining a logging mechanism in a memory system.

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those of ordinary skill in the art to which the present invention pertains can easily implement them. However, the present invention may be embodied in several different forms and is not limited to the embodiments described herein. And in order to clearly explain the present invention in the drawings, parts irrelevant to the description are omitted, and similar reference numerals are attached to similar parts throughout the specification.

1 is a schematic block diagram of a computing device according to an embodiment of the present invention. 1 is an example of a possible computing device, and a computing device according to an embodiment of the present invention may be implemented in various other structures.

Referring to FIG. 1 , a computing device 100 according to an embodiment of the present invention includes a central processing unit (CPU) 110 and a memory 120 .

The memory 120 is accessed and used by the CPU 100 . In some embodiments, memory 120 may be the main memory of a computing device. In this case, the memory 120 may be a byte-addressable memory.

In some embodiments, the computing device 100 may further include a separate storage device 130 .

In some embodiments, the computing device 100 may further include a memory bridge 140 to connect the memory 120 and the storage device 130 to the CPU 110 . The memory bridge 140 may be, for example, a northbridge or a memory controller hub (MCH).

Referring back to FIG. 1 , the memory system 120 used as the memory 120 includes a memory controller 121 and a memory subsystem 122 , and the memory subsystem 122 includes a plurality of memory controllers 121 . It is connected through the channels 123a, 123b, and 123c of the memory controller 121. The memory controller 121 receives a request from the CPU 110, for example, an input/output (I/O) request, and receives the received I/O request. Access the memory subsystem 122 based on the O request.

The memory subsystem 122 includes a plurality of phase-change memory (PCM) modules 122a and 122b and a non-blocking memory module 122c. Hereinafter, a phase-change random access memory (PRAM) will be described as an example of the PCM. In addition, a memory having a write speed faster than that of PRAM is used as the non-blocking memory module 122c, and it will be described below that a dynamic random access memory (DRAM) module is used as the non-blocking memory module 122c.

The PRAM modules 122a and 122b are provided as a space for storing data, and each of the PRAM modules 122a and 122b is connected to the memory controller 121 through the corresponding channels 123a and 123b, that is, the PRAM channels 123a and 123b. is connected to The DRAM module 122c is provided as a space for storing non-blocking codes, and the DRAM module 122c is also provided to the memory controller 121 through the corresponding channel 123c, that is, the DRAM channel 123c. connected. The non-blocking code is a code that can be used to reconstruct the original data together with the remaining data even if some data is omitted from the original data.

The memory controller 121 divides write data to be written to the memory subsystem 122 into a plurality of sub-data according to an I/O request, and generates a non-blocking code based on the plurality of sub-data. The memory controller 121 writes the plurality of sub data to the plurality of PRAM modules 122a and 122b through the plurality of PRAM channels 123a and 123b, and writes a non-blocking code to the DRAM module 122c through the DRAM channel 123c. write as In addition, when the read operation is impossible in some of the PRAM modules 122a and 122b of the plurality of PRAM modules 122a and 122b for writing because the write data is divided, the memory controller 110 controls some of the PRAM modules 122a and 122b in which the read operation is possible. After reading the sub data from and reading the non-blocking code from the DRAM module 122c, original write data may be reconstructed from the read sub data and the non-blocking code.

As shown in FIG. 1 , when two PRAM modules 122a and 122b are used, the memory controller 121 may divide write data into two sub data. For example, when the write data is 64-byte data, the memory controller 121 divides the write data into two 32-byte sub-data and writes the write data to the two PRAM modules 122a and 122b, respectively. The memory controller 121 may encode two sub-data to generate a non-blocking code and write it to the DRAM module 122c. In addition, the memory controller 121 reads sub data from one of the two PRAM modules 122a and 122b, reads a non-blocking code from the DRAM module 122c, and adds the read sub data and the non-blocking code to write the original write. data can be reconstructed.

Although FIG. 1 shows an example in which two PRAM modules 122a and 122b and two PRAM channels 123a and 123b corresponding thereto are used, the number of PRAM modules is not limited to two. In the above, an example of dividing the raw data into two sub data has been described with reference to FIG. 1, but the number of sub data into which the raw data is divided is not limited to two, and the raw data is divided into two or more sub data can get

For example, the raw data may be divided into four sub-data (data A, data B, data C, and data D). In this case, the memory subsystem 122 may include at least four PRAM modules (PRAM module A, PRAM module B, PRAM module C, PRAM module D), wherein data A, data B, data C, and data D are may be stored in PRAM module A, PRAM module B, PRAM module C, and PRAM module D, respectively.

In one example, the memory controller 121 may encode data A, data B, data C, and data D to generate one non-blocking code and store it in the DRAM module. In this case, even if the memory controller 121 fails to read data A from one PRAM module (eg, PRAM module A), the remaining three PRAM modules (eg, PRAM module B, PRAM module C, and PRAM module) The original data can be reconstructed from the three data (data B, data C, and data D) read from D) and the non-blocking code read from the DRAM module.

In another example, the memory controller 121 may encode data obtained by combining data A and B and data obtained by combining data C and D to generate one non-blocking code and store it in the DRAM module. In this case, even if the memory controller 121 fails to read data A and data B from the two PRAM modules (eg, PRAM module A and PRAM module B), the remaining two PRAM modules (eg, PRAM module C, PRAM) The original data can be reconstructed from the two data (data C, data D) read from the module D) and the non-blocking code read from the DRAM module.

In another example, the memory controller 121 encodes data A and data B to generate one non-blocking code and stores it in the DRAM module, and encodes data C and data D to generate another non-blocking code. It can be stored in a DRAM module. In this case, the two non-blocking codes may be stored in different DRAM modules. In this case, even if the memory controller 121 fails to read data A and data C from the two PRAM modules (eg, PRAM module A and PRAM module C), the remaining two PRAM modules (eg, PRAM module B, PRAM) The original data can be reconstructed from the two data (data B, data D) read from the module D) and the two non-blocking codes read from the DRAM module.

Referring back to FIG. 1 , the PRAM module 122a or 122b connected to one channel includes a plurality of PRAM chips (or PRAM banks) 124 . In some embodiments, each PRAM chip (or PRAM bank) may be divided into a plurality of partitions PART0-PARTn. The PRAM module 122a or 122b connected to one channel may consist of one rank or may be extended to a plurality of ranks. In some embodiments, if a plurality of ranks connected to one channel can operate independently of each other, each rank can operate as an independent PRAM module. In this case, a plurality of PRAM modules (ie, a plurality of ranks) may share one channel. The DRAM module 122c connected to one channel includes a plurality of DRAM chips (or DRAM banks). The DRAM module 122c connected to one channel may consist of one rank or may be extended to a plurality of ranks.

Next, an example of the PRAM 120 included in the memory system 100 according to an embodiment of the present invention will be described.

FIG. 2 is a diagram schematically showing one memory cell in a PRAM, FIG. 3 is a diagram showing a current applied to the memory cell shown in FIG. 2, and FIG. 4 is a diagram showing the memory cell shown in FIG. 2 in FIG. It is a diagram showing the temperature change when one current is applied.

The memory cell shown in FIG. 2 is an example, and the memory cell of the PRAM according to the embodiment of the present invention may be implemented in various forms.

Referring to FIG. 2 , the memory cell 200 of the PRAM includes a phase change element 210 and a switching element 220 . The switching device 220 may be implemented with various devices such as a MOS transistor and a diode. The phase change element 210 includes a phase change film 211 , an upper electrode 212 formed on the upper wall film film, and a lower electrode 213 formed under the phase change film 211 . For example, the phase change layer 210 may include a mixture of germanium (Ge), antimony (Sb), and tellurium (Te) as a phase change material (also referred to as a “GST material”). can

The phase change material may switch between an amorphous state having a relatively high resistivity and a crystalline state having a relatively low resistivity. In this case, the state of the phase change material may be determined by the heating temperature and heating time.

Referring again to FIG. 2 , when a current is applied to the memory cell 200 , the applied current flows through the lower electrode 213 . When a current is applied to the memory cell 200 for a short time, the applied current heats the adjacent film of the lower electrode 213 . At this time, a portion of the phase change layer 211 (a portion hatched in FIG. 2 ) becomes a crystalline state or an amorphous state due to a difference in the heating profile. A crystalline state is called a "set state", and an amorphous state is called a "reset state".

3 and 4 , when a high current reset pulse RESET is applied to the memory cell 200 for a short time tRST, the phase change layer 211 is in a reset state. When the phase change material of the phase change layer 211 is heated according to the application of the reset pulse RESET and the temperature Tr is higher than the melting point, the phase change material is melted and then cooled to change to an amorphous state. When the set pulse SET having a current lower than the reset pulse RESET is applied to the phase change layer 211 for a time tSET longer than the reset pulse RESET, the phase change layer 211 is in a set state. . According to the application of the set current SET, when the phase change material is heated and reaches a crystallization temperature lower than the melting point of the temperature Ts, it changes to a crystalline state. When a current lower than the set pulse SET is applied or a current is applied for a short time, the reset state and the set state are maintained, so that data can be written into the memory cell 200 .

In this case, the reset state and the set state may be set to data of “1” and “0”, respectively, which may be detected by measuring the resistivity of the phase change element 210 of the memory cell 200 . Alternatively, the reset state and the set state may be set to data of “0” and “1”, respectively.

Accordingly, data stored in the memory cell 200 may be read by applying the read pulse READ to the memory cell 200 . The read pulse READ may be applied for a short time tREAD with a low current so that the state of the memory cell 200 may not be changed. A current magnitude of the read pulse READ may be lower than that of the set pulse SET, and an applied time tREAD may be shorter than an application time tRST of the reset pulse RESET. Since the resistivity of the phase change element 210 of the memory cell 200 varies depending on the state, the magnitude of the current flowing through the phase change element 210 or the magnitude of the voltage drop in the phase change element 210 is determined in the memory cell 200 . ) state, that is, data stored in the memory cell 200 can be read.

In one embodiment, when the read pulse READ is applied, the state of the memory cell 200 may be read by the difference in the magnitude of the voltage applied to the memory cell 200 . In this case, since the phase change element 210 of the memory cell 200 has a large resistance in the reset state, the large case of the voltage sensed by the phase change element 210 is set to the reset state, and the phase change element 210 has a large resistance. A case in which the sensed voltage is small may be determined as a set state. In another embodiment, when a voltage is applied to the memory cell 200 , the state of the memory cell 200 may be read by a difference in output current. In this case, the case where the current sensed by the phase change element 210 is small may be determined as the reset state, and the case where the current sensed by the phase change element 210 is large may be determined as the set state.

In the PRAM, data writing is performed through a series of reset and set processes, so a write operation is slower than a read operation due to a long reset pulse.

5 is a schematic block diagram of a PRAM in a memory system according to an embodiment of the present invention. The PRAM shown in FIG. 5 may be one PRAM chip or one PRAM bank.

Referring to FIG. 5 , the PRAM 500 includes a memory cell array 510 , a row address buffer 520 , a row data buffer 530 , a row decoder 540 , a sense amplifier 550 , and a write driver. (560).

The memory cell array 510 includes a plurality of word lines (not shown) extending approximately in a row direction, a plurality of bit lines (not shown) extending approximately in a column direction, and connected thereto and arranged in a substantially matrix form. and a plurality of memory cells (not shown). The memory cell may be, for example, the memory cell 200 described with reference to FIG. 2 .

The row address buffer 520 and the row data buffer 530 form a row buffer. Each row buffer is logically paired by a row address buffer 520 and a row data buffer 530 and is selected by a buffer address.

The row address buffer 520 stores command data and addresses (particularly, row addresses) transmitted from a memory controller (not shown). The row data buffer 530 stores data transferred from the memory cell array 510 .

In some embodiments, PRAM 500 may employ a non-volatile memory interface to use multiple row buffers 520 , 530 . In one embodiment, the non-volatile memory interface may be a double data rate (DDR) interface, for example, a low-power double data rate 2 (LPDDR2)-non-volatile memory (NVM) interface. The row address buffer 520 receives a row address and a bank address through the non-volatile memory interface, and the row data buffer 530 outputs data through the non-volatile memory interface.

The row decoder 540 selects a target row from a plurality of rows of the memory cell array 510 by decoding the row address. That is, the row decoder 540 selects a word line from which data is read or data is written from among a plurality of word lines of the memory cell array 510 .

In some embodiments, the row address transferred from the memory controller may include an upper address and a lower address. In this case, the upper address may be transferred to the row address buffer 520 , and the lower address may be transferred directly to the row decoder 540 . In this case, the row decoder 540 may select a target row by combining the high-order address stored in the row address buffer 520 and the directly transmitted low-order address.

The sense amplifier 550 reads data stored in the memory cell array 510 . The sense amplifier 550 may read data through a plurality of bit lines from a plurality of memory cells connected to the word line selected by the row decoder 540 . The write driver 560 writes input data to the memory cell array 510 . The write driver 560 may write data through a plurality of bit lines to a plurality of memory cells connected to a word line selected by the row decoder 540 .

In some embodiments, since a write operation is slower than a read operation in the PRAM 500 , in order to solve this problem, the PRAM 500 may first store input data in a buffer and then write it to the memory cell array 510 . . To this end, the PRAM 500 may include overlay windows 570 and 580 as memory-mapped registers. The overlay window may include an overlay window register 570 and a program buffer 580 . In one embodiment, after information about the write data (eg, the first data address and the number of bytes to be written) is written to the register 570 , the write data is stored in the program buffer 580 . Next, when a predetermined value is written to the overlay window register 570 , the data stored in the program buffer 580 is written to the memory cell array 510 . In this case, the memory controller may check whether the write operation to the memory cell array 510 is completed by polling the overlay window register 570 .

6 is a diagram for explaining an example of a method of partitioning a memory cell array in a PRAM according to an embodiment of the present invention, and FIG. 7 is a diagram for explaining an example of a partitioning method in a PRAM according to an embodiment of the present invention .

Referring to FIG. 6 , in some embodiments, one memory cell array 510 , for example, a PRAM bank may be divided into a plurality of partitions PART0 - PART15 . 6 illustrates an example in which the memory cell array 510 is divided into 16 partitions PART0-PART15. In this case, the plurality of row buffers 520 and 530 may be connected to the plurality of partitions PART0-PART15. For example, each partition can perform 64-bit parallel I/O processing.

In some embodiments, the plurality of partitions PART0 - PART15 may share a read circuit such as a sense amplifier ( 550 in FIG. 5 ) and a row decoder ( 540 in FIG. 5 ).

Referring to FIG. 7 , in some embodiments, each partition may include a plurality of sub-arrays. The sub-array may be referred to as a resistive tile. 7 shows that one partition includes 64 tiles (Tile0-Tile63).

Each tile includes a plurality of memory cells, or PRAM cores, connected to a plurality of bit lines (eg 2048 bit lines) and a plurality of word lines (eg 4096 word lines). For convenience of explanation, FIG. 7 illustrates only one memory cell among a plurality of memory cells included in each tile and one bit line BL and a word line WL connected thereto. The change element and the switching element are shown as resistors and diodes, respectively.

A local column decoder (hereinafter referred to as “LYDEC”) 710 may be connected to each tile. The LYDEC 710 is connected to a plurality of bit lines BL of a corresponding tile. Also, a plurality of global bit lines GBL corresponding to a plurality of tiles may be formed in the partition. Each global bit line GBL is connected to a plurality of bit lines BL of a corresponding tile, and may be connected to a global column decoder (hereinafter referred to as “GYDEC”). In some embodiments, LYDEC 710 may be used together with GYDEC to select a bit line (BL) in a corresponding tile of a corresponding partition. The sense amplifier 550 of FIG. 5 may read data through the selected bit line BL, or the write driver 570 of FIG. 5 may write data through the selected bit line BL.

In order to maximize parallelism, a sub word line driver (hereinafter referred to as “SWD”) 720 may be connected to each tile. A global word line GWL is formed in the partition, and the global word line GWL may be connected to a main word line driver (hereinafter referred to as “MWD”) 730 . In this case, a plurality of word lines WL formed in the partition may be connected to the global word lines GWL. All SWDs in the partition are connected to MWD 730 . In some embodiments, SWD 720 may be used together with MWD 730 to drive word lines WL in the corresponding tile. In this case, the driven word line WL may be selected by the row decoder ( 540 of FIG. 5 ).

When the partition structure shown in FIGS. 6 and 7 is used, a plurality of input/output (I/O) operations per partition (for example, 64 I/O operations in the example of FIG. 7 ) may be simultaneously performed. can In addition, as shown in FIGS. 6 and 7 , since a local decoder and a word line driver are used in each partition, the memory system can access different partitions in parallel. However, different partitions can support I/O services at the same time only if the types of I/O requests they receive are different.

For example, as shown in FIG. 8 , while a write operation is in progress in partition 0 of the PRAM, a read service may be provided in a partition different from partition 0, for example, partition 1. As such, since read and write can be provided in parallel from different partitions, another read operation may proceed while a slow write operation is in progress. Therefore, many read requests can be processed in parallel during write latency without waiting for the write operation to complete.

However, while a write operation is in progress on partition 0 of the PRAM, a read service cannot be provided from partition 0. Therefore, after the write operation in partition 0 is completed, a read operation in partition 0 may proceed. In this case, the response time of the read request (ie, the time it takes to complete the read operation) may correspond to the sum of the write delay time and the read delay time. As described above, an embodiment for preventing a case in which a response time of a read request takes a long time will be described.

Next, a memory system according to an embodiment of the present invention will be described with reference to FIG. 8 .

8 is a schematic block diagram of a memory system according to an embodiment of the present invention.

Referring to FIG. 8 , a memory system according to an embodiment of the present invention includes a memory controller 800 and a memory subsystem.

As described with reference to FIG. 1 , the memory controller 800 is connected to a memory subsystem including the PRAM modules 122a and 122b and the DRAM module 122c through a plurality of channels 123a, 123b, and 123c. , a cache 810 , a cache control module 820 , and a migration module 830 .

Memory subsystem 122 includes PRAM modules 122a and 122b that are connected to memory controller 800 through PRAM channels 123a and 123b, respectively, and DRAM modules that are connected to memory controller 800 through DRAM channels 123c. (122c). Hereinafter, an example in which two PRAM channels 123a and 123b, ie, PRAM modules 122a and 122b are used will be described for convenience of description, but the present invention is not limited thereto.

The cache 810 stores raw data provided from the CPU when a write request is received from the CPU, and also stores cache information. In some embodiments, the cache 810 may divide and store the original data into a plurality of sub data DATA_A and DATA_B. The cache 810 uses a memory having a faster write speed than PRAM, for example, DRAM or magnetoresistive random access memory (MRAM). Accordingly, the write delay by the PRAM in the memory system can be hidden from the CPU.

The migration module 830 generates a non-blocking code from the sub-data DATA_A and DATA_B stored in the cache 810 . The migration module 830 writes the sub data DATA_A and DATA_B to the PRAM modules 122a and 122b through the corresponding PRAM channels 123a and 123b, respectively, and writes the non-blocking code to the DRAM module ( 122c ), migrating the data in cache 810 to memory subsystem 123 . In some embodiments, the migration may proceed during an idle time of the memory controller 800 .

In an embodiment, an exclusive OR (XOR) operation may be used as a coding for generating a non-blocking code. In this case, when 64-byte raw data is divided into two 32-byte sub-data (DATA_A, DATA_B), 32-byte non-blocking is performed by bitwise XOR operation on the 32-byte sub data (DATA_A, DATA_B). A code may be generated. For example, when the original data of “001011100110” is divided into DATA_A of “001011” and DATA_B of “100110”, the non-blocking code may be generated as “101101”. In this case, DATA_B of “100110” may be recovered through the XOR operation of DATA_A and the non-blocking code, or DATA_A of “001011” may be recovered through the XOR operation of DATA_B and the non-blocking code.

In another embodiment, other encodings capable of generating a non-blocking code other than XOR may be used. When such encoding is used, the size of the non-blocking code can be reduced compared to the XOR operation.

As an example, error correction coding (ECC) may be used as a coding for generating a non-blocking code. For example, a parity code may be generated as a non-blocking code through low density parity check (LDPC) encoding.

As another example, erasure coding may be used as coding for generating a non-blocking code. In erasure coding, original data is divided into n data chunks, and k code chunks can be generated from the n data chunks by using an erasure coding algorithm. By using signed chunks as many as the number of unavailable data chunks, the original data can be recovered through n chunks.

In another embodiment, the encoding provided for error correction in a typical PRAM module and its memory controller may be used.

When the memory controller 800 receives a read request from the CPU, the cache control module 820 inquires the lockup module 810 to determine whether it is a cache hit or a cache miss. If the read request is a hit, the cache control module 820 reads data from the cache 810 . If the read request is a miss, the memory controller 800 reads data from the memory subsystem 820 . At this time, there may be a case in which sub data cannot be read from any one of the PRAM modules 122a and 122b of the two PRAM modules 122a and 122b. For example, when a write operation is in progress in the same partition as the partition in which the sub data 122b is stored in the PRAM module 122b (that is, when a partition conflict occurs), the sub data 122b is written from the PRAM module 122b. can't read In this case, the memory controller 800 reads the sub data DATA_A from the PRAM module 122a and reads the non-blocking code from the DRAM module 122c. In addition, the cache control module 820 of the memory controller 800 reconstructs the original data from the non-blocking code and the sub data DATA_A. For example, when an XOR operation is used as encoding for generating a non-blocking code, the cache control module 820 may reconstruct the original data by performing an XOR operation on the sub data DATA_A and the non-blocking code.

As such, according to one embodiment of the present invention, when data is read from the memory subsystem due to a cache miss, it is necessary to wait until the write operation is completed, even if data cannot be directly read from the PRAM module due to a partition conflict or the like. It is possible to provide read data using a non-blocking code without

9 is a schematic block diagram of a memory system according to another embodiment of the present invention.

Referring to FIG. 9 , the memory controller 900 includes a lookup module 910 , a cache control module 820 , and a migration module 830 , and the lookup module 910 includes a cache 911 and a migration queue 912 . includes

The cache 911 may store the lookup table 911b in addition to the original data 911a. In some embodiments, lookup table 911b may include a plurality of entries corresponding to cache indexes, each entry pointing to a cache entry (eg, a cache line) in the storage space of cache 911 . can Incoming I/O requests from the CPU can be separated into tags and cache indexes. The tag and cache index may be determined by the size of the cache 911 . For example, when using 512K cache indexes, the address of the I/O request (e.g., 32 bits), excluding the offset (e.g., 5 bits), has a cache index of 19 bits and a can be separated by tags. In this case, the lookup table 911b may have 512K entries to correspond to a 19-bit cache index, that is, 512K cache indexes. In one embodiment, each entry may include a tag array, a counter, and a valid bit. The tag array stores tags of the address of the I/O request, and the valid bit may indicate whether data exists in the corresponding cache entry. The counter may also be updated upon access of the corresponding cache entry.

The migration queue 912 stores information of cache entries requiring migration. The migration queue 912 may be implemented with a memory having a faster write speed than that of PRAM, for example, DRAM or MRAM.

The cache control module 820 may transmit a lookup command to the lookup module 910 to determine whether the I/O request is a cache hit/miss. A cache hit or a cache miss of the I/O request may be determined based on the address of the I/O request and the lookup table 911b of the lookup module 910 . In case of a cache miss, the cache control module 820 may transmit a find command to the lookup module 910 to determine whether an empty cache entry exists. It may be determined whether an empty cache entry exists based on the lookup table 911b of the lookup module 910 . The cache control module 820 may transmit an update command to the lookup module 910 to update the lookup table 911b. Accordingly, in the case of a cache hit, the counter of the lookup table corresponding to the cache entry of the cache hit may be updated, and in the case of a cache miss, a new entry may be added to the lookup table and the counter may be updated.

The migration module 830 may transmit a read command to the lookup module 910 to read information (ie, head information) pointed to by a head in the migration queue 912 to start migration. Then, the lookup module 910 reads head information from the migration queue 912 , and migration of data stored in a cache entry corresponding to the head information may start. The migration module 830 may transmit a remove command to the lookup module 910 in order to remove migration-completed data from the cache entry. Then, the lookup module 910 may remove the queue entry corresponding to the head from the migration queue 912 , move the head to the next queue entry, and remove data from the corresponding cache entry. When a new entry is added (that is, when new data is stored in the cache entry), the lookup module 910 may add information of the cache entry newly input to the migration queue 912 through an insert command. have.

The memory controller 900 may further include memory control units (MCUs) 951 , 952 , and 953 for controlling the PRAM modules 122a and 122b and the DRAM module 122c, respectively. In addition, the memory controller 900 is a memory control unit (MCU) 951, 952, corresponding to the memory request according to the read/write from the cache control module 820 or the memory request according to the migration from the migration control module (830) 953) may further include a multiplexer 940 for forwarding.

10 is a flowchart illustrating an operation of a cache control module in a memory controller according to an embodiment of the present invention.

Referring to FIG. 10 , the cache control module ( 820 in FIG. 8 or 9 ) determines whether a request from the CPU is a cache hit or a cache miss with reference to cache information of a cache ( 810 in FIG. 8 or 911 in FIG. 9 ) do (S1010). In case of a cache hit (S1010: Yes), the cache control module 820 provides a service corresponding to the request through the cache (S1020, S1030, S1035). That is, if the request is a read request (S1020: Yes), the cache control module 820 reads data corresponding to the read request from the cache 810 or 911 (S1030). If the request is a write request (S1020: No), the cache control module 820 writes data corresponding to the write request to the cache 810 or 911 (S1035). In some embodiments, the cache control module 820 may update cache information according to a cache hit ( S1050 ).

In the case of a cache miss (S1010: No), if the request is a write request (S1040: Yes), the cache control module 820 refers to the cache information to see if there is an empty entry (ie, a cache line) in the cache 810 or 911 It is determined (S1045). If there is an empty entry in the cache 810 or 911 (S1045: Yes), the cache control module 820 writes data corresponding to the write request to the cache (ie, an empty entry in the cache) 810 or 911 (S1050) . In some embodiments, the cache control module 820 may update the cache information by adding information about an entry in which data is written to the cache information ( S1050 ). If there is no empty entry in the cache 810 or 911, the cache control module ( 820) waits until writing to the PRAM module is completed (S1055: No)). After writing to the PRAM module is completed and an empty entry is made in the cache 810 or 911 (S1055: Yes), the cache control module 820 writes data corresponding to the write request to the empty entry of the cache 810 or 911. Write (S1050).

In the case of a cache miss, if the request is a read request (S1040: No), the cache control module 820 indicates that the current memory subsystem 122 corresponds to the original data from the PRAM module (122a, 122b in FIG. 8 or 9). It is determined whether a condition for reading all sub data is satisfied (S1060). In some embodiments, if no writes are in progress to either of the PRAM modules 122a and 122b, the memory subsystem 122 may read all subdata corresponding to the original data from the PRAM modules 122a, 122b. Alternatively, even when writing to any one of the PRAM modules 122a and 122b is in progress, if the partition in progress and the partition from which the sub data is to be read do not collide, the memory subsystem 122 transmits the PRAM channel (123a in FIG. 8 or 9). , 123b), all sub data corresponding to the original data can be read from the PRAM modules 122a and 122b.

If the memory subsystem 122 can read all the sub data corresponding to the original data from the PRAM modules 122a and 122b (S1060: Yes), the cache control module 820 sends the sub data from the PRAM modules 122a and 122b. is read and transmitted to the CPU (S1070). If the memory subsystem 122 cannot read the sub data from some PRAM module (eg, 122b) (S1060: No), the cache control module 820 reads the sub data from the PRAM module 122a capable of reading data. Read, and read the non-blocking code from the DRAM module (122c of FIG. 8 or 9) through the DRAM channel (123c of FIG. 8 or 9) (S1075). The cache control module 820 reconstructs the original data from the sub data and the non-blocking code and transmits it to the CPU (S1075).

11 is a flowchart illustrating an operation of a migration module in a memory controller according to an embodiment of the present invention.

Referring to FIG. 11 , the migration module ( 830 of FIG. 8 or 9 ) determines whether data to start migration is stored in the cache 810 or 911 ( S1110 ). In some embodiments, the migration module 830 may check whether the migration queue ( 912 of FIG. 9 ) is empty ( S1110 ). If the migration queue 912 is empty, that is, if there is no data to be migrated in the cache 810 or 911 (S1110: Yes), the migration module 830 waits until information of a new cache entry is added to the migration queue 912 . It waits (that is, until new data is stored in the cache 911).

If the migration queue 912 is not empty, that is, if there is data to be migrated in the cache 810 or 911 (S1110: No), the migration module 830 reads the data to be migrated from the cache 810 or 911, and the raw data A non-blocking code is generated from a plurality of divided sub data (S1120). In some embodiments, the migration module 830 may read data stored in a cache entry corresponding to the head information in the migration queue 912 ( S1120 ). The migration module 830 writes sub data to the corresponding PRAM module through the corresponding PRAM channel, and writes the non-blocking code to the DRAM module (122c in FIG. 8 or 9) through the DRAM channel (123c in FIG. 8 or 9). Write to (S1130). In some embodiments, the migration module 830 may write only some sub data among the plurality of sub data to the corresponding PRAM module through the corresponding PRAM channel, and write the non-blocking code to the DRAM module through the DRAM channel ( S1130 ). . In one embodiment, when the raw data is divided into two sub data, the migration module 830 transfers one sub data to the corresponding PRAM module (FIG. 8 or FIG. It can be written to 122a of 9 (S1130). If all sub-data is written to the PRAM module through all PRAM channels, the read request may be blocked if a read request and a partition conflict occur when a read request occurs, so writing may proceed only for some sub-data. Then, even if a partition collision occurs in the PRAM module 122a for a read request, the original data can be reconstructed with the non-blocking code and data read from another PRAM module (122b of FIG. 8 or 9) that is not being written.

In some embodiments, when writing is completed in the PRAM module 122a on which the write operation has been performed (S1140: Yes), the migration module 830 may write the remaining partial sub data to the corresponding PRAM module through the corresponding PRAM channel. There is (S1160). In one embodiment, when the original data is divided into two sub data, the migration module 830 may write the remaining sub data to the corresponding PRAM module 122b through the PRAM channel (123b in FIG. 8 ) ( S1160 ). ).

In some embodiments, before writing the remaining partial sub data to the corresponding PRAM module (S1160), if a cache hit occurs with respect to the data being migrated (S1150: Yes), the migration module 830 performs the remaining partial sub data Migration can be terminated without writing to the . If a cache hit occurs with respect to the data while migrating the data of the cache 911 to the PRAM module, the migration can be terminated because the requested data needs to be processed preferentially. If the cache hit does not occur (S1150: No), the migration module 830 may write the remaining partial sub data to the corresponding PRAM module through the corresponding PRAM channel (S1160).

When writing of the remaining partial sub data is completed (S1170: Yes), the migration module 830 deletes data of a corresponding cache entry from the cache 911 (S1180). In some embodiments, the migration module 830 may delete a queue entry from the migration queue 912 ( S1180 ).

As described above, according to an embodiment of the present invention, since writing is performed first in the cache instead of the PRAM module having a long write delay, it is possible to hide the long write delay of the PRAM module. In addition, since write and read with partition conflict can proceed simultaneously, data of a read request can be provided without blocking the read request. In addition, since the cache can be emptied by migrating the data in the cache to the PRAM during the idle time of the memory controller, the overall response speed of the memory system can be increased. Accordingly, the memory system according to an embodiment of the present invention can be used as the main memory of the CPU, and, unlike the DRAM, a nonvolatile memory system can be provided.

In general, to provide memory persistency, data must be retained when the computing device is shut down due to a power failure, etc. . To this end, when the computing device is rebooted, a logging mechanism that searches a log area first, restores it to a point in time at which it was terminated, and drives the computing device may be used.

As shown in FIG. 12 , a log area 1220 exists in addition to the data storage area 1210 in the PRAM module 1200 for the logging mechanism. When the memory controller receives a cache line flush command (clflush) for log data from the CPU, the memory controller stores the data of the cache in the log area. When the next memory controller receives a cache line flush command (clflush) and a fence command (sfense) for data, the memory controller stores the data in the cache in the data storage area of the PRAM module. Therefore, when the computing device is rebooted after being shut down, if the log data in the log area is normal, the data can be recovered as the log data. If the log data in the log area is abnormal, it is determined that the command has not been executed and can be ignored. In this case, since the log data is redundantly stored in the log area 1220 before the data of the cache is stored in the data storage area of the PRAM, a data duplication problem may occur and a decrease in the speed of instruction execution may occur.

However, according to an embodiment of the present invention, data stored in the cache ( 810 in FIG. 8 or 911 in FIG. 9 ) may be continuously written to the non-volatile memory PRAM module through migration. In this case, if a volatile memory such as DRAM is used as the cache (810 or 911), data can be written to the PRAM module before the data in the cache is lost through the backup battery even in the event of a power failure, so the logging mechanism is not used. Even if it does, it can provide memory continuity due to power failure. In some embodiments, cache 810 or 911 may be implemented with non-volatile memory, for example MRAM. In this case, even if the computing device is shut down due to a power failure, etc., since data is retained in the non-volatile caches 810 and 911, memory continuity may be provided without a logging mechanism, and a backup battery may not be used.

Although the embodiments of the present invention have been described in detail above, the scope of the present invention is not limited thereto. is within the scope of the right.

Claims (22)

a memory subsystem comprising a plurality of first and second memory modules; and
a memory controller connected to the plurality of first memory modules and the second memory module through a plurality of channels,
The memory cell array of each first memory module is divided into a plurality of partitions,
The memory controller generates a non-blocking code from a plurality of sub data in which original data is divided, writes the non-blocking code to the second memory module, and writes the plurality of sub data to the plurality of first memory modules, respectively write and do not read the sub data from some first memory modules of the plurality of first memory modules under a predetermined condition when a read request is made; Reconstructs the original data from the non-blocking code read from the memory module,
The predetermined condition includes a condition that a write operation is in progress in a partition in which some other sub data among the plurality of sub data is stored,
At the time of the read request, if a write operation is in progress in a partition other than the partition in which the other partial sub data is stored among the plurality of partitions of the partial first memory module, the memory controller is configured to read some sub data
memory system. In claim 1,
wherein the memory controller includes a cache configured to store data corresponding to the write request in response to a write request from a central processing unit (CPU). In claim 2,
When the raw data is stored in the cache, the memory controller is configured to, when migrating the raw data stored in the cache to the memory subsystem, write the non-blocking code to the second memory module, and A memory system for writing sub data to the plurality of first memory modules, respectively. In claim 3,
The plurality of sub data includes first sub data and second sub data,
When each of the plurality of sub data is written to the plurality of first memory modules, the memory controller writes the first sub data to a corresponding first memory module of the plurality of first memory modules, and the first sub data writing the second sub data to a corresponding first memory module among the plurality of first memory modules after the writing of
memory system. In claim 4,
and after completion of writing the plurality of sub-data to the first plurality of memory modules, the memory controller removes the original data from the cache. In claim 4,
When writing the first sub-data to the corresponding first memory module, the memory controller writes the non-blocking code to the second memory module. a memory subsystem comprising a plurality of first and second memory modules;
a memory controller connected to the plurality of first memory modules and the second memory module through a plurality of channels; and
a cache for storing data corresponding to the write request in response to a write request from a central processing unit (CPU);
The memory controller generates a non-blocking code from a plurality of sub data obtained by dividing the original data stored in the cache, writes the non-blocking code to the second memory module when the original data is migrated, and Writes data to the plurality of first memory modules, respectively, and reads the sub data from some of the plurality of first memory modules under a predetermined condition at the time of a read request without reading the sub data from some of the remaining first memory modules Reconstructs the original data from some of the sub data of the sub data and the non-blocking code read from the second memory module,
and when a cache hit occurs on the raw data while migrating the raw data to the memory subsystem, the memory controller stops the migration of the raw data. delete In claim 1,
The memory controller includes a cache for storing data corresponding to the write request in response to a write request from a central processing unit (CPU),
The predetermined condition further includes a condition in which a cache miss occurs in response to the read request of the original data. In claim 2,
The cache is a memory system implemented as a non-volatile memory. In claim 1,
wherein the memory system is main memory used by a CPU of a computing device. In claim 1,
The plurality of first memory modules is a memory system implemented by a phase change memory. A memory control device coupled through a plurality of channels to a memory subsystem comprising a first memory module, a second memory module, and a third memory module, the memory control device comprising:
In response to a write request from a central processing unit (CPU), a cache for storing data corresponding to the write request, and
The original data stored in the cache is divided into a plurality of sub data including first and second sub data, a non-blocking code is generated from the plurality of sub data, and the first sub data is converted into the second sub data during migration. Write to one memory module, write the second sub data to the second memory module, write the non-blocking code to the third memory module, and read from the second memory module under a predetermined condition upon a read request from the CPU a memory controller that reconstructs the original data from the first sub data read from the first memory module without reading the second sub data and the non-blocking code read from the third memory module,
The memory cell array of the second memory module is divided into a plurality of partitions,
The predetermined condition includes a condition that a write operation is in progress in a partition in which the second sub data is stored among the plurality of partitions,
At the time of the read request, if a write operation is in progress in a partition other than a partition in which the second sub data is stored among the plurality of partitions, the memory controller reads the second sub data from the second memory module
memory control unit. In claim 13,
The memory controller writes any one of the first and second sub data to a corresponding one of the first and second memory modules, and after writing of the one sub data is completed, the first and second sub data writing the other sub data among the 2 sub data to a corresponding memory module among the first and second memory modules
memory control unit. 15. In claim 14,
after the first and second sub-data is written to the first and second memory modules, the memory controller removes the original data from the cache. 15. In claim 14,
When writing the one sub-data to the corresponding memory module, the memory controller writes the non-blocking code to the third memory module. A memory control device coupled through a plurality of channels to a memory subsystem comprising a first memory module, a second memory module, and a third memory module, the memory control device comprising:
In response to a write request from a central processing unit (CPU), a cache for storing data corresponding to the write request, and
The original data stored in the cache is divided into a plurality of sub data including first and second sub data, a non-blocking code is generated from the plurality of sub data, and the first sub data is converted into the second sub data during migration. Write to one memory module, write the second sub data to the second memory module, write the non-blocking code to the third memory module, and read from the second memory module under a predetermined condition upon a read request from the CPU a memory controller that reconstructs the original data from the first sub data read from the first memory module without reading the second sub data and the non-blocking code read from the third memory module,
When a cache hit occurs with respect to the original data during the migration, the memory controller stops the migration of the original data. delete In claim 13,
The predetermined condition further includes a condition in which a cache miss occurs in response to the read request of the original data. In claim 13,
The cache is a memory control device implemented as a non-volatile memory. In claim 13,
The first memory module and the second memory module are implemented by a phase change memory memory control device. The memory control device according to any one of claims 13 to 17, 19 and 20, and
the memory subsystem
A memory system comprising a.

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