KR102444434B1 - Spike neural network circuit including comparator operated by conditional bias current - Google Patents

Abstract

A spike neural network circuit according to an embodiment of the present invention is configured to compare a voltage of a threshold signal with a voltage of a membrane signal generated based on a synapse and an operation signal that is configured to generate an operation signal based on an input spike signal and a weight and a neuron configured to generate an output spike signal using the comparator, wherein the comparator includes a bias circuit configured to conditionally supply a bias current of the comparator in accordance with the membrane signal.

Description

SPIKE NEURAL NETWORK CIRCUIT INCLUDING COMPARATOR OPERATED BY CONDITIONAL BIAS CURRENT

BACKGROUND OF THE INVENTION 1. Field of the Invention [0001] The present invention relates to spike neural network circuits, and more particularly, to a spike neural network circuit comprising a comparator driven by a conditional bias current.

An artificial neural network (ANN) can process data or information in a manner similar to a biological neural network. Unlike a perceptron-based neural network or a convolution-based neural network, in a spike neural network, a signal of a specific level is not transmitted, but a spike having a toggling pulse shape for a short time. A signal may be transmitted.

The spike neural network may be implemented using a semiconductor device. Recently, as the number of neurons integrated in the spike neural network increases as the spike neural network is used in various fields, power consumption by the spike neural network increases.

The present invention is to solve the above technical problem, the present invention can provide a spike neural network circuit including a comparator operated by a conditional bias current.

A spike neural network circuit according to an embodiment of the present invention is configured to compare a voltage of a threshold signal with a voltage of a membrane signal generated based on a synapse and an operation signal that is configured to generate an operation signal based on an input spike signal and a weight and a neuron configured to generate an output spike signal using the comparator, wherein the comparator includes a bias circuit configured to conditionally supply a bias current of the comparator in accordance with the membrane signal.

A spike neural network circuit according to another embodiment of the present invention is a synapse configured to generate an operation signal based on an input spike signal and a weight, and a bias generated based on a current of a membrane signal and a bias signal generated based on the operation signal and a neuron configured to generate an output spike signal with a comparator configured to compare the current, wherein the comparator includes a bias circuit for conditionally supplying a bias current in accordance with the membrane signal.

The spike neural network circuit according to an embodiment of the present invention may include a comparator operated by a conditional bias current. Accordingly, the power consumption of the spike neural network circuit can be improved.

1 is a block diagram exemplarily illustrating a spike neural network circuit according to an embodiment of the present invention.
FIG. 2 is a block diagram illustrating in more detail synapses of the synaptic circuit of FIG. 1 and neurons of the neuron circuit.
FIG. 3 exemplarily shows a block diagram of the comparator of FIG. 2 .
FIG. 4 exemplarily shows a block diagram of the comparator of FIG. 2 .
FIG. 5 exemplarily shows a timing diagram illustrating an operation of the comparator of FIG. 4 .
FIG. 6 exemplarily shows a timing diagram illustrating an operation of the comparator of FIG. 4 .
7 is a block diagram illustrating in more detail the synapses of the synaptic circuit of FIG. 1 and the neurons of the neuron circuit.
FIG. 8 exemplarily shows a block diagram of the comparator of FIG. 7 .
9 exemplarily shows a block diagram of the comparator of FIG. 7 .

Hereinafter, embodiments of the present invention will be described clearly and in detail to the extent that those skilled in the art can easily practice the present invention.

The present invention relates to a circuit implemented in a semiconductor device for performing computation of a neural network. The neural network of the present invention may be an artificial neural network (ANN) capable of processing data or information in a manner similar to a biological neural network. The neural network may include a plurality of layers including artificial neurons similar to biological neurons and synapses connecting the plurality of layers. Hereinafter, a spike neural network that processes a spike signal having a toggling pulse form for a short time will be representatively described. However, the circuit according to an embodiment of the present invention is not limited to the spike neural network and other neural networks It can also be used to implement

1 is a block diagram exemplarily illustrating a spike neural network circuit according to an embodiment of the present invention. The spike neural network circuit 100 may include an axon circuit 110 , a synaptic circuit 120 , and a neuron circuit 130 .

The axon circuit 110 may include axons that generate input spike signals. The axon of the axon circuit 110 may perform a function of outputting a signal to another neuron similarly to an axon of a biological neural network. For example, each of the axons of the axon circuit 110 may generate an input spike signal based on data or information input to the spike neural network circuit 100 from the outside. For another example, each of the axons of the axon circuit 110 first receives the output spike signals output from the neuron circuit 130 according to the input spike signals transmitted to the synaptic circuit 120 (feedback) )) may generate a new input spike signal based on the output spike signals. The input spike signal may be a pulse signal that toggles for a short time. The axon circuit 110 may generate input spike signals and transmit them to the synaptic circuit 120 .

The synaptic circuit 120 may connect the axon circuit 110 and the neuron circuit 130 . The synaptic circuit 120 may include synapses 121 that determine whether or not the axon of the axon circuit 110 and the neurons of the neuron circuit 130 are connected and the strength of the connection. Each of the synapses 121 may have a unique weight. Each of the synapses 121 may receive an input spike signal and apply a weight to the input spike signal. The weight is the above-described correlation between the axon and the neuron, the strength of the connection between the axons of the axon circuit 110 and the neurons of the neuron circuit 130, and the (following) neuron of the neuron circuit 130 for the input spike signal. It may be a numerical value indicating a correlation or the like. Each of the synapses 121 may output a weight to the neuron circuit 130 according to the input spike signal. Each of the synapses 121 may generate an operation signal based on the input spike signal and a weight and output the operation signal to the neuron circuit 130 .

The spike neural network circuit 100 may include a plurality of layers each including a plurality of neurons. Some synapses 121 of the synaptic circuit 120 may represent a correlation between the first layer and the second layer, and other synapses 121 of the synaptic circuit 120 may show a correlation between the third layer and the fourth layer. relationship can be expressed. That is, the synapses 121 of the synapse circuit 120 may represent correlations between various layers.

Referring to Figure 1, the synapses 121 are shown to be arranged on a two-dimensional array (array). The input spike signals may be transmitted in a first direction from the axon circuit 110 to the synaptic circuit 120 . The calculation signal (ie, the calculation result) in which the weight is applied to the input spike signal may be transmitted in a second direction from the synaptic circuit 120 to the neuron circuit 130 . For example, the first direction and the second direction may be perpendicular to each other. However, unlike the illustration of FIG. 1 , the synapses 121 may be disposed on a three-dimensional array.

The neurons 131 of the neuron circuit 130 may receive operation signals in which weights are applied to the input spike signals in the synaptic circuit 120 , respectively. Each of the neurons 131 may perform a function of receiving a signal output from another neuron, similar to a dendrite of a biological neural network. Referring to FIG. 1 , each of the neurons 131 may be connected to synapses 121 disposed along the second direction and may receive operation signals output from the synapses 121 . Operation signals of the synapses 121 arranged along the second direction in each of the neurons 131 may be accumulated. However, the number, arrangement, etc. of the synapses 121 connected to each of the neurons 131 are not limited to those illustrated in FIG. 1 .

Each of the neurons 131 may compare the sum signal accumulated by the operation signals of the synapses 121 with a threshold signal (ie, a reference signal) and generate an output spike signal when the sum signal is greater than the threshold signal (ie, neuron fire). Output spike signals of the neuron circuit 130 may be provided back to the axon circuit 110, output to the outside of the spike neural network circuit 100, or output to other components of the spike neural network circuit 100 have.

FIG. 2 is a block diagram illustrating in more detail synapses of the synaptic circuit of FIG. 1 and neurons of the neuron circuit. FIG. 2 will be described with reference to FIG. 1 . The spike neural network circuit 100_1 may include first to third synapses 121_1 to 121_3 and a neuron 131_1 . The spike neural network circuit 100_1 is the spike neural network circuit 100 of FIG. 1 , and for convenience of explanation, the illustration of the axon circuit 110 is omitted, and some synapses 121_1 of the synaptic circuit 120, Only 121_2 and 121_3 are shown, and only one neuron 131_1 of the neuron circuit 130 is shown in FIG. 2 .

The first synapse 121_1 may include a transistor MP1 and a current source CS1. The current source CS1 may receive the first weight (weight 1) and generate a current corresponding to the first weight. For example, the current source CS1 may be a transistor connected between the power supply voltage VDD and the transistor MP1. The transistor of the current source CS1 may receive a voltage representing the first weight through a gate terminal. It may be connected to a source terminal power voltage VDD of the transistor of the current source CS1 . A drain terminal of the transistor of the current source CS1 may be connected to a source terminal of the transistor MP1. Each of the source and drain terminals of the transistor may also be referred to as a first end or a second end. The current source CS1 may output a current corresponding to the first weight to the transistor MP1.

The transistor MP1 may receive a first input spike signal (input 1; for example, a negative pulse signal) through a gate terminal. The source terminal of the transistor MP1 may be connected to the current source CS1 . A drain terminal of the transistor MP1 may be connected to a transmission line. The transistor MP1 may be a switch that is turned on or off according to the first input spike signal. When the transistor MP1 is turned on according to the first input spike signal, the transistor MP1 may output a current output from the current source CS1 according to the first input spike signal, ie, an operation signal, to the transmission line. The first synapse 121_1 may generate a first operation signal (operation 1) based on the first input spike signal and the first weight. The first operation signal may be determined by a product of the first input spike signal and the first weight.

In the embodiment, the transistor MP1 is illustrated as a p-channel metal-oxide semiconductor (PMOS), but the scope of the present invention is not limited thereto. PMOS, n-channel metal-oxide semiconductor (NMOS), or a combination of PMOS and NMOS may be implemented as the switch. The transistor of the current source CS1 may also be PMOS, NMOS, or a combination of PMOS and NMOS.

In an embodiment, the first synapse 121_1 may further include a digital to analog converter (DAC). The DAC of the first synapse 121_1 may receive digital bits indicating the first weight and output a voltage indicating the first weight to the current source CS1 . The first synapse 121_1 is a register storing digital bits, a memory cell (eg, a static random access memory (SRAM) cell, a dynamic random access memory cell (DRAM) cell, a latch, a NAND flash memory cell, It may further include a NOR flash memory cell, a resistive random access memory (RRAM) cell, a ferroelectric random access memory (FRAM) cell, a phase change random access memory (PRAM) cell, a magnetic random access memory (MRAM) cell, and the like.

In an embodiment, as shown in FIG. 2 , the first synapse 121_1 includes only a current source CS1 and a transistor MP1, and registers or memory cells storing the above-described DAC and digital bits spike Although the neural network circuit 100 is included in the implemented semiconductor device, it may be separated from the synaptic circuit 120 . In this case, the DAC separated from the synaptic circuit 120 may transmit a voltage representing a weight to the synaptic circuit 120 or registers or memory cells storing digital bits may transmit digital bits to the synaptic circuit 120 . . In either case, the current source CS1 of the first synapse 121_1 may receive a voltage representing the first weight.

The second synapse 121_2 may be implemented in the same way as the first synapse 121_1 . The second synapse 121_2 may receive a voltage representing a second weight (weight 2) and may receive a second input spike signal (input 2). The second synapse 121_2 may generate a second operation signal (operation 2) based on the second input spike signal and the second weight. The third synapse 121_3 may be implemented in the same way as the first synapse 121_1 . The third synapse 121_3 may receive a voltage representing a third weight (weight 3) and may receive a third input spike signal (input 3). The third synapse 121_3 may generate a third operation signal (operation 3) based on the third input spike signal and the third weight. Here, the first to third weights may be the same as or different from each other, and the first to third input spike signals may also be the same or different from each other.

The neuron 131_1 may include a comparator 132_1 that compares a threshold signal with a membrane signal (sum signal) in which operation signals output from the first to third synapses 121_1 to 121_3 are combined. The membrane signal may be generated based on the computational signals. The comparator 132_1 may compare the voltage Vm of the membrane signal and the voltage Vth of the threshold signal. The neuron 131_1 may generate an output spike signal (output) based on the comparison result of the comparator 132_1 . For example, when the voltage (Vm) of the membrane signal becomes greater (higher) than the voltage (Vth) of the threshold signal, or when the voltage (Vm) of the membrane signal reaches the voltage (Vth) of the threshold signal, An output spike signal can be output (fired). For another example, the neuron 131_1 has a voltage (Vm) of the membrane signal becomes smaller (lower) than the voltage (Vth) of the threshold signal, or when the voltage (Vm) of the membrane signal reaches the voltage (Vth) of the threshold signal Then, an output spike signal can be output (ignition).

The neuron 131_1 may include a bias circuit 133_1 . The bias circuit 133_1 may conditionally supply a bias current to the comparator 132_1 according to the membrane signal. The comparator 132_1 may perform a comparison operation based on the bias current and may be operated by the bias current. The bias circuit 133_1 may be implemented separately from the comparator 132_1 or may be included in the comparator 132_1 . Since the spike neural network circuit 100 operates based on the input spike signal and the output spike signal, in a section in which the voltage (Vm) of the membrane signal is greater than the voltage (Vth) of the threshold signal, the voltage (Vm) of the membrane signal is the threshold signal It is relatively shorter than a section smaller than the voltage (Vth) of Most of the neuron 131_1 may operate in a section in which the voltage Vm of the membrane signal is smaller than the voltage Vth of the threshold signal, and the comparison operation of the neuron 131_1 is performed when the voltage Vm of the membrane signal is relatively high. only will be needed

The bias circuit 133_1 may not continuously supply a bias current. The bias circuit 133_1 does not supply the bias current to the comparator 132_1 when the voltage Vm of the membrane signal is relatively low, and supplies the bias current to the comparator 132_1 when the voltage Vm of the membrane signal is relatively high. can Accordingly, current and power consumed by the comparator 132_1 may be reduced or minimized. In particular, as the number of neurons 131 of the neuron circuit 130 increases, the above-described current and power reduction are more effective. Since the bias current is conditionally supplied according to an operating condition (the voltage level of the membrane signal), it may also be referred to as a conditional bias current, and the bias circuit 133_1 may also be referred to as a conditional bias circuit.

The spike neural network circuit 100_1 may include a capacitor Cm in which charges are accumulated by the first to third extension signals (currents) output from the first to third synapses 121_1 to 121_3. . A first end of the capacitor Cm may be connected to the first to third synapses 121_1 to 121_3 , and a second end of the capacitor Cm may be connected to the power supply voltage GND. The capacitor Cm may be output from the first to third synapses 121_1 to 121_3 and be charged by currents corresponding to the first to third weights. The voltage Vm of the capacitor Cm is the voltage Vm of the membrane signal and may be an accumulated value of currents output from the first to third synapses 121_1 to 121_3. The voltage Vm of the capacitor Cm may be a value determined by first to third weights output from the first to third synapses 121_1 to 121_3 to the first to third input spike signals. The voltage Vm of the capacitor Cm may be provided to the neuron 131_1 . Although the number of synapses connected to the capacitor Cm through the transmission line is illustrated in FIG. 2 as being three, the scope of the present invention is not limited thereto. The spike neural network circuit 100 may further include other capacitors in which charges are accumulated by currents output from other synapses. The capacitor Cm may be referred to as a membrane capacitor or a membrane.

The spike neural network circuit 100_1 may include a transistor MN1 that discharges charges accumulated in the capacitor Cm according to a leakage signal. The transistor MN1 may receive a leakage signal through a gate terminal. The transistor MN1 may be connected between the capacitor Cm and the power supply voltage GND. The transistor MN1 may be connected in parallel with the capacitor Cm. The transistor MN1 may control a speed at which stretch signals output from the first to third synapses 121_1 to 121_3 are accumulated in the capacitor Cm. The voltage of the leakage signal may be predefined. The transistor MN1 is illustrated in FIG. 2 as being an NMOS, but may be implemented using PMOS, NMOS, or a combination of PMOS and NMOS.

In an embodiment, unlike shown in FIG. 2 , the transistors MP1 to MP3 and CS1 to CS3 of the first to third synapses 121_1 to 121_3 are connected between the transmission line and the power supply voltage GND. Each may be implemented using NMOS. In this case, the capacitor Cm may be connected between the transmission line and the power supply voltage VDD, and the transistor MN1 may be implemented using PMOS instead of NMOS.

FIG. 3 exemplarily shows a block diagram of the comparator of FIG. 2 . FIG. 3 will be described with reference to FIG. 2 . The comparator 132_1a may be the comparator 132_1 of FIG. 2 , and the bias circuit 133_1a may be included in the comparator 132_1a and may be the bias circuit 133_1 of FIG. 2 .

The bias circuit 133_1a may include a transistor MN2 receiving the voltage Vm of the membrane signal through the gate terminal and the transistor MN3 receiving the voltage Vbias1 of the first bias signal through the gate terminal. . The transistor MN2 may be turned on or off according to the voltage Vm of the membrane signal. When the voltage Vm of the membrane signal is greater than the threshold voltage of the transistor MN2 , the transistor MN2 may be turned on. A drain terminal of the transistor MN2 may be connected to a source terminal of the transistor MN3 . The source terminal of the transistor MN2 may be connected to the power supply voltage GND. The transistor MN3 may generate a bias current based on the voltage Vbias1 of the first bias signal. A drain terminal of the transistor MN3 may be connected to a node n1 (common node). A source terminal of the transistor MN3 may be connected to a drain terminal of the transistor MN2 . When the transistor MN2 is turned on, the bias current of the transistor MN3 may be supplied to the comparator 132_1a through the transistor MN2. When the transistor MN2 is turned off, the bias current of the transistor MN3 may be supplied through the transistor MN2. A bias current may not be supplied to the comparator 132_1a. Only when the transistor MN2 is turned on, the bias current of the transistor MN3 may flow through the transistor MN2 and power by the bias current and the power supply voltage VDD may be consumed. Here, the power supply voltage VDD of the comparator 132_1a may be the same as or different from the power supply voltage VDD of the synapses 121 .

Referring to FIG. 3 , transistors MN2 and MN3 may be connected in series. 3 , the transistor MN2 may be connected between the node n1 and the transistor MN3 , and the transistor MN3 may be connected between the transistor MN2 and the power supply voltage GND. The transistors MN2 and MN3 may be implemented using NMOS, PMOS, or a combination of NMOS and PMOS.

The comparator 132_1a may include a transistor MN4 receiving a threshold signal through a gate terminal and a transistor MN5 receiving a membrane signal through a gate terminal. Source terminals of the transistors MN4 and MN5 may be commonly connected to the node n1 . A drain terminal of the transistor MN4 may be connected to the node n2 . A drain terminal of the transistor MN5 may be connected to the node n3 . The transistor MN4 may generate a current flowing between the nodes n1 and n2 according to the voltage Vth of the threshold signal. The transistor MN5 may generate a current flowing between the nodes n1 and n3 according to the voltage Vm of the membrane signal. The transistors MN4 and MN5 may serve as a switch for performing a comparison operation on the threshold signal and the membrane signal.

The comparator 132_1a may include a transistor MP4 connected between the node n2 and the power supply voltage VDD and a transistor MP5 connected between the node n3 and the power supply voltage VDD. The gate terminal and the drain terminal of the transistor MP4 may be connected to each other (diode connection). A gate terminal of the transistor MP5 may be connected to the node n2 . The transistors MP4 and MP5 provide a high impedance to the load end of the comparator 132_1a to increase the amplification factor of the comparator 132_1a, which amplifies the difference between the voltage Vth of the threshold signal and the voltage Vm of the membrane signal. have. The voltage of the node n3 may be determined according to a ratio of a current flowing through the transistor MP5 to a current flowing through the transistor MN5 . The transistors MN2, MN3, MN4, MN5, MP4, and MP5 may constitute a first stage of the comparator 132_1a.

The comparator 132_1a may include a transistor MN6 receiving a bias signal through a gate terminal and a transistor MP6 receiving a voltage of the node n3 through a gate terminal. A drain terminal of the transistor MN6 may be connected to the node n6 . The source terminal of the transistor MN6 may be connected to the power supply voltage GND. A drain terminal of the transistor MP6 may be connected to the node n6 . The source terminal of the transistor MP6 may be connected to the power supply voltage VDD. The transistors MN6 and MP6 may constitute the second stage of the comparator 132_1a. An output spike signal may be generated at node n4.

The voltage Vspike_out of the output spike signal may be determined according to a comparison result between the voltage Vm of the membrane signal and the voltage Vth of the threshold signal. When the voltage (Vm) of the membrane signal reaches the voltage (Vth) of the threshold signal, the logic value of the voltage (Vspike_out) of the output spike signal is changed from a first value (eg, low) to a second value (eg, high) ) (and vice versa), the output spike signal can be activated and fired.

In an embodiment, the types of transistors in FIG. 3 are not limited to those shown in FIG. 3 . Also, the logic value of the output spike signal is not limited to the above-described example.

FIG. 4 exemplarily shows a block diagram of the comparator of FIG. 2 . 4 will be described with reference to FIGS. 2 and 3 . The comparator 132_1b may be the comparator 132_1 of FIG. 2 , and the bias circuit 133_1b may be included in the comparator 132_1b and may be the bias circuit 133_1 of FIG. 2 . Differences between the comparator 132_1b and the comparator 132_1a will be mainly described, and descriptions of components having the same reference numerals will be omitted.

The bias circuit 133_1b may further include a transistor MN7 connected between the transistor MN2 and the power supply voltage GND. A gate terminal and a drain terminal of the transistor MN7 may be connected to each other (diode connection). The source terminal of the transistor MN2 may be connected to the drain terminal of the transistor MN7 instead of the power supply voltage GND. The transistor MN2 may receive a voltage increased by the threshold voltage of the transistor MN7 from the power supply voltage GND instead of the power supply voltage GND. Unlike the comparator 132_1a , when the voltage Vm of the membrane signal becomes greater than the sum of the threshold voltage of the transistor MN7 and the threshold voltage of the transistor MN2 , the bias current is increased through the transistors MN2 and MN7 in the comparator 132_1b . can be supplied to Accordingly, the period in which the bias current is supplied from the comparator 132_1b may be relatively shorter than that of the comparator 132_1a. Also, the transistor MN7 may further reduce the magnitude of the bias current of the comparator 132_1b.

The comparator 132_1b may further include transistors MN8 and MP8 constituting the inverter. Transistor MN8 may receive the voltage of node n4 through its gate terminal, the drain terminal of transistor MN8 may be connected to node n5, and the source terminal of transistor MN8 may receive a supply voltage ( GND) can be connected. Transistor MP8 may receive the voltage of node n4 through its gate terminal, the drain terminal of transistor MP8 may be connected to node n5, and the source terminal of transistor MP8 may receive a power supply voltage ( VDD) can be connected. An output spike signal may be generated at node n5. When the voltage (Vm) of the membrane signal reaches the voltage (Vth) of the threshold signal, the logic value of the voltage (Vspike_out) of the output spike signal is changed from the second value to the first value, so that the output spike signal is activated and can be fired .

The comparator 132_1b may further include transistors MP9, MN9, and MN10. Transistor MP9 may receive the voltage of node n5 through a gate terminal, drain terminal of transistor MP9 may be connected to node n6, and source terminal of transistor MP9 may receive a supply voltage ( VDD) can be connected. Transistor MN9 may receive the voltage of node n5 through its gate terminal, the drain terminal of transistor MN9 may be connected to node n6, and the source terminal of transistor MN9 may be connected to transistor MN10. ) can be connected to Transistor MN10 may receive a voltage Vbias2 of a second bias signal through a gate terminal, a drain terminal of transistor MN10 may be connected to a source terminal of transistor MN9, and The source terminal may be connected to the power voltage GND. The transistors MP9 , MN9 , and MN10 may generate a dormant adjustment signal at the node n6 .

The comparator 132_1b may further include a capacitor Cq. One end of the capacitor Cq may be connected to the node n6 and the other end of the capacitor Cq may be connected to the power supply voltage GND. When the output spike signal is activated, the transistor MP9 is turned on and charges may be accumulated in the capacitor Cq by the current flowing through the transistor MP9. When the output spike signal is deactivated, charges charged in the capacitor Cq may be discharged through the transistors MN9 and MN10. When the output spike signal is deactivated, the transistor MN9 may be turned on. The transistor MN10 may control the rate or time at which the charge (ie, the idle period adjustment signal) charged in the capacitor Cq is discharged according to the second bias signal.

The comparator 132_1b may further include a transistor MN11 that receives a dormant adjustment signal (the voltage of the node n6 ) through a gate terminal. A drain terminal of the transistor MN11 may be connected to the node n7 , and a source terminal of the transistor MN11 may be connected to the power supply voltage GND. The transistor MN11 may be a pull-down transistor that drives the voltage Vm of the membrane signal to the power supply voltage GND according to the voltage of the node n6 . The transistor MN11 may electrically connect the node n7 where the membrane signal is generated according to the resting period adjustment signal and the power supply voltage GND.

The capacitor Cq and the transistors MN9 to MN11 and MP9 may constitute the resting period adjustment circuit 134_1b for reducing the voltage Vm of the membrane signal to the power supply voltage GND. The resting period adjustment circuit 134_1 may adjust a period in which the membrane signal is deactivated or a period in which the output spike signal is inactivated. The quiescence of the neuron 131_1 may indicate a time during which the voltage Vm of the membrane signal is driven or maintained with the power supply voltage GND corresponding to reset, or a time during which the output spike signal is activated and then deactivated. . The rest period may be adjusted based on the capacitance of the second bias signal, the transistor MN10, and the capacitor Cq. Even when the input spike signal is activated during the rest period and calculation results are output from the synapses 121 , the voltage Vm of the membrane signal is maintained as the power supply voltage GND, and thus the calculation results may be ignored.

The comparator 132_1b may further include a transistor MP11 that receives the voltage Vspike_out of the output spike signal through a gate terminal. A drain terminal of the transistor MP11 may be connected to the node n7 and a source terminal of the transistor MP11 may be connected to the power supply voltage VDD. The transistor MP11 may be a pull-up transistor that drives the voltage Vm of the membrane signal to the power supply voltage VDD according to the voltage Vspike_out of the output spike signal. For example, the transistor MP11 may be turned on immediately after the output spike signal is activated, thereby driving the voltage Vm of the membrane to the power supply voltage VDD, and thus the voltage Vm of the membrane is momentarily up- It can represent an up-swing. The transistor MP11 may electrically connect the node n7 at which the membrane signal is generated immediately after the output spike signal is activated and the power supply voltage VDD.

When the output spike signal is activated, the transistor MP11 is turned on so that the voltage Vm of the membrane rises momentarily, and then the transistor MN11 is turned on so that the membrane voltage Vm is changed to the power supply voltage GND corresponding to the reset state. ) can be driven. When the membrane voltage Vm falls to the power supply voltage GND, new operation signals may be received from the synapses 121 .

In an embodiment, the spike neural network circuit 100_1 may further include a voltage generator generating first and second bias signals, a leakage signal, and a threshold signal. Each of the voltage levels of the first and second bias signals, the leakage signal, and the threshold signal can be predefined and programmed into the voltage generator.

In an embodiment, the types of transistors in FIG. 4 are not limited to those shown in FIG. 3 . Also, the logic value of the output spike signal is not limited to the above-described example.

FIG. 5 exemplarily shows a timing diagram illustrating an operation of the comparator of FIG. 4 . FIG. 5 will be described with reference to FIG. 4 . In FIG. 5 , a horizontal axis may indicate time and a vertical axis may indicate one of voltage and current.

Exemplarily, the membrane signal may be a sine wave. In the interval between time points T1 to T2 , the voltage Vm of the membrane signal may be lower than the voltage Vth of the threshold signal, the logic value of the voltage of the node n3 may be a second value, and the voltage of the node n4 The logic value of may be the first value, and the bias current of the comparator 132_1b may not be supplied. When the voltage Vm of the membrane signal is lower than the sum of the threshold voltages of the transistors MN7 and MN2 , the bias current of the comparator 132_1b may not be supplied.

In the interval between time points T2 to T3 , the voltage Vm of the membrane signal may be higher than the voltage Vth of the threshold signal, the logic value of the voltage of the node n3 may be a first value, and the voltage of the node n4 A logic value of may be a second value, and a bias current of the comparator 132_1b may be supplied. When the voltage Vm of the membrane signal is greater than the sum of the threshold voltages of the transistors MN7 and MN2 , the bias current of the comparator 132_1b may be supplied. The power consumption of the comparator 132_1b in the period between time points T1 to T2 may be smaller than the power consumption of the comparator 132_1b in the period between time points T2 to T3.

FIG. 6 exemplarily shows a timing diagram illustrating an operation of the comparator of FIG. 4 . FIG. 6 will be described with reference to FIG. 4 . In FIG. 6 , a horizontal axis may indicate time and a vertical axis may indicate voltage. Referring to FIG. 6 , as the input spike signal is repeatedly activated and deactivated, the voltage Vm of the membrane signal may gradually increase. When the voltage Vm of the membrane signal reaches the voltage Vth of the threshold signal near the time T4, the voltage of the node n4 of the comparator 132_1b is activated and the voltage of the voltage Vspike_out of the output spike signal is activated. can The voltage Vm of the membrane signal near the time T4 may exhibit an instantaneous up-swing by the transistor MP11. After the voltage Vspike_out of the output spike signal is activated, the voltage Vm of the membrane signal may be reduced to the power supply voltage GND by the transistor MN11 and may be deactivated. After the voltage of the voltage Vspike_out of the output spike signal is activated, the voltage of the node n6 (the resting period adjustment signal) may be discharged by the transistor MN10 operating based on the second bias signal.

Again, as the input spike signal is repeatedly activated and deactivated, the voltage Vm of the membrane signal may gradually increase. When the voltage Vm of the membrane signal reaches the voltage Vth of the threshold signal near the time T5, the voltage of the node n4 of the comparator 132_1b is activated and the voltage of the voltage Vspike_out of the output spike signal is activated. can Referring to FIG. 6 , the period in which the output spike signal is activated may be much shorter than the period in which the output spike signal is deactivated.

7 is a block diagram illustrating in more detail the synapses of the synaptic circuit of FIG. 1 and the neurons of the neuron circuit. 7 will be described with reference to FIGS. 1 and 2 . The spike neural network circuit 100_2 may include first to third synapses 121_1 to 121_3 , a capacitor Cm, and a transistor MN1. The spike neural network circuit 100_2 is the spike neural network of FIG. 1 . The circuit 100, for convenience of explanation, the axon circuit 110 is omitted, and only some synapses (121_1, 121_2, 121_3) of the synaptic circuit 120 are shown. The first to third synapses 121_1 to 121_3 of the spike neural network circuit 100_2, the capacitor Cm, and the transistor MN1 are the first to third synapses 121_1 to 121_1 of the spike neural network circuit 100_1 121_3), the capacitor Cm, and the transistor MN1 are substantially the same. The difference between the spike neural network circuit 100_2 and the spike neural network circuit 100_1 will be mainly described.

The spike neural network circuit 100_2 may include a neuron 131_2 . For convenience of description, only one neuron 131_2 of the neuron circuit 130 is illustrated. The neuron 131_2 may include a comparator 132_2 and a bias circuit 133_2 . The neuron 131_1 may compare the membrane signal with the threshold signal, but the neuron 131_2 may compare the membrane signal with the first bias signal. The first bias signal may be used to generate a bias current of the comparator 132_2 and may be provided as the threshold signal of FIG. 2 at the same time. That is, the first bias signal may also be referred to as a threshold signal. The bias circuit 133_2 may conditionally supply a bias current to the comparator 132_2 according to the membrane signal. The neuron 131_2 may operate similarly to the neuron 131_1 except that the neuron 131_2 uses the first bias signal as a threshold signal.

FIG. 8 exemplarily shows a block diagram of the comparator of FIG. 7 . FIG. 8 will be described with reference to FIG. 7 . The comparator 132_2a may be the comparator 132_2 of FIG. 7 , and the bias circuit 133_2a may be included in the comparator 132_2a and may be the bias circuit 133_2 of FIG. 7 .

The comparator 132_2a may include a transistor MP12 that receives the voltage Vbias1 of the first bias signal through a gate terminal. A drain terminal of the transistor MP12 may be connected to the node n8 . The source terminal of the transistor MP12 may be connected to the power supply voltage VDD. The transistor MP12 may generate a bias current based on the first bias signal. The transistor MP12 may output a bias current corresponding to the first bias signal to the transistor MN13 .

The comparator 132_2a may include transistors MN13 and MN14. The transistor MN13 may receive a bias current corresponding to the first bias signal. A gate terminal and a drain terminal of the transistor MN13 may be connected to each other (diode connection). A source terminal of the transistor MN13 may be connected to the node n9 . The transistor MN13 may be connected between the nodes n8 and n9 . The transistor MN14 may receive a bias current corresponding to the first bias signal through the transistor MN13 . A gate terminal and a drain terminal of the transistor MN14 may be connected to each other (diode connection). A source terminal of the transistor MN14 may be connected to a power supply voltage GND. The transistor MN14 may be connected between the node n9 and the power supply voltage GND. The transistors MN13 and MN14 may copy a bias current corresponding to the first bias signal to the bias circuit 133_2a (current mirroring).

The bias circuit 133_2a may include a transistor MN15 receiving the voltage of the node n8 through a gate terminal and a transistor MN16 receiving the voltage of the node n9 through the gate terminal. A drain terminal of the transistor MN15 may be connected to the node n10 . A source terminal of the transistor MN15 may be connected to a drain terminal of the transistor MN16 . A drain terminal of the transistor MN16 may be connected to a source terminal of the transistor MN15 . A source terminal of the transistor MN16 may be connected to a drain terminal of the transistor MN17 . A bias current corresponding to the first bias signal may flow through the transistors MN15 and MN16 .

Unlike the illustration, the comparator 132_2a may not include the transistors MN13 and MN15. In this case, the drain terminal of the transistor MP12 and the drain terminal of the transistor MN14 may be connected to each other, and the drain terminal of the transistor MN16 and the drain terminal of the transistor MP16 may be connected to each other.

The bias circuit 133_2a may include a transistor MN17 that receives the voltage Vm of the membrane signal through a gate terminal. A drain terminal of the transistor MN17 may be connected to a source terminal of the transistor MN16 . The source terminal of the transistor MN17 may be connected to the power supply voltage GND. The transistor MN17 may be connected between the transistor MN16 and the power supply voltage GND. The transistor MN17 may be turned on or off according to the voltage Vm of the membrane signal. When the voltage Vm of the membrane signal is greater than the threshold voltage of the transistor MN17 , the transistor MN17 may be turned on. When the transistor MN17 is turned on, a bias current corresponding to the first bias signal may be supplied to the comparator 132_2a through the transistor MN17, and when the transistor MN17 is turned off, the first bias through the transistor MN2. A bias current corresponding to the signal may not be supplied to the comparator 132_2a. A bias current may flow through the transistor MN17 only when the transistor MN17 is turned on, and power by the bias current and the power supply voltage VDD may be consumed.

The bias circuit 133_2a may include a transistor MP16. The gate terminal and the drain terminal of the transistor MP16 may be connected to each other (diode connection) and may be connected to the node n10 . A source terminal of the transistor MP16 may be connected to the transistor MP17. The bias circuit 133_2a may include a transistor MP17 that receives the voltage Vm of the membrane signal through a gate terminal. The source terminal of the transistor MP17 may be connected to the power supply voltage VDD. A drain terminal of the transistor MP17 may be connected to a source terminal of the transistor MP16.

The comparator 132_1a of FIG. 3 compared the voltage Vm of the membrane signal and the voltage Vth of the threshold signal. On the other hand, the comparator 132_2a may compare the current of the membrane signal with the bias current of the first bias signal. A pull-up current according to the voltage Vm of the threshold signal may be generated through the transistors MP16 and MP17. The transistors MP16 and MP17 may drive the logic value of the voltage Vspike_out of the output spike signal to the second value by generating a pull-up current. A pull-down current (bias current) according to the first bias signal may be generated through the transistors MN15 and MN16 . The transistors MN15 and MN16 may drive a logic value of the voltage Vspike_out of the output spike signal to a first value by generating a pull-down current. The voltage Vspike_out of the output spike signal may be determined according to a comparison result between the current of the membrane signal and the current of the first bias signal. For example, when the current of the membrane signal becomes smaller than the bias current of the first bias signal or the current of the membrane signal reaches the bias current of the first bias signal, the logic value of the voltage Vspike_out of the output spike signal becomes the second value. By changing from to the first value, the output spike signal may be activated and ignited. As another example, when the current of the membrane signal becomes greater than the bias current of the first bias signal or the current of the membrane signal reaches the bias current of the first bias signal, the output spike signal may be activated and fired. The output spike signal may be generated at node n10.

In an embodiment, the types of transistors in FIG. 8 are not limited to those shown in FIG. 8 . Also, the logic value of the output spike signal is not limited to the above-described example.

9 exemplarily shows a block diagram of the comparator of FIG. 7 . FIG. 9 will be described with reference to FIGS. 2 and 3 and FIGS. 7 and 8 . The comparator 132_2b may be the comparator 132_2 of FIG. 7 , and the bias circuit 133_2b may be included in the comparator 132_2b and may be the bias circuit 133_2 of FIG. 7 . The difference between the comparator 132_2b and the comparator 132_2a and the difference between the comparator 132_2b and the comparator 132_1b will be mainly described, and descriptions of components having the same reference numerals will be omitted. Transistors MP12, MP16, MP17, and MN13 to MN17 of the comparator 132_2b have been described with reference to FIG. 8 . Transistors MN8 to MN11, MP8, MP9, and MP11 of the comparator 132_2b have been described with reference to FIG. 4 . The transistors MN9 to MN11 and MP9 and the capacitor Cq may constitute the idle period adjustment circuit 134_2b. The idle period adjustment circuit 134_2b may be implemented substantially the same as the idle period adjustment circuit 134_1b.

The comparator 132_2b may include transistors MN6 and MP6 constituting the inverter. The transistor MN6 may receive the voltage of the node n10 through a gate terminal. A drain terminal of the transistor MN6 may be connected to the node n4 . A source terminal of the transistor MN6 may be connected to the power supply voltage GND. The transistor MP6 may receive the voltage of the node n10 through the gate terminal. A drain terminal of the transistor MP6 may be connected to the node n4 . The source terminal of the transistor MP6 may be connected to the power voltage VDD.

In an embodiment, the types of transistors in FIG. 9 are not limited to those shown in FIG. 9 . Also, the logic value of the output spike signal is not limited to the above-described example.

The contents described above are specific examples for carrying out the present invention. The present invention will include not only the above-described embodiments, but also simple design changes or easily changeable embodiments. In addition, the present invention will include techniques that can be easily modified and implemented in the future using the above-described embodiments.

100: spike neural network circuit;
110: axon circuit;
120: synaptic circuit;
130: neuron circuit;

Claims (20)

a synapse configured to generate a computational signal based on the input spike signal and the weight; and
a neuron configured to generate an output spike signal using a comparator configured to compare a voltage of a threshold signal with a voltage of a membrane signal generated based on the computational signal;
the comparator comprises a bias circuit configured to conditionally supply a bias current of the comparator in accordance with the membrane signal;
the neuron is further configured to inactivate the membrane signal based on a resting modulating signal, and
During a period in which the membrane signal is deactivated, the voltage of the membrane signal is a ground voltage. The method of claim 1,
The bias circuit is:
a first transistor configured to be turned on or off according to the membrane signal; and
and a second transistor coupled to the first transistor and configured to generate the bias current based on a bias signal. 3. The method of claim 2,
When the first transistor is turned on, the bias current of the second transistor is supplied through the first transistor, and
A spike neural network circuit in which the bias current of the second transistor is not supplied when the first transistor is turned off. 3. The method of claim 2,
wherein the bias circuit further includes a third transistor coupled between the second transistor and a power supply voltage. 3. The method of claim 2,
The comparator is:
a third transistor coupled to a first end of the second transistor and configured to receive the membrane signal; and
and a fourth transistor coupled to the first end of the second transistor and configured to receive the threshold signal. The method of claim 1,
and the neuron is turned on when the output spike signal is activated, and a transistor configured to electrically connect a power supply voltage of the comparator to a node generating the membrane signal. The method of claim 1,
and wherein the neuron comprises a resting period adjustment circuitry configured to adjust the period in which the membrane signal is inactive. 8. The method of claim 7,
The resting period adjustment circuit comprises:
a first transistor turned on or off according to the output spike signal and configured to generate the idle adjustment signal;
a second transistor coupled to a first terminal of the first transistor and coupled between the first transistor and a power supply voltage of the comparator; and
and a third transistor coupled to the second end of the first transistor and configured to electrically connect a power supply voltage of the comparator to a node at which the membrane signal is generated according to the resting period adjustment signal. The method of claim 1,
The synapse is:
a first transistor configured to receive the weight; and
a second transistor coupled to the first transistor and configured to receive the input spike signal;
A spike neural network circuit in which the operation signal is output through the first and second transistors. The method of claim 1,
The spike neural network circuit further comprising a membrane capacitor in which the operation signal is accumulated and the membrane signal is generated. a synapse configured to generate a computational signal based on the input spike signal and the weight; and
a neuron configured to generate an output spike signal using a comparator configured to compare a bias current generated based on a bias signal with a current of a membrane signal generated based on the computational signal;
The comparator includes a bias circuit for conditionally supplying the bias current according to the membrane signal,
the neuron is further configured to inactivate the membrane signal based on a resting modulating signal, and
During a period in which the membrane signal is deactivated, the voltage of the membrane signal is a ground voltage. 12. The method of claim 11,
A spike neural network circuit in which the output spike signal is activated according to a result of comparing the current of the membrane signal and the bias current. 12. The method of claim 11,
The bias circuit is:
a first transistor configured to be turned on or off according to the membrane signal; and
and a second transistor configured to generate the bias current and coupled to the first transistor. 14. The method of claim 13,
When the first transistor is turned on, the bias current of the second transistor is supplied through the first transistor, and
A spike neural network circuit in which the bias current of the second transistor is not supplied when the first transistor is turned off. 14. The method of claim 13,
The bias circuit further comprises a third transistor configured to be turned on or off according to the membrane signal and connected to the first power supply voltage of the comparator,
The first transistor is connected to a second power supply voltage of the comparator,
the current of the membrane signal is generated by the third transistor,
wherein the bias current is generated by the first and second transistors. 12. The method of claim 11,
and the neuron is turned on when the output spike signal is activated, and a transistor configured to electrically connect a power supply voltage of the comparator to a node generating the membrane signal. 12. The method of claim 11,
and wherein the neuron comprises a resting period adjustment circuitry configured to adjust the period in which the membrane signal is inactive. 18. The method of claim 17,
a first transistor turned on or off according to the output spike signal and configured to generate the idle adjustment signal;
a second transistor coupled to a first terminal of the first transistor and coupled between the first transistor and a power supply voltage of the comparator; and
and a third transistor coupled to a second end of the first transistor and configured to electrically connect a power supply voltage of the comparator to a node at which the membrane signal is generated according to the resting period adjustment signal. 12. The method of claim 11,
The synapse is:
a first transistor configured to receive the weight; and
a second transistor coupled to the first transistor and configured to receive the input spike signal;
A spike neural network circuit in which the operation signal is output through the first and second transistors. 12. The method of claim 11,
The spike neural network circuit further comprising a membrane capacitor in which the operation signal is accumulated and the membrane signal is generated.

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