KR102440415B1 - A substrate support assembly for multi-zone temperature control and a plasma processing system having the same - Google Patents

Abstract

According to one aspect of the present invention, there is provided a substrate support assembly for multi-zone temperature control, comprising a semiconductor switch as a heating element, for each of a plurality of zones specified about an upper support surface of the substrate support assembly on which a substrate is supported. a first line electrically connected to a first electrode of the first heater; Any two lines of a second line electrically connected to the second electrode of A substrate support assembly is provided.

Description

A SUBSTRATE SUPPORT ASSEMBLY FOR MULTI-ZONE TEMPERATURE CONTROL AND A PLASMA PROCESSING SYSTEM HAVING THE SAME

The present invention relates to a substrate support assembly for multi-zone temperature control and a plasma processing system including the substrate support assembly.

In a semiconductor process, an electrostatic chuck (ESC) capable of uniformly heat-treating a wafer and minimizing particle generation is mainly used. In recent years, as semiconductor circuits become ultra-miniaturized and high-performance, the demand for equipment capable of more precisely controlling the semiconductor process is increasing. In particular, since the uniformity of the temperature distribution on the substrate during the process significantly affects the process result, how to configure the heater structure of the chuck is highlighted as a major concern, and research and development are being actively conducted on it.

However, according to the techniques introduced so far, including the prior art, a resistance heating element is arranged in a matrix form in most chuck heaters, a diode for preventing crosstalk is disposed between the resistance heating elements, and a switch connected to each resistance heating element It was a method in which the power supplied to each resistance heating element was controlled through the However, the number of heater (eg, micro-heater) zones installed in the chuck increases (from several zones to several hundred zones (eg, 144 zones, 156 zones, etc.)) to precisely control the temperature distribution to the substrate. Accordingly, the number of devices for implementing this increased exponentially, and various problems such as an increase in economical cost for manufacturing the chuck, lack of arrangement space, and noise generation occurred.

Korean Patent Laid-Open Publication No. 2002-43601 (Jun. 10, 2002)

An object of the present invention is to solve all the problems of the prior art described above.

In addition, the present invention uses a semiconductor switch as a heating element of a heater, thereby minimizing the number of parts and lowering the complexity of implementing a multi-zone heater, and further reducing manufacturing cost and simplifying maintenance work. serve another purpose.

In addition, another object of the present invention is to minimize the number of layers in which the lines are disposed by allowing any two of the lines electrically connected to the semiconductor switch to be disposed laterally so as not to cross the same layer with each other. do.

A representative configuration of the present invention for achieving the above object is as follows.

According to one aspect of the present invention, there is provided a substrate support assembly for multi-zone temperature control, comprising a semiconductor switch as a heating element, for each of a plurality of zones specified about an upper support surface of the substrate support assembly on which a substrate is supported. a first line electrically connected to a first electrode of the first heater; Any two lines of a second line electrically connected to the second electrode of A substrate support assembly is provided.

According to another aspect of the present invention, there is provided a plasma processing system comprising a chamber comprising a substrate support assembly, the substrate support assembly comprising a semiconductor switch as a heating element and an upper support surface of the substrate support assembly on which a substrate is supported. and a heater layer in which a plurality of first heaters capable of independently temperature control are disposed for each of a plurality of zones specified around Any two lines of a first line connected to , a second line electrically connected to the second electrode of the first heater, and a third line electrically connected to the third electrode of the first heater do not cross each other. A plasma processing system is provided that is laterally disposed on the same layer.

In addition to this, other substrate support assemblies and other plasma processing systems for implementing the present invention are further provided.

According to the present invention, by using the semiconductor switch as the heating element of the heater, the number of parts can be minimized and the complexity can be reduced in implementing the multi-zone heater, and furthermore, the manufacturing cost can be reduced and the maintenance work can be simplified.

In addition, according to the present invention, any two lines of the lines electrically connected to the semiconductor switch are arranged laterally so as not to cross the same layer, so that the number of layers in which the lines are arranged can be minimized. .

1 schematically illustrates a plasma processing system 100 according to an embodiment of the present invention.
2 is a diagram exemplarily showing a structure of a substrate support assembly 200 according to an embodiment of the present invention.
3 to 5 are views exemplarily showing the structure of the heater layer 220 of the substrate support assembly 200 according to an embodiment of the present invention.
6 is a diagram illustrating another structure of the substrate support assembly 200 according to an embodiment of the present invention.
7 and 8 are diagrams exemplarily illustrating a temperature control method of the substrate support assembly 200 according to an embodiment of the present invention.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS [0012] DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS [0014] DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS [0016] Reference is made to the accompanying drawings, which show by way of illustration specific embodiments in which the present invention may be practiced. These embodiments are described in sufficient detail to enable those skilled in the art to practice the present invention. It should be understood that the various embodiments of the present invention are different but need not be mutually exclusive. For example, certain shapes, structures, and characteristics described herein may be implemented with changes from one embodiment to another without departing from the spirit and scope of the present invention. In addition, it should be understood that the location or arrangement of individual components within each embodiment may be changed without departing from the spirit and scope of the present invention. Accordingly, the following detailed description is not to be taken in a limiting sense, and the scope of the present invention should be taken as encompassing the scope of the claims and all equivalents thereto. In the drawings, like reference numerals refer to the same or similar elements throughout the various aspects.

Hereinafter, various preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings in order to enable those of ordinary skill in the art to easily practice the present invention.

Configuration of plasma processing system 100

1 shows a schematic cross-sectional view of a plasma processing system 100 including a substrate support assembly 200 in accordance with an embodiment of the present invention. The processing herein may be a concept including various processing that can be processed using plasma, such as deposition processing, etching processing, annealing processing, surface treatment processing, and the like.

The plasma processing system 100 according to an embodiment of the present invention may include a chamber 110 that may be sealed by being surrounded by sidewalls, upper and lower portions. For example, the chamber 110 may be a vacuum chamber whose surface is made of anodized aluminum, and may be electrically grounded.

A substrate support assembly 200 extending from a lower portion of the chamber 110 to an upper portion to support the substrate W may be disposed in the chamber 110 . For example, the substrate support assembly 200 may be in the form of a cylinder, a cube, or a rectangular parallelepiped (or, such a shape is bent in an a or a shape), and the material thereof is aluminum (Al), titanium (Ti). ), silicon carbide (SiC), and the like. In addition, a processing gas may be supplied through a gas port (not shown) between the substrate W and the support surface of the substrate support assembly 200 supporting the substrate W, for example, the processing gas includes A heat transfer gas such as helium (He) gas or argon (Ar) gas may be included. Meanwhile, the substrate support assembly 200 may be electrically connected to a direct current (DC) or alternating current (AC) source for temperature control, cooling, clamping, and the like of the substrate.

In addition, at least one coil 120 disposed in an annular or concentric circle shape and electrically connected to an RF source (not shown) may be disposed on the outer upper portion of the chamber 110, and the at least one coil ( As RF power is applied and adjusted to 120 , plasma may be generated and controlled in the chamber 110 .

In addition, the controller 130 may control the operation of the plasma processing apparatus 100 inside or outside the chamber 110 , for example, such that a processing gas is supplied into the chamber 110 , or RF power. to control plasma, and to control heating and cooling of the substrate support assembly 200 . On the other hand, the controller 130 according to an embodiment of the present invention may be equipped with a memory means to control the above operation and a microprocessor mounted therein to have arithmetic capability.

In the above, a schematic configuration of the plasma processing system 100 that may be related to the practice of the present invention has been described. Hereinafter, the structure of the substrate support assembly 200 according to an embodiment of the present invention will be described in detail.

Structure of the substrate support assembly 200

2 is a diagram exemplarily showing a structure of a substrate support assembly 200 according to an embodiment of the present invention.

Referring to FIG. 2 , the substrate support assembly 200 according to an embodiment of the present invention may include an electrostatic clamping layer 210 , a heater layer 220 , and a cooling plate 230 .

First, the electrostatic clamping layer 210 according to an embodiment of the present invention uses an electrostatic force to fix the substrate w on the support surface 201 of the upper portion of the substrate support assembly 200 . can By fixing the substrate w on the support surface 201 in this way, it is possible to minimize a temperature deviation that may occur between regions inside the substrate. Meanwhile, the support surface 201 of the upper portion of the substrate support assembly 100 according to an embodiment of the present invention may be partially similar to the support surface of a conventional vacuum chuck, electrostatic chuck, susceptor, or other workpiece. can

Specifically, the electrostatic clamping layer 210 may include a layer on which either one of a mono-polar electrode or a bi-polar electrode 211 is disposed, and the electrostatic electrode The substrate w may be fixed on the support surface 201 of the upper portion of the substrate support assembly 200 by electrostatic force generated by applying a high-voltage constant voltage to the 211 . For example, the electrostatic clamping layer 210 may be formed based on an insulating layer or a ceramic layer (eg, alumina).

Next, the heater layer 220 according to an embodiment of the present invention has a temperature required to perform processing (eg, etching, heat treatment, etc.) on the substrate w supported by the substrate support assembly 200 . Heating to provide

Specifically, the heater layer 220 includes a plurality of regions (eg, 144 regions divided in a matrix form or a radial form, etc.) that are specified around the upper support surface of the substrate support assembly 100 on which the substrate is supported. A layer in which a plurality of first heaters 221 capable of independently temperature control to a target are disposed, and a layer in which at least three lines for controlling power supplied to the plurality of first heaters 221 are disposed. can For example, the layer in which the plurality of first heaters 221 are disposed and the layer in which at least three lines are disposed may be a layer configured based on an insulating layer, in order to increase heat conduction by the first heater 221 . It may further include a metal layer. In addition, the plurality of first heaters 221 as described above may be arranged in a predetermined pattern in the corresponding layer, for example, in a matrix form, a radial form, a concentric circle form, etc. composed of a plurality of rows and a plurality of columns. . Meanwhile, the at least three lines above may be made of a material having a low resistivity, such as copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), or the like. Meanwhile, the size of each zone according to an embodiment of the present invention may be the same, but may be specified differently depending on the center and the periphery or the distance from the center.

For example, each of the plurality of first heaters 221 may be configured to include a semiconductor switch (eg, a MOSFET, a bipolar junction transistor (BJT), etc.) as a heating element, and the semiconductor It may be configured by including three electrodes electrically connected to the switch (ie, the first electrode, the second electrode, and the third electrode). In addition, the heater layer 220 has a first line electrically connected to the first electrode 221, a second line electrically connected to the second electrode, and a third line electrically connected to the third electrode. Any two of the three lines may be arranged laterally so as not to cross each other on the same layer. According to an embodiment of the present invention, when the semiconductor switch as above is a MOSFET, the first electrode is a drain electrode (or a source electrode) of the MOSFET, and the second electrode is the second electrode. The electrode is the source electrode (or drain electrode) of the MOSFET, and the third electrode above may be the gate electrode of the MOSFET. The first electrode is a collector electrode (or emitter electrode) of the junction-type transistor, the second electrode is an emitter electrode (or collector electrode) of the junction-type transistor, and the third electrode may be a base electrode of the corresponding junction type transistor.

More specifically, referring to FIG. 3A , the heater layer 220 may include the first to third insulating layers 310 , 320 , and 330 , and the semiconductor switch 500 is the first heater ( 221 , which may be disposed laterally on the first insulating layer 310 , and a first line 301 electrically connected to the first electrode 500a of the semiconductor switch 500 is connected to the first insulating layer ( The second line 302 may be disposed laterally on the second insulating layer 320 under the 310 and electrically connected to the second electrode 500b of the corresponding semiconductor switch 500 and the corresponding semiconductor switch ( A third line 303 electrically connected to the third electrode 500c of the 500 may be laterally disposed on the third insulating layer 330 under the second insulating layer 320 .

Similarly, referring to FIG. 4A , the heater layer 220 may include the first to third insulating layers 410 , 420 , and 430 , and the semiconductor switch 500 is disposed on the first heater 221 . A first line 401 that may be disposed laterally on the first insulating layer 410 as a , and electrically connected to the first electrode 500a of the semiconductor switch 500 and a second of the semiconductor switch 500 . A second line 402 electrically connected to the electrode 500b may be laterally disposed on the second insulating layer 420 under the first insulating layer 410 above, and the corresponding semiconductor switch 500 . A third line 403 electrically connected to the third electrode 500c may be laterally disposed on the third insulating layer 430 under the second insulating layer 420 .

Meanwhile, as described above, by allowing any one of the first line to the third line 301 , 302 , 303 , 401 , 402 , and 403 to be electrically connected to the common ground, the total line for controlling the heater number can be minimized.

For example, referring to FIGS. 3B and 4B , the second line 302 electrically connected to the first electrode 500b of the semiconductor switch 500 or the first electrode 500a of the semiconductor switch 500 and A first line 401 that is electrically connected may be electrically connected to a common ground. More specifically, if the above semiconductor switch is a MOSFET, a line connected to the drain electrode or a line connected to the source electrode may be electrically connected to the common ground.

On the other hand, it should be noted that the line arrangement and the layer order according to the present invention are not necessarily limited to those listed above, and can be changed as much as possible within the range that can achieve the object of the present invention.

Meanwhile, according to an embodiment of the present invention, the first heater 221 described above may be configured to further include a resistor as a heating element together with a semiconductor switch.

For example, referring to FIGS. 5A and 5B , the first heater 221 may further include a semiconductor switch 500 and a resistor 510 connected in series with one electrode of the semiconductor switch 500 . can That is, the first line 301 electrically connected to the first electrode 500a of the semiconductor switch 500, the second electrode 500b of the semiconductor switch 500, and one end of the resistor 510 are connected in series, and Any two lines of the second line 302 electrically connected to the other end of the resistor 510 and the third line 303 electrically connected to the third electrode 500c of the corresponding semiconductor switch 500 are identical to each other. It may also be arranged laterally so that the layers do not intersect each other. That is, by adding a resistor 510 as well as the semiconductor switch 500 , the temperature controllable range may be expanded.

On the other hand, the connection between the semiconductor switch and the resistor according to the present invention is not necessarily limited to the above-listed series connection, and it can be changed to be connected in parallel within the range that can achieve the object of the present invention. make it clear

In addition, in the upper portion (see FIG. 6 ) or the lower portion (see FIG. 2 ) of the heater layer 220 according to an embodiment of the present invention, higher power (eg, the second heater) compared to the first heater 221 as described above The power of 226 is 100W to 10000W, and the power of the first heater 221 may be 5W to 20W) and is relatively wider than the number of at least one zone (ie, the plurality of zones of the first heater 221 ). A layer 225 in which a plurality of second heaters 226 capable of independently temperature control for a small number of zones) is disposed may be further included. For example, the second heater 226 as described above may be a heater used for average temperature change, step-wise temperature control, and the like, and may be partially similar to a conventional main heater or primary heater. In addition, the layer in which the plurality of second heaters 226 are disposed may be a layer based on an insulating layer, similar to the layer in which the plurality of first heaters 221 are disposed, and heat conduction by the second heater 226 is reduced. It may further include a metal layer to increase. On the other hand, the plurality of second heaters 226 as described above may be composed of various heating elements such as a resistive heater, a ceramic heater, a carbon heater, and a predetermined pattern in the corresponding layer, for example, a spiral shape, a concentric circle shape, a r shape. etc. may be placed. Here, the type or shape of the heater according to the present invention is not necessarily limited to those listed above, and within the scope that can achieve the object of the present invention, other types of heating elements or various patterns (eg, square, rectangular , hexagonal, annular, radial, etc.)

Next, the cooling plate 230 may be disposed under the heater layer 220 , the substrate w, the substrate support assembly 200 (eg, the heater layer 220 ), or the inside of the chamber 110 . Cooling to control the temperature of the can be made.

Specifically, at least one channel 231 for cooling may be formed in the cooling plate 230 , and cooling may be performed as a refrigerant is supplied through the at least one channel 231 . For example, such a refrigerant may be composed of water, ethylene glycol, silicone oil, liquid Teflon, a mixture of water and glycol, and the like. However, at least one channel 231 of the cooling plate 230 may be configured to include a cooling element (not shown) capable of absorbing surrounding heat rather than supplying the refrigerant as above, and cooling the cooling plate 230 . Cooling can be achieved by controlling the power supplied to the device.

Meanwhile, in the cooling plate 230 , at least one conduit or at least one connector insulated from each other for supplying power to the electrostatic plate layer 210 or the heater layer 220 is to be embedded. may be

In the above, an exemplary structure of the substrate support assembly 200 according to the present invention has been described. Hereinafter, a method of controlling the temperature of the heater of the substrate support assembly 200 according to an embodiment of the present invention will be described.

temperature control method

Referring to FIG. 7 , in the heater layer 221 , each of the 24 MOSFETs 500 arranged in 4 rows and 6 columns (4 X 6 matrix structure) is disposed as the first heater 221 , and each MOSFET ( The first line 701 electrically connected to the first electrode (that is, the drain electrode) 501 of 500 is electrically connected to the thermal switches SW_A, SW_B, SW_C, SW_D, SW_E, SW_F, respectively. The third line 703 electrically connected to the third electrode (ie, the gate electrode) 503 of each MOSFET 500 may be electrically connected to the row switches SW_1 , SW_2 , SW_3 , SW_4 , respectively. . In addition, the second line 702 electrically connected to the second electrode (ie, the source electrode) 502 of each MOSFET 500 may be electrically connected to a common ground. In addition, these row switches (SW_1, SW_2, SW_3, SW_4) and column switches (SW_A, SW_B, SW_C, SW_D, SW_E, SW_F) are a predetermined controller for controlling the heater (not shown; for example, these controllers are , may be controlled by the switch control signal SW_sig provided from the controller 130 described above). Meanwhile, each MOSFET 500 may be connected to each voltage source (not shown) by row switches SW_1, SW_2, SW_3, SW_4 and column switches SW_A, SW_B, SW_C, SW_D, SW_E, SW_F. have.

For example, it may be assumed that the row switch SW_1 is turned on by the first switch control signal SW_sig_1 and the column switch SW_A is turned on by the second switch control signal SW_sig_2. . That is, when the row switch SW_1 is turned on, a voltage V _GS greater than or equal to the threshold voltage V _TH of the MOSFET may be provided to the third electrode (ie, the gate electrode) 503 of each MOSFET in the row. have. When the column switch SW_A is turned on while the switch SW_1 is turned on in the row 1 above, the first electrode (ie, the drain electrode) 701 of each of the MOSFETs 500 in the column A is turned on. can be provided with a voltage V _DS greater than the above voltage V _GS , whereby a current I _D is generated in the MOSFET 500 where the above row 1 and column A are crossed. be able to flow In addition, the current I _D flowing through the MOSFET 500 as above may be converted into thermal energy within the MOSFET 500 and converted into Joule heat, and the area corresponding to each of the MOSFET 500 is heated by the Joule heat. this can be done That is, by controlling the turn-on time of the switches constituting the row switch and the column switch as described above, temperature control for each of the MOSFETs 500 is possible. In addition, with reference to the power consumed by each MOSFET according to the combination of the row switch and the column switch, the turn-on time of the row switch and the column switch for adjusting the desired temperature profile (or target temperature) for a plurality of zones is determined. can be specified.

On the other hand, the power supply method according to the present invention is not necessarily limited to the above-described switch method, and may be variously modified into a pulse voltage or the like within a range capable of achieving the object of the present invention.

For example, referring to FIG. 8 , in the heater layer 221 , each of the 24 MOSFETs 500 and the resistor 510 arranged in 4 rows and 6 columns (4 X 6 matrix structure) is the first heater 221 . ) and a pulse according to a predetermined duty time from a voltage source on the first line 801 electrically connected to the first electrode (ie, drain electrode) 501 of each MOSFET 500 . Voltages PV_A_1, PV_B_1, PV_C_1, PV_D_1, PV_E_1, PV_F_1 may be provided, and a third line 803 electrically connected to a third electrode (ie, a gate electrode) 503 of each MOSFET 500 . ), pulse voltages PV_3_1 , PV_3_2 , PV_3_3 , and PV_3_4 according to a predetermined duty time may be provided from the voltage source, respectively. In addition, the second line 802 in which the second electrode (ie, the source electrode) of each MOSFET 500 and one end of the resistor 510 are connected in series and the other end of the resistor 510 is electrically connected. All can be electrically connected to a common ground. In addition, the duty times of the pulse voltages (PV_A_1, PV_B_1, PV_C_1, PV_D_1, PV_E_1, PV_F_1, PV_3_1, PV_3_2, PV_3_3, PV_3_4) respectively supplied to the first line 801 and the third line 803 control the heater control. It may be controlled by a predetermined controller (not shown; for example, such a controller may be included in the controller 130 described above).

For example, the pulse voltages PV_A_1, PV_B_1, PV_C_1, PV_D_1, PV_E_1, PV_F_1 are sequentially provided to the first lines 801a, 801b, 801c, 801d, 801e, and 801f at the first duty time, and the third line It may be assumed that the pulse voltages PV_3_1, PV_3_2, PV_3_3, and PV_3_4 are sequentially provided to (803a, 803b, 803c, and 803d) as the second duty time. That is, when the pulse voltages PV_3_1, PV_3_2, PV_3_3, and PV_3_4 are provided to the third lines 803a, 803b, 803c, and 803d at the second duty time, the MOSFETs of the corresponding third lines 803a, 803b, 803c, and 803d A gate voltage (V _G ) equal to or greater than the threshold voltage (V _TH ) of the corresponding MOSFET may be sequentially supplied to each third electrode (ie, the gate electrode) 503 in response to the corresponding duty time. In addition, when the pulse voltages PV_A_1, PV_B_1, PV_C_1, PV_D_1, PV_E_1, PV_F_1 are provided to the first lines 801a, 801b, 801c, 801d, 801e, and 801f at the first duty time, the first lines 801a and 801b , 801c, 801d, 801e, and 801f), the drain voltage V _D may be sequentially supplied to the first electrode (ie, the drain electrode) 501 of the MOSFET 500 corresponding to the corresponding duty time. In this case, the duty times of the pulse voltages PV_A_1, PV_B_1, PV_C_1, PV_D_1, PV_E_1, PV_F_1, PV_3_1, PV_3_2, PV_3_3, PV_3_4 provided to the first line 801 and the third line 803 are mutually different. A current I _D may flow through the overlapping MOSFET 500 and the resistor 510 . Accordingly, the current I _D flowing through the MOSFET 500 and the resistor 510 may be converted into thermal energy in the MOSFET 500 and the resistor 510 and converted into Joule heat, and the corresponding MOSFET ( 500) and a region corresponding to each of the resistors 510 may be heated.

Meanwhile, the pulse voltage provided to the first line 801 and the pulse voltage provided to the third line 803 as described above are sequentially target averages for each MOSFET 500 by the predetermined controller. Power may be supplied, or target average power may be supplied to the plurality of MOSFETs 500 by a time division multiplexing method.

For example, first, while the pulse voltage PV_3_4 is provided to the third line 803d for a predetermined duty time (the duty time may be pre-calculated to control each MOSFET to a target temperature) (in this case) In the third line (803a, 803b, 803c), the pulse voltage may not be provided), the first line (801a, 801b, 801c, 801d, 801e, 801f) has a predetermined duty time (this duty time is, When the pulse voltage is provided by time-divisioning each MOSFET to control the target temperature to a target temperature), the first MOSFET 504 and its resistance, the second MOSFET 505 and its resistance, and the third MOSFET 506 and its resistance, the fourth MOSFET 507 and its resistance, the fifth MOSFET 508 and its resistance, and the sixth MOSFET 509 and its resistance, a current (I _D ) flows in response to the above time-divided duty time Heating can be achieved. Then, while the pulse voltage PV_3_3 is provided to the third line 803c at a predetermined duty time (this duty time can be pre-calculated to control each MOSFET to a target temperature) (in this case, The other third lines 803a, 803b, 803d may not be provided with a pulse voltage), and a predetermined duty time on the first line 801a, 801b, 801c, 801d, 801e, 801f (these duty times are for each MOSFET) may be pre-calculated to control the target temperature) and time-divided to provide a pulse voltage, the first MOSFET 504a and its resistance, the second MOSFET 505a and its resistance, and the third MOSFET 506a and its resistance In response to the above time-divided duty time in the resistor, the fourth MOSFET 507a and its resistance, the fifth MOSFET 508a and its resistance, and the sixth MOSFET 509a and its resistance, a current I _D flows and heating is performed. can be done Then, as the above process is repeatedly performed for other third lines 803a and 803b, temperature control is possible for all MOSFETs 500 .

As another example, while the pulse voltages PV_3_3 and PV_3_4 are provided to the third lines 803c and 803d for a predetermined duty time (the duty time may be pre-calculated to control each MOSFET to a target temperature) (In this case, the pulse voltage may not be provided to the other third lines 803a and 803b), the first lines 801a, 801b, 801c, 801d, 801e, 801f have a predetermined duty time (this duty time , which may be pre-calculated to control each MOSFET to a target temperature) and time-divided to provide a pulse voltage, the first MOSFETs 504 and 504a and their respective resistors, the second MOSFETs 505 and 505a and their respective resistors, the third MOSFETs 506 and 506a and their respective resistors, the fourth MOSFETs 507 and 507a and their respective resistors, the fifth MOSFETs 508 and 508a and their respective resistors, and the sixth MOSFET 509, 509a) and its respective resistors, in response to the above time-divided duty time, a current (I _D ) flows to allow heating. Then, as the above process is repeatedly performed for other third lines 803a and 803b, temperature control is possible for all MOSFETs 500 .

The embodiments according to the present invention described above may be implemented in the form of program instructions that can be executed through various computer components and recorded in a computer-readable recording medium. The computer-readable recording medium may include program instructions, data files, data structures, etc. alone or in combination. The program instructions recorded on the computer-readable recording medium may be specially designed and configured for the present invention, or may be known and used by those skilled in the art of computer software. Examples of the computer-readable recording medium include hard disks, magnetic media such as floppy disks and magnetic tapes, optical recording media such as CD-ROMs and DVDs, and magneto-optical media such as floppy disks. medium), and hardware devices specially configured to store and execute program instructions, such as ROM, RAM, flash memory, and the like. Examples of program instructions include not only machine language codes such as those generated by a compiler, but also high-level language codes that can be executed by a computer using an interpreter or the like. A hardware device may be converted into one or more software modules to perform processing in accordance with the present invention, and vice versa.

In the above, the present invention has been described with reference to specific matters such as specific components and limited embodiments and drawings, but these are provided to help a more general understanding of the present invention, and the present invention is not limited to the above embodiments, Those of ordinary skill in the art to which the invention pertains can make various modifications and changes from these descriptions.

Therefore, the spirit of the present invention should not be limited to the above-described embodiments, and the scope of the spirit of the present invention is not limited to the scope of the scope of the present invention. will be said to belong to

100: plasma processing system
110: chamber
120: coil
130: controller
200: substrate support assembly
210: electrostatic clamping layer
220: heater layer
230: cooling plate
500: semiconductor switch
510: resistance

Claims (20)

A substrate support assembly for multi-zone temperature control, comprising:
A heater layer including a semiconductor switch as a heating element, and in which a plurality of first heaters capable of independently controlling temperature are disposed in each of a plurality of zones specified around an upper support surface of the substrate support assembly on which a substrate is supported. ), including
The heater layer includes a first line electrically connected to the first electrode of the first heater, a second line electrically connected to the second electrode of the first heater, and a third electrode of the first heater electrically. Any two of the connected third lines do not intersect each other and are arranged laterally on the same layer.
substrate support assembly. According to claim 1,
The heater layer includes a first insulating layer, a second insulating layer and a third insulating layer,
The plurality of first heaters are disposed on the first insulating layer,
the first line and the second line are disposed in a second insulating layer under the first insulating layer and the third line is disposed in a third insulating layer under the second insulating layer;
wherein the first line is disposed in a second insulating layer under the first insulating layer and the second line and the third line are disposed in a third insulating layer under the second insulating layer
substrate support assembly. According to claim 1,
The first heater may further include a resistor connected in series or in parallel with the semiconductor switch as a heating element.
substrate support assembly. According to claim 1,
The plurality of first heaters are arranged in the form of a mattress consisting of a plurality of rows and a plurality of columns on the heater layer
substrate support assembly. According to claim 1,
any one of the first line, the second line, and the third line is electrically connected to a common ground
substrate support assembly. According to claim 1,
The semiconductor switch is a MOSFET, the first electrode and the second electrode are a drain electrode of the MOSFET and a source electrode of the MOSFET, and the third electrode is a gate of the MOSFET ) electrode
substrate support assembly. According to claim 1,
the semiconductor switch is a junction-type transistor (BJT), the first electrode and the second electrode are a collector electrode of the junction-type transistor and an emitter electrode of the junction-type transistor, and the third electrode is the base electrode of the junction type transistor
substrate support assembly. According to claim 1,
The heater layer further includes a layer in which a plurality of second heaters capable of independently controlling the temperature of at least one area having high power compared to the first heater and relatively wide are disposed.
substrate support assembly. According to claim 1,
and an electrostatic clamping layer on which an electrostatic electrode for clamping the substrate is disposed.
substrate support assembly. According to claim 1,
Power supplied to the first line, the second line, and the third line is controlled by time division multiplexing.
substrate support assembly. A plasma processing system comprising:
a chamber comprising a substrate support assembly;
The substrate support assembly comprises:
A heater layer including a semiconductor switch as a heating element, and in which a plurality of first heaters capable of independently controlling temperature are disposed in each of a plurality of zones specified around an upper support surface of the substrate support assembly on which a substrate is supported. ), including
The heater layer includes a first line electrically connected to the first electrode of the first heater, a second line electrically connected to the second electrode of the first heater, and a third electrode of the first heater electrically. Any two of the connected third lines do not intersect each other and are arranged laterally on the same layer.
Plasma processing system. 12. The method of claim 11,
The heater layer includes a first insulating layer, a second insulating layer and a third insulating layer,
The plurality of first heaters are disposed on the first insulating layer,
the first line and the second line are disposed in a second insulating layer under the first insulating layer and the third line is disposed in a third insulating layer under the second insulating layer;
wherein the first line is disposed in a second insulating layer under the first insulating layer and the second line and the third line are disposed in a third insulating layer under the second insulating layer
Plasma processing system. 12. The method of claim 11,
The first heater may further include a resistor connected in series or in parallel with the semiconductor switch as a heating element.
Plasma processing system. 12. The method of claim 11,
The plurality of first heaters are arranged in the form of a mattress consisting of a plurality of rows and a plurality of columns on the heater layer
Plasma processing system. 12. The method of claim 11,
any one of the first line, the second line, and the third line is electrically connected to a common ground
Plasma processing system. 12. The method of claim 11,
The semiconductor switch is a MOSFET, the first electrode and the second electrode are a drain electrode of the MOSFET and a source electrode of the MOSFET, and the third electrode is a gate of the MOSFET ) electrode
Plasma processing system. 12. The method of claim 11,
the semiconductor switch is a junction-type transistor (BJT), the first electrode and the second electrode are a collector electrode of the junction-type transistor and an emitter electrode of the junction-type transistor, and the third electrode is the base electrode of the junction type transistor
Plasma processing system. 12. The method of claim 11,
The heater layer further includes a layer in which a plurality of second heaters capable of independently controlling the temperature of at least one area having high power compared to the first heater and relatively wide are disposed.
Plasma processing system. 12. The method of claim 11,
and an electrostatic clamping layer on which an electrostatic electrode for clamping the substrate is disposed.
Plasma processing system. 12. The method of claim 11,
Power supplied to the first line, the second line, and the third line is controlled by time division multiplexing.
Plasma processing system.

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