KR102438390B1 - Finer grain dynamic random access memory - Google Patents

Abstract

Systems, apparatus, and methods related to DRAM, such as fine-grained dynamic random access memory (DRAM), are described. For example, an array of memory cells in a memory device may be divided into regions. Each zone may include a plurality of memory cell banks. Each zone may be associated with a data channel configured to communicate with a host device. In some examples, each channel of the array may include two or more data pins. The ratio of data pins per channel may be 2 or 4 in various examples. Another example could include 8 data pins per channel.

Description

Fine-grained dynamic random access memory {FINER GRAIN DYNAMIC RANDOM ACCESS MEMORY}

cross reference

This patent application is a U.S. patent claiming the benefit and priority of U.S. Provisional Patent Application No. 62/521,044 (filed date: June 16, 2017, titled "Finer Grain Dynamic Random Access Memory", inventor: Keeth) PCT Application No. PCT/US2018/033317 (Application Date: 2018 May 18, , titled "Finer Grain Dynamic Random Access Memory", inventor: Keeth, claims priority, each of these basic applications is assigned to the assignee of the present invention, each of these basic applications is It is incorporated herein by reference.

technical field

The following relates generally to operating memory arrays, and more particularly to fine grain dynamic random access memory (DRAM).

BACKGROUND Memory devices are widely used to store information in various electronic devices such as computers, wireless communication devices, cameras, digital displays, and the like. Information is stored by programming the various states of the memory device. For example, a binary device has two states, often denoted as a logic "1" or a logic "0". In other systems, more than two states may be stored. To access the stored information, a component of the electronic device may read or sense the state stored in the memory device. To store information, a component of the electronic device may program or write state to the memory device.

Magnetic Hard Disk, Random Access Memory (RAM), Read Only Memory (ROM), DRAM, Synchronous Dynamic RAM (SDRAM), Ferroelectric RAM (FeRAM), Magnetic RAM (MRAM), Resistive RAM (RRAM), Flash Memory, Phase Shift There are various types of memory devices, including memory (PCM) and the like. A memory device may be volatile or non-volatile.

Improving memory devices may generally include increasing memory cell density, increasing read/write speeds, increasing reliability, increasing data retention, reducing power consumption, or reducing manufacturing costs, among other metrics in general. Advances in memory technology have enabled improvements to many of these metrics, but high-reliability, low-latency, and/or low-power devices tend to be expensive and difficult to scale. As the number of applications for high-reliability, low-latency, low-power memory increases, so does the demand for scalable, efficient, and cost-effective devices for these applications.

1 illustrates an example of a memory die supporting features and operation in accordance with an example of the present invention;
2 depicts an example of a device that supports features and operations in accordance with an example of the present invention;
3 illustrates an example of a memory die supporting features and operation in accordance with an example of the present invention;
4 illustrates an example of a memory die supporting features and operation in accordance with examples of the present invention;
5 depicts an example of a memory die supporting features and operation in accordance with an example of the present invention;
6 depicts an example of a memory die supporting features and operation in accordance with an example of the present invention;
7 is a diagram illustrating an example of a data channel configuration supporting features and operations according to an example of the present invention;
8 illustrates an example of signal path routing supporting features and operation in accordance with examples of the present invention; and
9 is a diagram illustrating an example of a system that supports features and operations in accordance with an example of the present invention.

Some memory devices may include relatively long conductive paths between various components. Driving a signal through a long conductive path can consume more power than driving a signal through a shorter path and can introduce additional challenges and inefficiencies. Some memory technologies may include multiple channel terminals distributed throughout the die area. Distributing the channel terminals across the die area can shorten the conductive path between the host device and the memory cell and reduce the amount of power required to access the memory cell. For example, some channel terminals may be located in an input/output (I/O) region (eg, of a memory cell).

An array of memory cells in a memory device may be divided into any number of zones. Each zone may include a plurality of memory cell banks. Each zone may be communicatively coupled to a host device using a channel that may include a predetermined number of data pins, a predetermined number of command/address pins, and a predetermined number of clock pins. A zone may be configured to minimize a distance between an interface of a host device and a memory cell in the zone. By minimizing or at least reducing the length of the signal path between the interface and the memory cell in the zone, the memory device can achieve high data throughput (e.g., less than 3 picofarads (pF) per access operation) within an energy budget (e.g. multiple TB/s). In some memory devices, the memory die may have a centralized interface or ball-out for memory cells. In such a memory device, the length of the signal path between the interface and the memory cell may be longer.

Features of the invention introduced above are further described below in the context of an exemplary array (eg, FIG. 1 ). Specific examples are described for various examples or aspects of systems (eg, FIGS. 2 and 9 ) and memory devices ( FIGS. 3-8 ).

1 shows an example of a memory die 100 in accordance with various aspects disclosed herein. Memory die 100 may also be referred to as an electronic memory device, a memory array, a memory cell array, or a memory cell deck in some examples. Memory die 100 may include memory cells 105 programmable to store multiple states. Memory cells 105 may be arranged in one or more banks of memory cells that may be independently accessible. Each memory cell 105 may be programmable to store two states, denoted as logic 0 and logic 1. In some cases, memory cell 105 may be configured to store more than two logical states.

memory cell 105 may store charge in a capacitor representing a programmable state; For example, a charging capacitor and a non-charging capacitor may each exhibit two logic states. DRAM architectures may use this design, and the capacitors used may include dielectric materials with linear or paraelectric electrical polarization properties as insulators. The FeRAM architecture may also take advantage of this design.

Operations such as read and write may be performed on the memory cell 105 by activating an access line 110 and a digit line 115 . The access line 110 is also known as a word line 110 , and the bit line 115 is also known as a digit line 115 . References to word lines and bit lines, or similar terms thereof, may be interchanged without loss of understanding or operation. Activating the word line 110 or the digit line 115 may include applying a voltage to the respective line. The word line 110 and the digit line 115 are formed of a metal (eg, copper (Cu), aluminum (Al), gold (Au), tungsten (W), etc.), a metal alloy, carbon, a conductively doped semiconductor. , or other conductive materials, alloys, compounds, and the like.

1 , each row of memory cells 105 may be connected to a single word line 110 , and each column of memory cells 105 may be connected to a single number line 115 . can By activating one word line 110 and one digit line 115 (eg, by applying a voltage to the word line 110 or digit line 115 ), a single memory cell 105 becomes its intersection point. can be accessed from Accessing the memory cell 105 may include reading from or writing to the memory cell 105 . The intersection of the word line 110 and the digit line 115 may be referred to as an address of a memory cell. Additionally or alternatively, for example, each row 105 of memory cells may be arranged into one or more banks of memory cells.

In some architectures, the cell's logical storage device, such as a capacitor, may be electrically isolated from the digit line by an optional component (not shown). The word line 110 may be coupled to and control the selection component. For example, the select component may be a transistor, and the word line 110 may be coupled to the gate of the transistor. Activating the word line 110 may result in an electrical connection or a closed circuit between the capacitor of the memory cell 105 and its corresponding digit line 115 . The digit line can then be accessed to read from or write to the memory cell 105 .

Access to memory cell 105 may be controlled via row decoder 120 and column decoder 130 . For example, the row decoder 120 may receive a row address from the memory controller 140 and activate an appropriate word line 110 based on the received row address. Similarly, column decoder 130 may receive a column address from memory controller 140 and activate the appropriate digit line 115 . The row decoder 120 and the column decoder 130 may receive a row address and a column address, respectively, for a memory cell located within one specific memory cell bank. Additionally or alternatively, each memory cell bank may be in electronic communication with separate row decoder 120 and column decoder 130 . For example, the memory die 100 may include a plurality of word lines 110 denoted WL_1 through WL_M, and a number of digit lines 115 denoted DL_1 through DL_N, where M and N correspond to the array size. depend on Thus, by activating word line 110 and digit line 115, for example WL_2 and DL_3, the memory cell 105 at the intersection can be accessed.

Upon accessing the memory cell 105 , the cell may be read or sensed by the sense component 125 to determine the stored state of the memory cell 105 . For example, after accessing a memory cell 105 , a capacitor in the memory cell 105 may be discharged to a corresponding digit line 115 . Discharging the capacitor can in some cases be caused by biasing the capacitor or applying a voltage to the capacitor. Discharging may cause a change in voltage on digit line 115 and sensing component 125 may determine the stored state of memory cell 105 compared to a reference voltage (not shown). For example, if digit line 115 has a voltage higher than the reference voltage, sensing component 125 may determine that the state stored in memory cell 105 is a logic one and vice versa. Sensing component 125 may include various transistors or amplifiers for detecting and amplifying differences in signals, which may be referred to as latching. The detected logic state of memory cell 105 may then be output via column decoder 130 as output 135 . In some cases, sensing component 125 may be part of column decoder 130 or row decoder 120 . Alternatively, the sensing component 125 may be coupled to or in electronic communication with the column decoder 130 or row decoder 120 .

A memory cell 105 may be set or written by similarly activating the associated word line 110 and digit line 115 , for example a logic value may be stored in the memory cell 105 . Column decoder 130 or row decoder 120 may receive data to be written to memory cell 105 , for example, input/output 135 . Memory cell 105 can be written to by applying a voltage across the capacitor.

Memory controller 140 operates (eg, reads, writes, rewrites, reads, writes, rewrites) memory cells 105 via various components, such as row decoder 120 , column decoder 130 , and sensing component 125 . , refresh, discharge, etc.) can be controlled. Memory controller 140 may be a component of memory die 100 or may be external to memory die 100 in various examples. In some cases, one or more of the row decoder 120 , the column decoder 130 , and the sensing component 125 may be co-located with the memory controller 140 . Memory controller 140 may generate row and column address signals to activate desired word lines 110 and digit lines 115 . Memory controller 140 may activate desired word line 110 and digit line 115 of a particular memory cell bank through at least one channel traversing memory die 100 . Memory controller 140 may also generate and control various voltages or currents used during operation of memory die 100 . For example, the memory controller may apply a discharge voltage to the word line 110 or the digit line 115 after accessing one or more memory cells 105 . Memory controller 140 may be coupled to memory cell 105 via channel 145 . Although channel 145 is shown in FIG. 1 as a logical connection with row decoder 120 and column decoder 130 , one of ordinary skill in the art will recognize that other configurations may be used. As described herein, memory controller 140 may exchange data with cell 105 multiple times (eg, from read or write operations) per clock cycle.

Memory controller 140 may also be configured to communicate commands, data, and other information with a host device (not shown). The memory controller 140 may modulate a signal communicated between the memory array and the host device using a modulation scheme. Based on the type of modulation scheme selected, the I/O interface may be configured.

In general, the amplitude, shape, or duration of the applied voltage or current discussed herein may be adjusted or changed and may be different for the various operations discussed when operating the memory die 100 . Also, one, multiple, or all memory cells 105 in memory die 100 may be accessed concurrently or together; For example, multiple or all cells of memory die 100 may be accessed concurrently or together during a reset operation that sets all memory cells 105 or groups of memory cells 105 to a single logical state.

2 illustrates an apparatus or system 200 that supports channel routing for a memory device in accordance with various examples disclosed herein. The system 200 may include a host device 205 and a plurality of memory devices 210 . The plurality of memory devices 210 may be examples of fine-grained memory devices (eg, fine-grained DRAM or fine-grained FeRAM).

The host device 205 may be an example of a processor (eg, a central processing unit (CPU), a graphics processing unit (GPU)), or a system on a chip (SoC). have. In some cases, the host device 205 is a separate component from the memory device 210 , such that the host device 205 may be manufactured separately from the memory device 210 . The host device 205 may be external to the memory device 210 (eg, a laptop, server, personal computing device, smart phone, personal computer). In system 200 , memory device 210 may be configured to store data for host device 205 .

The host device 205 may exchange information with the memory device 210 using signals that communicate via a signal path. A signal path may be a path that a message or transmission may take from a sending component to a receiving component. In some cases, the signal path may be a conductor coupled with at least two components, wherein the conductor optionally allows electrons to flow between the at least two components. A signal path may be formed in a wireless medium, such as in the case of wireless communications (eg, radio frequency (RF) or optical). The signal path may be at least partially coupled to a first substrate, such as an organic substrate of a memory device, and/or a package substrate (eg, at least one of, if not both, memory device 210 and host device 205 ). For example, a second substrate such as a second organic substrate) may be included. In some cases, memory device 210 may function as a slave type device to host device 205 , which may function as a master type device.

In some applications, system 200 may benefit from a high-speed connection between host device 205 and memory device 210 . As such, some memory devices 210 support applications, processes, host devices, or processors with multiple terabytes per second (TB/s) bandwidth requirements. Satisfying these bandwidth constraints within an acceptable energy budget can present challenges in certain circumstances.

The memory device 210 may be configured such that the signal path between the memory cell in the memory device 210 and the host device 205 is as short as the material properties, operating environment, component layout, and application permit. For example, memory device 210 may be a bufferless memory device with a point-to-point connection between the host device and the memory array. In another example, the data channel coupling the host device 205 and the memory device 210 may include a point-to-many-point configuration, with one pin of the host device 205 . is associated with corresponding pins of at least two memory arrays. In another example, the data channel coupling the host device 205 and the memory device 210 may be configured to be shorter than other designs, such as other proximity memory applications (eg, graphics cards using GDDR5-compatible DRAM). .

The memory die of the memory device 210 may be configured to operate with many types of communication media (eg, a substrate such as an organic substrate and/or a high density interposer such as a silicon interposer). The host device 205 may in some cases be configured to have an interface or ballout that includes a design (eg, matrix or pattern) of terminals.

3 shows an example of a device or devices 300 according to various examples disclosed herein. The memory device 300 includes at least one memory die 305 and a communication medium 310 . Communication medium 310 may in some cases be an example of a substrate.

Memory die 305 may include a plurality of memory cells (shown in FIG. 1 and described with reference thereto) that may be programmable to store different logic states. For example, each memory cell stores one or more logical states (eg, logic '0', logic '1', logic '00', logic '01', logic '10', logic '11'). can be programmed to The memory cells of the memory die 305 may use different storage technologies to store data, including DRAM, FeRAM, phase change memory (PCM), 3D XPoint ^™ memory, NAND memory, or NOR memory, or combinations thereof. have. In some cases, a single memory device comprises a first memory die using a first memory technology (eg, DRAM), and a second memory die using a second memory technology (eg, FeRAM) different from the first memory technology (eg, FeRAM). 2 memory dies.

Memory die 305 may be an example of a two-dimensional (2D) array of memory cells. In some cases, multiple memory dies 305 may be stacked on top of each other to form a three-dimensional (3D) array. A memory die may include a plurality of memory cell decks stacked on top of each other. Such a configuration can increase the number of memory cells that can be formed on a single die or substrate as compared to a 2D array. This can reduce production costs, increase the performance of the memory array, or both. Each level of the array may be positioned such that memory cells across each level are approximately aligned with each other to form a stack of memory cells. In some cases, the memory dies 305 may be directly stacked on each other. In other cases, one or more memory dies 305 may be located away from the stack of memory dies (eg, in a different memory stack).

The first memory device 315 may be an example of a single die package including a single memory die 305 and a communication medium 310 . The second memory device 320 may be an example of a two-height device that includes two memory dies 305 - a and 305 - b and a communication medium 310 . The third memory device 325 may be an example of a four-height device that includes four memory dies 305 - a through 305 - d and a communication medium 310 . The fourth memory device 330 may be an example of an eight tall device that includes eight memory dies 305 - a through 305 - h and a communication medium 310 . Memory device 300 may include any number of memory dies 305 that may be stacked on top of a common substrate in some examples. The dies are shown in different shades to more clearly show the different layers. In some cases, memory dies of different layers may be configured similarly to adjacent dies of a memory device.

Memory die 305 may include one or more vias (eg, through-silicon vias (TSVs)). In some cases, one or more vias may be part of an internal signal path that couples the controller with the memory cell. Vias may be used to communicate between memory dies 305 , for example, when memory dies 305 are stacked on top of each other. Some vias may be used to facilitate communication between the controller of the memory device and at least some of the memory dies 305 . In some cases, a single via may be coupled to multiple memory dies 305 .

Communication medium 310 may be any structure or medium used to couple memory die 305 with a host device such that signals may be exchanged between memory die 305 and a host device. The communication medium 310 may be an example of a substrate, an organic substrate, a high density interposer, a silicon interposer, or a combination thereof. The communication medium 310 may be located above, below, or on the side of the memory array. Communication medium 310 is not limited to being under other components and may be any configuration for a memory array and/or other components. In some examples, communication medium 310 may be referred to as a substrate, but is not limited to such reference.

Communication medium 310 may be formed of different types of materials. In some cases, communication medium 310 may be an example of one or more organic substrates. For example, the communication medium 310 may include a package substrate (eg, an organic substrate) coupled with at least one, if not both, of a host device and a stack of memory die 305 . In another example, the communication medium 310 can include an organic substrate and a package substrate of a memory device. The substrate may be an example of a printed circuit board that mechanically supports and/or electrically connects the components. The substrate may use conductive tracks, pads, and other features etched from one or more layers of conductive material (eg, copper) laminated on and/or between layers of non-conductive material. The components may be fastened (eg, soldered) onto the substrate to electrically connect and mechanically fasten the components. In some cases, the non-conductive material of the substrate is resin impregnated phenolic paper or phenolic cotton paper, resin impregnated glass fiber, metal core board, polyimide foil, Kapton, UPILEX, polyimide-fluoropolymer composite. It can be formed from a variety of different materials including foil, Ajinomoto build-up film (ABF) or other materials or combinations thereof.

In some cases, the communication medium 310 may be a high-density interposer, such as a silicon interposer. The high-density interposer may be configured to provide a wide signal path between connected components (eg, a memory device and a host device). A high-density interposer can provide a wide signal path by providing a large number of channels to connect components. In some cases, the channels may be thin connector traces (eg, copper), thus losing each individual channel. Because each channel can have high resistance, the power required to transmit data can increase in a non-linear relationship with frequency as the frequency of the data being transmitted increases. This characteristic can impose an actual frequency threshold (eg, ceiling) that can be used to transmit data over the channel of the silicon interposer given the amount of transmit power. The channels may be independent of each other in some cases. Some channels may be unidirectional and some channels may be bidirectional.

In some cases, a buffer layer may be located between the memory die 305 and the communication medium 310 . The buffer may be configured to drive (eg, re-drive) signals to and from the memory die 305 . In some cases, the memory stack may be bufferless, meaning that, among other components, there is, in particular, no buffer layer or the base layer does not include a redriver.

4 shows an example of a memory die 400 in accordance with various examples disclosed herein. Memory die 400 may be an example of memory die 305 described with reference to FIG. 3 . In some cases, the memory die 400 may be referred to as a memory array, a memory cell array, or a memory cell deck. The various components of memory die 400 may be configured to provide high bandwidth data transfer between a memory device associated with memory die 400 and a host device.

The memory die 400 includes a plurality of banks 405 of memory cells (indicated by white boxes), a plurality of input/output (I/O) regions 410 across the memory cells of the memory die 400 (sometimes I (also referred to as /O stripes or I/O regions), and a plurality of data channels 415 that can couple the memory die 400 with a host device. Each memory cell bank 405 may include a plurality of memory cells configured to store data. The memory cells may be DRAM memory cells, FeRAM memory cells, or other types of memory cells.

Memory die 400 may be divided into cell regions 420 associated with different data channels 415 . For example, a single data channel 415 may be configured to couple a single cell region 420 with a host device. In some cases, pins of an I/O channel may be configured to couple multiple cell regions 420 of memory die 400 to power, ground, virtual ground, and/or other support components.

Between the interface of any given memory cell and data channel 415 to provide high throughput data (eg, multiple TB/s) between the host device (not shown) and the memory die 400 . may be shorter than other previous solutions. Also, shortening the data path between any given memory cell and the host device can reduce the power consumed during an access operation (eg, a read operation or a write operation) of that given memory cell. Different architectures and/or strategies may be used to reduce the size of the data path.

In some examples, the memory die 400 may be divided into a plurality of cell regions 420 . Each cell region 420 may be associated with a data channel 415 . Although two different types of cell regions 420 are shown, the entire memory die 400 may be filled with any number of cell regions 420 having any shape. Cell region 420 may include a plurality of memory cell banks 405 . There may be any number of banks 405 in cell region 420 . For example, the memory die 400 has a first cell region 420 that may include eight banks 405 , and a second cell region 420 - that may include 16 banks 405 - a . a) is shown.

However, different numbers (e.g., 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, etc.) of banks are possible. The size of the cell region 420 may be selected based on the bandwidth constraints of the host device, the power requirements of the host device or memory device, the size of the data channel, the data rate associated with the data channel, other considerations, or any combination thereof. have. In some cases, the memory die 400 may be partitioned such that each cell region 420 is the same size. In other cases, the memory die 400 may be partitioned such that the memory die 400 may have cell regions 420 of different sizes.

The data channel 415 (associated with the cell region) may include a number of pins for coupling the memory cells of the cell region 420 with a host device. At least a portion of the data channel 415 may include a channel of a substrate (eg, a high-density interposer or an organic substrate). Data channel 415 may include a data width that specifies the number of data pins 425 (sometimes referred to as DQ pins) within data channel 415 . For example, a data channel has 2 data pins (eg X2 channel), 4 data pins (eg X4 channel), 8 data pins (eg X8 channel), 16 data pins (eg, X16 channel) and the like. The data channel may also include at least one command/address (C/A) pin 430 . Each memory cell within cell region 420 may be configured to transfer data to and from a host device using pins 425 , 430 associated with cell region 420 . Data channel 415 may also include a clock pin (eg, CLK) and/or a read clock pin or a return clock pin (RCLK).

The I/O interface of the memory die 400 may be configured to support multiple channel widths (eg, x4, x8, x16, x32, etc.). In some examples, different modulation schemes may be used to communicate data over channels having different widths to maintain data bandwidth, data throughput, or data accessibility. For example, four-symbol pulse-amplitude modulation (PAM4) can be used to modulate signals communicating over the X4 channel, and Non-Return to Zero modulation) (NRZ) can be used to modulate the signal communicating over the X8 channel.

The plurality of I/O regions 410 may include a plurality of power and ground pins configured to couple memory cells of the memory die 400 with power and ground. In some cases, I/O region 410 may include a TSV for communicating a power signal and/or a ground signal with a memory die located above or below the memory die 400 .

I/O region 410 may include an interface or terminal for data channel 415 . The interface or terminal may include a plurality of pins or pads configured to couple with a signal path. A signal path may couple the memory cell of region 420 with channel 415 . I/O region 410 may in some cases include a TSV to communicate signals (eg, using data channel 415 ) with a memory die located above or below memory die 400 . .

The I/O region 410 may in some cases bisect the bank 405 of memory cells in the cell region 420 . If the terminals for the channels are located in I/O region 410 , the length of the signal path to any individual memory cell in region 420 may be shortened. I/O region 410 may be configured to bisect region 420 . In some cases, I/O region 410 is such that 50% of bank 405 is on the first side of I/O region 410 and 50% of bank 405 is on the second side of I/O region 410 . It is possible to divide the bank 405 of the zone 420 so that it is on two sides. In another example, the I/O region 410 may be bisected such that the divisions of the banks 405 on either side of the I/O region 410 are unequal. In some cases, region 420 may be defined such that I/O region 410 bisects region 420 . Memory die 400 includes four I/O regions 410 . In another example, memory die 400 may have a different number of I/O regions (eg, 1, 2, 3, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, etc.).

5 shows an example of a memory die 500 that includes eight I/O regions 510 that bisect the memory die 500 . Using eight I/O regions 510 may change some characteristics of region 520 relative to memory die 400 . Memory die 500 may be an example of memory die 400 , so a complete description of some features of memory die 500 is not repeated herein. Components having similar names and/or similar numbers may be implemented similarly. For example, the memory die 500 may include a data channel 515 , which is an example of the data channel 415 described with reference to FIG. 4 .

In some cases, using eight I/O regions 510 may change the shape of region 520 . Region 520 may be configured to be bisected by I/O region 510 (or I/O region 510 may be configured to bisect region 520 ). In this way, the length of the signal path coupling the memory cell and the channel terminal located in the I/O region 510 can be minimized. As more I/O regions extend across the memory die, fewer banks 505 can be located between the I/O regions. If a single channel serves a region 520 of the bank 505 , the shape of the region 520 may be different from the shape of the region 420 . For example, zones 520 and 520 - a may include a single bank 505 located on each side of an I/O region 510 , where zones 420 and 420 - a are I/O regions 510 . It may include two banks located on each side of region 410 .

6 shows an example of a memory die 600 that includes two I/O regions 610 that bisect the memory die 600 . Using two I/O regions 610 may change some characteristics of region 620 relative to memory die 400 . Memory die 600 may be an example of memory die 400 , so a complete description of some features of memory die 600 is not repeated herein. Components having similar names and/or similar numbers may be implemented similarly. For example, the memory die 600 may include a data channel 615 , which is an example of the data channel 415 described with reference to FIG. 4 .

In some cases, using two I/O regions 610 may change the shape of region 620 . Region 620 may be configured to be bisected by I/O region 610 (or I/O region 610 may be configured to bisect region 620 ). As fewer I/O regions extend across the memory die, more banks 605 may be located between the I/O regions. If a single channel serves a region 620 of the bank 605 , the shape of the region 620 may be different from the shape of the region 420 . For example, zones 620 and 620 - a may include four banks 605 located on each side of I/O region 610 , where zones 420 and 420 - a are I/O regions 610 . It may include two banks located on each side of the O region 410 .

7 shows an example of a data channel configuration 700 in accordance with various examples disclosed herein. The data channel configuration 700 may include a first data channel configuration 705 and a second data channel configuration 710 . For example, a first data channel configuration 705 shows a data channel 715 serving a cell region 720 .

Data channel 715 shows a data channel for a stacked memory device that includes eight layers and has four channel widths (eg, with four data pins). Each row of pins in data channel 715 may be associated with a cell region in a separate layer. Cell region 720 illustrates a single layer of cell region. As such, cell region 720 may be associated with a single row of pins of data channel 715 . Because a single data channel may be configured to couple with multiple layers, the number of pins in the data channel may be based on the number of layers of the memory device.

In some examples, a data channel may be associated with a single cell region of any given layer or memory die (eg, not coupled with another cell region). Data channel 715 may be associated with a cell zone in eight layers, although any number of layers are possible. For example, data channel 715 may include 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, or 16 (or more) of the memory device. It may be associated with a cell region of a layer.

The first configuration 705 of the data channel 715 may include four data pins DQ1 to DQ4, a clock pin CLK, a read clock pin or return clock pin RCLK, and a command/address pin CA. can In other cases, the data channel 715 may have a different rank or a different channel width. In this situation, the number of data pins may be different. For example, the first configuration 705 of the data channel 715 may have a channel width of 8 and may include 8 data pins. Any number of data pins associated with a zone are contemplated by the present invention. The first configuration 705 of the data channel 715 may include any number of C/A pins. For example, data channel 715 may include 1, 2, 3, or 4 C/A pins. In some cases, the first configuration 705 of the data channel 715 may include an error correction code (ECC) pin to provide an error detection and correction procedure.

The second configuration 710 of the data channel 715 may include four data pins DQ1 to DQ4, a clock pin CLK, and two command/address pins CA. In other cases, the data channel 715 may have a different rank or a different channel width. In this situation, the number of data pins may be different. For example, the second configuration 710 of the data channel 715 may have a channel width of 8 and may include 8 data pins. Any number of data pins associated with a zone are contemplated by the present invention. The second configuration 710 of the data channel 715 may include any number of C/A pins. For example, data channel 715 may include 1, 2, 3, or 4 C/A pins. In some cases, the second configuration 710 of the data channel 715 may include an ECC pin to provide an error detection and correction procedure.

8 shows an example of signal path routing 800 in memory device 805 . The first memory device 805 - a includes a first signal path routing 800 - a, and the second memory device 805 - b includes a second signal path routing 800 - b. The example of signal path routing shows different options for connecting TSVs between different dies of memory device 805 .

The first memory device 805 - a may include a first memory die 810 , a second memory die 815 , a third memory die 820 , and a fourth memory die 825 . In another example, the first memory device 805 - a may include more or fewer memory dies than shown. The plurality of TSVs 830 may extend at least partially through each memory die 810 , 815 , 820 , 825 . Each die may include at least one pad 835 coupling the signal paths of the memory die 810 , 815 , 820 , 825 together. The stack of memory dies may include pads 835 coupled to data channels DQ Ch0, DQ Ch1, DQ Ch2, and DQ Ch3 at the bottom.

In a first signal path routing 800 - a, a TSV 830 may be coupled to a pad 835 in a neighboring row. For example, the TSV 830 in the DQ Ch0 column of the first memory die 810 may be communicatively coupled with the pads 835 below the first die 810 and in the DQ Ch1 column. In this way, the signal path may include TSVs offset from each other in adjacent layers. In the first signal path routing 800 - a, the memory device 805 - a may not include a signal path having TSVs going up in the same column in more than one die at a time.

The second memory device 805 - b may include a first memory die 850 , a second memory die 855 , a third memory die 860 , and a fourth memory die 865 . In another example, the second memory device 805 - b may include more or fewer memory dies than shown. A plurality of TSVs 870 extend at least partially through respective dies 850 , 855 , 860 , 865 . Each die includes at least one pad 875 coupling the signal paths of the die 850 , 855 , 860 , 865 together. The stack of memory dies may include pads 875 coupled to data channels DQ Ch0, DQ Ch1, DQ Ch2, and DQ Ch3 at the bottom.

In the second signal path routing 800 - b, each data channel terminates in a column associated with DQ Ch0. For example, the signal path for DQ Ch0 may be coupled with the first memory die 850 in a column associated with DQ Ch0. The signal path for DQ Ch1 may include a TSV 870 extending through the first memory die 850 , a lateral conductive path 880 , coupled with the second memory die 855 in a column associated with DQ Ch0 . can be The signal path for DQ Ch2 may include a TSV 870 extending through the first memory die 850 and the second memory die 855 , a lateral conductive path 880 , and may include a lateral conductive path 880 in the column associated with DQ Ch0. 3 is coupled with the memory die 860 . The signal path for DQ Ch3 may include a TSV 870 , a lateral conductive path 880 extending through a first memory die 850 , a second memory die 855 , and a third memory die 860 , and , coupled with the fourth memory die 865 in the column associated with DQ Ch0.

9 shows a diagram of a system 900 including a device 905 supporting fine-grained DRAM in accordance with aspects disclosed herein. The device 905 includes a memory controller 915 , a memory cell 920 , a basic input/output system (BIOS) component 925 , a processor 930 , an I/O controller 935 , and a peripheral component 940 . Two-way voice and data communication comprising components for transmitting and receiving communications, including a memory chip 955 , a system memory controller 960 , an encoder 965 , a decoder 970 , and a multiplexer 975 . It may contain components for These components may communicate electronically via one or more buses (eg, bus 910 ). Bus 910 may have a bus width of, for example, 16 data lines (“DQ” lines). Bus 910 may be in electronic communication with a bank of 32 memory cells.

Memory controller 915 or 960 may operate one or more memory cells described herein. Specifically, the memory controller may be configured to support flexible multi-channel memory. In some cases, memory controller 915 or 960 may operate the row decoder, column decoder, or both described with reference to FIG. 1 . Memory controller 915 or 960 may be in electronic communication with a host and may be configured to transmit data during each of the rising and falling edges of a clock signal of memory controller 915 or 960 .

Memory cell 920 may store the information described herein (ie, in the form of logic states). Memory cell 920 may represent, for example, memory cell 105 described with reference to FIG. 1 . Memory cell 920 may be in electronic communication with memory controller 915 or 960 , and memory cell 920 and memory controller 915 or 960 may be a chip, which may be one or several planar memory devices described herein. (955). Chip 955 may be managed, for example, by system memory controller 915 or 960 . Memory cell 920 may represent a first memory cell array having a plurality of regions coupled to a substrate. Each region of the plurality of regions may include a plurality of memory cell banks and a plurality of channels crossing the first memory cell array. At least one of the plurality of channels may be coupled to the at least one zone. Memory controller 915 or 960 may be configured to transfer data between the coupling region and memory controller 915 or 960 .

The BIOS component 925 is a software component including the BIOS that operates as firmware capable of initializing and executing various hardware components. BIOS component 925 may also manage data flow between the processor and various other components, eg, peripheral components, input/output control components, and the like. BIOS component 925 may include programs or software stored in read-only memory (ROM), flash memory, or any other non-volatile memory.

The processor 930 may be an intelligent hardware device (eg, a general purpose processor, a digital signal processor (DSP), a CPU, a microcontroller, an application-specific integrated circuit (ASIC), an electric field programmable gate array). (Field Programmable Gate Array: FPGA), programmable logic device, discrete gate or transistor logic component, discrete hardware component, or any combination thereof. In some cases, processor 930 may be configured to operate a memory array using memory controller 915 or 960 . In other cases, the memory controller 915 or 960 may be integrated into the processor 930 . Processor 930 may be configured to execute computer readable instructions stored in memory to perform various functions (eg, functions or tasks that support flexible multi-channel memory).

, ANDROID

, MS-DOS

, MS-WINDOWS

, OS/2

, UNIX

, LINUX

와 같은 운영 체제 또는 다른 알려진 운영 체제를 이용할 수 있다. 다른 경우에, I/O 제어기(935)는 모뎀, 키보드, 마우스, 터치 스크린 또는 유사한 디바이스를 나타내거나 이와 상호 작용할 수 있다. 일부 경우에, I/O 제어기(935)는 프로세서의 일부로서 구현될 수 있다. 사용자는 I/O 제어기(935)를 통해 또는 I/O 제어기(935)에 의해 제어되는 하드웨어 구성 요소를 통해 디바이스(905)와 상호 작용할 수 있다.I/O controller 935 may manage input and output signals to device 905 . The I/O controller 935 may also manage peripheral devices that are not integrated into the device 905 . In some cases, I/O controller 935 may represent a physical connection or port with an external peripheral device. I/O controller 935 is iOS

, ANDROID

, MS-DOS

, MS-WINDOWS

, OS/2

, UNIX

, linux

An operating system such as , or other known operating systems may be used. In other cases, I/O controller 935 may represent or interact with a modem, keyboard, mouse, touch screen, or similar device. In some cases, I/O controller 935 may be implemented as part of a processor. A user may interact with device 905 through I/O controller 935 or through hardware components controlled by I/O controller 935 .

Peripheral component 940 may include any input or output device, or an interface for such device. Examples include disk controllers, sound controllers, graphics controllers, Ethernet controllers, modems, universal serial bus (USB) controllers, serial or parallel ports, or peripheral device card slots, such as peripheral component interconnects. It may include a Component Interconnect: PCI) or an accelerated graphics port (AGP) slot.

Input 945 may represent a signal external to device or device 905 that provides an input to device 905 or a component thereof. It may include a user interface or include an interface with another device or an interface between other devices. In some cases, input 945 may be managed by I/O controller 935 , and may interact with device 905 via peripheral component 940 .

Output 950 may also represent a device or a signal external to device 905 configured to receive an output from device 905 or any component thereof. Examples of output 950 may include a graphic display, audio speaker, printed device, other processor or printed circuit board, or the like. In some cases, output 950 may be a peripheral element that interfaces with device 905 via peripheral component(s) 940 . Output 950 may be managed by an I/O controller 935 .

The system memory controller 915 or 960 may be in electronic communication with a first array of memory cells (eg, memory cells 920 ). The host may be a component or device that controls or directs operations on the memory controller 915 or 960 and the device of which the corresponding memory array is a part. The host may be a component of a computer, mobile device, or the like. Alternatively, the device 905 may be referred to as a host. In some examples, system memory controller 915 or 960 is a GPU.

The encoder 965 may represent a device or a signal external to the device 905 that performs error correction encoding on data to be stored in the device 905 or a component thereof. The encoder 965 may write the encoded data to at least one selected memory through at least one channel, and may encode the data through error correction coding.

The decoder 970 may represent a device or a signal external to the device 905 sequencing the command signal and the addressing signal into the device 905 or a component thereof. In some examples, memory controller 915 or 960 may be co-located within decoder 970 .

The multiplexer 975 may represent a device or a signal external to the device 905 that multiplexes data to the device 905 or a component thereof. The multiplexer 975 may multiplex data to be transmitted to the encoder 965 and demultiplex data received from the encoder 965 . A multiplexer 975 may be in electronic communication with a decoder 970 . In some examples, multiplexer 975 may be in electronic communication with a controller, such as system memory controller 915 or 960 .

Components of device 905 may include circuitry designed to perform its functions. It may include various circuit elements, such as conductive lines, transistors, capacitors, inductors, resistors, amplifiers, or other active or inactive elements configured to perform the functions described herein. Device 905 may be a computer, server, laptop computer, notebook computer, tablet computer, mobile phone, wearable electronic device, personal electronic device, or the like. Alternatively, device 905 may be a part or aspect of such a device. In some examples, device 905 is an aspect of a computer with high reliability, mission critical, or low latency constraints or parameters, such as a vehicle (eg, autonomous vehicle, airplane, spacecraft, etc.). Device 905 may be or include logic circuitry for artificial intelligence (AI), augmented reality (AR), or virtual reality (VR) applications.

In one example, a memory device may include an array of memory cells having a plurality of zones, each of which may include a plurality of banks of memory cells, and a plurality of channels across the memory cell array. Each channel may be associated with a region of the memory cell array and may be configured to communicate signals between a host device and a plurality of memory cell banks of the region.

In some examples, the memory device can further include an I/O region extending across the memory cell array, the I/O region occupying an area of the memory cell array that may be free of memory cells. In some examples of a memory device, the I/O region may include a TSV configured to couple the memory cell array with a power node or a ground node.

In some examples, the memory device can further include a plurality of channel interfaces distributed over the memory cell array. In some examples of memory devices, the plurality of channel interfaces may be bump-out. In some examples of memory devices, a channel interface of a plurality of channel interfaces may be located in each quadrant of the memory cell array.

In some examples, the memory device can further include a plurality of signal paths extending between the memory cells of the region and a channel interface associated with the region. In some examples of memory devices, a channel interface may be located in the memory cell array to minimize the length of the signal path.

In some examples, the memory device can further include a second memory cell array stacked on top of the memory cell array. In some examples of memory devices, the second array of memory cells can have a region that can each include a plurality of banks of memory cells. In some examples, the memory device can further include a second plurality of channels traversing the second array of memory cells. In some examples of the memory device, each channel of the second plurality of channels may be coupled with a second region of the second memory cell array to communicate signals between the plurality of memory cell banks of the second region and the host device. can be configured.

In some examples, the memory device can further include a TSV extending through the memory cell array to couple the second memory cell array with the second plurality of channels. In some examples of memory devices, a channel may establish a point-to-point connection between a zone and a host device. In some examples of memory devices, each channel may include 4 or 8 data pins. In some examples of memory devices, a region of an array of memory cells may include eight or more banks of memory cells.

In some examples, the memory device can further include an interface configured to bi-directionally communicate with the host device. In some examples of the memory device, the interface may be configured to communicate a signal modulated using at least one or both of the NRZ modulation scheme or the PAM4 scheme.

In one example, a memory device comprises an array of memory cells having a region each including a plurality of banks of memory cells, an I/O region extending across the array of memory cells, the I/O region extending there through, including signals to and from the array of memory cells. The I/O region may include a plurality of terminals configured to route may be coupled and configured to communicate a signal between a host device and a plurality of banks of memory cells in the region.

In some examples, the memory device can further include a plurality of channel interfaces located in the I/O region of the memory cell array, the signal path coupling the region with the plurality of channel interfaces. In some examples of the memory device, the I/O region can include a TSV configured to couple a second memory cell array stacked on top of the memory cell array with a channel interface.

In some examples of memory devices, the channel interface of the region may be located in an I/O region that bisects the region serviced by the channel interface. In some examples of a memory device, the I/O region may include a TSV configured to couple the memory cell array with a power node or a ground node. In some examples of memory devices, the I/O region may occupy an area of an array of memory cells that may not have memory cells. In some examples of memory devices, the memory cell array may be bisected by two I/O regions. In some examples of memory devices, the memory cell array may be bisected by four I/O regions.

In one example, a system includes a host device, a memory device including a memory die having a plurality of regions each having a plurality of banks of memory cells, and a plurality of channels configured to communicatively couple the host device and the memory device. and each channel may be associated with a region of the memory die and configured to communicate signals between a host device and a plurality of memory cell banks of the region.

In some examples, a system can include an interface configured to bi-directionally communicate with a host device. In some examples of the system, the interface may be configured to communicate signals modulated using at least one or both of the NRZ modulation scheme or the PAM4 scheme. In some examples of the system, the host device may be an example of a GPU. In some examples of the system, the memory device may be located in the same package as the host device.

In one example, a memory device may include a memory cell array having a plurality of zones each including a plurality of memory cell banks, and a plurality of channels across the memory cell array, each channel comprising at least one of the memory cell arrays. It may be coupled to one zone, and each channel may include two or more data pins and one or more command/address pins.

In some examples of memory devices, each channel may include two data pins. In some examples of memory devices, each channel may include one command/address pin. In some examples of memory devices, each region of the array may include four banks of memory cells. In some examples of memory devices, each channel may include four data pins. In some examples of memory devices, each channel may include two command/address pins. In some examples of memory devices, each region of the array may include a bank of eight memory cells. In some examples of memory devices, each bank of memory cells may be contiguous with a channel.

In some examples of memory devices, a first set of each of the plurality of banks may be contiguous with a channel, and a second set of each of the plurality of banks may be contiguous with another bank and not contiguous with a channel. In some examples, the memory device may include 128 data pins, and may be configured at a ratio of 2, 4, or 8 data pins per channel.

In some examples, the memory device may include 1, 2, 3, 4, or 6 command/address pins per channel. In some examples, the memory device may include 256 data pins, and may be configured at a ratio of 2, 4, or 8 data pins per channel. In some examples, the memory device may include 1, 2, 3, 4, or 6 command/address pins per channel. In some examples of memory devices, the array may include a plurality of memory dies, each of which may include a plurality of channels.

In some examples of memory devices, each of the plurality of memory dies may be coupled to a different channel of the plurality of channels. In some examples, the memory device can include a buffer layer coupled with the array. In some examples, the memory device can include an organic substrate at the bottom of the array.

In some examples of memory devices, the array may be configured with a pin rate of 10, 16, 20, or 24 Gbps. In some examples, the memory device can include an interface configured to bi-directionally communicate with the host device. In some examples of the memory device, the interface may be configured for at least one or both of binary modulation signaling or pulse-amplitude modulation.

In one example, the system may include at least one memory die that may include a plurality of regions, each of which may include a plurality of banks of memory cells, one or more channels associated with each memory die, each channel comprising a memory cell die may be coupled to at least one region of , and each channel may include two or more data pins, and an organic substrate underlying the memory die.

In some examples, a system may include a host device and an interface configured to bidirectionally communicate with the host device, and the interface may support at least one or both of NRZ signaling or PAM4. In some examples of the system, the host device may include a GPU.

In some examples, the system may include a plurality of memory arrays, each including 128 or 256 data pins and configured at a ratio of 2, 4, or 8 data pins per channel. In some embodiments, the system may include a buffer layer positioned between the at least one memory die and the organic substrate.

The information and signals described herein may be represented using any of a variety of different technologies and techniques. For example, data, instructions, commands, information, signals, bits, symbols, and chips that may be referenced throughout the above description include voltages, currents, electromagnetic waves, magnetic fields or particles, optical fields or particles, or any combination thereof. can be expressed as Some figures may depict the signal as a single signal; It is understood by those of ordinary skill in the art that a signal may represent a bus of a signal, and that the bus may have various bit widths.

The term “virtual ground” as used herein refers to a node in an electrical circuit that is maintained at a voltage of approximately zero volts (0V) but is not directly connected to ground. Therefore, the voltage of the virtual ground may fluctuate temporarily and return to about 0V in the steady state. Virtual grounding can be implemented using various electronic circuit elements, such as voltage dividers made up of operational amplifiers and resistors. Other implementations are possible. By “virtual ground” or “virtually grounded” we mean connected to about 0V.

As used herein, the terms “electronic communication” and “coupled” refer to a relationship between components that support the flow of electrons between the components. This may include direct connections between components or may include intermediate components. In electronic communications or components coupled to each other may not actively exchange electrons or signals (eg, in an energized circuit) or not actively exchange electrons or signals (eg, in a non-energized circuit). However, the circuit may be configured and operable to exchange electrons or signals when the circuit is energized. For example, two components physically connected through a switch (eg, a transistor) may be coupled regardless of whether they are in electronic communication or the state of the switch (ie, open or closed).

As used herein, the term “layer” refers to a layer or sheet of geometric structures. Each layer may have three dimensions (eg, height, width, depth) and may cover some or all of the surface. For example, the layer may be a three-dimensional structure, for example a thin film, in the form of two dimensions greater than the third dimension. A layer may include different elements, components and/or materials. In some cases, one layer may consist of two or more sub-layers. In some of the accompanying drawings, two dimensions of the three-dimensional layer are shown for purposes of illustration. However, one of ordinary skill in the art will recognize that the layers are three-dimensional in nature.

As used herein, the term “electrode” may refer to an electrical conductor and, in some cases, may be used as an electrical contact with a memory cell or other component of a memory array. Electrodes may include traces, wires, conductive lines, conductive layers, etc. that provide conductive paths between elements or components of the memory array.

The term “isolated” refers to a relationship between components through which electrons cannot currently flow; Components are insulated from each other if there is an open circuit between them. For example, two components physically connected by a switch can be isolated from each other when the switch is opened.

Devices discussed herein, including memory arrays, may be formed on semiconductor substrates such as silicon, germanium, silicon-germanium alloys, gallium arsenide, gallium nitride, and the like. In some cases, the substrate is a semiconductor wafer. In other cases, the substrate is a silicon-on-insulator (SOI) substrate, such as silicon-on-glass (SOG) or silicon-on-sapphire (SOI). -sapphire: SOP), or an epitaxial layer of semiconductor material on another substrate. In some examples, the substrate may be an organic build-up substrate formed of a material such as ABF or BT. The conductivity of the substrate or sub-regions of the substrate may be controlled through doping using various species including, but not limited to, phosphorus, boron or arsenic. Doping may be performed during initial formation or growth of the substrate, by ion implantation, or by any other doping means.

A transistor or transistors discussed herein may refer to a field effect transistor (FET) and may include a three terminal device including a source, a drain, and a gate. The terminals may be connected to other electronic components via a conductive material, for example a metal. The source and drain may be conductive and may include heavily doped, eg, degenerate, semiconductor regions. The source and drain may be separated by a lightly doped semiconductor region or channel. When the channel is n-type (ie, the majority of carriers are electrons), the FET may be referred to as an n-type FET. When the channel is p-type (ie, the majority of carriers are holes), the FET may be referred to as a p-type FET. The channel may be capped by an insulating gate oxide. The channel conductivity can be controlled by applying a voltage to the gate. For example, a channel can become conductive when a positive or negative voltage is applied to an n-type FET or a p-type FET, respectively. A transistor may be "on" or "activated" when a voltage above the threshold voltage of the transistor is applied to the transistor gate. A transistor may be "off" or "deactivated" when a voltage lower than the threshold voltage of the transistor is applied to the transistor gate.

The description presented herein in connection with the appended drawings describes exemplary configurations and does not represent all examples that may be implemented or are within the scope of the claims. As used herein, the term "exemplary" means "serving as an example, instance, or illustration," and is not meant to indicate "preferred" or "advantageous over other examples." The detailed description includes specific details for providing an understanding of the described techniques. However, these techniques may be practiced without these specific details. In some instances, well-known structures and devices are shown in block diagram form in order to avoid obscuring the concepts of the described examples.

In the accompanying drawings, similar components or features may have the same reference label. Furthermore, various components of the same type can be distinguished by following a reference label with a dash and a second label to distinguish similar components. Where only the first reference label is used herein, the description may apply to any of the similar components having the same first reference label irrespective of the second reference label.

The information and signals described herein may be represented using any of a variety of different technologies and techniques. For example, data, instructions, commands, information, signals, bits, symbols, and chips that may be referenced throughout the above description include voltages, currents, electromagnetic waves, magnetic fields or particles, optical fields or particles, or any combination thereof. can be expressed as

The various illustrative blocks and modules described in connection with the present invention may be general-purpose processors, DSPs, ASICs, FPGAs or other programmable logic devices, discrete gate or transistor logic, discrete hardware components, or configured to perform the functions described herein. It can be implemented or carried out in any combination of these designed. A general purpose processor may be a microprocessor, but in the alternative, the processor may be any processor, controller, microcontroller, or state machine. A processor may also be implemented as a combination of computing devices (eg, a combination of a DSP and a microprocessor, multiple microprocessors, one or more microprocessors in association with a DSP core, or any other such configuration).

The functions described herein may be implemented in hardware, software executed by a processor, firmware, or any combination thereof. If implemented in software executed by a processor, the functions may be stored on or transmitted over as one or more instructions or code on a computer-readable medium. Other examples and implementations are within the scope of the invention and the appended claims. For example, due to the nature of software, the functions described above may be implemented using software executed by a processor, hardware, firmware, hardwired, or any combination thereof. Features implementing the functionality may also be physically located in various locations, including distributed such that portions of the functionality are implemented in different physical locations. Also, the term "or" as used in a list of items (e.g., a list of items beginning with a phrase such as "at least one" or "one or more") used herein, including in the claims, means, for example, At least one item of A, B or C represents an inclusive item meaning A or B or C or AB or AC or BC or ABC (ie, A and B and C). Also, as used herein, the phrase “based on” should not be construed as referring to a closed set of conditions. For example, exemplary steps described as “based on condition A” may be based on condition A and condition B without departing from the scope of the present invention. In other words, the phrase “based on” as used herein should be interpreted in the same way as the phrase “based at least in part on”.

Computer-readable media includes both non-transitory computer storage media and communication media including any medium that facilitates transfer of a computer program from one place to another. A non-transitory storage medium may be any available medium that can be accessed by a general purpose or special purpose computer. By way of example, and not limitation, non-transitory computer readable media include RAM, ROM, electrically erasable programmable read only memory (EEPROM), compact disk (CD) ROM or other optical disk storage device, magnetic disk storage device. or any other magnetic storage device, or any other non-transitory, means that can be used to carry or store the desired program code means in the form of instructions or data structures and that can be accessed by a general purpose or special purpose computer or general purpose or special purpose processor. media may be included. Also, any connection is properly termed a computer-readable medium. For example, if the Software uses a coaxial cable, fiber optic cable, twisted pair, Digital Subscriber Line (DSL), or wireless technology such as infrared, radio, and microwave, a website, server, or other remote When transmitted from a source, the definition of a medium includes coaxial cable, fiber optic cable, twisted pair, digital subscriber line (DSL), or wireless technologies such as infrared, radio and microwave. As used herein, disk and disk include CD, laser disk, optical disk, digital versatile disk (DVD), floppy disk, and Blu-ray disk, where disk is In general, data is reproduced magnetically, whereas a disc refers to data reproduced optically with a laser. Combinations of the above are also included within the scope of computer-readable media.

The description herein is provided to enable any person skilled in the art to make or use the present invention. Various modifications to the present invention will be apparent to those skilled in the art, and the generic principles defined herein may be applied to other modifications without departing from the scope of the invention. Accordingly, the present invention is not to be limited to the examples and designs described herein, but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims (20)

A memory device comprising:
a plurality of stacked layers each comprising a respective memory die;
an array of memory cells of a layer of memory die of said plurality of stacked layers, said array of memory cells having a plurality of regions each comprising a plurality of banks of memory cells, a first region of said plurality of regions comprising a first set of banks and a second set of banks the memory cell array comprising a bank of ;
an input/output (I/O) region of the array partitioning the first region, wherein the first set of banks is located on a first side of the I/O region and the second set of banks comprises the I/O region. an input/output (I/O) region located on a second side of the O region; and
a plurality of channels traversing the memory cell array, the plurality of channels positioned on the second side of the I/O region and the first set of banks positioned on the first side of the I/O region and at least one channel coupled to all of said second set of banks and said set of channels, said set of channels being in said I/O region, said at least one channel being a separate layer of said plurality of stacked layers. and a plurality of sets of pins with each set associated therewith, the set of channels comprising the plurality of channels configured to communicate a signal between the first region and a host device. The method according to claim 1,
and the I/O region occupies an area of the array devoid of memory cells. 3. The method according to claim 2,
and the I/O region comprises a through-silicon via (TSV) configured to couple the memory cell array with a power node or a ground node. The method according to claim 1,
and a plurality of channel interfaces distributed over the array of memory cells. 5. The method according to claim 4,
wherein the plurality of channel interfaces includes a bump-out terminal. 6. The method of claim 5,
and a channel interface of the plurality of channel interfaces is located in each quadrant of the memory cell array. 5. The method according to claim 4,
further comprising a plurality of signal paths extending between the memory cells of the region and a channel interface associated with the region, wherein the channel interface is configured to be connected to the array of memory cells such that the channel interface minimizes the length of the plurality of signal paths. A memory device in which it is located. The method according to claim 1,
a second memory cell array in a second layer of said plurality of stacked layers, said second memory cell array having a region each comprising a plurality of memory cell banks; and
a second plurality of channels traversing the second memory cell array, each channel of the second plurality of channels coupled with a second region of the second memory cell array, the plurality of memory cells of the second region and the second plurality of channels configured to communicate signals between a bank and the host device. The method according to claim 1,
wherein each set of pins includes at least one data pin and at least one command/address pin. 10. The method of claim 9,
at least one pin of the host device is coupled with a corresponding pin of the array and a second array. A memory device comprising:
a plurality of stacked layers each comprising a respective memory die;
A memory die of a layer of the plurality of stacked layers comprising an array of memory cells having a plurality of zones each comprising a plurality of banks of memory cells, wherein a first zone of the plurality of zones comprises a first set of banks and the memory die comprising a second set of banks;
an input/output (I/O) region extending across the memory cell array, the I/O region partitioning the first region and positioned between the first set of banks and the second set of banks an input/output (I/O) region comprising a first I/O region; and
a plurality of channels located in the I/O region of the memory cell array, the plurality of channels comprising: the first set of banks and the second in the first region divided by the first I/O region at least one channel coupled to all of the banks of the set and in the first I/O region, the set of channels comprising: the at least one channel being each with a separate layer of the plurality of stacked layers; and a set of pins comprising a plurality of sets of associated pins, the set of channels comprising the plurality of channels configured to communicate a signal between the first region and a host device. 12. The method of claim 11,
and a plurality of channel interfaces located in the I/O region of the memory cell array, wherein a signal path couples the region with the plurality of channel interfaces. 13. The method of claim 12,
wherein the I/O region comprises a through-silicon via (TSV) configured to couple a second memory cell array stacked over the memory cell array with a channel interface. 13. The method of claim 12,
and a channel interface of the first region is located within the I/O region, the I/O region bisecting the first region served by the channel interface. 12. The method of claim 11,
and the I/O region comprises a through silicon via (TSV) configured to couple the memory cell array with a power node or a ground node. 12. The method of claim 11,
and the I/O region occupies an area of the memory cell array devoid of memory cells. 12. The method of claim 11,
wherein the memory cell array is bisected by two I/O regions or four I/O regions. As a system,
host device;
a memory device comprising a plurality of stacked layers each including a respective memory die;
A memory die of a layer of the plurality of stacked layers having a plurality of zones each comprising a plurality of banks of memory cells, wherein a first zone of the plurality of zones comprises a first set of banks and a second set of banks. said memory die comprising;
an input/output (I/O) region of the memory die dividing the first region and between the first set of banks and the second set of banks; and
a plurality of channels configured to communicatively couple the host device and the memory device, the plurality of channels comprising: the first set of banks and the second set of the first region divided by the I/O region at least one channel coupled to all of the banks of and also in the I/O region, comprising a set of channels, wherein the at least one channel comprises a separate layer and each set of the plurality of stacked layers. and an associated plurality of sets of pins, the set of channels comprising the plurality of channels configured to communicate signals between the first zone and the host device. 19. The method of claim 18,
and an interface configured to bidirectionally communicate with the host device, wherein the interface includes a Non-Return to Zero (NRZ) modulation scheme or a four-symbol pulse-amplitude modulation scheme. : A system configured to communicate the modulated signal using at least one or both of: PAM4) schemes. 19. The method of claim 18,
wherein the host device includes a graphics processing unit (GPU) and the memory device is located in the same package as the host device.

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