KR102430388B1 - Diplay device and display panel - Google Patents

Abstract

Embodiments of the present invention relate to a display device and a display panel, and more particularly, to a display panel in which data lines and gate lines intersect each other, a data driving circuit driving the data lines, and a gate line driving system. a gate driving circuit, wherein the gate driving circuit and the data driving circuit are located or connected to a non-active region positioned at one side of the active region of the display panel, and electrically connect the gate line and the gate driving circuit to the display panel By further disposing a redirect gate line and disposing the redirect gate line in a direction different from the direction of the gate line, the size of a specific bezel area (eg, left and right bezel areas) can be reduced or almost eliminated.

Description

Display device and display panel {DIPLAY DEVICE AND DISPLAY PANEL}

The present invention relates to a display device and a display panel.

As the information society develops, the demand for a display device for displaying an image is increasing in various forms, and in recent years, various display devices such as a liquid crystal display device, a plasma display device, and an organic light emitting display device are utilized.

Such a display device may include a display panel in which data lines and gate lines are disposed, a data driving circuit driving the data lines, a gate driving circuit driving the gate lines, and the like.

The display panel may include an active area on which an image is displayed and a non-active area (also referred to as a bezel area) that is an outer area. In the active region of the display panel, data lines and gate lines may be disposed to cross each other.

Considering the arrangement directions of data lines and gate lines in the display panel, the data driving circuit is connected or bonded to the non-active region positioned in the longitudinal direction of the data line, and the gate driving circuit is positioned in the longitudinal direction of the gate line. It can be connected, bonded or mounted to the non-active area.

The non-active region to which the data driving circuit is connected or bonded and the non-active region to which the gate driving circuit is connected, bonded, or mounted may exist in different directions with respect to the active region.

For example, the non-active region to which the data driving circuit is connected or bonded exists in a downward direction of the active region, and the non-active region to which the gate driving circuit is connected, bonded, or mounted is in a left or right or left and right direction of the active region. may exist in

As described above, there has been a problem in that the bezel areas in various directions of the display panel are inevitably enlarged.

Against this background, an object of the embodiments of the present invention is to provide a display device and a display panel having a small or almost no bezel.

Another object of the embodiments of the present invention is to electrically connect or mount the data driving circuit and the gate driving circuit in the non-active region in the same direction with respect to the active region, so that the bezel region in a specific direction (eg, the left and right bezel regions) ) to provide a display device and a display panel that can significantly reduce the size of the display.

Another object of the embodiments of the present invention is to electrically connect a data driving circuit and a gate driving circuit to a non-active region in the same direction with respect to the active region by using a spin-on glass insulating film having a high heat resistance insulating film characteristic. It is to provide a display device and a display panel that enable to be mounted or mounted.

Another object of the embodiments of the present invention is to significantly reduce the size of other non-active regions by mounting the gate-in-panel type gate driving circuit together in the non-active region to which the data driving circuit is connected or bonded. An object of the present invention is to provide a display device and a display panel.

Another object of the embodiments of the present invention is to mount the chip-on-glass type or chip-on-film-type gate driving circuit together in the non-active region to which the data driving circuit is connected or bonded, thereby increasing the size of other non-active regions. It is to provide a display device and a display panel that can greatly reduce the

In one aspect, embodiments of the present invention provide a display device including a display panel in which a data line and a gate line intersect each other, a data driving circuit driving the data line, and a gate driving circuit driving the gate line. can provide

The gate driving circuit and the data driving circuit may be located in or connected to a non-active region positioned at one side of the active region of the display panel.

A redirect gate line may be further disposed on the display panel to electrically connect the gate line and the gate driving circuit.

The redirect gate line may be disposed in a direction different from the direction of the gate line.

The redirect gate line and the gate line may be connected in an active region of the display panel.

The gate line may be positioned on the spin-on-glass insulating layer, and the redirect gate line may be positioned under the spin-on-glass insulating layer. The gate line may be connected to the redirect gate line through a contact hole of the spin-on glass insulating layer.

The spin-on-glass insulating layer may be a planarization high heat-resistance insulating layer.

In the non-active region of the display panel, all or a part of the gate driving circuit electrically connected to the redirect gate line may overlap a region in which a data line extends or a data link line electrically connected to the data line is disposed.

A spin-on glass insulating layer may be positioned between the gate driving circuit and the data link line.

The data driving circuit may be electrically connected to a source-drain material present on the spin-on-glass insulating layer. The data link line may include a first gate material under the spin-on glass insulating layer. The source-drain material electrically connected to the data driving circuit may be electrically connected to the data link line through a contact hole of the spin-on glass insulating layer.

The redirect gate line may include a first gate material that exists under the spin-on glass insulating layer. The gate driving circuit may include a second gate material and a source-drain material disposed on the spin-on glass insulating layer. The gate driving circuit may be connected to the redirect gate line through a contact hole of the spin-on glass insulating layer.

The data link line may be the same material as the redirect gate line.

The gate driving circuit electrically connected to the redirect gate line and overlapping a region in which the data link line is disposed in whole or in part may include a gate-in-panel type gate driving circuit.

Meanwhile, in the non-active region of the display panel, the redirect gate line may overlap a region in which a data line extends or a data link line electrically connected to the data line is disposed.

The data link line may be of a different material than the redirect gate line.

A spin-on glass insulating layer may be positioned between the data link line and the redirect gate line.

The data driving circuit may be electrically connected to a conductive material present on the spin-on-glass insulating layer. The data link line may be a source-drain material present on the spin-on glass insulating layer. The conductive material electrically connected to the data driving circuit may be electrically connected to the data link line through the conductive material.

The gate driving circuit may be electrically connected to a conductive material present on the spin-on-glass insulating layer. The redirect gate line is positioned under the spin-on glass insulating layer and may be a first gate material. The conductive material electrically connected to the gate driving circuit may be connected to the redirect gate line through a contact hole of the spin-on-glass insulating layer.

The gate driving circuit electrically connected to the redirect gate line overlapping the region where the data link line is disposed may include a chip-on-glass or chip-on-film gate driving circuit.

The gate driving circuit and the data driving circuit may be located or connected to a non-active region located at one side of the active region of the display panel, and the gate driving circuit may be located closer to or connected to the active region than the data driving circuit.

The gate driving circuit and the data driving circuit may be positioned or connected to a non-active region positioned at one side of the active region of the display panel, and the gate driving circuit and the data driving circuit may be positioned or connected to each other.

The gate driving circuit and the data driving circuit may be integrated to be positioned or connected to a non-active region positioned at one side of the active region of the display panel.

In another aspect, embodiments of the present invention provide a display panel including a data line disposed in a first direction to which a data signal is applied, and a gate line disposed in a second direction different from the first direction and applied with a gate signal. can provide

The display panel may further include a redirect gate line disposed in a direction different from the second direction (eg, the first direction), electrically connected to the gate line, and transmitting a gate signal to the gate line.

In the non-active region existing in the first direction with respect to the active region, the data signal may be applied to the data line and the gate signal may be applied to the redirect gate line.

The redirect gate line and the gate line may be connected in an active region of the display panel.

The redirect gate line may be disposed on the first gate material layer, the gate line may be disposed on the second gate material layer, and a spin-on glass insulating layer may be disposed between the first gate material layer and the second gate material layer.

In the non-active region of the display panel, a data line extending or a data link line electrically connected to the data line may exist, and the data link line may overlap a gate-in-panel type gate driving circuit.

The data link line may be made of the same material as the redirect gate line.

According to the embodiments of the present invention described above, it is possible to provide a display device and a display panel having a small or almost no bezel.

According to embodiments of the present invention, by electrically connecting or mounting the data driving circuit and the gate driving circuit in the non-active region in the same direction with respect to the active region, a bezel region in a specific direction (eg, left and right bezel regions) It is possible to provide a display device and a display panel capable of significantly reducing the size of the display device.

According to embodiments of the present invention, a data driving circuit and a gate driving circuit are electrically connected to or mounted in a non-active region in the same direction with respect to the active region by using a spin-on glass insulating film having a high heat resistance insulating film characteristic. It is possible to provide a display device and a display panel that enable this.

According to embodiments of the present invention, by mounting the gate-in-panel type gate driving circuit together in the non-active region to which the data driving circuit is connected or bonded, the size of other non-active regions can be greatly reduced. A device and a display panel may be provided.

According to embodiments of the present invention, by mounting the chip-on-glass type or chip-on-film-type gate driving circuit together in the non-active region to which the data driving circuit is connected or bonded, the size of other non-active regions is greatly reduced. It is possible to provide a display device and a display panel that can be greatly reduced.

1 is a schematic system configuration diagram of a display device according to embodiments of the present invention.
2 to 4 are plan views of display devices according to embodiments of the present invention.
5 is a plan view of a display device according to an exemplary embodiment of the present invention, and is a plan view of the display device having a structure for reducing left and right bezel areas.
6 is a diagram illustrating a data driving structure of a display device according to embodiments of the present invention.
7 is a diagram illustrating a gate driving structure of a display device according to example embodiments.
8 is a diagram illustrating a main stacking order of a display device according to embodiments of the present invention.
9 is a diagram illustrating a jumping structure between major metals in a display device according to embodiments of the present invention.
10 is a plan view illustrating a signal transmission structure for reducing the size of left and right bezel areas in a display device according to embodiments of the present invention.
11 and 12 are exemplary plan and cross-sectional views illustrating a jumping structure for connecting a gate line and a redirect gate line in an active region of a display panel according to embodiments of the present invention.
13 and 14 are other exemplary plan and cross-sectional views illustrating a jumping structure for connecting a gate line and a redirect gate line in an active region of a display panel according to embodiments of the present invention.
15 is an exemplary plan view for explaining a signal transmission structure for reducing the size of left and right bezel regions when a gate driving circuit is a gate-in-panel type in a display device according to embodiments of the present invention.
16 is a plan view of an overlapping region between a data link line and a gate-in-panel type gate driving circuit in a display device according to embodiments of the present invention.
17 and 18 are a plan view and a cross-sectional view illustrating a connection structure between a data link line and a data driving circuit in a display device according to embodiments of the present invention.
19 and 20 are a plan view and a cross-sectional view illustrating a connection structure between a redirect gate line and a gate driving circuit in a display device according to embodiments of the present invention.
21 is a plan view illustrating a connection structure between a data link line and a data driving circuit and a connection structure between a redirect gate line and a gate driving circuit in a display device according to example embodiments.
22 is an exemplary plan view for explaining a signal transmission structure for reducing the size of left and right bezel regions when a gate driving circuit is a glass-on-panel type or a chip-on-film type in a display device according to embodiments of the present disclosure; to be.
23 is a plan view of an overlapping area between a data link line and a redirect gate line in a display device according to example embodiments.
24 is a cross-sectional view illustrating a connection structure between a data link line and a data driving circuit in a display device according to example embodiments.
25 is a cross-sectional view illustrating a connection structure between a redirect gate line and a gate driving circuit in a display device according to example embodiments.
26 is a diagram illustrating a case in which signal wires are formed in a single layer in a non-active region in a display device according to embodiments of the present invention.
27 is a plan view and a cross-sectional view illustrating a case in which signal wires are formed in two layers in a non-active region in a display device according to embodiments of the present invention.
28 is a plan view and a cross-sectional view illustrating a case in which signal wires are formed in two layers in a non-active region in a display device according to embodiments of the present invention.

Hereinafter, some embodiments of the present invention will be described in detail with reference to exemplary drawings. In adding reference numerals to components of each drawing, the same components may have the same reference numerals as much as possible even though they are indicated in different drawings. In addition, in describing the present invention, when it is determined that a detailed description of a related known configuration or function may obscure the gist of the present invention, the detailed description may be omitted.

In addition, in describing the components of the present invention, terms such as first, second, A, B, (a), (b), etc. may be used. These terms are only for distinguishing the elements from other elements, and the essence, order, order, or number of the elements are not limited by the terms. When it is described that a component is “connected”, “coupled” or “connected” to another component, the component may be directly connected or connected to the other component, but other components may be interposed between each component. It should be understood that each component may be “interposed” or “connected,” “coupled,” or “connected” through another component.

1 is a schematic system configuration diagram of a display device according to embodiments of the present invention.

Referring to FIG. 1 , in the display device according to the present exemplary embodiment, a plurality of data lines DL and a plurality of gate lines GL are disposed, and a plurality of data lines DL and a plurality of gate lines GL are disposed. A display panel DISP in which a plurality of sub-pixels SP defined by is arranged, a data driving circuit DDC driving a plurality of data lines DL, and a gate driving a plurality of gate lines GL It includes a driving circuit GDC, a controller CTR controlling the data driving circuit DDC and the gate driving circuit GDC, and the like.

In the display panel DISP, the plurality of data lines DL and the plurality of gate lines GL may be disposed to cross each other.

Each of the plurality of data lines DL may be disposed in a first direction (eg, a row direction or a column direction), and each of the plurality of gate lines GL may be disposed in a second direction (eg, a column direction) that is different from the first direction. direction or row direction).

The controller CTR supplies various driving control signals DCS and GCS to the data driving circuit DDC and the gate driving circuit GDC to control the data driving circuit DDC and the gate driving circuit GDC.

The controller (CTR) starts scanning according to the timing implemented in each frame, and converts the input image data input from the outside to match the data signal format used by the data driving circuit (DDC) to convert the converted image data (Data) ) and control the data drive at an appropriate time according to the scan.

The above-described controller CTR includes, along with the input image data, various types including a vertical synchronization signal Vsync, a horizontal synchronization signal Hsync, an input data enable signal (DE), a clock signal CLK, and the like. Timing signals are received from the outside (eg host system).

The controller CTR controls the driving of the data driving circuit DDC and the gate driving circuit GDC, and various timings such as a vertical sync signal Vsync, a horizontal sync signal Hsync, an input DE signal, and a clock signal. The signal is received, and various driving control signals DCS and GCS are generated and output to the data driving circuit DDC and the gate driving circuit GDC.

The controller CTR may be a timing controller used in a typical display technology or a control device that further performs other control functions including the timing controller.

The data driving circuit DDC receives the image data Data from the controller CTR and supplies data voltages to the plurality of data lines DL to drive the plurality of data lines DL. Here, the data driving circuit DDC is also referred to as a source driving circuit.

The data driving circuit DDC may be implemented by including at least one source driver integrated circuit (SDIC).

Each source driver integrated circuit SDIC may include a shift register, a latch circuit, a digital to analog converter (DAC), an output buffer, and the like.

Each source driver integrated circuit (SDIC) is a tape carrier package (TCP: Tape Carrier Package, hereinafter referred to as TCP, tape automated bonding (TAB: Tape Automated Bonding) type) type or chip on film (COF: Chip On) type. Film (hereinafter referred to as COF) type, etc., may be connected to the display panel (DISP), and may be mounted on the display panel (DISP) as a chip on glass (COG: Chip On Glass, hereinafter referred to as COG) type, etc. In some cases, it may be integrated and disposed on the display panel DISP.

The gate driving circuit GDC sequentially supplies a gate signal of an on voltage or an off voltage to the plurality of gate lines GL under the control of the controller CTR. GL) sequentially. Here, the gate driving circuit GDC is also referred to as a scan driving circuit.

The gate driving circuit GDC may be implemented by including at least one gate driver integrated circuit (GDIC).

Each gate driving circuit integrated circuit GDIC may include a shift register, a level shifter, and the like.

Each gate driver integrated circuit GDIC may be connected to the display panel DISP as a TCP type or a COF type, and may be mounted on the display panel DISP as a COG type, etc. In some cases, the display panel ( DISP), or may be implemented as a gate in panel (GIP) type and directly disposed on the display panel DISP.

When a specific gate line is opened by the gate driving circuit GDC, the data driving circuit DDC converts the image data data received from the controller CTR into an analog data voltage to form a plurality of data lines DL. supplied with

The data driving circuit DDC may be located only on one side (eg, upper or lower side, or left or right side) of the display panel DISP, and in some cases, the display panel DISP according to the driving type, the panel design type, etc. ) may be located on both sides (eg, top and bottom, or left and right).

The gate driving circuit GDC may be located only on one side (eg, left or right, or upper or lower side) of the display panel DISP, and in some cases, depending on a driving type, a panel design method, etc., the display panel DISP ) may be located on both sides (eg, left and right, or upper and lower).

The display device according to the present embodiments may be an organic light emitting display device, a liquid crystal display device, a plasma display device, or the like.

Each sub-pixel SP in the display panel DISP of the display device may include at least one transistor and circuit elements such as a capacitor. The type and number of circuit elements constituting each sub-pixel SP may be variously determined according to a panel type, a provided function, a design method, and the like.

2 to 5 are plan views of display devices according to embodiments of the present invention.

2 to 5 , the display panel DISP has an active area A/A that is an area where an image is displayed, and a non-active area that is outside the active area A/A and does not display an image. (N/A).

The non-active area N/A, which is an image non-display area, is also referred to as a bezel area.

A plurality of sub-pixels SP defined by a plurality of data lines DL and a plurality of gate lines GL may be arranged in the active area A/A, which is an image display area.

In the non-active area N/A, various signal lines for driving the plurality of sub-pixels SP in the active area A/A are disposed, and a data driving circuit DDC and a gate driving circuit GDC are disposed. and the like may be electrically connected to the driving circuits.

Referring to FIG. 5 , when the active area A/A has a rectangular shape, the non-active area N/A is a left non-active area N/A-L located to the left of the active area A/A. ), a right non-active area N/A-R positioned to the right of the active area A/A, and an upper non-active area N/A-U positioned above the active area A/A; , a lower non-active area N/A-D positioned below the active area A/A.

The utilization method of each of these four non-active regions (N/A-L, N/A-R, N/A-U, N/A-D) is the type (type) or connection of each of the data driving circuit (DDC) and the gate driving circuit (GDC) It may vary depending on location, etc.

Meanwhile, in this specification, left, right, top, bottom, first direction, second direction, row direction, column direction, etc. are relative, and left and right may be upper (or lower) and lower (or upper). and the upper and lower sides may be left (or right) and right (or left).

The first direction is a direction of the data line DL and may be a column direction or a row direction. The second direction is different from the first direction, and may be a row direction or a column direction.

In some cases, at least one of the first direction and the second direction may be an oblique direction.

2 and 3 , the data driving circuit DDC may be electrically connected to the lower non-active regions N/A-D. The gate driving circuit GDC may be electrically connected to the right non-active region N/A-R.

According to the example of FIG. 2 , the data driving circuit DDC may be electrically connected to the lower non-active regions N/A-D in a TCP type or a COF type.

The data driving circuit DDC may include a data driving film DF and a source driver integrated circuit SDIC mounted thereon.

According to the example of FIG. 2 , the gate driving circuit GDC may be electrically connected to the right non-active region N/A-R in a TCP type or a COF type.

The gate driving circuit GDC may include a gate driving film GF and a gate driver integrated circuit GDIC mounted thereon.

As shown in FIG. 2 , in the display panel DISP, since the data driving circuit DDC is electrically connected to the lower non-active areas N/A-D in a COF type or a TCP type, a lower non-active area (N/A-D) requires a bonding region to which the data driving circuit DDC is connected in a COF type or a TCP type. Accordingly, the size of the lower non-active area N/A-D is inevitably increased.

In addition, as shown in FIG. 2 , in the display panel DISP, since the gate driving circuit GDC is electrically connected to the right non-active region N/A-R in a COF type or a TCP type, the right non- The active region N/A-R requires a bonding region to which the gate driving circuit GDC is connected in a COF type or a TCP type. Accordingly, the size of the right non-active area N/A-R is inevitably increased.

According to the example of FIG. 3 , the data driving circuit DDC may be electrically connected to a bonding area (also referred to as a pad part) in the lower non-active area N/A-D in a COG type or the like. The gate driving circuit GDC may be electrically connected to a bonding area (also referred to as a pad part) in the right non-active area N/A-R in a COG type or the like.

As shown in FIG. 3 , in the display panel DISP, since the data driving circuit DDC is electrically connected to the lower non-active area N/A-D in a COG type, the lower non-active area N/ A-D) requires a bonding region to which the data driving circuit DDC is connected in a COG type. Accordingly, the size of the lower non-active area N/A-D is inevitably increased.

Also, as shown in FIG. 3 , in the display panel DISP, since the gate driving circuit GDC is electrically connected to the right non-active region N/A-R in a COG type, the right non-active region ( N/A-R) requires a bonding region to which the gate driving circuit GDC is connected in a COG type. Accordingly, the size of the right non-active area N/A-R is inevitably increased.

According to the example of FIG. 4 , the data driving circuit DDC may be electrically connected to a bonding area in the lower non-active area N/A-D in a COG type or the like. The gate driving circuit GDC may be implemented as a GIP type and may be electrically connected to a mounting area (also referred to as a pad part) in the left non-active area N/A-R.

As shown in FIG. 4 , in the display panel DISP, since the data driving circuit DDC is electrically connected to the lower non-active area N/A-D in a COG type, the lower non-active area N/ A-D) requires a bonding region to which the data driving circuit DDC is connected in a COG type. Accordingly, the size of the lower non-active area N/A-D is inevitably increased.

In addition, as shown in FIG. 4 , in the display panel DISP, since the gate driving circuit GDC is electrically connected to the left non-active region N/A-L in a COG type, the left non-active region ( N/A-L) requires a mounting region in which the gate driving circuit GDC is mounted in a GIP type. Accordingly, the size of the left non-active area N/A-L is inevitably increased.

2 to 4 , the non-active region N/A in which the data driving circuit DDC and the gate driving circuit GDC are in different directions with respect to the active region A/A Because it is connected or mounted on the display device, based on the image display screen (corresponding to the active area (A/A)) of the display device, the bezel area (eg, the lower bezel area) where the data driving circuit (DDC) is connected or mounted and the gate There is a disadvantage in that all of the bezel areas (eg, left and right bezel areas or left bezel areas or right bezel areas) to which the driving circuit GDC is connected or mounted become large.

5 is a plan view of a display device according to an exemplary embodiment of the present invention, and is a plan view of the display device having a structure for reducing left and right bezel areas.

Referring to FIG. 5 , in the display device according to the exemplary embodiment of the present invention, a non-active area (eg, a lower non-active area N/A-D) in the same direction with respect to the active area A/A) Since both the data driving circuit DDC and the gate driving circuit GDC are connected to or mounted on the device, the size of the bezel area (eg, the left and right bezel areas) can be greatly reduced.

Hereinafter, a case in which both the data driving circuit DDC and the gate driving circuit GDC are connected or mounted in the lower non-active regions N/A-D with respect to the active region A/A will be described as an example. However, the present invention is not limited thereto, and both the data driving circuit DDC and the gate driving circuit GDC may be connected or mounted in another non-active region such as the upper non-active region N/A-U.

Accordingly, since the gate driving circuit GDC does not need to be connected or mounted in the left non-active region N/A-L and the right non-active region N/A-R, the left non-active region N/A-L and the right non-active area (N/A-R) can be greatly reduced. Accordingly, the size (size) of the left and right bezel regions can be reduced to the limit.

Meanwhile, as shown in FIG. 5 , the lower non-active regions N/A-D to which both the data driving circuit DDC and the gate driving circuit GDC are connected or mounted are disposed in the active region A/A. It may include a link region in which the connected signal lines (data line, gate line) are extended or where the connected link lines are disposed, and a pad region in which a circuit such as a data driving circuit (DDC) is connected or mounted. can

Below, both the data driving circuit DDC and the gate driving circuit GDC are connected or mounted in the lower non-active region N/A-D with respect to the active region A/A to greatly reduce the left and right bezel areas. A possible signal transmission structure will be described in more detail.

6 is a diagram illustrating a data driving structure for reducing left and right bezel areas in a display device according to embodiments of the present invention, and FIG. 7 is a diagram illustrating a data driving structure for reducing left and right bezel areas in a display device according to embodiments It is a diagram showing a gate driving structure.

Referring to FIG. 6 , the data line DL disposed in the active area A/A of the display panel DISP extends or the data line DL disposed in the active area A/A of the display panel DISP. The data link line DLL electrically connected to the DL may be disposed in the lower non-active area N/A-D.

The data link line DLL may electrically connect the data line DL in the active area A/A and the data driving circuit DDC connected or mounted to the lower non-active area N/A-D. have. Here, the data driving circuit DDC may be implemented in various types such as a TCP type, a COF type, or a COG type.

Referring to FIG. 7 , the gate driving circuit GDC may be connected or mounted in the lower non-active regions N/A-D where the data link line DLL is disposed and the data driving circuit DDC is connected or mounted. have.

The gate driving circuit GDC may be implemented in various types such as a TCP type, a COF type, or a COG type.

That is, the gate driving circuit GDC and the data driving circuit DDC are non-active regions N/A positioned on one side (eg, the lower side) of the active region A/A of the display panel DISP. It may be located (mounted) or connected to the lower non-active areas N/A-D.

In this way, the gate driving circuit GDC, together with the data driving circuit DDC, is disposed in the longitudinal direction (first direction) of the data line DL with respect to the active area A/A of the display panel DISP. Although located (mounted) or connected to the lower non-active region N/A-D, which is the located non-active region N/A, the gate line GL to be connected to the gate driving circuit GDC is a data line It is disposed in a second direction (eg, row direction) different from the first direction (eg, column direction) that is the longitudinal direction of (DL).

Accordingly, an additional signal line is required to electrically connect the gate driving circuit GDC not positioned in the longitudinal direction of the gate line GL to the gate line GL. This additional signal line is called a redirect gate line (RGL).

Referring to FIG. 7 , the redirect gate line RGL may be disposed in a direction different from the longitudinal direction (eg, row direction) of the gate line GL, and may be disposed in a longitudinal direction (eg, column direction) of the data line DL. may be disposed in a first direction (eg, a column direction).

The redirect gate line RGL connects the gate line GL disposed in the second direction (eg, the row direction) and the gate driving circuit GDC disposed in the lower direction in the active area A/A. In the present specification, the first direction (eg, the column direction) may be a direction corresponding to the lower direction or the upper direction. The second direction (eg, a row direction) may be a direction corresponding to a left direction or a right direction.

Accordingly, the gate signal output from the gate driving circuit GDC may be transmitted in the first direction along the redirect gate line RGL and then transmitted in the second direction along the gate line GL. That is, the redirect gate line RGL may serve to change the transfer direction of the gate signal.

As described above, the size of the left and right bezel regions can be significantly reduced through the arrangement position of the gate driving circuit GDC and the additional configuration of the redirect gate line RGL.

Meanwhile, referring to FIG. 7 , the redirect gate line RGL and the gate line GL may be connected through a contact hole or the like in the active area A/A of the display panel DISP.

As described above, since the redirect gate line RGL and the gate line GL are connected in the active area A/A of the display panel DISP, the redirect gate line RGL and the gate line GL Since the extended structure does not need to exist in the left and right bezel areas, the size of the left and right bezel areas can be further reduced.

Hereinafter, a structure for reducing the size of the left and right bezel regions briefly described above will be described in more detail below.

8 is a diagram illustrating a main stacking order of a display device according to embodiments of the present invention.

Referring to FIG. 8 , in the display panel DISP of the display device according to the embodiments of the present invention, several main conductive materials (eg, Metal 1, Metal 2, Metal 3) are provided to form various electrodes or signal lines. , ITO, etc.) can be used limitedly.

The main conductive material may include, for example, a gate material (GATE 1, GATE 2), a source-drain material (S/D), and a transparent electrode material such as indium tin oxide (ITO).

The first gate material GATE 1 may be classified as a first metal Metal 1 and may be used for the redirect gate line RGL in the active region A/A or the non-active region N/A. have.

Alternatively, the first gate material GATE 1 may be used as a data link line DLL in the non-active region N/A.

The second gate material GATE 2 may be classified as a second metal 2 , and a signal line such as a gate line GL in the active region A/A, and an active region A/A or It may be used as a gate electrode of a transistor in the non-active region N/A. Here, the second gate material GATE 2 may be the same material as the first gate material GATE 1 or a different material.

The source-drain material S/D may be classified as a third metal Metal 3, and the data line DL in the active area A/A and/or the non-active area N/A, etc. It can be used for a signal line of , and a source or drain electrode of a transistor in the active region A/A.

Alternatively, the source-drain material S/D may be used as a source or drain electrode of the transistor in the non-active region N/A. For example, the source-drain material S/D may be used as source and drain electrodes of a transistor constituting the GIP-type gate driving circuit GDC in the non-active region N/A.

In addition to the first, second, and third metals corresponding to the first gate material GATE 1, the second gate material GATE 2, and the source-drain material S/D, the second 4 Metals and the like may also be present.

In addition, a transparent electrode material such as ITO (Indium Tin Oxide) may be used as a common electrode, etc. can

On the other hand, for electrical separation between the aforementioned main conductive materials (eg, Metal 1, Metal 2, Metal 3, ITO, etc.), a layer made of a main conductive material (eg, Metal 1, Metal 2, Metal 3, ITO, etc.) An insulating layer may exist between (Layer). Such an insulating film may serve as a planarization film.

In particular, between the first gate material GATE 1 corresponding to the first metal and the source-drain material S/D corresponding to the third metal, a spin on glass (SOG: Spin On Glass, hereinafter referred to as SOG) material An SOG insulating layer SOG_INS made of may be positioned.

More specifically, it exists between the first gate material layer made of the first gate material GATE 1 corresponding to the first metal and the second gate material layer made of the second gate material GATE 2 corresponding to the second metal. In the insulating layer, an SOG insulating layer SOG_INS made of a spin-on glass material may be positioned.

The SOG insulating film (SOG_INS) is applied by a spin coating method, which is a siloxane-based compound, a silozne-based compound and a silicate-based compound, and a silsesquioxane-based compound. It may include one or more compounds among the compounds.

The SOG insulating film SOG_INS has an advantage of maintaining insulating properties even in a high-temperature process in addition to the advantage of realizing a flat insulating film through a simple coating method.

9 is a diagram illustrating a jumping structure between major metals GATE 1 and S/D in a display device according to embodiments of the present invention.

The first gate material GATE 1 and the source-drain material S/D may be separated (insulated) by the SOG insulating layer SOG_INS, and may be connected through a contact hole of the SOG insulating layer SOG_INS.

This jumping structure will be described in more detail.

A first gate material GATE 1 that may be used as a data link line DLL or a redirect gate line RGL is disposed on the substrate SUB.

The first insulating layer INS1 may be disposed on the substrate SUB while exposing the first gate material GATE 1 . Here, the first insulating layer INS1 may be made of silicon nitride (SiNx) or the like.

A SOG insulating layer SOG_INS may be disposed on the first insulating layer INS1 .

A second insulating layer INS2 may be disposed on the SOG insulating layer SOG_INS.

A source-drain material S/D may be disposed on the second insulating layer INS2 .

The source-drain material S/D may contact the first gate material GATE 1 through a contact hole of the second insulating layer INS2 and the SOG insulating layer SOG_INS.

A third insulating layer INS3 may be disposed on the source-drain material S/D and the second insulating layer INS2 .

A planarization layer PAC may be disposed on the third insulating layer INS3 .

A fourth insulating layer INS4 may be disposed on the planarization layer PAC.

The jumping structure of FIG. 9 electrically connects the redirect gate line RGL made of the first gate material GATE 1 and the source-drain material S/D constituting the GIP-type gate driving circuit GDC. can be used to

In addition, in the jumping structure of FIG. 9 , the data link line DLL made of the first gate material GATE 1 and the bump of the data driving circuit DDC are connected to the source-drain material S/D through ITO or the like. ) can be used to electrically connect

Meanwhile, as described above, the redirect gate line RGL is positioned on the first gate material layer made of the first gate material GATE 1 , and the gate line GL is the first gate material layer made of the second gate material GATE 2 . 2 may be located on the gate material layer.

In addition, an SOG insulating layer SOG_INS may be positioned between the first gate material layer and the second gate material layer.

Under a structure in which one redirect gate line RGL overlaps a plurality of gate lines GL, each of the redirect gate line RGL and the gate line GL is formed on a different layer and separated by an SOG insulating layer SOG_INS. , in the active area A/A of the display panel DISP, one redirect gate line RGL is not connected to a plurality of gate lines GL that are not to be connected, and is a gate line ( GL) can be connected correctly.

Meanwhile, the above-mentioned SOG insulating layer SOG_INS may be a planarization high heat resistance insulating layer.

That is, by using the SOG insulating layer SOG_INS, it is possible to make an insulating layer having excellent insulating properties even in a high-temperature process and having a planarization function. Through this, it is possible to configure, connect, or mount both the data driving circuit DDC and the gate driving circuit GDC in the non-active region N/A in the same direction with respect to the active region A/A. can make you

10 is a plan view illustrating a signal transmission structure for reducing the size of left and right bezel areas in a display device according to embodiments of the present invention.

Referring to FIG. 10 , the display panel DISP includes a data line DL disposed in a first direction and to which a data signal is applied, and a gate line GL disposed in a second direction different from the first direction and applied with a gate signal. ) may be included.

In addition, the display panel DISP is disposed in the first direction, is electrically connected to the gate line GL in the active region A/A, and is a redirect gate line GL that transmits a gate signal to the gate line GL. RGL) may be further included.

The redirect gate line RGL may be disposed in a direction different from the direction of the gate line GL, and may be disposed in the same direction as the direction of the data line DL.

The redirect gate line RGL may electrically connect the gate line GL and the gate driving circuit GDC.

In the non-active region N/A-D existing in the first direction with respect to the active region A/A, a data signal is applied to the data line DL, and a gate signal is applied to the redirect gate line RGL. can be

That is, in the non-active area N/A-D existing in the first direction with respect to the active area A/A, the data signal and the gate signal may vertically overlap.

11 and 12 are plan views illustrating a jumping structure for connecting the gate line GL and the redirect gate line RGL in the active area A/A of the display panel DISP according to embodiments of the present disclosure; and a cross-sectional view, and FIGS. 13 and 14 are the connection between the gate line GL and the redirect gate line RGL in the active area A/A of the display panel DISP according to embodiments of the present invention. It is another exemplary drawing of a plan view and a cross-sectional view showing a jumping structure for However, in FIGS. 11 and 13 , pixel structures such as transistors and pixel electrodes are omitted.

11 and 13 , in the region where the data line DL and the gate line GL intersect in the active region A/A, the gate line GL is to be connected to the redirect gate line RGL. can

A jumping connection structure of the gate line GL and the redirect gate line RGL will be described with reference to cross-sectional views X-X' of FIGS. 12 and 14 .

A redirect gate line RGL is positioned on the substrate SUB.

An insulating layer INS is positioned on the substrate SUB while exposing the redirect gate line RGL.

A SOG insulating layer SOG_INS is positioned on the insulating layer INS.

A gate line GL is disposed on the SOG insulating layer SOG_INS, and the gate line GL is connected to the redirect gate line RGL through a contact hole between the SOG insulating layer SOG_INS and the insulating layer INS.

A gate insulating layer GI is positioned on the gate line GL.

A data line DL is positioned on the gate insulating layer GI.

A jumping contact point between the gate line GL and the redirect gate line RGL may be located on the gate line GL as shown in FIG. 11, or as shown in FIG. 13, the gate line ( GL).

As described above, the gate line GL is positioned on the SOG insulating film SOG_INS, the redirect gate line RGL is positioned under the SOG insulating film SOG_INS, and the gate line GL is a contact of the SOG insulating film SOG_INS. By being connected to the redirect gate line RGL through a hole, in the active area A/A of the display panel DISP, the can

Meanwhile, the gate driving circuit GDC and the data driving circuit DDC are disposed in the lower non-active region N/A-D located on one side (lower side) of the active region A/A of the display panel DISP. may be located or connected.

The gate driving circuit GDC may be located closer to or connected to the active region A/A than the data driving circuit DDC.

This arrangement structure may be useful when the gate driving circuit GDC is a GIP type.

Meanwhile, the gate driving circuit GDC and the data driving circuit DDC may be positioned side by side or may be connected.

This arrangement structure may be useful when the gate driving circuit GDC is of the same type as the data driving circuit DDC (eg, a COG type, a COF type, or a TCP type).

Meanwhile, the gate driving circuit GDC and the data driving circuit DDC are integrated to be located or connected to the non-active regions N/A-D located at one side of the active region A/A of the display panel DISP. can

As described above, when the gate driving circuit GDC and the data driving circuit DDC are integrated into one integrated circuit and implemented, it can be used for a small display, a mobile device, etc. as well as a general mid-to-large display.

15 is an exemplary plan view for explaining a signal transmission structure for reducing the size of left and right bezel regions when the gate driving circuit GDC is a gate-in-panel type in the display device according to embodiments of the present invention.

As described above, the lower non-active area N/A-D of the display panel DISP includes the data link line DL extending or connected to the data line DL disposed in the first direction in the active area A/A. DLL) and a link region in which the redirect gate line RGL disposed in the first direction extends in the active region A/A, and circuits such as the data driving circuit DDC and the gate driving circuit GDC are connected It may include a pad area to be (bonded) or mounted.

Referring to FIG. 15 , in the lower non-active area N/A-D of the display panel DISP, the pad area includes a GDC mounting area in which the GIP type gate driving circuit GDC is mounted, and a COF type or COG type. may include a DDC bonding region to which the data driving circuit DDC is bonded.

In the GDC mounting region, a plurality of GIP-type gate driving circuits GDC may be mounted. One GIP-type gate driving circuit GDC may be connected to one redirect gate line RGL.

One or more data driving circuits DDC of a COF type or a COG type may be bonded to the DDC bonding region.

The GDC mounting area may be located closer to the active area A/A than the DDC bonding area.

In FIG. 15 , one data line DL, one gate line GL, and one redirect gate line RGL are illustrated for convenience of explanation, but in reality, a fairly large number of data lines DL and gates are shown. A line GL and a redirect gate line RGL may be disposed.

Region A is a region where a plurality of data link lines DLL overlaps a plurality of GIP-type gate driving circuits GDC.

Region B is a region in which one data link line DLL is connected to a COF-type or COG-type data driving circuit DDC.

Region C is a region in which one redirect gate line RGL is connected to one GIP type gate driving circuit GDC.

As described above, the gate driving circuit GDC, which is electrically connected to the redirect gate line RGL and partially or entirely overlaps the region where the data link line DLL is disposed, is a GIP (Gate In Panel) type. gate driving circuit GDC.

As described above, since the gate driving circuit GDC is implemented as a GIP type and embedded in the display panel DISP to overlap the data link line DLL, the number of integrated circuit components required for the display device can be reduced. , the left and right bezel areas can be greatly reduced.

Hereinafter, regions A, B, and C will be described in more detail with reference to FIGS. 16 to 21 .

16 is a cross-sectional view of an overlapping region A between a data link line DLL and a gate-in-panel type gate driving circuit GDC in a display device according to example embodiments.

In the lower non-active area N/A-D of the display panel DISP, the GIP type gate driving circuit GDC electrically connected to the redirect gate line RGL; GIP #1, GIP #2, GIP #3 All or part of it may overlap a region in which the data link line DLL is disposed.

That is, in the lower non-active area N/A-D of the display panel DISP, the data line DL extends or the data link line DLL electrically connected to the data line DL exists, and the data link line (DLL) may overlap the GIP-type gate driving circuit GDC.

The data line DL may be made of a source-drain material S/D.

The data link line DLL may be a line from which the data line DL extends or is electrically connected to the data line DL.

The data link line DLL is positioned on the substrate SUB, and the insulating layer INS1 is positioned thereon.

A SOG insulating layer SOG-INS may be disposed on the insulating layer INS1 .

GIP-type gate driving circuits GDC (GIP #1, GIP #2, and GIP #3) may be mounted on the SOG insulating layer SOG-INS.

The data link line DLL may be a first gate material GATE 1 formed on a layer different from the source-drain material S/D corresponding to the data line DL.

As described above, since the SOG insulating layer SOG_INS is positioned between the GIP type gate driving circuits GDC (GIP #1, GIP #2, GIP #3) and the data link line DLL, even in a high-temperature process, the GIP type It may be formed by excellently insulating the gate driving circuit (GDC; GIP #1, GIP #2, GIP #3) of the data link line (DLL).

A GIP type gate driving circuit (GDC; GIP #1, GIP #2, GIP #3) includes a plurality of transistors (eg, a pull-up transistor, a pull-down transistor, a control transistor of a Q node, a control transistor of a QB node, etc.) can exist.

In FIG. 16 , GIP-type gate driving circuits (GDCs; GIP #1, GIP #2, and GIP #3) are a simplified representation of one of several transistors therein.

Referring to FIG. 16 , the transistors constituting the GIP type gate driving circuit (GDC; GIP #1, GIP #2, and GIP #3) include a source electrode S, a drain electrode D, and a gate electrode G. include

The source electrode (S) and the drain electrode (D) of the transistor may be a source-drain material (S/D).

The gate electrode G of the transistor may be the second gate material GATE 2 .

17 and 18 are plan views and cross-sectional views illustrating a connection structure between a data link line DLL and a data driving circuit DDC in a display device according to example embodiments.

17 and 18 , in the lower non-active area N/A-D of the display panel DISP, the data line DL extends or the data link line DLL is electrically connected to the data line DL. , and the data link line DLL may overlap the GIP type gate driving circuit GDC.

The data link line DLL may be electrically connected to the data line DL through the contact hole CNT-D1 .

The data line DL may be a source-drain material S/D.

The data link line DLL may be a first gate material GATE 1 formed on a layer different from the source-drain material S/D corresponding to the data line DL.

In region B for connection between the data link line DLL and the data driving circuit DDC,

A data link line DLL made of a first gate material GATE 1 is disposed on the substrate SUB, and an insulating layer INS1 is disposed thereon.

A SOG insulating film SOG-INS is disposed on the insulating film INS1 .

Another insulating layer INS2 may be disposed on the SOG insulating layer SOG-INS.

A source-drain material S/D is positioned on the other insulating layer INS2 .

The source-drain material S/D may be connected to the data link line DLL through the contact hole CNT-D2 of the insulating layers INN2 , SOG-INS, and INS1 .

A transparent electrode such as ITO may be disposed on the source-drain material S/D.

The data driving circuit DDC may be connected to a transparent electrode such as ITO through a conductive pattern such as a bump.

In other words, the data driving circuit DDC is electrically connected to the source-drain material S/D existing on the SOG insulating layer SOG_INS.

In addition, the data link line DLL may include the first gate material GATE 2 existing under the SOG insulating layer SOG_INS.

The source-drain material S/D electrically connected to the data driving circuit DDC may be electrically connected to the data link line DLL through the contact hole CNT-D2 of the SOG insulating layer SOG_INS.

Accordingly, the data driving circuit DDC may be connected to the lower non-active region N/A-D in which the gate driving circuit GDC is mounted.

19 and 20 are plan views and cross-sectional views illustrating a connection structure between a redirect gate line RGL and a gate driving circuit GDC in a display device according to example embodiments.

The redirect gate line RGL, which is the first gate material GATE 1 , is positioned on the substrate SUB.

An insulating layer INS1 is positioned on the redirect gate line RGL.

A SOG insulating layer SOG-INS is positioned on the insulating layer INS1 .

A GIP-type gate driving circuit (eg, GIP #1) may be mounted on the SOG insulating layer SOG-INS.

The drain electrode (D) or the source electrode (S) of the transistor constituting the gate driving circuit (GDC, eg, GIP #1) in the GIP block region is connected to the redirect gate line (RGL) through the contact hole (CNT-G1). can be connected with

The drain electrode D or the source electrode S of the transistor may be a source-drain material S/D.

In other words, the redirect gate line RGL may include the first gate material GATE 1 existing under the SOG insulating layer SOG_INS.

The gate driving circuit GDC may include a second gate material GATE 2 and a source-drain material S/D existing on the SOG insulating layer SOG_INS.

The second gate material GATE 2 corresponds to the gate electrode G of the transistor constituting the GIP type gate driving circuit GDC, and the source-drain material S/D is the GIP type gate driving circuit GDC. ) corresponds to the source electrode (S) and the drain electrode (D) of the transistor constituting the transistor.

The gate driving circuit GDC may be connected to the redirect gate line RGL through the contact hole CNT-G1 of the SOG insulating layer SOG_INS.

Accordingly, the gate driving circuit GDC may be mounted in the lower non-active region N/A-D to which the data driving circuit DDC is connected.

A connection structure between the data link line DLL and the data driving circuit DDC and a connection structure between the redirect gate line RGL and the gate driving circuit GDC in the display device according to the embodiments of the present invention are shown together. Same as 21.

17 to 20 and 21 , the data link line DLL may be made of a first gate material GATE 1 that is the same material as the redirect gate line RGL.

As described above, by forming the data link line DLL and the redirect gate line RGL of the same material, the gate driving circuit GDC and the data driving circuit DDC are formed in the same non-active region N/A-D. It enables to be mounted or connected, and through this, the size of the left and right bezel areas can be greatly reduced.

22 is an exemplary plan view for explaining a signal transmission structure for reducing the size of left and right bezel regions when the gate driving circuit GDC is a COG type or a COF type in a display device according to embodiments of the present disclosure; . However, in the description below, the same content as the above description will be omitted, and content with a difference will be mainly described.

As described above, the lower non-active area N/A-D of the display panel DISP includes the data link line DL extending or connected to the data line DL disposed in the first direction in the active area A/A. DLL) and a link region in which the redirect gate line RGL disposed in the first direction extends in the active region A/A, and circuits such as the data driving circuit DDC and the gate driving circuit GDC are connected It may include a pad area to be (bonded) or mounted.

Referring to FIG. 22 , in the lower non-active region N/A-D of the display panel DISP, the pad region includes a GDC bonding region to which a COF-type or COG-type gate driving circuit GDC is bonded, and a COF-type region. Alternatively, it may include a DDC bonding region to which the COG-type data driving circuit DDC is bonded.

A plurality of gate driving circuits GDC of a COF type or a COG type may be bonded or connected to the GDC bonding region. One gate driving circuit GDC of a COF type or a COG type may be connected to one redirect gate line RGL.

At least one data driving circuit DDC of a COF type or a COG type may be bonded or connected to the DDC bonding region.

The GDC bonding region and the DDC bonding region may be arranged side by side.

In FIG. 22 , one data line DL, one gate line GL, and one redirect gate line RGL are illustrated for convenience of explanation, but in reality, a fairly large number of data lines DL and gates are shown. A line GL and a redirect gate line RGL may be disposed.

Region D is a region where a plurality of data link lines DLL and a plurality of redirect gate lines RGL overlap.

Region E is a region in which one data link line DLL is connected to a COF-type or COG-type data driving circuit DDC.

Region F is a region in which one redirect gate line RGL is connected to one COF type or COG type gate driving circuit GDC.

The gate driving circuit GDC electrically connected to the redirect gate line RGL overlapping the region where the data link line DLL is disposed is a COG (Chip On Glass) type or COF (Chip On Film) type gate driving circuit. It may include a circuit GDC.

As described above, in the lower non-active area N/A-D of the display panel DISP, the redirect gate line RGL is disposed to overlap the area where the data link line DLL is disposed, so that the COG (Chip On) Glass) type, COF (Chip On Film) type, or TCP (Tape Carrier Package) type gate driving circuit (GDC) in non-active area (N/A-D) to which data driving circuit (DDC) is bonded or connected together It can be bonded or connected. Accordingly, the left and right bezel areas can be greatly reduced.

23 is a plan view of an overlapping region between a data link line DLL and a redirect gate line RGL in a display device according to example embodiments. 24 is a cross-sectional view illustrating a connection structure between a data link line DLL and a data driving circuit DDC in a display device according to example embodiments. 25 is a cross-sectional view illustrating a connection structure between a redirect gate line RGL and a gate driving circuit GDC in a display device according to example embodiments.

Referring to FIG. 23 , in region D, a plurality of data link lines DLL and a plurality of redirect gate lines RGL may overlap each other with an SOG insulating layer SOG_INS interposed therebetween.

Referring to FIG. 23 , when the gate driving circuit GDC is a COG type or a COF type, the data link line DLL may be made of a source-drain material S/D, and the redirect gate line RGL is The first gate material GATE 1 may be used.

That is, the data link line DLL may be made of a material different from that of the redirect gate line RGL.

According to the properties of these materials and layers, the gate driving circuit (GDC) and the data driving circuit (DDC) of the COG (Chip On Glass) type, the COF (Chip On Film) type, or the TCP (Tape Carrier Package) type are non-active. It can be connected or bonded to areas (N/A-D).

As described above, since the SOG insulating layer SOG_INS is positioned between the data link line DLL and the redirect gate line RGL, the same data link line DLL and the redirect gate line RGL are non-reactive in the high-temperature process. It can be formed to be effectively insulated from the active regions N/A-D.

Referring to FIG. 24 , in region E, one data link line DLL is connected to a source driver integrated circuit SDIC that is a COF type or a COG type data driving circuit DDC.

A SOG insulating layer SOG_INS is positioned on the insulating layer INS1 , and another insulating layer INS2 is positioned on the SOG insulating layer SOG_INS.

A data link line DLL is disposed on the other insulating layer INS2 .

Another insulating layer INS3 is disposed on the source-drain material S/D.

A conductive material (eg, ITO) is disposed on another insulating layer INS3 , and the conductive material (eg, ITO) is connected to the source-drain material S/D through a contact hole of another insulating layer INS3 . do.

The source driver integrated circuit SDIC, which is a COF type or COG type data driving circuit DDC, is electrically connected to a conductive material (eg, ITO) present on the insulating layer GI of the SOG insulating layer SOG_INS through bumps or the like. can be connected to

Accordingly, the source driver integrated circuit SDIC, which is a data driving circuit DDC such as a COF type, a COG type, or a TCP type, is connected to the data link line DLL through a conductive material (eg, ITO). Here, the data link line DLL may be a source-drain material S/D.

Referring to FIG. 25 , in region F, one redirect gate line RGL may be connected to a gate driver integrated circuit GDIC that is one gate driving circuit GDC such as a COF type, a COG type, or a TCP type.

The insulating layer INS1 may be disposed on the redirect gate line RGL, which may be the first gate material GATE 1 , and the SOG insulating layer SOG_INS may be disposed thereon.

Another insulating layer INS2 may be positioned on the SOG insulating layer SOG_INS.

A conductive material (eg, ITO) may be disposed on the other insulating layer INS2 , and the conductive material (eg, ITO) passes through a contact hole between the other insulating layer INS2 and the SOG insulating layer SOG_INS to form the redirect gate line RGL. ) can be associated with

The conductive material (eg, ITO) may be connected to the gate driver integrated circuit GDIC, which is one gate driving circuit GDC of the COF type or the COG type, through a bump or the like.

In other words, the gate driver integrated circuit GDIC, which is one COF-type or COG-type gate driving circuit GDC, is electrically connected to a conductive material (eg, ITO) present on the SOG insulating layer SOG_INS.

The redirect gate line RGL is positioned under the SOG insulating layer SOG_INS and is the existing first gate material GATE 1 .

A conductive material (eg, ITO) electrically connected to the gate driving circuit GDC may be connected to the redirect gate line RGL through a contact hole such as the SOG insulating layer SOG_INS.

Accordingly, in the non-active regions N/A-D to which the data driving circuit DDC is connected or bonded, one redirect gate line RGL connected to the gate line GL is of a COF type or a COG type or a TCP type. One gate driving circuit GDC may be connected to the gate driver integrated circuit GDIC.

26 is a diagram illustrating a case in which signal wires L1 , L2 , L3 , L4 , L5 , and L6 are formed in a single layer in a non-active region N/A-D in a display device according to embodiments of the present disclosure; 27 is a diagram in which signal lines L1, L2, L3, L4, L5, and L6 are formed in two layers in the non-active area N/A-D in the display device according to the embodiments of the present invention. It is a plan view and a cross-sectional view (Y-Y') showing one case. 28 illustrates a case in which signal lines L1 , L2 , L3 , L4 , L5 , and L6 are formed in two layers in the non-active region N/A-D in the display device according to the embodiments of the present invention. It is a plan view and a cross-sectional view (Z-Z') shown.

As described above, in the lower non-active area N/A-D of the display panel DISP, the data line DL disposed in the first direction in the active area A/A extends or is connected to the data link line ( DLL) and a link region in which the redirect gate line RGL disposed in the first direction extends in the active region A/A.

If the size (area) of the link region can be reduced, the size of the lower non-active region N/A-D in which the data driving circuit DDC and the gate driving circuit GDC are connected, bonded, or mounted can also be significantly reduced. .

The size (area) of the link area corresponds to the distance between the active area A/A and the pad area, and is referred to as a width of the link area below.

As shown in FIG. 26 , when six signal wirings L1 to L6 in the link area are disposed on the same layer, it is assumed that the width of the link area is W1.

As shown in FIG. 27 , when six signal wirings L1 to L6 in the link area are divided into two layers, the width of the link area may be reduced, and the value may be W2 smaller than W1. have.

Of the six signal lines L1 to L6, L2, L4, and L6 positioned in the lower layer and L1, L3, and L5 positioned in the upper layer are insulated by the SOG insulating layer SOG-INS.

A planarization layer PAC may be disposed on L1, L3, and L5 positioned on the upper layer.

As shown in FIG. 28 , when six signal wirings L1 to L6 in the link area are divided into three layers, the width of the link area can be further reduced, and the value of W3 is smaller than W2. can be

L3 and L6 positioned in the lowermost layer and L2 and L5 positioned in the middle layer are insulated by the first SOG insulating layer SOG-INS_1.

L2 and L5 positioned in the middle layer and L1 and L4 positioned in the uppermost layer are insulated by the second SOG insulating layer SOG-INS_2.

A planarization layer PAC may be disposed on the uppermost layers L1 and L4.

On the other hand, in the present specification, INS, INS1, INS2, INS3, GI, etc. are only for distinguishing from each other in the corresponding drawings, and are the same in that they are layers having an insulating function. INS, INS1, INS2, INS3, GI, etc. may be made of the same insulating material or may be made of different insulating materials.

According to the embodiments of the present invention described above, it is possible to provide a display device and a display panel DISP having a small or almost no bezel.

According to embodiments of the present invention, the data driving circuit DDC and the gate driving circuit GDC are electrically connected to the non-active region N/A in the same direction with respect to the active region A/A. or mounting, it is possible to provide a display device and a display panel DISP that can significantly reduce the size of the bezel area (eg, the left and right bezel areas) in a specific direction.

According to the embodiments of the present invention, the data driving circuit DDC and the gate driving circuit GDC are set based on the active region A/A by using the spin-on glass insulating film SOG_INS having a high heat resistance insulating film characteristic. It is possible to provide a display device and a display panel DISP that enable to be electrically connected or mounted to the non-active area N/A in the same direction.

According to embodiments of the present invention, by mounting the GIP-type gate driving circuit GDC in the non-active region N/A to which the data driving circuit DDC is connected or bonded, It is possible to provide a display device and a display panel DISP that can greatly reduce the size.

According to embodiments of the present invention, by mounting the gate driving circuit GDC of the COG type or the COF type in the non-active region N/A to which the data driving circuit DDC is connected or bonded, other non - It is possible to provide a display device and a display panel DISP that can greatly reduce the size of the active area N/A.

The above description and the accompanying drawings are merely illustrative of the technical spirit of the present invention, and those of ordinary skill in the art to which the present invention pertains can combine configurations within a range that does not depart from the essential characteristics of the present invention. , various modifications and variations such as separation, substitution and alteration will be possible. Therefore, the embodiments disclosed in the present invention are not intended to limit the technical spirit of the present invention, but to explain, and the scope of the technical spirit of the present invention is not limited by these embodiments. The protection scope of the present invention should be construed by the following claims, and all technical ideas within the equivalent range should be construed as being included in the scope of the present invention.

DDC: Data Drive Circuit
GDC: gate drive circuit
DISP: display panel
DL: data line
GL: gate line
RGL: redirect gate line
DLL: data link line
A/A: active area
N/A: non-active area
SOG_INS: Spin-on Glass Insulation Film
INS, INS1, INS2, INS3: insulating film

Claims (24)

a display panel in which data lines and gate lines cross each other;
a data driving circuit for driving the data line; and
a gate driving circuit for driving the gate line;
the gate driving circuit and the data driving circuit are located in or connected to a non-active region located at one side of an active region that is an image display region of the display panel;
A redirect gate line electrically connecting the gate line and the gate driving circuit is further disposed on the display panel;
The redirect gate line is disposed in a direction different from the direction of the gate line,
In the non-active region of the display panel, all or part of the gate driving circuit electrically connected to the redirect gate line overlaps with a region in which the data line extends or a data link line electrically connected to the data line is disposed. becomes,
A spin-on glass insulating layer is positioned between the gate driving circuit and the data link line.
According to claim 1,
The redirect gate line and the gate line are connected in an active region of the display panel.
According to claim 1,
the gate line is positioned on the spin-on glass insulating layer;
The redirect gate line is positioned under the spin-on glass insulating layer,
The gate line is connected to the redirect gate line through a contact hole of the spin-on glass insulating layer.
4. The method of claim 3,
The spin-on-glass insulating layer is a planarization high heat-resistance insulating layer.
delete delete According to claim 1,
the data driving circuit is electrically connected to a source-drain material present on the spin-on glass insulating layer;
the data link line includes a first gate material under the spin-on glass insulating layer;
A source-drain material electrically connected to the data driving circuit is electrically connected to the data link line through a contact hole of the spin-on-glass insulating layer.
According to claim 1,
the redirect gate line includes a first gate material present under the spin-on glass insulating layer;
the gate driving circuit includes a second gate material and a source-drain material present on the spin-on glass insulating layer;
The gate driving circuit is connected to the redirect gate line through a contact hole of the spin-on glass insulating layer.
According to claim 1,
The data link line is made of the same material as the redirect gate line.
According to claim 1,
and the gate driving circuit electrically connected to the redirect gate line and wholly or partially overlapping a region where the data link line is disposed includes a gate-in-panel type gate driving circuit.
According to claim 1,
In a non-active area of the display panel,
The redirect gate line is
A display device overlapping a region in which the data line extends or a data link line electrically connected to the data line is disposed.
12. The method of claim 11,
and the data link line is made of a material different from that of the redirect gate line.
12. The method of claim 11,
The spin-on-glass insulating layer is positioned between the data link line and the redirect gate line.
14. The method of claim 13,
the data driving circuit is electrically connected to a conductive material present on the spin-on glass insulating layer;
The data link line is a source-drain material present on the spin-on glass insulating layer,
A conductive material electrically connected to the data driving circuit is electrically connected to the data link line.
14. The method of claim 13,
the gate driving circuit is electrically connected to a conductive material present on the spin-on glass insulating layer;
the redirect gate line is located under the spin-on glass insulating layer and is a first gate material;
A conductive material electrically connected to the gate driving circuit,
The display device is connected to the redirect gate line through a contact hole of the spin-on-glass insulating layer.
12. The method of claim 11,
The gate driving circuit electrically connected to the redirect gate line overlapping a region where the data link line is disposed,
A display device including a gate driving circuit of a chip-on-glass type or a chip-on-film type.
According to claim 1,
the gate driving circuit and the data driving circuit are positioned or connected to a non-active region positioned at one side of the active region of the display panel;
wherein the gate driving circuit is located closer to or connected to the active region than the data driving circuit.
According to claim 1,
the gate driving circuit and the data driving circuit are positioned or connected to a non-active region positioned at one side of the active region of the display panel;
The gate driving circuit and the data driving circuit are positioned side by side or connected to each other.
According to claim 1,
A display device in which the gate driving circuit and the data driving circuit are integrated and positioned or connected to a non-active region positioned at one side of the active region of the display panel.
an active area corresponding to the image display area;
a non-active region existing in a first direction with respect to the active region;
a data line arranged in the first direction to which a data signal is applied;
a gate line disposed in a second direction different from the first direction and to which a gate signal is applied;
a redirect gate line disposed in a direction different from the second direction, electrically connected to the gate line, and transmitting the gate signal to the gate line; and
a gate driving circuit located in or connected to the non-active region;
in the non-active region, the data signal is applied to the data line, the gate signal is applied to the redirect gate line,
In the non-active region, all or part of the gate driving circuit electrically connected to the redirect gate line overlaps with a region in which the data line extends or a data link line electrically connected to the data line is disposed;
A spin-on glass insulating layer is positioned between the gate driving circuit and the data link line.
21. The method of claim 20,
The redirect gate line and the gate line are connected in an active region of the display panel.
21. The method of claim 20,
the redirect gate line is located in the first gate material layer;
the gate line is located in the second gate material layer;
The spin-on glass insulating layer is positioned between the first gate material layer and the second gate material layer.
21. The method of claim 20,
In the non-active region of the display panel, the data link line overlaps the gate driving circuit of the gate-in-panel type.
24. The method of claim 23,
The data link line is made of the same material as the redirect gate line.

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