KR102424642B1 - Inner spacer features for multi-gate transistors - Google Patents

Abstract

A semiconductor device according to the present disclosure includes a channel member including a first connecting portion, a second connecting portion, and a channel portion disposed between the first connecting portion and the second connecting portion, disposed over the first connecting portion, a first inner spacer feature in contact with the first connecting portion; a second inner spacer feature disposed below the first connecting portion and in contact with the first connecting portion; and a gate wrapping around the channel portion of the channel member. include structures. The channel member further includes a first ridge disposed at an interface between the channel portion and the first connecting portion on a top surface of the channel member. The first ridge extends partially between the first inner spacer feature and the gate structure.

Description

INNER SPACER FEATURES FOR MULTI-GATE TRANSISTORS

priority data

This application is entitled "INNER SPACER FEATURES FOR MULTI-GATE TRANSISTORS" (Attorney No. 2020-0185/24061.4197PV01), U.S. Provisional Patent Application No., filed April 24, 2020 No. 63/015,198, the entire contents of which are hereby incorporated by reference.

Field

The present invention relates to an internal spacer feature for a multi-gate transistor.

The semiconductor integrated circuit (IC) industry has grown exponentially. Technological advances in IC materials and design have created generations of ICs, each with smaller and more complex circuitry than the previous generation. During IC evolution, functional density (i.e., number of interconnected devices per chip area) has generally increased while geometry size (i.e., the smallest component that can be created using a manufacturing process) or line)) decreased. This scaling down process generally offers the advantage of increasing production efficiencies and lowering associated costs. This scaling down also increased the complexity of IC processing and manufacturing.

For example, as integrated circuit (IC) technology advances to smaller technology nodes, it increases gate-channel coupling, reduces off-state current, and Multi-gate devices have been introduced to improve gate control by reducing short-channel effects (SCE). A multi-gate device generally refers to a device in which a gate structure or a portion thereof is disposed over more than one side of a channel region. Fin-like field effect transistors (FinFETs) and multi-bridge-channel (MBC) transistors are examples of popular and promising candidates for multi-gate devices for high-performance and low-leakage applications. A FinFET has an elevated channel that is covered by a gate on more than one side (eg, the gate is the top and sidewalls of a “fin” of semiconductor material extending from the substrate). (covering sidewalls). MBC transistors have a gate structure that can extend partially or fully around the channel region to provide access to the channel region on two or more sides. Because the gate structure surrounds the channel region, the MBC transistor may also be referred to as a surrounding gate transistor (SGT) or gate-all-around (GAA) transistor. The channel region of an MBC transistor may be formed of nanowires, nanosheets, or other nanostructures, for which reason MBC transistors may also be referred to as nanowire transistors or nanosheet transistors.

Inner spacer features were implemented in the MBC transistor to space the gate structure from the epitaxial source/drain features. The design of the inner spacer features requires a difficult balance between having sufficient etch resistance and maintaining a low dielectric constant. Regarding the former, the inner spacer features need to be resistant to the etching process of the sacrificial layer to prevent damage to the source/drain features. With respect to the latter, etch-resistant dielectric materials tend to have higher than desirable dielectric constants, which can increase the parasitic capacitance between the gate structure and the source/drain features. Thus, while conventional inner spacer features may generally be suitable for their intended purpose, they are not satisfactory in all respects.

BRIEF DESCRIPTION OF THE DRAWINGS The present disclosure is best understood from the following detailed description when read in conjunction with the accompanying drawings. It is emphasized that, in accordance with standard practice in the industry, various features are not drawn to scale and are used for illustrative purposes only. Indeed, the dimensions of the various features may be arbitrarily increased or decreased for clarity of description.
1 depicts a flow diagram of a method of forming a semiconductor device in accordance with one or more embodiments of the present disclosure.
2-15 illustrate partial cross-sectional views of a workpiece during a manufacturing process according to the method of FIG. 1 in accordance with one or more aspects of the present disclosure.
16 illustrates an enlarged cross-sectional view of a channel region of a semiconductor device in accordance with one or more aspects of the present disclosure.

The following disclosure provides many different embodiments or examples for implementing different features of the presented subject matter. Specific example components and arrangements are described below to simplify the present disclosure. These are, of course, examples only and are not intended to be limiting. For example, in the description below, forming a first feature on or on a second feature may include embodiments in which the first feature and the second feature are formed in direct contact, and also the first feature and embodiments in which additional features may be formed between the first and second features such that the second features may not be in direct contact. In addition, this disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for simplicity and clarity, and does not in itself represent a relationship between the various embodiments and/or configurations discussed.

Also, spatially related terms such as “immediately below,” “below,” “below,” “above,” “above,” and the like, refer herein to the relationship of one element or feature to another element(s) or feature(s). It may be used for convenience of description for description as shown in the drawings. These spatially related terms are intended to include various orientations of the device in use or in operation in addition to the orientation shown in the figures. The device may be otherwise oriented (rotated 90 degrees or in other orientations), and the spatially related descriptors used herein may likewise be interpreted accordingly. Also, when a number or range of numbers is described as “about,” “approximately,” or the like, such terms are intended to include numbers that are within +/−10% of the recited number, unless otherwise specified. For example, the term “about 5 nm” includes a range of dimensions from 4.5 nm to 5.5 nm.

BACKGROUND This disclosure relates generally to multi-gate transistors and methods of fabrication, and more particularly to internal spacer features of MBC transistors.

As discussed above, MBC transistors may also be referred to as SGTs, GAA transistors, nanosheet transistors, or nanowire transistors. They may be n-type or p-type. MBC devices according to the present disclosure may have channel regions disposed within nanowire channel members, rod-shaped channel members, nanosheet channel members, nanostructured channel members, bridge-shaped channel members, and/or other suitable channel configurations. can An inner spacer feature was implemented between the channel members to space the gate structure from the source/drain feature. The inner spacer features cover the two ends of the sacrificial layer, and during the channel release process the inner spacer features include etching to the sacrificial layer and prevent the source/drain features from being damaged. For this reason, an ideal inner spacer feature should have sufficient etch resistance to slow the etch process to remove the sacrificial layer. Since the dielectric constant of a dielectric material is a reliable proxy of etch resistance, a dielectric material with good etch resistance tends to have a higher dielectric constant. Another concern is to avoid the use of high-k (high-k) materials. For example, inner spacer features formed of high-k (high-k) dielectric materials can lead to higher parasitic capacitances between the gate structure and the source/drain features. The search for dielectric materials with high etch resistance and low dielectric constant has not yet yielded promising results, and the industry is exploring various alternative solutions.

The present disclosure provides embodiments of semiconductor devices. A semiconductor device includes a plurality of channel members extending between two source/drain features. Each channel member is divided into a channel portion surrounded by the gate structure and a connection portion sandwiched between the gate spacer layer and the inner spacer feature or between two inner spacer features. An inner spacer feature according to the present disclosure includes an inner layer and an outer layer. The dielectric constant of the outer layer is greater than the dielectric constant of the inner layer. The outer and inner layers may include silicon, carbon, oxygen, and nitrogen. The oxygen content of the outer layer is less than that of the inner layer, and the nitrogen content of the outer layer is greater than the nitrogen content of the inner layer. A portion of the outer layer facing the gate structure may be etched away with the sacrificial layer to bring the gate structure into contact with the inner layer. The channel members of the present disclosure may not be straight. In some implementations, the channel member can include a first ridge and an opposing second ridge at the interface between the inner spacer feature and the gate structure. In some examples, the first and second ridges may extend partially between the inner spacer feature and the gate structure. Due to the outer layer, the inner spacer features of the present disclosure may have sufficient etch resistance to prevent damage to the source/drain features. A portion of the outer layer between the source/drain features and the gate structure may be removed. Since the dielectric constant of the inner layer is smaller than that of the outer layer, removing a portion of the outer layer can reduce the parasitic capacitance and improve device performance.

BRIEF DESCRIPTION OF THE DRAWINGS Various aspects of the present disclosure will now be described in greater detail with reference to the drawings. 1 depicts a flow diagram of a method 100 of forming a semiconductor device from a workpiece in accordance with one or more embodiments of the present disclosure. Method 100 is by way of example only and is not intended to limit the present disclosure to what is explicitly shown in method 100 . Additional steps may be provided before, during, and after the method 100, and some steps described may be replaced, eliminated, or moved for further embodiments of the method. Not all steps are described in detail herein for the sake of simplicity. The method 100 is described below with partial cross-sectional views of a workpiece at different manufacturing stages according to an embodiment of the method 100 .

1 and 2 , the method 100 includes a block 102 in which a workpiece 200 is provided. It is noted that since the workpiece 200 will be fabricated into a semiconductor device, the workpiece 200 may also be referred to as a semiconductor device 200 as the context requires. The workpiece 200 may include a substrate 202 . Although not explicitly shown in the figures, the substrate 202 may include n-type well regions and p-type well regions for fabricating transistors of different conductivity types. In one embodiment, the substrate 202 may be a silicon (Si) substrate. In some other embodiments, the substrate 202 may include other semiconductors such as germanium (Ge), silicon germanium (SiGe), or a III-V semiconductor material. Example III-V semiconductor materials are gallium arsenide (GaAs), indium phosphide (InP), gallium phosphide (GaP), gallium nitride (GaN), gallium arsenide phosphide (GaAsP), aluminum indium arsenide (AlInAs), aluminum gallium It may include arsenide (AlGaAs), gallium indium phosphide (GaInP), and indium gallium arsenide (InGaAs). The substrate 202 may also include an insulating layer, such as a silicon oxide layer, to have a silicon-on-insulator (SOI) structure. Each of the n-type well and the p-type well, when present, is formed in the substrate 202 and includes a doping profile. The n-type well may include a doping profile of an n-type dopant, such as phosphorus (P) or arsenic (As). The p-type well may include a doping profile of a p-type dopant, such as boron (B). Doping in the n-type well and the p-type well may be formed using ion implantation or thermal diffusion, and may be considered part of the substrate 202 . For the avoidance of doubt, the X direction, Y direction, and Z direction are perpendicular to each other.

2 , the workpiece 200 also includes a stack 204 disposed over a substrate 202 . Stack 204 includes a plurality of channel layers 208 interleaved with a plurality of sacrificial layers 206 . The channel layer 208 and the sacrificial layer 206 may have different semiconductor compositions. In some embodiments, the channel layer 208 is formed of silicon (Si), and the sacrificial layer 206 is formed of silicon germanium (SiGe). In this embodiment, the additional germanium content in the sacrificial layer 206 allows for selective removal or recessing of the sacrificial layer 206 without substantial damage to the channel layer 208 . In some embodiments, the sacrificial layer 206 and the channel layer 208 may be deposited using an epitaxial process. Suitable epitaxial processes include vapor-phase epitaxy (VPE), ultra-high vacuum chemical vapor deposition (UHV-CVD), molecular beam epitaxy (MBE). , and/or other suitable processes. As shown in FIG. 2 , a sacrificial layer 206 and a channel layer 208 are alternately deposited one after the other to form a stack 204 . It is noted that the three (3) layer sacrificial layer 206 and the three (3) layer channel layer 208 are alternately vertically arranged as shown in FIG. 3 , which is for illustrative purposes only. for the purpose of limiting it beyond what is specifically recited in the claims. It will be appreciated that any number of sacrificial layers and channel layers may be formed in the stack 204 . The number of layers depends on the desired number of channel members for the device 200 . In some embodiments, the number of channel layers 208 is between 2 and 10. For patterning purposes, a hard mask layer 210 may be deposited over the stack 204 . The hard mask layer 210 may be a single layer or multiple layers. In one example, the hard mask layer 210 includes a silicon oxide layer and a silicon nitride layer.

1 and 3 , the method 100 includes a block 104 in which a fin-shaped structure 212 is formed from a stack 204 . In some embodiments, portions of stack 204 and substrate 202 are patterned to form fin-shaped structures 212 . As shown in FIG. 3 , the fin-shaped structure 212 extends vertically from the substrate 202 in the Z direction. The fin-shaped structure 212 includes a base portion formed from a substrate 202 and a stack portion formed from a stack 204 . The fin-shaped structure 212 may be patterned using any suitable process including a double-patterning or multi-patterning process. In general, double patterning or multiple patterning processes combine a photolithography process with a self-aligned process, for example, one that can be obtained using a single, direct photolithography process. It is possible to create patterns with smaller pitches. For example, in one embodiment a layer of material is formed over a substrate and patterned using a photolithographic process. Spacers are formed next to the patterned material layer using a self-aligning process. The material layer is then removed, and the remaining spacers or mandrels can then be used to pattern the fin-shaped structure 212 by etching the stack 204 and substrate 202 . The etching process may include dry etching, wet etching, reactive ion etching (RIE) and/or other suitable processes.

As shown in FIG. 3 , the operation at block 104 also includes forming an isolation feature 214 adjacent to and around the base portion of the fin-shaped structure 212 . The isolation feature 214 is disposed between the fin-shaped structure 212 and the other fin-shaped structure 212 . The isolation feature 214 may also be referred to as a shallow trench isolation (STI) feature 214 . In one example process, a dielectric layer is first deposited over the workpiece 200 to fill the trench between the fin-shaped structure 212 and the neighboring fin-shaped structure with a dielectric material. In some embodiments, the dielectric layer is made of silicon oxide, silicon nitride, silicon oxynitride, fluorine-doped silicate glass (FSG), a low-k dielectric, combinations thereof, and/or other suitable materials. may include In various examples, the dielectric layer is formed by a CVD process, a subatmospheric CVD (SACVD) process, a flowable CVD process, an atomic layer deposition (ALD) process, physical vapor deposition ( PVD) process, spin-on-coating, and/or other suitable process. The deposited dielectric material is then thinned and planarized by, for example, a chemical mechanical polishing (CMP) process. The planarized dielectric layer is further recessed by a dry etch process, a wet etch process, and/or a combination thereof to form the isolation features 214 . As shown in FIG. 3 , the stack portion of the fin-shaped structure 212 rises above the isolation feature 214 . Although not explicitly shown in FIG. 3 , the hard mask layer 210 may also be removed during formation of the isolation feature 214 .

1 , 4 , and 5 , the method 100 includes a block 106 in which a dummy gate stack 220 is formed over the fin-shaped structure 220 . In some embodiments, a gate replacement process (or gate-last process) is employed in which the dummy gate stack 220 acts as placeholders for the functional gate structure. Other processes and configurations are possible. In some embodiments, the dummy gate stack 220 is formed over the isolation feature 214 and is disposed at least partially over the fin-shaped structure 212 . As shown in FIG. 4 , the dummy gate stack 220 extends in the longitudinal direction along the Y direction to surround the fin-shaped structure 212 . The dummy gate stack 220 includes a dummy dielectric layer 216 and a dummy gate electrode 218 . To illustrate how the dummy gate stack 220 is disposed over the fin-shaped structure 212 , a cross-sectional view taken along section A-A′ is provided in FIG. 5 . As shown in FIG. 5 , the portion of the fin-shaped structure 212 under the dummy gate stack 220 becomes the channel region 202C. Channel region 202C and dummy gate stack 220 also define source/drain regions 202SD that are not vertically overlapped by dummy gate stack 220 . The channel region 202C is disposed between the two source/drain regions 202SD. It is noted that the isolation feature 214 is not shown in FIG. 5 because the cross-sectional view of FIG. 5 is sliced through the fin-shaped structure 212 .

In some embodiments, dummy gate stack 220 is formed by various processing steps, such as layer deposition, patterning, etching, and other suitable processing steps. Exemplary layer deposition processes include low pressure CVD (LPCVD), CVD, plasma enhanced CVD (PECVD), PVD, ALD, thermal oxidation, electron beam evaporation, or other suitable deposition techniques, or combinations thereof. For example, the patterning process may include a lithographic process (eg, photolithography or electron beam lithography), which may include photoresist coating (eg, spin-on coating), soft baking, mask alignment, exposure, post exposure baking, photo resist development, rinsing, drying (eg, spin-drying and/or hard baking), other suitable lithographic techniques, and/or combinations thereof. In some embodiments, the etching process may include dry etching ( eg, RIE etching), wet etching, and/or other etching methods. In an example process, a dummy dielectric layer 216 , a dummy electrode layer for a dummy gate electrode 218 , and a gate top hard mask layer 222 are sequentially over the workpiece 200 including the fin-shaped structure 212 . are deposited In some cases, the gate top hard mask layer 222 may be multiple layers and may include a first hard mask 223 and a second hard mask 224 over the first hard mask 223 . The first hard mask 223 may include silicon oxide, and the second hard mask 224 may include silicon nitride. Deposition may be performed using one of the exemplary layer deposition processes described above. The dummy dielectric layer 216 and the dummy electrode layer are then patterned using a photolithography process to form a dummy gate stack 220 . In some embodiments, dummy dielectric layer 216 may include silicon oxide and dummy gate electrode 218 may include polycrystalline silicon (polysilicon).

After formation of the dummy gate stack 220 , a gate spacer layer 226 is formed next to the sidewalls of the dummy gate stack 220 . In some embodiments, the formation of the gate spacer layer 226 is accomplished by conformal deposition of one or more dielectric layers over the workpiece 200 and the gate spacer from top-facing surfaces of the workpiece 200 . and an etch-back of layer 226 . In one example process, one or more dielectric layers are deposited using CVD, SACVD, or ALD and etched back in an anisotropic etch process to form gate spacer layer 226 . The gate spacer layer 226 may be formed of silicon oxide, silicon nitride, silicon carbide, silicon oxynitride, silicon carbonitride, silicon oxycarbide, silicon oxycarbonitride, and/or combinations thereof. may include

1 and 6 , the method 100 includes a block 108 in which source/drain trenches 228 are formed in a fin-shaped structure 212 . In the embodiment shown in FIG. 6 , the source/drain regions 202SD of the fin-shaped structure 212 that are not masked by the gate top hard mask layer 222 and the gate spacer layer 226 are the source/drain trenches 228 . ) are recessed to form The etching process at block 108 may be a dry etching process or a suitable etching process. For example, the dry etching process may include an oxygen-containing gas, hydrogen, a fluorine-containing gas (eg, CF ₄ , SF ₆ , CH ₂ F ₂ , CHF ₃ , and/or C ₂ F ₆ ), a chlorine-containing gas (eg, Cl ₂ , CHCl ₃ , CCl ₄ , and/or BCl ₃ ), bromine containing gases (eg, HBr and/or CHBR ₃ ), iodine containing gases, other suitable gases and/or plasmas, and/or combinations thereof may be implemented. have. As shown in FIG. 6 , sidewalls of the sacrificial layer 206 and the channel layer 208 are exposed in the source/drain trench 228 .

1 and 7 , the method 100 includes a block 110 in which an inner spacer recess 230 is formed. At a block 110 , the exposed sacrificial layer 206 in the source/drain trenches 228 is selectively and partially recessed to form an inner spacer recess 230 , while the exposed channel layer 208 is recessed. is properly etched. In an embodiment in which the channel layer 208 consists essentially of silicon (Si) and the sacrificial layer 206 consists essentially of silicon germanium (SiGe), the selective and partial recessing of the sacrificial layer 206 is a SiGe oxidation process. and a subsequent SiGe oxide removal process. In that embodiment, the SiGe oxidation process may include the use of ozone (O ₃ ). In some other embodiments, the selective recessing may be a selective isotropic etching process (eg, a selective dry etching process or a selective wet etching process), and the extent to which the sacrificial layer 206 is recessed is controlled by the duration of the etching process. do. The selective dry etching process may include the use of one or more fluorine-based etchants such as fluorine gas or hydrofluorocarbons. The selective wet etch process may include a hydrogen fluoride (HF) or NH ₄ OH etchant. As shown in FIG. 7 , the channel layer 208 may be suitably etched in the block 110 , and the inner spacer recesses 230 may extend partially into the channel layer 208 along the Z direction. Each inner spacer recess 230 has a depth of between about 2 nm and about 5 nm (along the X direction) and a height of between about 7 nm and about 12 nm (along the Z direction). In other words, each inner spacer recess 230 has a height greater than its depth.

1 and 8 , the method 100 includes a block 112 in which a first layer of spacer material 232 is formed over a workpiece 200 . The first spacer material layer 232 may be deposited using ALD and may include silicon (Si), carbon (C), oxygen (O), and nitrogen. In some embodiments, the first spacer material layer 232 may include silicon oxycarbonitride, a silicon content of between about 30% and about 50%, a carbon content of between about 5% and about 15%. , an oxygen content of between about 5% and about 15%, and a nitrogen content of between about 40% and about 60%. In some alternative embodiments, the first spacer material layer 232 may include silicon carbonitride. Since the nitrogen content is between about 40% and about 60%, the first spacer material layer 232 has a first dielectric constant of between about 5 and about 8, and between about 2 g/cm ³ and about 4 g/cm ^{3 .} has a first density between A first layer of spacer material 232 is deposited to a thickness of between about 0.5 nm and about 2 nm. The thickness of the first spacer material layer 232 is selected to be thick enough to prevent damage to the source/drain features during the channel release process and thin enough to be removed along with the sacrificial layer 206 after the channel release process. do.

1 and 9 , the method 100 includes a block 114 in which a second layer of spacer material 234 is formed over the first layer of spacer material 232 . The second spacer material layer 234 may be deposited using ALD. The second spacer material layer 234 may also include silicon (Si), carbon (C), oxygen (O), and nitrogen as the first spacer material layer 232 , but the second spacer material layer 234 . ) is different from that of the first spacer material layer 232 . In some embodiments, the second spacer material layer 234 may include silicon oxycarbonitride, a silicon content of between about 30% and about 50%, a carbon content of between about 5% and about 15%, about 40%. and an oxygen content of between about 60%, and a nitrogen content of between about 10% and about 20%. In these embodiments, the oxygen content of the second spacer material layer 234 is greater than the oxygen content of the first spacer material layer 232 , and the nitrogen content of the second spacer material layer 234 is higher than that of the first spacer material layer 232 . ) is less than the nitrogen content of In some alternative embodiments, the second spacer material layer 234 may include silicon oxycarbide, porous silicon oxycarbide, or fluorine-doped silicon oxide. Since the oxygen content is between about 40% and about 60%, the second spacer material layer 234 has a second dielectric constant between about 1.5 and about 4, and between about 1 g/cm ³ and about 3 g/cm ^{3 .} has a second density between As a comparison, the first dielectric constant of the first spacer material layer 232 is greater than the second dielectric constant of the second spacer material layer 234 . Also, the first density of the first layer of spacer material 232 is higher than the second density of the second layer of spacer material 234 . The second spacer material layer 234 may be thicker than the first spacer material layer 232 . In some implementations, the second spacer material layer 234 may be between about 1 nm and about 3 nm.

1 and 10 , the method 100 includes a block 116 in which a first layer of spacer material 232 and a second layer of spacer material 234 are etched back to form inner spacer features 240 . include At block 116 , the etch-back process removes the first spacer material layer 232 and the second spacer material layer 234 on the channel layer 208 , the substrate 202 , and the gate spacer layer 226 to the interior An inner spacer feature 240 is formed in the spacer recess 230 . In some embodiments, the etch-back process at block 116 is an oxygen-containing gas, hydrogen, nitrogen, fluorine-containing gas (eg, CF ₄ , SF ₆ , CH ₂ F ₂ , CHF ₃ , and/or C ₂ F ₆ ). ), chlorine containing gases (eg Cl ₂ , CHCl ₃ , CCl ₄ , and/or BCl ₃ ), bromine containing gases (eg HBr and/or CHBR ₃ ), iodine containing gases (eg CF ₃ I), other It may be a dry etching process comprising the use of suitable gases and/or plasmas, and/or combinations thereof. As described above, each inner spacer recess 230 has a depth of between about 2 nm and about 5 nm (along the X direction) and a height of between about 7 nm and about 12 nm (along the Z direction). have Because each inner spacer feature 240 is formed within the inner spacer recess 230, each inner spacer feature also has a depth of between about 2 nm and about 5 nm (along the X direction) and (along the Z direction). ) has a height between about 7 nm and about 12 nm. In other words, each inner spacer feature 240 has a height (along the Z-direction) greater than its depth (along the X-direction). As shown in FIG. 10 , each inner spacer feature 240 includes an outer layer formed of a first spacer material layer 232 and an inner layer formed of a second spacer material layer 234 . For convenience of reference, the outer layer shares the same reference number as the first spacer material layer 232 , and the inner layer shares the same reference number as the second spacer material layer 234 . At the end of the operation at block 116 , the outer layer 232 embraces the inner layer 234 and separates the inner layer 234 from the channel layer 208 and the sacrificial layer 206 .

1 and 11 , the method 100 includes a block 118 in which a source/drain feature 242 is formed in a source/drain trench 228 . In some embodiments, source/drain features 242 may be formed using an epitaxial process such as VPE, UHV-CVD, MBE, and/or other suitable processes. The epitaxial growth process may use gas and/or liquid precursors that interact with the composition of the substrate 202 and channel layer 208 . Depending on the conductivity type of the MBC transistor to be formed, source/drain features 242 may be n-type source/drain features or p-type source/drain features. Examples of n-type source/drain features may include Si, GaAs, GaAsP, SiP, or other suitable materials, in situ by introducing n-type dopants such as phosphorus (P), arsenic (As) during epitaxial processing. It may be doped (in-situ), or it may be doped ex-situ using an implantation process ( ie , a junction implantation process). Examples of p-type source/drain features may include Si, Ge, AlGaAs, SiGe, boron-doped SiGe, or other suitable materials, with n-type dopants such as phosphorus (P), arsenic (As) during epitaxial processing. may be doped in situ by introducing

1 and 12 , the method 100 includes a contact etch stop layer (CESL) 244 and an interlayer dielectric (ILD) layer 246 over a workpiece 200 . and a block 120 to be deposited. CESL 244 may include silicon nitride, silicon oxide, silicon oxynitride, and/or other materials known in the art, and may include ALD, plasma enhanced chemical vapor deposition (PECVD) processes, and/or other suitable deposition or It may be formed by an oxidation process. 12 , CESL 244 may be deposited on the top surface of source/drain feature 242 and along sidewalls of gate spacer layer 226 . CESL 244 is also deposited over the top surfaces of gate spacer layer 226 and gate top hard mask layer 222 , although FIG. 12 only shows a cross-sectional view after gate top hard mask layer 222 has been removed. Block 120 also includes depositing an ILD layer 246 over CESL 244 . In some embodiments, the ILD layer 246 is tetraethylorthosilicate (TEOS) oxide, undoped silicate glass, or doped silicon oxide (eg, borophosphosilicate glass (BPSG); materials such as fused silica glass (FSG), phosphosilicate glass (PSG), boron doped silicon glass (BSG)), and/or other suitable dielectric materials includes materials. The ILD layer 246 may be deposited by a PECVD process or other suitable deposition technique. In some embodiments, after formation of the ILD layer 246 , the workpiece 200 may be annealed to improve the integrity of the ILD layer 246 . A planarization process, such as a chemical mechanical polishing (CMP) process, may be performed, as shown in FIG. 12 , to remove excess material and expose the top surface of the dummy gate stack 220 . The gate top hard mask layer 222 is removed by a planarization process.

1 and 13 , the method 100 includes a block 122 from which the dummy gate stack 220 is removed. In some embodiments, removal of dummy gate stack 220 creates gate trench 248 over channel region 202C. A gate structure 250 (described below) may then be formed in the gate trench 248 as described below. Removal of the dummy gate stack 220 may include one or more etching processes selective to the material within the dummy gate stack 220 . For example, the removal of the dummy gate stack 220 may be performed using a selective wet etch, a selective dry etch, or a combination thereof. After removal of dummy gate stack 220 , sidewalls of channel layer 208 and sacrificial layer 206 in channel region 202C are exposed in gate trench 248 .

1 and 14 , the method 100 includes a block 124 in which the sacrificial layer 206 in the channel region 202C is selectively removed to release the channel member 2080 . After removal of dummy gate stack 220 , block 124 of method 100 may include selectively removing sacrificial layer 206 between channel layers 208 in channel region 202C. Selective removal of the sacrificial layer 206 will release the channel layer 208 to form a channel member 2080 . The selective removal of the sacrificial layer 206 may be implemented by selective dry etching, selective wet etching, or other selective etching processes. In some embodiments, the selective wet etching comprises an APM etching (eg, ammonia hydroxide-hydrogen peroxide-water mixture). In some embodiments, the selective removal includes SiGe oxidation followed by silicon germanium oxide removal. For example, oxidation may be provided by ozone cleaning, followed by removal of silicon germanium oxide by an etchant such as NH ₄ OH. As shown in FIG. 14 , selective removal of the sacrificial layer 206 at block 124 is optional, but may still properly etch the channel member 2080 to reduce the thickness of the channel member 2080 along the Z direction. have. This proper etching of the channel member 2080 may form inter-member openings 249 . When viewed along the longitudinal direction (along the Y direction) of the dummy gate stack 220 , the opening 249 between each member has a racetrack-like shape. In accordance with the present disclosure, selective etching of the sacrificial layer 206 also removes the outer layer 232 adjacent the inter-member opening 249 , thereby exposing the inner layer 234 at the inter-member opening 249 . . The operation at block 124 does not remove the portion of the outer layer 232 between the inner layer 234 and the channel member 2080 . As a result, the inner layer 234 is kept spaced apart from the channel member 2080 by the outer layer 232 .

1 and 15 , method 100 includes a method 100 in which a gate structure 250 is formed over and around a channel member 2080 including forming into an inter-member opening 249 (shown in FIG. 14 ). a block 126 . At block 126 , gate structure 250 is formed in gate trench 248 (shown in FIG. 14 ) over workpiece 200 , left behind by removal of sacrificial layer 206 in channel region 202C. Deposited within the inter-member opening 249 . In this regard, the gate structure 250 surrounds each channel member 2080 in the Y-Z plane. In some embodiments, the gate structure 250 includes a gate dielectric layer 252 , and a gate electrode 254 formed over the gate dielectric layer 252 . In one example process, formation of gate structure 250 may include deposition of a gate dielectric layer 252 , deposition of a gate electrode 254 , and a planarization process to remove excess material.

In some embodiments, the gate dielectric layer 252 may include an interfacial layer and a high-k dielectric layer. High-k gate dielectrics used and described herein include, for example, dielectric materials having a dielectric constant greater than that of thermal silicon oxide (˜3.9). The interfacial layer may include a dielectric material such as silicon oxide, hafnium silicate, or silicon oxynitride. The interfacial layer may be deposited using chemical oxidation, thermal oxidation, ALD, CVD, and/or other suitable methods. The high-k dielectric layer may include a high-k dielectric layer such as hafnium oxide. Alternatively, the high-k dielectric layer may be formed of another high-k dielectric, such as titanium oxide (TiO ₂ ), hafnium zirconium oxide (HfZrO), tantalum oxide (Ta ₂ O ₅ ), hafnium silicon oxide (HfSiO ₄ ), zirconium. oxide (ZrO ₂ ), zirconium silicon oxide (ZrSiO ₂ ), lanthanum oxide (La ₂ O ₃ ), aluminum oxide (Al ₂ O ₃ ), zirconium oxide (ZrO), yttrium oxide (Y ₂ O ₃ ), SrTiO ₃ ( STO), BaTiO ₃ (BTO), BaZrO, Hafnium Lanthanum Oxide (HfLaO), Lanthanum Silicon Oxide (LaSiO), Aluminum Silicon Oxide (AlSiO), Hafnium Tantalum Oxide (HfTaO), Hafnium Titanium Oxide (HfTiO), (Ba,Sr ) TiO ₃ (BST), silicon nitride (SiN), silicon oxynitride (SiON), combinations thereof, or other suitable materials. The high-k dielectric layer may be formed by ALD, physical vapor deposition (PVD), CVD, oxidation, and/or other suitable methods.

The gate electrode 254 of the gate structure 250 is a single layer, or alternatively a metal layer having a work function selected to improve device performance (work function metal layer), a liner layer, a wetting layer, an adhesive layer, a metal alloy, or a metal silicide. may include multi-layer structures such as various combinations of For example, the gate electrode 254 may include titanium nitride (TiN), titanium aluminum (TiAl), titanium aluminum nitride (TiAlN), tantalum nitride (TaN), tantalum aluminum (TaAl), tantalum aluminum nitride (TaAlN), or tantalum aluminum. Carbide (TaAlC), Tantalum Carbonitride (TaCN), Aluminum (Al), Tungsten (W), Nickel (Ni), Titanium (Ti), Ruthenium (Ru), Cobalt (Co), Platinum (Pt), Tantalum Carbide ( TaC), tantalum silicon nitride (TaSiN), copper (Cu), other refractory metals, or other suitable metallic materials, or combinations thereof. In various embodiments, the gate electrode 254 may be formed by ALD, PVD, CVD, electron beam evaporation, or other suitable process. Also, the gate electrode may be formed separately for the n-type transistor and the p-type transistor, and different metal layers may be used (eg, to provide different n-type and p-type workfunction metal layers). In various embodiments, a planarization process, such as a CMP process, may be performed to remove excess material for both the gate dielectric layer 252 and the gate electrode 254 , thereby providing a substantially planar top of the gate structure 250 . A surface may be provided. In some embodiments, since the inner layer 234 of the inner spacer feature 240 is exposed at the inter-member opening 249 (shown in FIG. 14 ) and the gate structure 250 fills the inter-member opening 249 . , the gate structure 250 comes into contact with the inner layer 234 . With reference to gate structure 250 and inner spacer features 240 , each channel member 2080 can be considered to include a channel portion 2082 capped at both ends by a connecting portion 2084 . Channel portion 2082 is surrounded by gate structure 250 . Each connection portion 2084 is vertically sandwiched between two inner spacer features 240 or between a gate spacer 226 and a topmost inner spacer feature 240 . Each connection portion 2084 is connected between the source/drain feature 242 and the channel portion 2082 .

To further illustrate features of inner spacer feature 240 and channel member 1080 of the present disclosure, an enlarged partial cross-sectional view of channel region 202C is provided in FIG. 16 . The thickness of each channel member 1080 of the present disclosure is not uniform throughout its length along the X direction. The channel portion 2082 of the channel member 2080 has a first thickness T1 along the Z direction, and the connecting portion 2084 of the channel member 2080 has a second thickness T2 along the Z direction. As shown in FIG. 16 , the channel member 2080 also has a bottom ridge 260 on the bottom surface of the channel member 2080 , and a top ridge on the top surface of the channel member 2080 . (top ridge) 262 . A bottom ridge 260 and a top ridge 262 are disposed adjacent the interface between the inner spacer feature 240 and the gate structure 250 . In other words, the bottom ridge 260 and the top ridge 262 are disposed adjacent the interface between the channel portion 2082 and the connecting portion 2084 . The tips of the bottom ridge 260 and the top ridge 262 may define a third thickness T3 . In some embodiments, the first thickness T1 may be substantially similar to the second thickness T2 . In these embodiments, the third thickness T3 is greater than the first thickness T1 and the second thickness T2. In some examples, the first thickness T1 can be between about 5 nm and about 10 nm, the second thickness T2 can be between about 5 nm and about 10 nm, and the third thickness T3 may be between about 8 nm and about 15 nm. Bottom ridge 260 and top ridge 262 are the result of an isotropic etch to form inner spacer recess 230 and an isotropic etch to selectively remove sacrificial layer 206 . The former goes outside in and the latter goes inside out, and the rounded etch edges meet at the interface between the gate structure 250 and the inner spacer feature 240 as shown in FIG. 16 . A bottom ridge 260 and an upper ridge 262 are formed. With the presence of the bottom ridge 260 and the top ridge 262 , the channel member 2080 of the present disclosure has a barbell-like shape when viewed along the longitudinal direction ( ie , the Y direction) of the gate structure 250 . like shape). As shown in FIG. 16 , the uppermost channel member 2080T does not have a top ridge 262 because the connecting portion of the uppermost channel member 2080T does not fit vertically between the two inner spacer features 240 . may not, and may have a different shape when viewed along the Y direction.

Although not intended to be limiting, one or more embodiments of the present disclosure provide many advantages to semiconductor devices and their formation. For example, embodiments of the present disclosure provide an inner spacer feature comprising an inner layer and an outer layer. The thickness of the outer layer is chosen such that it is thick enough to prevent damage to the source/drain features but thin enough to be consumed during the channel release process. Since the dielectric constant of the outer layer is greater than that of the inner spacer, removal of the outer layer can reduce the parasitic capacitance. In terms of the final structure, the gate structure may be in direct contact with the inner layer. Due to the degree of etching during the formation of the inner spacer recess and removal of the sacrificial layer, the channel member according to the present disclosure has a bottom ridge and an opposing top ridge. As a result, the channel member of the present disclosure may have a barbell-like shape.

In one exemplary aspect, the present disclosure relates to a semiconductor device. A semiconductor device comprises: a channel member including a first connecting portion, a second connecting portion, and a channel portion disposed between the first connecting portion and the second connecting portion; a first inner spacer feature in contact with the first inner spacer feature, a second inner spacer feature disposed below the first connecting portion and in contact with the first connecting portion, and a gate structure wrapping around the channel portion of the channel member. The channel member further includes a first ridge disposed at an interface between the channel portion and the first connecting portion on a top surface of the channel member. The first ridge extends partially between the first inner spacer feature and the gate structure.

In some embodiments, the channel member further comprises a second ridge disposed at an interface between the channel portion and the first connecting portion on a bottom surface of the channel member, the second ridge comprising the second inner spacer feature and the gate structure. In some embodiments, the first inner spacer feature comprises an outer layer and an inner layer, wherein the dielectric constant of the outer layer is greater than the dielectric constant of the inner layer. In some embodiments, the inner layer is spaced from the channel member by the outer layer, and the inner layer is in contact with the gate structure. In some embodiments, the density of the outer layer is higher than the density of the inner layer. In some examples, the outer layer comprises silicon carbonitride or silicon oxycarbonitride, and the inner layer comprises silicon oxycarbide, porous silicon oxycarbide, or and fluorine-doped silicon oxide. In some embodiments, the outer layer and the inner layer comprise silicon, carbon, oxygen, and nitrogen, the oxygen content of the outer layer is less than the oxygen content of the inner layer, and the nitrogen content of the outer layer is the inner layer greater than the nitrogen content of the layer. In some embodiments, the oxygen content of the outer layer is between about 5% and about 15%, the oxygen content of the inner layer is between about 40% and about 60%, and the nitrogen content of the outer layer is between about 40% and between about 60%, and the nitrogen content of the inner layer is between about 10% and about 20%.

In another exemplary aspect, the present disclosure relates to a semiconductor device. A semiconductor device comprises: a channel member including a first connecting portion, a second connecting portion, and a channel portion disposed between the first connecting portion and the second connecting portion along a first direction; a first source/drain feature, a second source/drain feature in contact with the second connecting portion, and a first inner spacer feature disposed over the first connecting portion along a second direction perpendicular to the first direction; , a second inner spacer feature disposed below the first connecting portion along the second direction, and a gate structure wrapping around the channel portion of the channel member. The first inner spacer feature includes an outer layer and an inner layer, the inner layer being spaced apart from the channel member by the outer layer, the inner layer in contact with the gate structure.

In some embodiments, the first inner spacer feature has a first dimension along the first direction and a second dimension along the second direction, the first dimension being less than the second dimension. In some embodiments, the channel member further comprises a first ridge disposed at an interface between the channel portion and the first connecting portion on a top surface of the channel member. The channel member further includes a second ridge disposed at an interface between the channel portion and the first connecting portion on a bottom surface of the channel member. The first ridge extends partially between the first inner spacer feature and the gate structure, and the second ridge extends partially between the second inner spacer feature and the gate structure. In some embodiments, the dielectric constant of the outer layer is greater than the dielectric constant of the inner layer. In some embodiments, the density of the outer layer is higher than the density of the inner layer. In some embodiments, the outer layer comprises silicon carbonitride or silicon oxycarbonitride and the inner layer comprises silicon oxycarbide, porous silicon oxycarbide, or fluorine doped silicon oxide. In some examples, the outer layer and the inner layer comprise silicon, carbon, oxygen, and nitrogen, the oxygen content of the outer layer is less than the oxygen content of the inner layer, and the nitrogen content of the outer layer is the inner layer more than the nitrogen content of In some embodiments, the oxygen content of the outer layer is between about 5% and about 15%, the oxygen content of the inner layer is between about 40% and about 60%, and the nitrogen content of the outer layer is between about 40% and between about 60%, and the nitrogen content of the inner layer is between about 10% and about 20%.

In another exemplary aspect, the present disclosure relates to a method of manufacturing a semiconductor device. The method includes receiving a workpiece comprising a substrate and a stack over the substrate, the stack comprising a plurality of channel layers interleaved by a plurality of sacrificial layers, and patterning the stack and the substrate to form a fin forming a structure; forming a dummy gate stack over a channel region of the fin-shaped structure while the source/drain region of the fin-shaped structure is exposed; and recessing the source/drain region to form a source/drain forming a trench and exposing the plurality of channel layers and sidewalls of the plurality of sacrificial layers; and selectively and partially etching the plurality of sacrificial layers to form inner spacer recesses; depositing a first layer of inner spacer material in the recess; depositing a second layer of inner spacer material over the first layer of inner spacer material; etch back to form inner spacer features within the inner spacer recess, each of the inner spacer features comprising an outer layer formed from the first inner spacer material layer and an inner layer formed from the second inner spacer material layer - removing the dummy gate stack to expose the plurality of channel layers and sidewalls of the plurality of sacrificial layers in the channel region, and the plurality of sacrificial layers to release the plurality of channel layers in the channel region selectively etching the layer and forming a gate structure that wraps around each of the channel layers. The selectively etching includes etching the outer layer, and the gate structure is in contact with the inner layer.

In some embodiments, a thickness of the first inner spacer material layer is less than a thickness of the second inner spacer material layer. In some embodiments, depositing the first inner spacer material layer and depositing the second inner spacer material layer comprises using atomic layer deposition (ALD), wherein the first inner spacer material layer and the second inner spacer material layer includes silicon, carbon, oxygen, and nitrogen. In some examples, the oxygen content of the first inner spacer material layer is between about 5% and about 15%, the oxygen content of the second inner spacer material layer is between about 40% and about 60%, and the first inner spacer material layer has an oxygen content of between about 40% and about 60%. The nitrogen content of the spacer material layer is between about 40% and about 60%, and the nitrogen content of the second inner spacer material layer is between about 10% and about 20%.

The foregoing has outlined features of some embodiments so that those skilled in the art may better understand aspects of the present disclosure. A person skilled in the art can readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same effects as the embodiments introduced herein. You have to understand that there is Those skilled in the art will also appreciate that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that various changes, substitutions, and modifications can be made herein without departing from the spirit and scope of the present disclosure. have to recognize

<Note>

1. A semiconductor device comprising:

a channel member comprising a first connecting portion, a second connecting portion, and a channel portion disposed between the first connecting portion and the second connecting portion;

a first inner spacer feature disposed over and in contact with the first connecting portion;

a second inner spacer feature disposed below the first connecting portion and in contact with the first connecting portion; and

a gate structure wrapping around the channel portion of the channel member

includes,

the channel member further comprising a first ridge disposed at an interface between the channel portion and the first connecting portion and on a top surface of the channel member;

and the first ridge extends partially between the first inner spacer feature and the gate structure.

2. according to clause 1,

the channel member further comprising a second ridge disposed at an interface between the channel portion and the first connecting portion and on a bottom surface of the channel member;

and the second ridge extends partially between the second inner spacer feature and the gate structure.

3. according to clause 1,

the first inner spacer feature comprises an outer layer and an inner layer;

and a dielectric constant of the outer layer is greater than a dielectric constant of the inner layer.

4. according to item 3,

the inner layer is spaced from the channel member by the outer layer;

and the inner layer is in contact with the gate structure.

5. Item 3,

and a density of the outer layer is higher than a density of the inner layer.

6. according to claim 3,

the outer layer comprises silicon carbonitride or silicon oxycarbonitride;

wherein the inner layer comprises silicon oxycarbide, porous silicon oxycarbide, or fluorine-doped silicon oxide.

7. according to item 3,

wherein the outer and inner layers comprise silicon, carbon, oxygen, and nitrogen;

the oxygen content of the outer layer is less than the oxygen content of the inner layer,

wherein the nitrogen content of the outer layer is greater than the nitrogen content of the inner layer.

8. Item 7,

the oxygen content of the outer layer is between about 5% and about 15%;

the oxygen content of the inner layer is between about 40% and about 60%;

the nitrogen content of the outer layer is between about 40% and about 60%;

wherein the nitrogen content of the inner layer is between about 10% and about 20%.

9. A semiconductor device comprising:

a channel member including a first connecting portion, a second connecting portion, and a channel portion disposed between the first connecting portion and the second connecting portion along a first direction;

a first source/drain feature in contact with the first connecting portion;

a second source/drain feature in contact with the second connecting portion;

a first inner spacer feature disposed over the first connecting portion along a second direction perpendicular to the first direction;

a second inner spacer feature disposed below the first connecting portion along the second direction; and

a gate structure that wraps around the channel portion of the channel member

includes,

the first inner spacer feature comprises an outer layer and an inner layer;

the inner layer is spaced from the channel member by the outer layer;

and the inner layer is in contact with the gate structure.

10. Item 8,

the first inner spacer feature has a first dimension along the first direction and a second dimension along the second direction;

and the first dimension is less than the second dimension.

11. Item 9,

the channel member further comprising a first ridge disposed at an interface between the channel portion and the first connecting portion and on a top surface of the channel member;

the channel member further comprising a second ridge disposed at an interface between the channel portion and the first connecting portion and on a bottom surface of the channel member;

the first ridge extends partially between the first inner spacer feature and the gate structure;

and the second ridge extends partially between the second inner spacer feature and the gate structure.

12. Item 9,

wherein the dielectric constant of the outer layer is greater than the dielectric constant of the inner layer.

13. Item 9,

and a density of the outer layer is higher than a density of the inner layer.

14. Item 9,

the outer layer comprises silicon carbonitride or silicon oxycarbonitride;

wherein the inner layer comprises silicon oxycarbide, porous silicon oxycarbide, or fluorine-doped silicon oxide.

15. Item 9,

wherein the outer and inner layers comprise silicon, carbon, oxygen, and nitrogen;

the oxygen content of the outer layer is less than the oxygen content of the inner layer,

wherein the nitrogen content of the outer layer is greater than the nitrogen content of the inner layer.

16. Clause 15,

the oxygen content of the outer layer is between about 5% and about 15%;

the oxygen content of the inner layer is between about 40% and about 60%;

the nitrogen content of the outer layer is between about 40% and about 60%;

wherein the nitrogen content of the inner layer is between about 10% and about 20%.

17. A method comprising:

receiving a workpiece comprising a substrate and a stack over the substrate, the stack comprising a plurality of channel layers interleaved by a plurality of sacrificial layers;

patterning the stack and the substrate to form a fin-shaped structure;

forming a dummy gate stack over a channel region of the fin-shaped structure while the source/drain regions of the fin-shaped structure are exposed;

recessing the source/drain regions to form source/drain trenches and to expose sidewalls of the plurality of channel layers and the plurality of sacrificial layers;

selectively and partially etching the plurality of sacrificial layers to form inner spacer recesses;

depositing a first inner spacer material layer in the inner spacer recess;

depositing a second layer of inner spacer material over the first layer of inner spacer material;

etching back the first inner spacer material layer and the second inner spacer material layer to form inner spacer features in the inner spacer recesses, each of the inner spacer features comprising the first inner spacer material an outer layer formed from the layer and an inner layer formed from the second inner spacer material layer;

removing the dummy gate stack to expose sidewalls of the plurality of channel layers and the plurality of sacrificial layers in the channel region;

selectively etching the plurality of sacrificial layers to release the plurality of channel layers in the channel region; and

forming a gate structure to wrap around each of the channel layers;

includes,

wherein the selectively etching comprises etching the outer layer, and wherein the gate structure is in contact with the inner layer.

18. Item 17,

and a thickness of the first inner spacer material layer is less than a thickness of the second inner spacer material layer.

19. Item 17,

depositing the first inner spacer material layer and depositing the second inner spacer material layer comprises the use of atomic layer deposition (ALD);

wherein the first layer of inner spacer material and the second layer of inner spacer material include silicon, carbon, oxygen, and nitrogen.

20. Item 19,

the oxygen content of the first inner spacer material layer is between about 5% and about 15%;

the oxygen content of the second inner spacer material layer is between about 40% and about 60%;

the nitrogen content of the first inner spacer material layer is between about 40% and about 60%;

wherein the nitrogen content of the second inner spacer material layer is between about 10% and about 20%.

Claims (10)

A semiconductor device comprising:
a channel member comprising a first connecting portion, a second connecting portion, and a channel portion disposed between the first connecting portion and the second connecting portion;
a first inner spacer feature disposed over and in contact with the first connecting portion;
a second inner spacer feature disposed below the first connecting portion and in contact with the first connecting portion; and
a gate structure wrapping around the channel portion of the channel member
includes,
the channel member further comprising a first ridge disposed at an interface between the channel portion and the first connecting portion and on a top surface of the channel member;
and the first ridge extends partially between the first inner spacer feature and the gate structure. According to claim 1,
the channel member further comprising a second ridge disposed at an interface between the channel portion and the first connecting portion and on a bottom surface of the channel member;
and the second ridge extends partially between the second inner spacer feature and the gate structure. According to claim 1,
the first inner spacer feature comprises an outer layer and an inner layer;
and a dielectric constant of the outer layer is greater than a dielectric constant of the inner layer. 4. The method of claim 3,
the inner layer is spaced from the channel member by the outer layer;
and the inner layer is in contact with the gate structure. 4. The method of claim 3,
and a density of the outer layer is higher than a density of the inner layer. 4. The method of claim 3,
the outer layer comprises silicon carbonitride or silicon oxycarbonitride;
wherein the inner layer comprises silicon oxycarbide, porous silicon oxycarbide, or fluorine-doped silicon oxide. 4. The method of claim 3,
wherein the outer and inner layers comprise silicon, carbon, oxygen, and nitrogen;
the oxygen content of the outer layer is less than the oxygen content of the inner layer,
wherein the nitrogen content of the outer layer is greater than the nitrogen content of the inner layer. A semiconductor device comprising:
a channel member including a first connecting portion, a second connecting portion, and a channel portion disposed between the first connecting portion and the second connecting portion along a first direction;
a first source/drain feature in contact with the first connecting portion;
a second source/drain feature in contact with the second connecting portion;
a first inner spacer feature disposed over the first connecting portion along a second direction perpendicular to the first direction;
a second inner spacer feature disposed below the first connecting portion along the second direction; and
a gate structure that wraps around the channel portion of the channel member
includes,
the first inner spacer feature comprises an outer layer and an inner layer;
the inner layer is spaced from the channel member by the outer layer;
the inner layer is in contact with the gate structure;
wherein the dielectric constant of the outer layer is greater than the dielectric constant of the inner layer. 9. The method of claim 8,
the first inner spacer feature has a first dimension along the first direction and a second dimension along the second direction;
and the first dimension is less than the second dimension. As a method,
receiving a workpiece comprising a substrate and a stack over the substrate, the stack comprising a plurality of channel layers interleaved by a plurality of sacrificial layers;
patterning the stack and the substrate to form a fin-shaped structure;
forming a dummy gate stack over a channel region of the fin-shaped structure while the source/drain regions of the fin-shaped structure are exposed;
recessing the source/drain regions to form source/drain trenches and to expose sidewalls of the plurality of channel layers and the plurality of sacrificial layers;
selectively and partially etching the plurality of sacrificial layers to form inner spacer recesses;
depositing a first inner spacer material layer in the inner spacer recess;
depositing a second layer of inner spacer material over the first layer of inner spacer material;
etching back the first inner spacer material layer and the second inner spacer material layer to form inner spacer features in the inner spacer recesses, each of the inner spacer features comprising the first inner spacer material an outer layer formed from the layer and an inner layer formed from the second inner spacer material layer;
removing the dummy gate stack to expose sidewalls of the plurality of channel layers and the plurality of sacrificial layers in the channel region;
selectively etching said plurality of sacrificial layers to release said plurality of channel layers in said channel region and to form openings corresponding to said plurality of sacrificial layers, said openings comprising said interior spacer features and said plurality of channels; Defined by layer - ; and
forming a gate structure to wrap around each of the channel layers;
includes,
The selectively etching includes etching a portion of the outer layer of each of the inner spacer features and a portion of each of the plurality of channel layers over each of the openings, the gate structure comprising the inner layer How to contact with.

Images