KR102424641B1 - Semiconductor package and method of forming the same - Google Patents

Abstract

A semiconductor package is fabricated by attaching a first component to a second component. The first component is assembled by forming a first redistribution structure over a substrate. Then, a through via is formed over the first redistribution structure, and a die is attached below the active surface of the first redistribution structure. The second component includes a second redistribution structure, which is then attached to the through via. A further molding compound is deposited between the first redistribution structure and the second redistribution structure and around a side of the second component.

Description

Semiconductor package and method for forming the same

Priority Claims and Cross-References

This application claims priority to U.S. Provisional Application No. 62/888,277, filed on August 16, 2019, which is incorporated herein by reference.

The semiconductor industry has experienced rapid growth due to continuous improvement in the integration density of various electronic components (eg, transistors, diodes, resistors, capacitors, etc.). For most parts, the improvement in integration density results from repeated reductions in the minimum feature size, which allows more components to be integrated within a given area. BACKGROUND OF THE INVENTION As the demand for shrinking electronic devices increases, the need for smaller and more productive packaging techniques for semiconductor dies has emerged. An example of such a packaging system is a Package-on-Package (PoP) technology. In PoP devices, a top semiconductor package is stacked on top of a bottom semiconductor package to provide a high level of integration and component density. PoP technology generally enables the production of semiconductor devices with small footprints and enhanced functionality on printed circuit boards (PCBs).

A semiconductor package is fabricated by attaching a first component to a second component. The first component is assembled by forming a first redistribution structure over a substrate. Then, a through via is formed over the first redistribution structure, and a die is attached below the active surface of the first redistribution structure. The second component includes a second redistribution structure, which is then attached to the through via. A further molding compound is deposited between the first redistribution structure and the second redistribution structure and around a side of the second component.

Aspects of the present disclosure are best understood from the following detailed description when taken in conjunction with the accompanying drawings. It should be noted that, in accordance with standard practice in the industry, various features are not drawn to scale. In fact, the dimensions of various features may have been arbitrarily increased or decreased for clarity of description.
1 illustrates a cross-sectional view of an integrated circuit die in accordance with some embodiments.
2A-2G illustrate cross-sectional views of intermediate steps during a process for forming a package component in accordance with some embodiments.
3A-3H illustrate cross-sectional views of intermediate steps during a process for forming a package component in accordance with some embodiments.
4A-4H illustrate cross-sectional views of intermediate steps during a process for forming a package component in accordance with some embodiments.
5A-5H illustrate cross-sectional views of intermediate steps during a process for forming a package component in accordance with some embodiments.
6A-6H illustrate cross-sectional views of intermediate steps during a process for forming a package component in accordance with some embodiments.

The following disclosure provides many different embodiments or examples for implementing different features of the invention. Specific examples of components and configurations are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, in the following description, forming a first feature on or over a second feature may include embodiments in which the first and second features are formed in direct contact, and the first and second features Embodiments in which additional features may be formed between the first and second features such that the features do not directly contact may also be included. In addition, this disclosure may repeat reference numbers and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity, and does not in itself indicate a relationship between the various embodiments and/or configurations being described.

Also, spatially relative terms such as “below”, “below”, “lower”, “above”, “above”, etc. refer to one component or another component(s) of a feature as illustrated in the drawings. May be used herein for ease of description to describe the relationship to feature(s). The spatially relative terminology is intended to encompass different orientations of the device in use or operation in addition to the orientation shown in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations), and spatially relative descriptors used herein may likewise be interpreted accordingly.

In accordance with some embodiments, one or more integrated circuit dies and other devices are attached to a dual-sided redistribution structure and embedded in an encapsulant to form a semiconductor system-in-package (SiP) structure. One of the redistribution structures may have a fan-out design, and the other may be formed on a carrier-type substrate. The placement of the integrated circuit die and the layout of the redistribution structure provide versatility in the overall package. In addition, the method, as well as the design of the package and redistribution structures, facilitates thinner SiP structures with greater strength and reduced overall package warpage.

1 illustrates a cross-sectional view of an integrated circuit die 50 in accordance with some embodiments. The integrated circuit die 50 will be packaged in subsequent processing to form an integrated circuit package. The integrated circuit die 50 includes a logic die (eg, a central processing unit (CPU), a graphics processing unit (GPU), a system-on-a-chip (SoC), an application processor (AP), a microcontroller, etc.), a memory die (eg, dynamic random access memory (DRAM) die, static random access memory (SRAM) die, etc.), power management die (eg, power management integrated circuit (PMIC) die), radio frequency (RF) die, sensor die, micro-electro-mechanical-system (MEMS) die, signal processing die (eg, digital signal processing (DSP) die), front end die (eg, analog front-end (AFE) die), etc., or these may be a combination of

The integrated circuit die 50 may be formed on a wafer, which may include different device regions that are singulated in a subsequent step to form a plurality of integrated circuit dies. The integrated circuit die 50 may be processed according to applicable manufacturing processes to form an integrated circuit. For example, the integrated circuit die 50 includes a semiconductor substrate 52 such as silicon, doped or undoped, or an active layer of a semiconductor-on-insulator (SOI) substrate. The semiconductor substrate 52 may include other semiconductor materials such as germanium; compound semiconductors including silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and/or indium antimonide; alloy semiconductors including SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, and/or GaInAsP; or a combination thereof. Other substrates may also be used, such as multilayer or gradient substrates. Semiconductor substrate 52 has an active surface, often referred to as a front-side (eg, facing up in FIG. 1 ), and an inactive surface, often referred to as, a back side (eg, facing down in FIG. 1 ).

A device 54 (one is shown in FIG. 1 ) may be formed on the front surface of the semiconductor substrate 52 . Device 54 may be an active element (eg, a transistor, diode, etc.), a capacitor, a resistor, or the like. An inter-layer dielectric (ILD) 56 is over the front surface of the semiconductor substrate 52 . ILD 56 may surround and cover device 54 . ILD 56 may include one or more dielectric layers formed of a material such as PSG (Phospho-Silicate Glass), BSG (Boro-Silicate Glass), BPSG (Boron-Doped Phospho-Silicate Glass), USG (undoped silicate glass), etc. can

A conductive plug 58 extends through the ILD 56 to electrically and physically couple the device 54 . For example, when device 54 is a transistor, conductive plug 58 may couple the gate and source/drain regions of the transistor. The conductive plug 58 may be formed of tungsten, cobalt, nickel, copper, silver, gold, aluminum, or the like, or a combination thereof. An interconnect structure 60 is over the ILD 56 and the conductive plug 58 . The interconnect structure 60 interconnects the devices 54 to form an integrated circuit. Interconnect structure 60 may be formed, for example, by a metallization pattern in a dielectric layer on ILD 56 . The metallization pattern includes metal lines and vias formed in one or more low-k dielectric layers. The metallization pattern of the interconnect structure 60 is electrically coupled to the device 54 by a conductive plug 58 .

The integrated circuit die 50 further includes pads 62, such as aluminum pads, to which external connections are made. The pads 62 are on the active side of the integrated circuit die 50 , such as on and/or on the interconnect structure 60 . One or more passivation films 64 are on the integrated circuit die 50 , such as on portions of the interconnect structure 60 and pads 62 . An opening extends through the passivation film 64 to the pad 62 . A die connector 66 , such as a conductive pillar (eg, formed of a metal such as copper), extends through the opening in the passivation film 64 and is physically and electrically coupled to respective pads of the pads 62 . ring is In some embodiments, die connector 66 includes an under-bump metallization (UBM) structure. Although only four die connectors 66 are illustrated in FIG. 1 , there may be many more as will be illustrated in subsequent drawings of integrated circuit die 50 . The die connector 66 (eg, copper pillars) may be formed, for example, by plating or the like. Die connector 66 electrically couples respective integrated circuits of integrated circuit die 50 .

Optionally, solder regions (eg, solder balls or solder bumps, not shown) may be disposed on pad 62 and/or die connector 66 . The solder region may be used to perform chip probe (CP) testing on the integrated circuit die 50 . CP testing may be performed on the integrated circuit die 50 to determine whether the integrated circuit die 50 is a known good die (KGD). Accordingly, only the integrated circuit die 50 that is KGD undergoes subsequent processing and is packaged, and the integrated circuit die 50 that fails CP testing is not packaged. After testing, the solder regions may be removed in subsequent processing steps.

Dielectric layer 68 may (or may not) be on the active side of integrated circuit die 50 , such as on passivation film 64 and die connector 66 . The dielectric layer 68 laterally encapsulates the die connector 66 , and after singulation the dielectric layer 68 is laterally coterminous with the integrated circuit die 50 . . Initially, the dielectric layer 68 may bury the die connector 66 such that the topmost surface of the dielectric layer 68 is above the top surface of the die connector 66 . In some embodiments where solder regions are disposed on die connector 66 , dielectric layer 68 may also fill solder regions as well. Alternatively, the solder regions may be removed prior to forming the dielectric layer 68 .

The dielectric layer 68 may include a polymer such as PBO, polyimide, BCB, or the like; nitrides such as silicon nitride and the like; oxides such as silicon oxide, PSG, BSG, BPSG, and the like; Others or combinations thereof may be used. The dielectric layer 68 may be formed, for example, by spin coating, lamination, chemical vapor deposition (CVD), or the like. In some embodiments, die connector 66 is exposed through dielectric layer 68 during formation of integrated circuit die 50 . In some embodiments, the die connector 66 remains buried and is exposed during a subsequent process for packaging the integrated circuit die 50 . Exposing the die connector 66 may remove any solder regions that may be present on the die connector 66 .

At some point in the process, an adhesive layer 70 may be applied to the backside of the integrated circuit die 50 . In some embodiments, an adhesive layer is formed over the backside of the integrated circuit die 50 prior to attaching the integrated circuit die to the semiconductor package component, as described in more detail below.

In some embodiments, the integrated circuit die 50 is a stacked device including a plurality of semiconductor substrates 52C. For example, the integrated circuit die 50 may be a memory device, such as a hybrid memory cube (HMC) module, a high bandwidth memory (HBM) module, or the like, including a plurality of memory dies. In this embodiment, the integrated circuit die 50 includes a plurality of semiconductor substrates 52 interconnected by through-substrate vias (TSVs). Each of the semiconductor substrates 52 may (or may not) have an interconnect structure 60 .

The following describes the formation of a semiconductor package incorporating an integrated circuit die 50 in accordance with some embodiments. 2A-2G describe various intermediate steps in the formation of a first component in accordance with some embodiments. As will be described, the first component may include a fan-out redistribution structure to which the integrated circuit die 50 is attached. 3A-3H describe the formation of a second component that may be attached to a first component described with reference to FIGS. 2A-2G , in accordance with some embodiments. As will be described, the second component may include a substrate-type redistribution structure. Although not specifically described, the second component may include a fan-out redistribution structure similar to that of the first component. 4A-4H describe additional processing for attaching a second component to a first component and forming a semiconductor package in accordance with some embodiments.

Referring first to FIG. 2A , in forming the first component 100 , a first carrier substrate 102 is provided, and a release layer 104 is formed on the first carrier substrate 102 . The first carrier substrate 102 may be a glass carrier substrate, a ceramic carrier substrate, or the like. The first carrier substrate 102 may be a wafer such that a plurality of packages may be simultaneously formed on the first carrier substrate 102 and each package may include one or more dies. The release layer 104 may be formed of a polymer-based material, which may be removed along with the first carrier substrate 102 from the structures above to be formed at a later stage. In some embodiments, the release layer 104 is an epoxy-based heat-release material, which loses its adhesive properties when heated, such as a light-to-heat-conversion (LTHC) release coating. In some embodiments, the release layer 104 may be a UV glue that loses its adhesive properties when exposed to ultra-violet (UV) light. The release layer 104 may be dispensed as a liquid and cured, may be a laminate film laminated onto the first carrier substrate 102 , or otherwise.

2B-2E , a first-side redistribution structure 106 may be formed on the release layer 104 . In the illustrated embodiment, the first side redistribution structure 106 includes one or more dielectric layers and a metallization pattern (sometimes referred to as a redistribution layer or redistribution line). The first side redistribution structure 106 will be described as having three layers of a metallization pattern. More or fewer dielectric layers and metallization patterns may be formed in the first side redistribution structure 106 . If fewer dielectric layers and metallization patterns are to be formed, the steps and processes described below may be omitted. As more dielectric layers and metallization patterns are formed, the steps and processes described below may be repeated.

Referring now to FIG. 2B , a dielectric layer 110 is formed over the release layer 104 . The lower surface of the dielectric layer 110 may be in contact with the upper surface of the release layer 104 . In some embodiments, dielectric layer 110 is formed of a photosensitive material, such as polybenzoxazole (PBO), polyimide, benzocyclobutene (BCB), or the like, which can be patterned using a lithographic mask. In some embodiments, dielectric layer 110 may include a nitride such as silicon nitride; It is formed of silicon oxide, an oxide such as phosphosilicate glass (PSG), borosilicate glass (BSG), boron-doped phosphosilicate glass (BPSG), or the like. The dielectric layer 110 may be formed by spin coating, lamination, CVD, or the like, or a combination thereof. The dielectric layer 110 is patterned to form an opening that exposes a portion of the release layer 104 . Patterning may be accomplished by an acceptable process, such as by exposing, developing and curing dielectric layer 110 to light when dielectric layer 110 is a photosensitive material, or by etching using, for example, anisotropic etching.

A metallization pattern 112 is then formed on the dielectric layer 110 . The metallization pattern 112 includes on a major surface of the dielectric layer 110 a portion of a line (also referred to as a conductive line) extending along it. The metallization pattern 112 is formed with a via portion (also referred to as a conductive via) extending through the dielectric layer 110 to physically and electrically couple the first side redistribution structure 106 with an external connector to be formed at a later stage. referred to). As an example for forming the metallization pattern 112 , a seed layer is formed over the dielectric layer 110 and in an opening extending through the dielectric layer 110 . In some embodiments, the seed layer is a metal layer, which may be a single layer or a composite layer comprising a plurality of sublayers formed of different materials. In some embodiments, the seed layer includes a titanium layer and a copper layer over the titanium layer. The seed layer may be formed using, for example, physical vapor deposition (PVD) or the like. A photoresist is then formed on the seed layer and patterned. The photoresist may be formed by spin coating or the like and exposed to light for patterning. The pattern of photoresist corresponds to the metallization pattern 112 . The patterning forms openings through the photoresist to expose the seed layer. A conductive material is then formed in the openings of the photoresist and on the exposed portions of the seed layer. The conductive material may be formed by plating such as electroplating or electroless plating. The conductive material may include a metal such as copper, titanium, tungsten, aluminum, or the like. The portion of the seed layer over which no conductive material has been formed and the photoresist are removed. The photoresist may be removed by an acceptable ashing or stripping process, such as using an oxygen plasma or the like. Once the photoresist is removed, the exposed portions of the seed layer are removed by using an acceptable etching process, such as by wet or dry etching, for example. The remaining portion of the conductive material and the portion below the seed layer form the metallization pattern 112 .

In FIG. 2C , a dielectric layer 114 is deposited over the metallization pattern 112 and the dielectric layer 110 . Dielectric layer 114 may be formed and patterned in a manner similar to dielectric layer 110 .

Then, a metallization pattern 116 is formed. The metallization pattern 116 includes a portion of the line extending along the major surface of the dielectric layer 114 . The metallization pattern 116 further includes a via portion extending through the dielectric layer 114 to physically and electrically couple the metallization pattern 112 . The metallization pattern 116 may be formed in a similar manner and of a similar material to the metallization pattern 112 . In some embodiments, the metallization pattern 116 has a different size than the metallization pattern 112 . For example, the conductive lines and/or vias of the metallization pattern 112 may be wider or thicker than the conductive lines and/or vias of the metallization pattern 116 . Also, the metallization pattern 112 may be formed with a larger pitch than the metallization pattern 116 .

In FIG. 2D , a dielectric layer 118 is deposited over the metallization pattern 116 and the dielectric layer 114 . Dielectric layer 118 may be formed and patterned in a manner similar to dielectric layers 110 and/or 114 .

Then, a metallization pattern 120 is formed. The metallization pattern 120 includes a portion of the line extending along the major surface of the dielectric layer 118 . The metallization pattern 120 further includes a via portion extending through the dielectric layer 118 to physically and electrically couple the metallization pattern 116 . The metallization pattern 120 may be formed in a similar manner and of a similar material to the metallization patterns 112 and/or 116 .

In FIG. 2E , a dielectric layer 122 is deposited over the metallization pattern 120 and the dielectric layer 118 . Dielectric layer 122 may be formed and patterned in a similar manner to dielectric layer 110 to form openings 124 .

The dielectric layer 110 and the metallization pattern 112 are the bottommost dielectric layer and the metallization pattern of the first side redistribution structure 106 , respectively. Thus, all of the intermediate dielectric layers and metallization patterns (eg, dielectric layers 114 , 118 , and 122 and metallization patterns 116 and 120 ) of the first side redistribution structure 106 include the first side redistribution patterns. It is disposed between the dielectric layer 110/metallization pattern 112 and a component to be formed or attached later on the structure 106 . In some embodiments, the metallization pattern 112 has a different size than the metallization patterns 116 and 120 . For example, the conductive lines of the metallization pattern 112 may have a thickness of from about 0.5 μm to about 15 μm, or about 5 μm, and the conductive lines of the metallization patterns 116 and 120 may be from about 0.5 μm to about 0.5 μm. It may have a thickness of 15 μm, or about 5 μm. A ratio of the thickness of the metallization pattern 112 to the thickness of the metallization pattern 120 may be about 0.3 to about 3, or about 1. In addition, the metallization pattern 112 may be formed with a larger pitch than the metallization patterns 116 and 120 . For example, the conductive lines of the metallization pattern 112 may have a pitch of from about 1 μm to about 100 μm, or about 10 μm, and the conductive lines of the metallization patterns 116 and 120 may be from about 1 μm to about 1 μm. It may have a pitch of 100 μm, or about 10 μm. The ratio of the pitch of the metallization pattern 112 to the pitch of the metallization pattern 120 may be about 0.1 to about 10, or about 1. It should be appreciated that the first side redistribution structure 106 may include any number of dielectric layers and metallization patterns. As more dielectric layers and metallization patterns are formed, the steps and processes described above may be repeated.

In FIG. 2F , a through via 126 is formed in a portion of the opening 124 and extends away from a top dielectric layer (eg, dielectric layer 122 ) of the first side redistribution structure 106 . As an example for forming the through via 126 , a seed layer (not shown) is applied over the first side redistribution structure 106 , such as of the dielectric layer 122 and the metallization pattern 120 exposed by the openings. formed on the part. In some embodiments, the seed layer is a metal layer, which may be a single layer or a composite layer comprising a plurality of sublayers formed of different materials. In some embodiments, the seed layer includes a titanium layer and a copper layer over the titanium layer. In some embodiments, the seed layer is made of copper, titanium, nickel, gold, palladium, etc., or a combination thereof. The seed layer may be formed using, for example, PVD or the like. A mask, such as photoresist (not shown), is formed on the seed layer and patterned. The photoresist may be formed by spin coating or the like, and may be exposed to light for patterning. The pattern of photoresist corresponds to through via 126 and exposes the seed layer. A conductive material is formed in the opening of the photoresist and on the exposed portion of the seed layer. The conductive material may be formed by an electro-chemical plating process or plating such as electroless plating, CVD, atomic layer deposition (ALD), PVD, or the like, or a combination thereof. The conductive material may include a metal such as copper, titanium, tungsten, aluminum, or the like. The photoresist may be removed.

With continued reference to FIG. 2F , a bond pad 128 is formed in a portion of the opening 124 and extending away from the dielectric layer 122 . The bond pad 128 may be formed in a similar manner to the through via 126 , and may be formed of the same material as the through via 126 . Further, the bond pad 128 may be formed before, after, or concurrently with the through via 126 .

The photoresist used for the bond pads 128 and for the through vias 126 and the portion of the seed layer over which the bond pads 128 and through vias 126 are not formed are removed. The photoresist may be removed by an acceptable ashing or stripping process, such as using an oxygen plasma or the like. Once the photoresist is removed, the exposed portions of the seed layer are removed, for example, by using an acceptable etching process, such as by wet or dry etching. The remainder of the seed layer and conductive material form bond pads 128 and through vias 126 .

As described below, an integrated circuit die (eg, the integrated circuit die 50 described above with reference to FIG. 1 ) may be attached to the bond pads 128 . In some embodiments, bond pad 128 is a UBM, which may include three layers of conductive material, such as, for example, a titanium layer, a copper layer, and a nickel layer. Other material and layer arrangements may be used to form bond pads 128 , such as a chromium/chromium-copper alloy/copper/gold arrangement, a titanium/titanium tungsten/copper arrangement, or a copper/nickel/gold arrangement. . Any suitable material or material layer that may be used for bond pad 128 is fully intended to be included within the scope of this application.

In FIG. 2G , one or more semiconductor devices, such as first integrated circuit die 50 , are attached to bond pads 128 to make electrical connection with first side redistribution structure 106 . For example, the first integrated circuit die 50 forms a solder joint 130 over the die connector 66 (whether a conductive pillar or a UBM), presses the die connector 66 to the bond pad 128 and , by reflowing the solder joint 130 to attach the first integrated circuit die 50 to the first side redistribution structure 106 . In some embodiments, the first integrated circuit die 50 may be attached using direct metal-to-metal bonding or hybrid bonding. 2G shows the integrated circuit die 50 as having a greater height than the through via 126 . However, it will be appreciated that the through via 126 may have a height approximately equal to or greater than the integrated circuit die 50 . For example, the through via 126 may have a height H _TV of about 10 μm to about 200 μm, and the integrated circuit die 50 may have a height H _IC1 of about 30 μm to about 250 μm. can The ratio of the height H _TV to the height H _IC1 may be about 0.04 to 8.

It should be noted that the first side redistribution structure 106 may be a fan-out redistribution structure with respect to the integrated circuit die 50 . As such, the metallization patterns (eg, metallization patterns 112 , 116 , and 120 ) may extend laterally more than the integrated circuit die 50 . The fan-out design may accommodate a greater number of external connectors while allowing thinner redistribution structures, which may thus extend laterally more than the integrated circuit die 50 . The first surface redistribution structure 106 is formed to have a thickness T ₁ , and the thickness T ₁ may be about 20 μm to about 100 μm.

An underfill material 132 may be dispensed between the first integrated circuit die 50 and the first side redistribution structure 106 . Underfill material 132 surrounds solder joint 130 and bond pad 128 . Underfill material 132 may be any acceptable material, such as a polymer, epoxy, molding underfill, or the like. The underfill material 132 may be dispensed using a needle or jetting dispenser, using a capillary flow process, or using another suitable process. In some embodiments, a curing process may be performed to cure the underfill material 132 . Although not explicitly shown in FIG. 2G , underfill material 130 may extend along sidewalls of first integrated circuit die 50 .

2G illustrates a single integrated circuit die 50 attached to bond pads 128 for illustrative purposes. In some embodiments, two or more integrated circuit dies 50 (each having the same or different functions) may be attached to bond pads 128 .

3A-3H illustrate cross-sectional views of intermediate steps during a process for forming the second component 200 in accordance with some embodiments. As described above, the second component 200 may later be attached to the first component 100 described above with respect to FIGS. 2A-2G . The second component 200 may be formed as a separate package or through wafer level processing. Although only the individual package component 200 is illustrated, it should be understood that the second component 200 may be part of a wafer. After formation, the respective second component 200 is singulated. The resulting second component 200 may also be referred to as an integrated package.

3A , a second carrier substrate 202 is provided, and a second surface redistribution structure may be formed on the second carrier substrate 202 . The second carrier substrate 202 may be a glass carrier substrate, a ceramic carrier substrate, or the like. The second carrier substrate 202 may be a wafer such that a plurality of packages may be simultaneously formed on the second carrier substrate 202 . A first metal film 204 is formed on the second carrier substrate 202 . The first metal layer 204 may include copper such as copper foil. The second carrier substrate 202 may have a thickness of about 10 μm to about 400 μm, or about 200 μm. The first metal layer 204 may have a thickness of about 1 μm to about 20 μm, or about 3 μm. The first metal film 204 may include copper or another conductive material.

In FIG. 3B , a photoresist 208 is then formed and patterned on the first metal film 204 . The photoresist 208 may be formed, such as by spin coating, and exposed to light for patterning. The patterning forms an opening through the photoresist 208 to expose the first metal film 204 .

In FIG. 3C , a second surface redistribution structure 206 is formed on the first metal film 204 . First, a first metal trace 210 is formed over the first metal film 204 , and the photoresist 208 is removed. The first metal trace 210 may be formed by electroplating and may include one or more layers of a conductive material. For example, a layer of gold (Au) may be deposited first, a layer of nickel (Ni) next, and a layer of copper (Cu) last. Au may be deposited to a thickness of at least about 0.1 μm, such as from about 0.01 μm to about 3 μm. Nickel may be deposited to a thickness of at least about 3 μm, such as between about 0.1 μm and about 10 μm. Copper may be deposited to a thickness of at least about 7 μm, such as between about 1 μm and about 25 μm. Thus, the first metal trace 210 may have a thickness of about 1 μm or more to about 35 μm, for example, about 10 μm or more. Such a thickness provides the advantages of adhering the first metal traces 210 to the first metal film 204 , maintaining internal cohesiveness, and/or allowing sufficient conductive properties. A thickness less than this may result in poor adhesion, cohesiveness and/or conductivity. The photoresist 208 may be removed by any suitable stripping method.

In FIG. 3D , a dielectric layer 212 is formed over the first metal trace 210 . The dielectric layer 212 may be formed by a thermal lamination process. The dielectric layer 212 may include prepreg or Ajinomoto Build-up Film (ABF). In some embodiments, dielectric layer 212 is a prepreg having a thickness of about 10 μm to about 100 μm, such as about 30 μm, or ABF having a thickness of about 10 μm to about 100 μm, such as about 20 μm. can An advantage of using a prepreg or ABF material as the dielectric layer 212 is that the second side redistribution structure 206 will have a high level of strength and reliability. When later coupled with the first side redistribution structure 106 , the entire semiconductor package will be less susceptible to warping.

In FIG. 3E , dielectric layer 212 is patterned to form openings exposing portions of first metal traces 210 . The opening includes a via opening 214 extending through the dielectric layer 212 to expose a portion of the first metal trace 210 . The opening further includes a line opening 216 running through the via opening 214 and providing routing capability. Dielectric layer 212 may be patterned using a single damascene or dual damascene process. Patterning may be performed by any suitable method, such as forming a photoresist and wet or dry etching the dielectric layer 212 and/or employing laser grinding (or laser drilling) techniques. Although shown with vertical sidewalls, it should be understood that the via opening 214 may have non-vertical sidewalls due to laser drilling techniques. The via opening 214 may have a width of about 30 μm to about 150 μm, such as about 65 μm.

In FIG. 3F , via openings 214 and line openings 216 in the upper region of dielectric layer 212 are conductive vias 218 (in via openings 214 ) and second metal traces 220 (line openings). is filled with a conductive material to form (in) 216 . The conductive material may be deposited by electroplating or electroless plating, or any suitable method. The second metal trace 220 may have a thickness of about 10 μm. Alternatively, conductive vias 218 may be initially formed before dielectric layer 212 is patterned to form second metal traces 220 .

The second side redistribution structure 206 (including first metal traces 210 , conductive vias 218 , and second metal traces 220 ) is formed with a thickness T ₂ , and has a thickness T ₂ . may be from about 20 μm to about 150 μm. The thickness T ₂ of the second surface redistribution structure 206 may be greater than or equal to the thickness T ₁ of the rear redistribution structure 106 . A ratio of the thickness T ₁ to the thickness T ₂ may be about 0.3 to about 3. Ratios within this range include the material comprising the integrated circuit die 50 and the dielectric of the first side redistribution structure 106 when the second component 200 is later attached to the first component 100 , for example. Provides sufficient stiffness to prevent or reduce warpage due to differences in the coefficient of thermal expansion (CTE) of the layer and metallization pattern. A ratio less than these values may not provide sufficient stiffness for the second component 200 to counteract the expansion of the components of the first component 100 . Ratios greater than these values may increase the signal length, thereby reducing the performance of the packaged device.

3G , solder resist 222 is formed and patterned to form openings 224 exposing conductive vias 218 and/or second metal traces 220 . In addition, exposed portions of conductive vias 218 and second metal traces 220 may be treated for protection purposes. For example, an electroless nickel electroless palladium immersion gold (ENEPIG) treatment or organic solderability preservative (OSP) may be performed on the exposed portions of the conductive vias 218 and the second metal traces 220 . The solder resist may have a thickness of about 5 μm to about 40 μm, such as about 10 μm. Solder resist 222 may also be used to protect areas of second side redistribution structure 206 from external damage.

In FIG. 3H , connectors 226 are formed over exposed portions of conductive vias 218 and second metal traces 220 . The connector 226 may be a solder ball formed in a manner similar to the solder regions on the first integrated circuit die 50 , and may be formed of a material similar to the solder regions on the first integrated circuit die 50 .

In the case of wafer level processing to form the second component 200 , the singulation process may be performed by sawing along the scribe area between adjacent second components 200 . As described below, the resulting individualized second component 200 is coupled to the first component 100 . In some embodiments, the first component 100 is likewise singulated before the second component 200 is attached. In some embodiments, the first component 100 is singulated after attaching the second component 200 .

4A-4H illustrate cross-sectional views of additional processing as well as intermediate steps for attaching the second component 200 to the first component 100 to form a package 400 , in accordance with some embodiments. .

Referring first to FIG. 4A , a package 400 in which the first component 100 is part of a wafer is illustrated. In some embodiments (but not illustrated in FIG. 4A ), the first component 100 is already individualized in the scribe area 404 .

Each individualized second component 200 is mounted to the first component 100 using a connector 226 . As described above, the first component 100 includes a through via 126 for attachment. Thus, the connector 224 is bonded to the corresponding through via 126 . In some embodiments, the connector 226 is reflowed to attach the second component 200 to the through via 126 . The connector 226 electrically couples the second component 200 to the first side redistribution structure 106 of the first package component 100 . The connector 226 may have an epoxy flux (not shown) formed thereon prior to reflow, at least a portion of the epoxy portion of the epoxy flux after the second component 200 is attached to the first component 100 . Remains. This remaining epoxy portion can act as an underfill to reduce stress and protect the joint as a result of reflowing the connector 226 . After attaching the second component 200 to the first component 100 , the first side redistribution structure 106 and the second side redistribution structure 206 may be separated from each other by a thickness T ₃ . The thickness T ₃ may be about 50 μm to about 500 μm. A ratio of the thickness T ₃ to the thickness T ₁ may be about 0.4 to about 5. A ratio of the thickness T ₃ to the thickness T ₂ may be about 0.3 to about 4.

In FIG. 4B , an encapsulant 310 is formed over the first component 100 and below and around the second component 200 . The encapsulant 310 further encapsulates the through via 126 , the first integrated circuit die 50 , and any other devices (if any) attached to the first component 100 and/or the second component 200 . seal it An encapsulant 310 is further formed in a gap region between adjacent second components 200 . The encapsulant 310 may be formed by a capillary flow process after the second package component 200 is attached, or may be formed by a suitable deposition method before the second package component 200 is attached. In some embodiments, the encapsulant 310 may be applied by compression molding, transfer molding, or the like. The encapsulant 310 may be applied in liquid or semi-liquid form and then cured thereafter. The encapsulant 310 may be a molding compound, epoxy, or the like.

As shown in the insets 401 and 402 of FIG. 4B , the encapsulant 310 may be formed around a lateral edge of the second side redistribution structure 206 of the second component 200 . The encapsulant 310 may partially or completely cover the lateral edge of the second component 200 . For example, as shown in inset 401 , encapsulant 310 can have a recessed upper surface with a peak positioned proximate to a lateral edge of second component 200 . The encapsulant 310 may partially or completely cover the lateral edge of the second side redistribution structure 206 . In some embodiments, the encapsulant 310 may further cover a portion of the lateral edge of the second carrier substrate 202 . Also, the lowest point on the upper surface may be below the portion of the second side redistribution structure 206 that is closest to the second carrier substrate 202 . As shown in the inset 402 , the encapsulant 310 covers all or a portion of the lateral edges of the second carrier substrate 202 as well as all of the lateral edges of the second side redistribution structure 206 . It may be formed to cover. In some embodiments, the encapsulant 310 may cover all of the lateral edges of the second carrier substrate 202 and even a portion of the upper surface of the second carrier substrate 202 (not specifically illustrated).

The encapsulant 310 provides additional support to the second side redistribution structure 206 , which makes the overall package 400 stronger, more reliable, and less susceptible to flexing. As explained above, the added strength and sturdiness comes from the upper portion of the encapsulant 310 attaching to the lateral edge of the second component 200 . The encapsulant 310 may be angled downward from the lateral edge of the second component 200 as shown in the inset 401 of FIG. 4B . The slope may have an angle θ from horizontal. The angle θ may be from about 0 degrees to about 45 degrees, or from about 45 degrees to about 60 degrees.

4C , the second carrier substrate 202 is removed from the package 400 exposing the second side redistribution structure 206 , in accordance with some embodiments. The second carrier substrate 202 may be detached, bonded, separated, or removed from the second side redistribution structure 206 using, for example, a thermal process to alter the adhesive properties of a release layer disposed on the second carrier substrate 202 . It can be physically peeled off. In some embodiments, an energy source, such as an ultraviolet (UV) laser, carbon dioxide (CO ₂ ) laser, or infrared (IR) laser, irradiates and heats the release layer until the release layer loses at least some of its adhesive properties. used If performed, the second carrier substrate 202 and the metal film 204 may be physically separated from the second side redistribution structure 206 and removed. In some embodiments, a planarization process or mechanical exfoliation process is performed to remove the second carrier substrate 202 to expose the second side redistribution structure 206 . The planarization process may also remove portions of the encapsulant 310 that may have formed over the top level of the second side redistribution structure 206 . The planarization process may be, for example, a chemical-mechanical polish (CMP), a grinding process, or the like. Even in embodiments in which the encapsulant 310 is formed to completely cover the lateral edges of the second component (and possibly over the top surface of the second carrier substrate 202 (eg, generally shown in the inset 402 of FIG. 4B ). )), the package 400 is not prone to forming creep on the top surface of the second side redistribution structure 206 due to the protection of the second carrier substrate 202 . Thus, after removal of the second carrier substrate 202 , the upper surface of the second carrier substrate 202 is free of the encapsulant 310 . As such, the top surface of the encapsulant 310 may be flush with or recessed from the top surface of the second side redistribution structure 206 .

With continued reference to FIG. 4C , in some embodiments, a passivation layer 320 is formed and patterned over the exposed second-side redistribution structure 206 . The passivation layer 320 may be a dielectric material formed in a manner and material similar to any one of the dielectric layers 110 , 114 , 118 and 112 . Alternatively, the passivation layer 320 may be a solder resist formed in a manner and material similar to the solder resist 222 .

In FIG. 4D , the package 400 may be flipped over and attached to a temporary substrate 406 such as a tape, wafer, panel, frame, ring, or the like. Then, the first carrier substrate 102 is removed. In some embodiments, carrier substrate bonding separation is performed to separate (or detach or bond separate) first carrier substrate 102 from first side redistribution structure 106 , such as dielectric layer 110 . According to some embodiments, the bonding separation is performed by light, such as laser light or UV light, on the release layer 104 such that the release layer 104 is thermally decomposed to allow the first carrier substrate 102 to be removed. including projecting

In FIG. 4E , a conductive connector 410 is formed on the first side redistribution structure 106 . The conductive connector 410 includes a ball grid array (BGA) connector, a solder ball, a metal pillar, a controlled collapse chip connection (C4) bump, a micro bump, and a bump formed by an electroless nickel-electroless palladium-immersion gold technique (ENEPIG). etc. The conductive connector 410 may include a conductive material such as solder, copper, aluminum, gold, nickel, silver, palladium, tin, or the like, or a combination thereof. In some embodiments, the conductive connector 410 is formed by initially forming a solder layer through evaporation, electroplating, printing, solder transfer, ball placement, or the like. Once the solder layer has been formed on the structure, a reflow may be performed to shape the material into the desired bump shape. In another embodiment, the conductive connector 410 includes metal pillars (eg, copper pillars) formed by sputtering, printing, electroplating, electroless plating, CVD, or the like. The metal pillars may be lead-free and may have substantially vertical sidewalls. In some embodiments, a metal cap layer is formed on top of the metal pillars. The metal cap layer may include nickel, tin, tin-lead, gold, silver, palladium, indium, nickel-palladium-gold, nickel-gold, etc., or combinations thereof, and may be formed by a plating process.

If not yet singulated, the structure may be singulated along the scribe region 404 (see eg, FIG. 4A ) to form individual packages 400 , in accordance with some embodiments. Alternatively, the structure is singulated prior to forming the conductive connector 410 . In some embodiments, the structure may be singulated using one or more saw blades that separate the package 400 into individual pieces, forming one or more individualized packages 400 . However, any suitable singulation method including laser grinding or one or more wet etching may also be used.

After singulation, the first side redistribution structure 106 has a width W ₁ , and the width W ₁ may be between about 3 mm and about 150 mm. The second component 200 and its second side redistribution structure 206 have a width W ₂ , and the width W ₂ can be between about 3 mm and about 150 mm. The width W ₂ may be less than or equal to the width W ₁ (eg, the width of the first component 100 and the first side redistribution structure 106 thereof). The ratio of the width W ₁ to the width W ₂ may be about 1 to about 3, or about 1. Ratios within this range provide an overall semiconductor package that is less susceptible to bending when the second side redistribution structure 206 is coupled to the first side redistribution structure 106 . In other words, the strength and width W ₂ of the second side redistribution structure 206 will balance out warpage that may occur from the first side redistribution structure 106 .

4F and 4G , after singulation, the package 400 is removed from the temporary substrate 406 and flipped over to be attached to another substrate, such as a substrate 502 (eg, carrier substrate, package substrate, PCB, etc.). can As shown, the package 400 may feature a passivation layer 320 ( FIG. 4F ), or the passivation layer 320 may be omitted ( FIG. 4G ). In some cases within package 400 , through via 126 may align with conductive via 218 as shown in the enlarged view of FIG. 4G . Depending on the method of formation, conductive vias 218 may have inwardly sloping sidewalls. In some cases, the inwardly sloping sidewalls may have a concave shape that provides an hourglass shape to the conductive vias 218 . In addition, conductive vias 218 may have tooth-shaped sidewalls. The tooth-like sidewalls may be due in part to the laser grinding method of drilling through the dielectric layer 212 as described above with respect to FIG. 3F .

In FIG. 4H , an embodiment similar to that described above with respect to FIG. 4F is illustrated in which an additional device 510 is attached to a substrate 502 . Additional devices 510 may include integrated passive components and active and/or passive components such as surface mount devices (SMDs) (eg, capacitors). Additionally, additional devices 510 include devices similar to integrated circuit die 50, and memory dies (eg, DRAM dies, stacked memory dies, high-bandwidth memory (HBM) dies, etc.), logic dies, CPUs ( A device designed for its intended purpose, such as a central processing unit) die, system-on-a-chip (SoC), component on a wafer (CoW), integrated fan-out structure (InFO), package, etc., or a combination thereof. may include.

5A-5H and 6A-6H illustrate the formation of a first component (including a first integrated circuit die 50), formation of a second component (a second integrated circuit die), in accordance with some embodiments. 50), and various intermediate steps in attaching the second component to the first component, and additional processing to form the semiconductor package.

5A-5H illustrate cross-sectional views of intermediate steps for forming a first component 501 , a second component 502 , and a package 504 in accordance with some embodiments. In particular, the figure shows certain intermediate steps in the formation of the first component 501 , the attachment of the second component 502 to the first component 501 , as well as further processing to form the package 504 . do.

In FIG. 5A , a first side redistribution structure 106 of a first component 501 has been provided, and a through via 126 and bond pads 128 have been formed over the first side redistribution structure 106 . Processes and materials similar to those described above with respect to FIGS. 2A-2F may be used. In FIG. 5B , a first integrated circuit die 50 is attached along with one or more other semiconductor devices 550 (only one is illustrated, but there may be a plurality of additional semiconductor devices). Processes and materials similar to those described above with respect to FIG. 2G may be used.

The first integrated circuit die 50 and other devices 550 include a memory die (eg, a DRAM die, a stacked memory die, a high-bandwidth memory (HBM) die, etc.), a logic die, a central processing unit (CPU) die, It may include a device designed for an intended purpose, such as a system-on-a-chip (SoC), component on a wafer (CoW), integrated fan-out structure (InFO), package, or the like, or a combination thereof. The first integrated circuit die 50 and the other device 550 may be formed in the process of the same technology node, or may be formed in the process of a different technology node. For example, the first integrated circuit die 50 may be comprised of a more advanced process node than the other devices 550 . The first integrated circuit die 50 and the other device 550 may have different sizes (eg, different heights and/or surface areas) or may have the same dimensions (eg, the same height and/or surface areas). An advantage of the first side redistribution structure 106 is that the integrated circuit die 50 , other devices 550 , a second component 502 that is later attached, and the other side of the first side redistribution structure 106 . It provides electrical connectivity between components that are later attached.

In some embodiments, the first integrated circuit die 50 and other devices include transistors, capacitors, inductors, resistors, metallization layers, external connectors, etc. therein as desired for specific functions. In some embodiments, the first integrated circuit die 50 and other devices may include more than one device of the same type, or may include different devices. 5B depicts a single integrated circuit die 50 , in some embodiments one, two, or more integrated circuit dies 50 or other devices may be attached to the first side redistribution structure 106 . 5B shows the integrated circuit die 50 as having a lower height than the through via 126 . This is to accommodate a second component 502 that will include another integrated circuit die (as shown in later figures). For example, the through via 126 may have a height H _TV of about 10 μm to about 200 μm, and the integrated circuit die 50 may have a height H _IC1 of about 30 μm to about 250 μm. can The ratio of the height H _TV to the height H _IC1 may be about 0.04 to 8.

In FIG. 5C , the second side redistribution structure 206 of the second component 502 has been provided, and a solder resist 222 may be formed and patterned to form an opening 228 in addition to the opening 224 . Processes and materials similar to those described above with respect to FIGS. 3A-3H may be used. Some or all of the openings 228 may expose portions of the conductive vias 218 and the second metal traces 220 . Openings 228 may be formed at the same time as openings 224 or at different times using the same or different patterning methods.

In FIG. 5D , a second integrated circuit die 50 may be attached to the second side redistribution structure 206 at the opening 228 and electrically coupled to the conductive vias 216 and the second metal traces 216 . can be Processes and materials similar to those described above with respect to FIGS. 2G and 5B may be used, including the formation of bond pads 528 , solder joints 530 , and underfill material 532 . Also, a connector 226 may be formed in the opening 224 .

In FIG. 5E , a second component including a second side redistribution structure 206 and a second integrated circuit die 50 , using processes and materials similar to those described above with respect to FIGS. 4A-4C . 502 is attached to the first component 501 , and the second carrier substrate 202 is removed. As described above with respect to package 400 , package 504 has a width W1 of first side redistribution structure 106 that is greater than width W2 of second side redistribution structure 206 . 4B to 4H , the encapsulant 310 may be formed around a lateral edge of the second-side redistribution structure 206 . As shown, the second component 502 is attached such that the backsides of the first integrated circuit die 50 and the second integrated circuit die 50 face each other. Either or both of the first and second integrated circuit dies 50 may have a dielectric layer 510 along their backside, which may then be interposed directly between the first and second integrated circuit dies 50 . have.

With continued reference to FIG. 5E , dielectric layer 510 may be similar to adhesive layer 70 and may be applied in a similar manner. The first and second integrated circuit die 50 may be vertically aligned such that at least a portion of the second integrated circuit die 50 is directly above at least a portion of the first integrated circuit die 50 . The first and second integrated circuit dies 50 may be centered with each other or alternatively may be positioned asymmetrically.

The package 504 may then be completed, as shown in FIGS. 5F-5H and in a similar manner, such as described above with respect to FIGS. 4D-4H . As shown in FIG. 5G , a third integrated circuit die 50 is fabricated using a process and materials similar to those described above with respect to FIGS. 2G , 5B, and 5D , the first side redistribution structure 106 . can be attached to and, as shown in FIG. 5H, a fourth integrated circuit die 50 and addition using processes and materials similar to those described above with respect to FIGS. 2G, 4H, 5B, 5D, and 6H. The device 550 of the may be attached to the second side redistribution structure 206 . Advantages of the illustrated layout include providing more space along the first side redistribution structure 106 to allow for a narrower package 504 in the horizontal direction and/or to attach additional devices.

As described above, the first side redistribution structure 106 and the second side redistribution structure 206 are separated by a thickness T ₃ . In this embodiment, the thickness T ₃ may be about 60 μm to about 500 μm. The ratio of the thickness T ₃ to the thickness T ₁ may be about 0.5 to about 25. The ratio of the thickness T ₃ to the thickness T ₂ may be about 0.4 to about 25. Also, the connector 226 may have a height H _C that is about 10 μm to about 300 μm, or about 150 μm. Thus, the total height of the through vias 126 and the connector 226 in the package 504 may be from about 50 μm to about 500 μm, or about 250 μm (the total height is the height H due to the reflow of the connector 226 ). Note that _C ) and height (H _TV ) may be less than the sum), which is substantially equal to the thickness T ₃ of the region between the first side redistribution structure 106 and the second side redistribution structure 206 . will be the same as As further shown in FIG. 5H , the total height of the first integrated circuit die 50 and the second integrated circuit die (height H _IC1 and H _IC2 , respectively, plus the thickness of the dielectric layer 510 ) ) will be substantially equal to the thickness T ₃ .

6A-6H illustrate cross-sectional views of intermediate steps for forming a package 604 in accordance with some embodiments. In particular, the figure shows certain intermediate steps in the formation of the first component 601 , the attachment of the second component 602 to the first component 601 , as well as further processing to form the package 604 . .

In FIG. 6A , a first side redistribution structure 106 of a first component 601 has been provided, and a through via 126 and bond pads 128 have been formed over the first side redistribution structure 106 . Processes and materials similar to those described above with respect to FIGS. 2A-2F and 5A may be used. In FIG. 6B , a first integrated circuit die 50 is attached along with one or more other semiconductor devices 650 . Processes and materials similar to those described above with respect to FIGS. 2G and 5B may be used. 6B shows the integrated circuit die 50 as having a lower height than the through via 126 . This is to accommodate a second component 602 that will include another integrated circuit die 50 . For example, the through via 126 may have a height H _TV of about 10 μm to about 300 μm, and the integrated circuit die 50 may have a height H _IC1 of about 30 μm to about 300 μm. can The ratio of the height H _TV to the height H _IC1 may be about 0.03 to about 10.

In FIG. 6C , the second side redistribution structure 206 of the second component 602 has been provided, and a solder resist 222 may be formed and patterned to form an opening 228 in addition to the opening 224 . Processes and materials similar to those described above with respect to FIGS. 3A-3H and 5C may be used. Some or all of the openings 228 may expose portions of the conductive vias 218 and the second metal traces 220 . Openings 228 may be formed at the same time as openings 224 or at different times using the same or different patterning methods.

In FIG. 6D , a second integrated circuit die 50 may be attached to the second side redistribution structure 206 at the opening 228 and electrically coupled to the conductive vias 216 and the second metal traces 216 . can be Processes and materials similar to those described above with respect to FIGS. 2G , 5B , 5D and 6B may be used, including the formation of bond pads 628 , solder joints 630 , and underfill material 632 . .

In FIG. 6E , a second component 602 including a second side redistribution structure 206 and a second integrated circuit die 50 is attached to the first component 601 , in FIGS. 4A-4C and 5E . The second carrier substrate 202 is removed using a process and material similar to that described above with respect to . As described above with respect to packages 400 and 504 , package 604 has a width ( W2 ) of first side redistribution structure 106 greater than width W2 of second side redistribution structure 206 . W1), and similarly as shown in FIGS. 4B to 4H , the encapsulant 310 may be formed around the lateral edge of the second-side redistribution structure 206 . As shown, the second component 602 is attached such that the second integrated circuit die 50 is laterally displaced from the first integrated circuit die 50 . The lateral displacement allows the back surface of the second integrated circuit die 50 to be lower than the back surface of the first integrated circuit die 50, but the back surface may be flush or the second integrated circuit die ( The back surface of 50 may be higher than the back surface of the first integrated circuit die 50 .

The package 604 may then be completed, as shown in FIGS. 6F-6H and in a manner similar to that described above with respect to, for example, FIGS. 4D-4H and 5F-5H . As shown in FIG. 6G, a third integrated circuit die 50 is first grown using processes and materials similar to those described above with respect to FIGS. 2G, 5B, 5D, 6B, and 6D. It may be attached to the ship structure 106 . Additionally, external connectors 610 may be formed to provide a means to later attach other integrated circuit devices or packages. And, as shown in Fig. 6H, a fourth method using similar processes and materials as described above with respect to Figs. 2G, 4H, 5B, 5D, 5G, 6B, 6D and 6G An integrated circuit die 50 and additional devices 650 may be attached to the second side redistribution structure 206 . Advantages of this layout include enabling a thinner package 604 .

As described above, the first side redistribution structure 106 and the second side redistribution structure 206 are separated by a thickness T ₃ . In this embodiment, the thickness T ₃ may be about 50 μm to about 500 μm. The ratio of the thickness T ₃ to the thickness T ₁ may be about 0.4 to about 25. A ratio of the thickness T ₃ to the thickness T ₂ may be about 0.03 to about 10. Also, the connector 226 may have a height H _C that is about 10 μm to about 300 μm, or about 150 μm. Thus, the total height of the through vias 126 and the connector 226 in the package 504 may be from about 100 μm to about 600 μm, or about 300 μm (the total height is the height H due to the reflow of the connector 226 ). Note that _C ) and height (H _TV ) may be less than the sum), which is substantially equal to the thickness T ₃ of the region between the first side redistribution structure 106 and the second side redistribution structure 206 . will be the same as As further shown in FIG. 5H , the thickness T ₃ is greater than the total height for stacking the first integrated circuit die 50 and the second integrated circuit die (height H _IC1 and height H _IC2 , respectively). smaller In other words, the lateral displacement of the first and second integrated circuit die 50 with respect to each other enables a smaller thickness T ₃ . In some embodiments, the thickness of the encapsulant 310 between the first side redistribution structure 106 and the back surface of the second integrated circuit die 50 may be from about 30 μm to about 300 μm, such as about 150 μm. have. Also, the thickness of the encapsulant 310 between the second-side redistribution structure 206 and the first integrated circuit die 50 may be about 30 μm to about 300 μm, for example, about 150 μm.

Embodiments may achieve advantages over system in package (SiP) structures for integrated circuits. For example, double-sided routing (eg, second side and first side redistribution structures) can make each routing side thinner and reduce overall package warpage while allowing a thinner overall semiconductor package. In addition, the carrier-type substrate used in one of the routing structures provides greater structural support and also reduces overall package warpage. The disclosed method also provides versatility in the layout of embedded integrated circuit dies and other devices. Indeed, vertically stacking the integrated circuit dies may provide sufficient space for additional devices to be attached to the first side redistribution structure, while laterally displacing the integrated circuit dies may result in an overall thinner package. structures can be made possible. It should also be noted that the first side redistribution structure may be wider than the second side redistribution structure, which allows an encapsulant to be formed around the second side redistribution structure to strengthen the package and further reduce overall package warpage. . Indeed, the disclosed method provides for application of the encapsulant in a manner that is free from fear of forming creep along the outer surface of the second side redistribution structure. This ensures that additional devices can be attached to the outer surface of the second side redistribution structure without interference from trace amounts of encapsulant.

In an embodiment, a semiconductor package is fabricated by attaching a first component to a second component. A first component is assembled by forming a first redistribution structure over a substrate. A through via is then formed over the first redistribution structure, and a die is attached below the active surface of the first redistribution structure. The second component includes a second redistribution structure, which is then attached to the through via. A further molding compound is deposited between the first redistribution structure and the second redistribution structure and around the side of the second component.

In another embodiment, a semiconductor package is fabricated by forming a first component, forming a second package component, and attaching the second component to the first component. The first component is formed by forming a redistribution structure over a substrate, forming a through via over the redistribution structure, and attaching a die to the redistribution structure. The second component is formed by forming another redistribution structure over another substrate, forming a connector over the redistribution structure, and attaching another die to the redistribution structure. The second component is attached by bonding the connector to the through via by flipping it over and reflowing the connector. After attachment, the substrate is removed from the second component.

In another embodiment, a semiconductor package includes a first redistribution structure on a substrate and a second redistribution structure stacked on an upper portion of the first redistribution structure. The second redistribution structure includes conductive vias. The first redistribution structure is wider than the second redistribution structure. A through via electrically couples the first redistribution structure to the second redistribution structure. A die is attached to the first redistribution structure and an active side of the die faces and is electrically coupled to the first redistribution structure. Another die is attached to the second redistribution structure and an active side of the die faces and is electrically coupled to the second redistribution structure. An encapsulant fills an area between the first redistribution structure and the second redistribution structure.

The foregoing has set forth features of several embodiments so that those skilled in the art may better understand aspects of the present disclosure. Those skilled in the art should appreciate that they can readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages as the embodiments introduced herein. do. Those skilled in the art should also appreciate that such equivalent constructions do not depart from the true meaning and scope of the present disclosure, and that various changes, substitutions and alterations may be made without departing from the true meaning and scope of the present disclosure.

Example

Embodiment 1. A method of forming a semiconductor package, comprising:

forming a first component, comprising:

forming a first redistribution structure on the first substrate;

forming a through via on the first redistribution structure;

attaching a first die to the first redistribution structure, an active side of the first die facing the first redistribution structure and electrically coupled to the first redistribution structure;

forming the first component comprising;

attaching a second component to the through via, the second component including a second redistribution structure attached to a second substrate; and

after attaching the second component, depositing a molding compound between the first redistribution structure and the second redistribution structure, wherein a portion of the molding compound forms lateral edges of the second redistribution structure. ) enclosing -

A method of forming a semiconductor package comprising:

Example 2. The method of Example 1,

forming the second redistribution structure on the second substrate;

attaching a second die to the second redistribution structure, an active side of the second die facing the second redistribution structure and electrically coupled to the second redistribution structure; and

depositing solder balls over the second redistribution structure;

Further comprising a method of forming a semiconductor package.

Embodiment 3. The method of embodiment 2, wherein attaching the second component comprises reflowing the solder ball to electrically couple the through via to the second redistribution structure. A method of forming a semiconductor package.

Embodiment 4. The method of embodiment 2, wherein attaching the second component comprises attaching the second component such that the second die is directly above the first die, the back side of the first die and facing the backside of the second die.

Embodiment 5. The method of embodiment 2, wherein attaching the second component comprises attaching the second component such that the second die is laterally displaced from the first die; and a lateral side of the first die faces a lateral side of the second die.

Embodiment 6. The method of Embodiment 2, wherein the forming of the second redistribution structure comprises:

forming a first metal trace on the second substrate;

depositing an Ajinomoto Build-up Film (ABF) over the first metal trace;

laser drilling an opening in the ABF;

forming a conductive via in the opening; and

forming a second metal trace over the conductive via;

A method of forming a semiconductor package comprising a.

Example 7. The method of Example 1,

removing the second substrate; and

attaching a passive element to the second redistribution structure after removing the second substrate;

Further comprising a method of forming a semiconductor package.

Embodiment 8. A semiconductor package, comprising:

As a first component,

a first redistribution structure;

a through via disposed over the first redistribution structure; and

a first die attached to the first redistribution structure, an active side of the first die facing the first redistribution structure;

the first component comprising;

As a second component,

a second redistribution structure;

a connector coupling the through via to the second redistribution structure; and

a second die attached to a first side of the second redistribution structure, an active side of the second die facing the second redistribution structure;

the second component comprising; and

An encapsulant disposed between the first redistribution structure and the second redistribution structure

A semiconductor package comprising a.

Embodiment 9 The semiconductor package of embodiment 8, wherein the encapsulant encapsulates lateral edges of the first die and the second die.

Embodiment 10 The semiconductor package of Embodiment 9, wherein the encapsulant contacts a lateral edge of the second redistribution structure.

Example 11. The method of Example 8,

a passivation layer disposed over a second side of the second redistribution structure, the second side opposite the first side; and

a third die disposed over the passivation layer on the second side of the second redistribution structure

Further comprising a, semiconductor package.

Embodiment 12 The semiconductor package of embodiment 8, wherein in a top view, a portion of the second die overlaps a portion of the first die.

Embodiment 13 The semiconductor package of embodiment 8, wherein the second die is laterally displaced from the first die.

Embodiment 14. The semiconductor package of embodiment 8, further comprising a passive element attached to the second surface of the second redistribution structure.

Example 15. A semiconductor package comprising:

a first redistribution structure having a first width;

a second redistribution structure disposed over the first redistribution structure, wherein the second redistribution structure includes conductive vias extending from a first metal trace to a second metal trace, wherein the first metal trace comprises the second redistribution structure It is disposed along a first surface of the wire structure, the second metal trace is disposed along a second surface of the second redistribution structure, the second redistribution structure has a second width, and the first width is greater than the second width;

a first die attached to the first redistribution structure, a first active side of the first die facing the first redistribution structure and electrically coupled to the first redistribution structure;

a second die attached to the second redistribution structure, a second active side of the second die facing the second redistribution structure and electrically coupled to the second redistribution structure;

an encapsulant directly interposed between the first redistribution structure and the second redistribution structure; and

a through via extending through the encapsulant, the through via electrically coupling the first redistribution structure to the second redistribution structure;

A semiconductor package comprising a.

Embodiment 16 The encapsulant of embodiment 15, wherein the encapsulant is disposed on all of the lateral edges of the first die, all of the lateral edges of the second die, and at least a portion of the lateral edges of the second redistribution structure. contact, the semiconductor package.

Embodiment 17 The semiconductor package of Embodiment 15, wherein the first redistribution structure is a fan-out redistribution structure.

Embodiment 18. The semiconductor package of embodiment 15, wherein the conductive via is disposed directly over the through via and electrically coupled to the through via.

Embodiment 19. The first die of embodiment 15, wherein the first die comprises a first back side opposite the first active side, and the second die comprises a second back side opposite the second active side. and the second rear surface is closer to the first redistribution structure than from the first rear surface to the first redistribution structure.

Embodiment 20 The semiconductor package of Embodiment 15, further comprising a passive element attached to and electrically coupled to a side of the second redistribution structure opposite to the first redistribution structure.

Claims (10)

A method of forming a semiconductor package, comprising:
forming a first component, comprising:
forming a first redistribution structure on the first substrate;
forming a through via on the first redistribution structure;
attaching a first die to the first redistribution structure, an active side of the first die facing the first redistribution structure and electrically coupled to the first redistribution structure;
forming the first component comprising;
attaching a second component to the through via, the second component including a second redistribution structure attached to a second substrate; and
after attaching the second component, depositing a molding compound between the first redistribution structure and the second redistribution structure, wherein a portion of the molding compound forms lateral edges of the second redistribution structure. ) enclosing -
A method of forming a semiconductor package comprising: The method according to claim 1,
forming the second redistribution structure on the second substrate;
attaching a second die to the second redistribution structure, an active side of the second die facing the second redistribution structure and electrically coupled to the second redistribution structure; and
depositing solder balls over the second redistribution structure;
Further comprising a method of forming a semiconductor package. 3. The method of claim 2, wherein attaching the second component comprises reflowing the solder ball to electrically couple the through via to the second redistribution structure. Way. 3. The method of claim 2, wherein attaching the second component comprises attaching the second component such that the second die is directly above the first die, wherein the backside of the first die is the second die A method of forming a semiconductor package that faces the rear surface of the. 3. The method of claim 2, wherein attaching the second component comprises attaching the second component such that the second die is laterally displaced from the first die. and a lateral side facing the lateral side of the second die. The method according to claim 2, wherein the forming of the second redistribution structure comprises:
forming a first metal trace on the second substrate;
depositing an Ajinomoto Build-up Film (ABF) over the first metal trace;
laser drilling an opening in the ABF;
forming a conductive via in the opening; and
forming a second metal trace over the conductive via;
A method of forming a semiconductor package comprising a. The method according to claim 1,
removing the second substrate; and
attaching a passive element to the second redistribution structure after removing the second substrate;
Further comprising a method of forming a semiconductor package. In the semiconductor package,
As a first component,
a first redistribution structure;
a through via disposed over the first redistribution structure; and
a first die attached to the first redistribution structure, an active side of the first die facing the first redistribution structure;
the first component comprising;
As a second component,
a second redistribution structure;
a connector coupling the through via to the second redistribution structure; and
a second die attached to a first side of the second redistribution structure, an active side of the second die facing the second redistribution structure;
the second component comprising; and
an encapsulant disposed between the first redistribution structure and the second redistribution structure, the encapsulant contacting a lateral edge of the second redistribution structure;
A semiconductor package comprising a. The semiconductor package of claim 8 , wherein the encapsulant encapsulates lateral edges of the first die and the second die. In the semiconductor package,
a first redistribution structure having a first width;
a second redistribution structure disposed over the first redistribution structure, wherein the second redistribution structure includes conductive vias extending from a first metal trace to a second metal trace, wherein the first metal trace comprises the second redistribution structure It is disposed along a first surface of the wire structure, the second metal trace is disposed along a second surface of the second redistribution structure, the second redistribution structure has a second width, and the first width is greater than the second width;
a first die attached to the first redistribution structure, a first active side of the first die facing the first redistribution structure and electrically coupled to the first redistribution structure;
a second die attached to the second redistribution structure, a second active side of the second die facing the second redistribution structure and electrically coupled to the second redistribution structure;
an encapsulant directly interposed between the first redistribution structure and the second redistribution structure; and
a through via extending through the encapsulant, the through via electrically coupling the first redistribution structure to the second redistribution structure;
A semiconductor package comprising a.

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