KR102423124B1 - QCA universal shift register using multiplexer and D flip-flop based on electronic correlations - Google Patents

Abstract

The present invention relates to a QCA general-purpose shift register using an electronic correlation-based multiplexer and a D flip-flop. A QCA general-purpose shift register according to the present invention has N QCA D flip-flops connected in series, and according to a combination of a mode select signal and a clock signal, register operation including stored data hold, data shift, and parallel data load Receives a QCA shift register performing any one operation and a mode selection signal, and transmits a signal to each of the N QCA D flip-flops so that the QCA shift register performs any one of the register operations according to the mode selection signal and first to nth QCA multiplexers. According to the present invention, it is possible to provide a QCA general-purpose shift register with simplified spatiotemporal complexity using quantum dot cellular automata.

Description

QCA universal shift register using multiplexer and D flip-flop based on electronic correlations

The present invention relates to a quantum-dot cellular automata (QCA) general-purpose shift register using an electron correlation-based multiplexer and a D flip-flop.

Moore's Law, published by Gordon Moore, has been successfully achieved through the miniaturization and power increase of transistors through VLSI technology, along with the performance of semiconductor integrated circuits doubling every 18 months. However, due to the physical limitations of CMOS (Complementary Metal-Oxide Semiconductor) technology, it is difficult to expect further development, so a new alternative technology is needed.

Quantum-dot Cellular Automata (QCA) is a technology that can overcome the limitations of conventional CMOS technology. It is a nano-sized device at the molecular or atomic level, and consumes extremely low power to design the next generation of electronic circuits. is popular in The basic building block of a QCA circuit implementation is a very compact QCA cell, so it is extremely dense. In addition, each technical and exploratory investigation into QCA enables the design of QCA circuits that can perform at high operating frequency (㎔) wavelengths with minimal energy consumption.

Meanwhile, a universal shift register (USR) is a register that stores bit information, and may shift data to the left or right when a clock signal is applied. Various structures have been proposed to implement such a general-purpose shift register using QCA technology, and the proposed QCA general-purpose shift register consists of a multiplexer and a shift register using a D flip-flop.

Multiplexers and D flip-flops are components that are widely used in digital logic system design, and many studies have been conducted to design efficient multiplexers and D flip-flops. In this study, a multiplexer or D flip-flop is constructed using multiple gates and inverters.

However, this method increases the number of cells, area and latency of the circuit, and various general-purpose shift registers based on QCA using these multiplexers and D flip-flops still have many flaws in time complexity, space complexity, etc.

Therefore, it is necessary to design a multiplexer and D flip-flop with reduced space-time complexity and consider a QCA general-purpose shift register having a structure that is very efficient in terms of space-time complexity and energy dissipation by using it.

Accordingly, it is an object of the present invention to provide a QCA general-purpose shift register having a structure with high efficiency in terms of space-time complexity and energy dissipation by using a multiplexer and a D flip-flop with reduced space-time complexity.

A QCA general-purpose shift register according to the present invention for achieving the above object is provided, and N series-connected QCA D flip-flops are provided, and according to a combination of a mode selection signal and a clock signal, stored data retention, data shift, and parallel data load A QCA shift register that performs any one of the register operations including and first to n-th QCA multiplexers for transferring signals to QCA D flip-flops, respectively.

The QCA multiplexer includes a first 2-to-1 QCA multiplexer that outputs any one of the first and second input signals as a first output signal according to a first mode selection signal, and a third and a second two-to-one QCA multiplexer for outputting any one of the fourth input signals as a second output signal, and a third two units for outputting any one of the first and second output signals according to a second mode selection signal 1 QCA multiplexer may be included.

In addition, the QCA 2-to-1 multiplexer includes first to fifth cells arranged horizontally adjacent to each other in series, a sixth cell vertically adjacent to the second cell, and a seventh cell vertically adjacent to the fourth cell. cell, a first fixed cell disposed adjacent to the first cell to input a signal corresponding to logic bit 0, a second fixed cell disposed adjacent to the fifth cell and configured to input a signal corresponding to logic bit 1; a first input cell disposed adjacent to the first and sixth cells to receive a first input signal; a second input cell disposed adjacent to the fifth and seventh cells to receive a second input signal; It may include a selection cell disposed diagonally to the sixth and seventh cells to receive a selection signal, and an output cell disposed vertically adjacent to the third cell to output an output signal.

In addition, the QCA D flip-flop includes first and second combinational logic cells performing an AND gate function, a third combinational logic cell receiving the clock signal and outputting an inverted signal, and the first and second combinations and a fourth combinational logic cell receiving an output signal of a logic cell and performing an OR gate function to output a flip-flop output signal, wherein the clock signal and 1-bit data are input to the first combinational logic cell; The output of the third combinational logic cell and the flip-flop output signal may be input to the second combinational logic cell.

And, in order to achieve the above object, in the present invention, it is possible to provide a quantum dot cellular automata device including the QCA general-purpose shift register.

According to the present invention, it is possible to provide a QCA general-purpose shift register having high energy efficiency using quantum dot cellular automata and excellent performance in terms of area, waiting time, and number of cells. In addition, the QCA general-purpose shift register and the QCA multiplexer and QCA D flip-flop used therein can be utilized in various combinational circuits or sequential circuits. In addition, the QCA multiplexer, QCA D flip-flop, and QCA general-purpose shift register according to the present invention use a structure that maximizes modularity and expandability, thereby maximizing circuit expandability and connectivity with other circuits. In addition, the QCA general-purpose shift resistor according to the present invention can be efficiently used in various devices using quantum dot cellular automata.

1 is a diagram referenced to explain a quantum dot cellular automata;
2 is a diagram referenced in the description of QCA wiring;
3 is a view showing the configuration of a logical combination cell capable of performing a majority vote gate function;
4 is a diagram illustrating a QCA clock having four clocking zones;
5 is a diagram showing the structure of a QCA 2 to 1 multiplexer used in the present invention;
6 is a logic diagram of a QCA 4 to 1 multiplexer used in the present invention;
7 is a diagram showing the structure of a QCA 4 to 1 multiplexer used in the present invention;
8 is a logic diagram of a QCA D flip-flop used in the present invention;
9 and 10 are diagrams showing the structure of the D flip-flop proposed in the previous study;
11 is a diagram showing the structure of a QCA D flip-flop used in the present invention;
12 is a logic diagram of a QCA shift register used in the present invention;
13 is a diagram showing the structure of a QCA shift register used in the present invention;
14 is a logic diagram of a QCA general-purpose shift register according to an embodiment of the present invention;
15 is a diagram showing the structure of a QCA general-purpose shift resistor according to an embodiment of the present invention;
16 is a view showing a simulation result of the QCA 2 to 1 multiplexer shown in FIG. 5;
17 is a view showing a simulation result of the QCA D flip-flop shown in FIG. 11, and
18 is a diagram illustrating a power dissipation map of the QCA 4 to 1 multiplexer shown in FIG. 7 and the QCA D flip-flop shown in FIG. 11 .

In this specification, when a component is referred to as being “connected” or “connected” to another component, the component may be directly connected or connected to another component, but another component in between. It should be understood that elements may exist. Also, other expressions describing the relationship between elements, such as "between" or "neighboring", etc., such as that one element "transmits" a signal to another element, should be interpreted similarly. do.

Hereinafter, the present invention will be described in more detail with reference to the drawings.

1 is a diagram referenced to describe a quantum dot cellular automata.

Quantum-dot Cellular Automata (QCA) has advantages such as high operating speed in the ㎔ range, low power consumption of about 100 W/cm2, and high device density of about 1012 devices/cm2.

Referring to FIG. 1 , a QCA cell is usually composed of four quantum-dots in a rectangular structure, and has two transient electrons capable of tunneling between the quantum-dots. Due to the coulombic repulsion, the two electrons are located diagonally in the cell. That is, as shown in (b) and (c) of FIG. 1, the transient electrons are located at the diagonals of 45° and -45°.

The QCA cell has two types of polarization with energy equivalent, and as shown in FIG. 1 (b), P = +1 polarization corresponding to logic bit 1, As shown, it can be represented by P=-1 polarization corresponding to 0 of the logic bit.

2 is a diagram referred to in the description of the QCA wiring.

Referring to FIG. 2 , the QCA wiring can be viewed as a series of horizontal cells that transmit information from one cell to another. When information encoded in a QCA cell is transmitted due to Coulomb interaction between neighboring QCA cells, the state of one cell affects the state of another cell.

QCA wiring is usually separated via different clock pulses to ensure that the signal is not degraded, but the signal can often be corrupted when using long chains of cells with the same clock phase.

2A shows a basic QCA wiring, an input value appears as an output value. In such a QCA wiring, when a value of “0” or “1” is input to the first input cell, the input value can be propagated to the adjacent cell while pushing out nearby electrons.

The structure in which the rotated cells are arranged as shown in FIG. 2B is called an inverter chain, and the inverted value is transmitted to the neighboring cells by the Coulomb repulsion force.

2 (c) or (d) shows a general QCA inverter. When QCA cells are arranged diagonally, the direction of the transient electrons is changed by the Coulomb repulsion force, and an inverted value can be output to the input value. have.

3 shows the configuration of a logical combination cell capable of performing a majority gate function.

As shown in Fig. 3, the 3-input majority vote gate consists of 3-input, 1-output, and a center cell. The following equation shows the function of the majority gate.

The basic logic gates, AND gates and OR gates, can be constructed using a three-input majority vote gater. That is, an AND gate or an OR gate can be made by fixing one of the three inputs to 0 or 1.

4 shows a QCA clock having four clocking zones.

The QCA circuit uses a clock system to synchronize and manage data transfers. In other words, since the electrons in quantum dots require high potential energy to tunnel through the junction, QCA clocking plays a very important role in the synchronization and flow of information along a specific direction.

As shown in Figure 4, the QCA circuit generally uses a clock with four clock phases such as switch, hold, release and relax, and the clock is essentially data can be viewed as a continuous pumping pump. The QCA clock system uses four clock phases to adjust the cell, and QCA clocking can be used for wire crossings.

During the switch phase, the inter-dot barrier is improved and the process remains stable in the hold phase. This means that all cells are polarized and the actual calculation is performed during these two steps. In the release phase, the barrier is lowered and the polarization of the cell is reduced. Eventually, the cell becomes completely unpolarized in the relaxation phase. In every cycle, deactivated cells are refreshed. Power consumption is low in QCA because only two excess electrons are moving. Most of the power is spent on the clocking scheme.

On the other hand, a multiplexer (multiplxer) is a combination circuit, selects one of the inputs and transmits them to the output line. As shown in [Table 1], when S is 0 and 1 in the 2-to-1 multiplexer, I0 and I1 are selected as output values, respectively.

S
Output
0
I0(A)
One
I1(B)

As shown in [Table 2], when the values of S0 and S1 are 00, 10, 01, and 11, respectively, in the 4-to-1 multiplexer, I0, I1, I2 and I3 are selected as output values, respectively.

S0
S1
Output
0
0
I0
One
0
I1
0
One
I2
One
One
I3

5 is a diagram showing the structure of a QCA 2 to 1 multiplexer used in the present invention.

Referring to FIG. 5 , the QCA 2 to 1 multiplexer 100 is vertically adjacent to the first to fifth cells 101 , 102 , 103 , 104 , 105 and the second cell 102 arranged horizontally in series. The sixth cell 106 disposed adjacent to each other, the seventh cell 107 disposed vertically adjacent to the fourth cell 104, and the first cell 101 disposed adjacent to each other to input a signal corresponding to logic bit 0 are disposed adjacent to the first fixed cell 108 and the fifth cell 105, the second fixed cell 109, the first and sixth cells 101 and 106 inputting a signal corresponding to the logic bit 1. It is disposed adjacent to the first input cell 110 , the fifth cell 105 , and the seventh cell 107 to which the first input signal I0 is input, and is disposed adjacent to the second input signal I1 to be inputted. The second input cell 111 , the sixth cell 106 , and the seventh cell 107 are diagonally disposed and vertically adjacent to the selection cell 112 to which the selection signal S is input, and the third cell 103 . It may include an output cell 113 disposed to output an output signal.

With this configuration, when the selection signal S is 0, it is possible to output I0 as an output signal, and when the selection signal S is 1, it is possible to output I1 as an output signal. In this way, unlike the existing majority gate-based circuit design, an optimal 2-to-1 multiplexer can be configured in consideration of the electron correlation between cells.

6 is a logic diagram of a QCA 4 to 1 multiplexer used in the present invention.

Referring to FIG. 6 , three 2-to-1 multiplexers are used, and a selection signal is inputted in the middle, and a symmetrically designed 4-to-1 multiplexer can be configured.

7 is a diagram showing the structure of a QCA 4 to 1 multiplexer used in the present invention.

Referring to FIG. 7 , the QCA 4-to-1 multiplexer 200 includes first to third QCA 2-to-1 multiplexers 100a, 100b, and 100c, and cells to which selection signals S0 and S1 are input. is placed in the middle and designed in a symmetrical structure to optimize modularity and expandability.

8 is a logic diagram of a QCA D flip-flop used in the present invention.

Referring to FIG. 8 , a D flip-flop may be configured with two AND gates, one OR gate, and one inverter.

The D flip-flop of this configuration is a circuit that detects the edge of the clock and reflects it to the output. If the clock is 0, the output remains unchanged regardless of the input value D. If the clock is 1, the input value D is output directly.

9 and 10 show the structure of a typical QCA D flip-flop proposed in the previous study.

The configuration of the D flip-flop shown in FIG. 9 uses a powerful inverter to increase signal strength, but uses a large number of cells and has low space efficiency.

The configuration of the D flip-flop shown in FIG. 10 uses an inverter having a simple structure, but has a disadvantage in that it requires a large number of clocks.

11 is a diagram showing the structure of a QCA D flip-flop used in the present invention.

11, the QCA D flip-flop 300 receives the first combination logic cell 310 and the second combination logic cell 320, which perform an AND gate function, and a clock signal C, and inverts it. The third combinational logic cell 330 for outputting one signal and the fourth combinational logic cell 330 and the first and second combinational logic cells 310 and 320 receive output signals, perform an OR gate function, and output a flip-flop output signal It may include a combinational logic cell 340 .

A clock signal C and 1-bit data D are input to the first combination logic cell 310, and a signal obtained by inverting the clock signal C, which is an output of the third combination logic cell 340, to the second combination logic cell 320; A flip-flop output signal that is an output of the fourth combinational logic cell 340 is input.

In this way, the first and second combinational logic cells 310 and 320 that perform an AND gate function are arranged in a fixed cell having one fixed value, and a third combinational logic that performs a NOT gate function of a simple structure. By using the cell 330, space efficiency can be maximized.

12 is a logic diagram of a QCA shift register used in the present invention.

Referring to FIG. 12 , a shift register includes a series of flip-flops, and is a circuit for shifting stored information by one bit every cycle. A clock pulse is applied synchronously to each D flip-flop, and the D value input to the D flip-flop moves from Q1 to Q4 at each clock. Shift registers can be classified into various types according to their input and output types.

13 is a diagram showing the structure of a QCA shift register used in the present invention.

The QCA shift register 400 shown in FIG. 13 has a 4-bit structure including four QCA D flip-flops 300a, 300b, 300c, and 300d, and the QCA D flip-flops 300a, 300b, 300c, and 300d The number may increase or decrease according to an increase or decrease in the number of bits used. The clock pulse signal C is synchronously applied to the QCA D flip-flops 300a, 300b, 300c, and 300d, respectively, and the value input to the QCA D flip-flops 300a, 300b, 300c, 300d is shifted in each clock signal do.

14 is a logic diagram of a QCA general-purpose shift register according to an embodiment of the present invention.

Referring to FIG. 14, the general-purpose shift register is a combination circuit that shifts bit information left and right according to the application of a clock signal.

The following [Table 3] shows the operation of the register when the selection signals S1 and S0 are 00, 01, 10 and 11. That is, it shows that it operates with unchanging motion, right shift, left shift, and parallel data load depending on the selection signal.

S1
S2
Register operation
0
0
Unchanged
0
One
Shift-right
One
0
shift_left
One
One
Parallel data loading

In Figure 14, I1-I4 are for parallel input, there are output values from Out0 to Out3, and clear resets the register. And, when the selection signal value is 00, the bit value of each D flip-flop does not change its position, and when the selection signal is 01 or 10, the value shifts to the right (or left) D flip-flop, and the leftmost ( (or rightmost) D flip-flop is input directly through the serial line. Finally, when the selection signal value is 11, it is inputted in parallel with I4, I3, I2 and I1.

15 is a diagram showing the structure of a QCA general-purpose shift register according to an embodiment of the present invention.

15, the QCA general-purpose shift register 500 includes first to fourth QCA multiplexers 200a, 200b, 200c, and 200d, and first to fourth QCA D flip-flops 300a, 300b, 300c, 300d) may be included.

The first to fourth QCA D flip-flops 300a, 300b, 300c, and 300d constitute a shift register, and the QCA multiplexers 200a, 200b, 200c, 200d and QCA D flip-flops 300a, 300b, 300c, and 300d). The number of may be increased or decreased according to an increase or decrease in the number of bits to be used.

The first to fourth D flip-flops 300a, 300b, 300c, and 300d constitute a shift register in a series-connected structure in which the output of the front-end flip-flop is connected to the input of the rear-end flip-flop, and the first to fourth QCA multiplexers ( According to a combination of the mode selection signal and the clock signal transmitted from 200a, 200b, 200c, and 200d), any one of a register operation including storing stored data, shifting data, and loading parallel data may be performed. The QCA multiplexers 200a, 200b, 200c, and 200d receive the mode selection signal, and according to the input mode selection signal, the first to fourth QCA D flip-flops 300a, 300b, 300c, 300d constituting the shift register. A signal is passed to cause any one of register operations to be performed, including holding stored data, shifting data, and loading parallel data.

FIG. 16 shows simulation results for the QCA 2 to 1 multiplexer shown in FIG. 5 .

As shown in Fig. 16, the components used in the present invention can be simulated using the QCADesigner tool.

The QCA 2-to-1 multiplexer 100 used in the present invention has a very simple configuration, unlike a conventional multiple gate-based circuit. Therefore, the QCA 2-to-1 multiplexer 100 used in the present invention has a small area and a short waiting time.

In addition, the QCA multiplexers 100 and 200 used in the present invention have a new structure utilizing the interaction between electrons in order to overcome the limitations on the area and waiting time of the circuit design using the existing majority gate.

In the following [Table 4], in the case of 2-to-1, the QCA 2-to-1 multiplexer 100 according to the present invention and the QCA multiplexer proposed by Mardiris VA and the like (Mardiris VA, Karafyllidis IG (2009) Design and simulation of Modular 2 to 1 quantum-dot cellular automata (QCA) multiplexers. Int J Circuit Theory Appl 38(8):771-785), QCA multiplexer proposed by Hashemi S et al. (Hashemi S, Navi K (2012) New robust QCA D flip flop and memory structures. Microelectron J 43(12):929-940), a QCA multiplexer proposed by Roohi A et al. (Roohi A, Khademolhosseini H, Sayedsalehi S, Navi K (2011) A novel architecture for quantum-dot cellular automata multiplexer. Int J Comput Sci 8(6):55-60), Sen B et al. (Sen B, Goswami M, Mazumdar S, Sikdar BK (2015) Towards modular design of reliable quantumdot cellular automata logic circuit using multiplexers. Comput Electron Eng 45:42-54), Das JC. The QCA multiplexer proposed by Das JC, De DD (2016) Optimized multiplexer design and simulation using quantum dotcellular automata. Indian J Pure Appl Phys 54:802-811, Das JC et al. (Das JC, De D (2016) ) Shannon's expansion theorem-based multiplexer synthesis using QCA. Nanomater Energy 5:53-60), QCA multiplexer proposed by Singh S et al. (Singh S, Pandey S, Wairya S (2016) Modular design of 2n:1 quantum dot cellular automata multiplexers and its application, via clock zone based crossover. Int J Modern Educ Comput Sci 7:41-52).

In addition, in [Table 4], in the case of 4-to-1, the QCA 4 to 1 multiplexer 200 according to the present invention and the QCA multiplexer proposed by Ahmad F (Ahmad F (2018) An optimal design of QCA based 2n: 1/1:2n multiplexer/demultiplexer and its efficient digital logic realization. Microprocess Microsyst 56:64-75), a QCA multiplexer proposed by Purkayastha T et al. (Purkayastha T, De D, Chattopadhyay T (2018) Universal shift register implementation using quantum dot Ain Shams Eng J 9:291-310) was compared and summarized.

Structure

cell count
Area(n㎡)
Latency
(clock phase)
AT product 2-to-1 QCA multiplexer proposed by Mardiris VA et al.
62
0.08
4
0.32 QCA multiplexer proposed by Hashemi S et al.
38
0.05
4
0.20 QCA multiplexer proposed by Roohi A et al.
27
0.03
3
0.09 Das J.C. QCA multiplexer proposed by et al.
23
0.02
2
0.04 Das J.C. QCA multiplexer proposed by et al.
17
0.01
2
0.02 QCA multiplexer proposed by Das JC et al.
21
0.02
3
0.06 QCA multiplexer proposed by Singh S et al.
18
0.02
2
0.04 QCA 2 to 1 multiplexer according to the present invention
13
0.01
One
0.01 4-to-1 QCA multiplexer proposed by Ahmad F
79
0.11
6
0.66 QCA multiplexer proposed by Purkayastha T et al.
101
0.11
5
0.55 QCA according to the invention
4 to 1 multiplexer
69
0.08
4
0.32

In [Table 4], AT Product means the product of area and waiting time, and as shown in [Table 4], the QCA 2-to-1 multiplexer 100 according to the present invention reduces the number of cells by 19% compared to the conventional best circuit. It can be seen that the waiting time is only 1/2. In addition, it can be seen that the QCA 4 to 1 multiplexer 200 according to the present invention reduces the number of cells by about 38% and the waiting time by 25% compared to the conventional best circuit.

FIG. 17 shows simulation results for the QCA D flip-flop shown in FIG. 11 .

The QCA D flip-flop 300 used in the present invention can be used in a 4-bit general-purpose shift register that minimizes the AT product by minimizing space complexity. In addition, the QCA D flip-flop 300 used in the present invention has very low energy consumption.

The following [Table 5] shows the QCA D flip-flop 300 used in the present invention and the QCA D flip-flop proposed by Hashemi S et al. (Hashemi S, Navi K (2012) New robust QCA D flip flop and memory structures. Microelectron J 43(12):929-940) and the QCA D flip-flop proposed by Das JC et al. (Das JC, De D (2016) Shannon's expansion theorem-based multiplexer synthesis using QCA. Nanomater Energy 5:53-60) and summarized did it

Structure

cell count
Area(n㎡)
Latency
(clock phase)
AT product QCA D flip-flop proposed by Hashemi S et al.
46
0.05
5
0.25 QCA D flip-flop proposed by Das JC et al.
34
0.03
3
0.09 QCA D flip-flop according to the present invention
24
0.02
4
0.08

As shown in Table 5, the QCA D flip-flop 300 used in the present invention when using one or more clock phases reduces the number and area of cells by 56% and 67%, respectively, compared to the previously designed structure. it can be seen that

The following [Table 6] shows the QCA general-purpose shift register 500 and Sabbaghi-Nadooshan R according to the present invention. The QCA universal shift register proposed by Sabbaghi-Nadooshan R, Kianpour M (2014) A novel QCA implementation of MUX-based universal shift register. J Comput Electron 13(1):198-210), proposed by Purkayastha T et al. Comparing and organizing shift registers (Purkayastha T, De D, Chattopadhyay T (2018) Universal shift register implementation using quantum dot cellular automata. Ain Shams Eng J 9:291-310).

Structure
cell count

Area(n㎡)
Latency
(clock phase)
AT product Sabbaghi-Nadooshan R QCA general-purpose shift register proposed by et al.
1954
3.06
37
113.22 QCA universal shift register proposed by Purkayastha T et al.
1286
1.59
16
25.44 QCA universal shift register according to the present invention
1048
1.04
13
13.52

As shown in [Table 6], it can be seen that, in the QCA general-purpose shift register 500 according to the present invention, compared to the previously designed structure, the number and area of cells are reduced by almost 40%, and the waiting time is reduced by 44%. have.

FIG. 18 shows a power dissipation map. FIG. 18 (a) is a QCA 4 to 1 multiplexer shown in FIG. 7, and FIG. 18 (b) is a power dissipation map for the QCA D flip-flop shown in FIG. indicates.

To determine the power dissipation and polarization of a QCA cell, quantum mechanical calculations computed by the Hamilton matrix are required. A Hamiltonian matrix using Hartree-Fock approximation is used to compute the power analysis of the QCA cell array.

Hamilton's expression is as follows.

Here the sum is above the cell near the region. Ek is the “polarization energy” or energy cost of two adjacent cells with opposite polarizations, fi is the geometrical factor that captures the static reduction with the distance between cells, and Pi is the polarization of the i-th cell.

를 나타내기 위해

를 사용하여 표기법을 더 단순화할 수 있다.The tunneling energy between the two cell states is controlled by a clocking mechanism. Weighted sum of neighboring polarizations

to indicate

can be used to further simplify the notation.

In equation (4), the term (Pdiss) representing the instantaneous power dissipated as shown in equation (4) can be performed.

는 코히어런트 벡터(coherence vector)이고,

는 3차원 에너지 벡터이다.here,

is a coherence vector,

is a three-dimensional energy vector.

Specifically, the dissipated energy of the entire circuit for each input combination is evaluated by the tool at various tunneling energy levels based on non-adiabatic transitions.

In Figure 18, it is shown that the dark cells of the circuit consume more energy than others.

Energy dissipation comparisons between the QCA 4:1 multiplexer according to the present invention and other multiplexers are listed in [Table 7], [Table 8], and [Table 9] below.

Circuit
Average leakage energy dissipation (meV)
0.5 E _k
1.0 E _k
1.5E _k QCA multiplexer proposed by Ahmad F
0.02974

0.08050
0.13654 QCA multiplexer proposed by Purkayastha T et al.
0.03197
0.16759
0.16759 QCA according to the invention
4 to 1 multiplexer
0.02017

0.05946
0.10584

Circuit
Average switching energy dissipation (meV)
0.5 E _k
1.0 E _k
1.5E _k QCA multiplexer proposed by Ahmad F
0.03127

0.02628
0.02192 QCA multiplexer proposed by Purkayastha T et al.

0.08009
0.06793
0.05658 QCA according to the invention
4 to 1 multiplexer
0.11356

0.09942
0.08567

Circuit
Average energy dissipation of circuit (meV)
0.5 E _k
1.0 E _k
1.5E _k QCA multiplexer proposed by Ahmad F
0.06101

0.10679
0.15846 QCA multiplexer proposed by Purkayastha T et al.
0.11206
0.16296
0.22417 QCA according to the invention
4 to 1 multiplexer
0.13373

0.15888
0.19151

Energy dissipation comparison between the QCA D flip-flop and other D flip-flops used in the present invention is listed in [Table 10], [Table 11], and [Table 12].

Circuit
Average leakage energy dissipation (meV)
0.5 E _k
1.0 E _k
1.5E _k QCA D flip-flop proposed by Hashemi S et al.
0.01399

0.04292
0.07734 QCA D flip-flop proposed by Das JC et al.
0.01027
0.03152
0.05647 QCA D flip-flop according to the present invention
0.00778

0.02249
0.03913

Circuit
Average switching energy dissipation (meV)
0.5 E _k
1.0 E _k
1.5E _k QCA D flip-flop proposed by Hashemi S et al.
0.07316

0.06339
0.05391 QCA D flip-flop proposed by Das JC et al.

0.04850
0.04168
0.03518 QCA D flip-flop according to the present invention
0.00221

0.00182
0.00157

Circuit
Average energy dissipation of circuit (meV)
0.5 E _k
1.0 E _k
1.5E _k QCA D flip-flop proposed by Hashemi S et al.
0.08715

0.10631
0.13125 QCA D flip-flop proposed by Das JC et al.
0.03518
0.07320
0.09165 QCA D flip-flop according to the present invention
0.00999

0.02430
0.04071

As shown in [Table 7] to [Table 12], the QCA 4 to 1 multiplexer used in the present invention has about 30% lower leakage energy loss, and the QCA D flip-flop shows excellent results in all energy consumption tests. Able to know.

In the present invention, a 2-to-1 multiplexer is designed based on electron correlation between cells, and a 4-to-1 Mux is designed using 3 2-to-1 multiplexers based on a coplanar structure. In addition, the space complexity of the D flip-flop is minimized to construct a 4-bit general-purpose shift register that minimizes AT products. In particular, the proposed D flip-flop has very low energy consumption. The proposed components can then be used to construct a 4-bit general-purpose shift register.

On the other hand, in the QCA general-purpose shift register according to the present invention, the configuration and method of the described embodiments are not limitedly applicable as described above, but all or part of each embodiment may be modified so that various modifications may be made to the embodiments. They may be selectively combined and configured.

In addition, although preferred embodiments of the present invention have been illustrated and described above, the present invention is not limited to the specific embodiments described above, and the technical field to which the present invention belongs without departing from the gist of the present invention as claimed in the claims In addition, various modifications may be made by those of ordinary skill in the art, and these modifications should not be individually understood from the technical spirit or perspective of the present invention.

Claims (5)

A QCA shift having N QCA D flip-flops connected in series and performing any one of a register operation including holding stored data, shifting data, and loading data in parallel according to a combination of a mode selection signal and a clock signal. register; and
and N QCA multiplexers receiving the mode selection signal and transferring the signals to the N QCA D flip-flops so that the QCA shift register performs any one of the register operations according to the mode selection signal, ,
The QCA D flip-flop is,
first and second combinational logic cells performing an AND gate function;
a third combination logic cell receiving the clock signal and outputting an inverted signal;
and a fourth combinational logic cell that receives the output signals of the first and second combinational logic cells and outputs a flip-flop output signal by performing an OR gate function;
QCA general-purpose shift, characterized in that the clock signal and the flip-flop input signal are input to the first combinational logic cell, and the output of the third combinational logic cell and the flip-flop output signal are input to the second combinational logic cell register. The method of claim 1,
The QCA multiplexer includes three QCA 2 to 1 multiplexers,
One of the three QCA 2-to-1 multiplexers outputs any one of the first and second input signals as a first output signal according to a first mode selection signal,
The other one of the three QCA 2-to-1 multiplexers outputs any one of the third and fourth input signals as a second output signal according to the first mode selection signal,
and another one of the three QCA 2-to-1 multiplexers outputs any one of the first and second output signals according to a second mode selection signal. 3. The method of claim 2,
The QCA 2 to 1 multiplexer,
first to fifth cells arranged horizontally adjacent in series;
a sixth cell vertically adjacent to the second cell;
a seventh cell vertically adjacent to the fourth cell;
a first fixed cell disposed adjacent to the first cell to input a signal corresponding to a logic bit 0;
a second fixed cell disposed adjacent to the fifth cell to input a signal corresponding to logic bit 1;
a first input cell disposed adjacent to the first and sixth cells to receive a first input signal;
a second input cell disposed adjacent to the fifth and seventh cells to receive a second input signal;
a selection cell diagonally disposed in the sixth and seventh cells to receive a selection signal; and
and an output cell vertically adjacent to the third cell and outputting an output signal. delete A quantum dot cellular automata device comprising the QCA universal shift register of any one of claims 1 to 3.

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