KR102408961B1 - Method for processing a delayed task and electronic device implementing the same - Google Patents

Abstract

According to various embodiments of the present disclosure, an electronic device may include one or more processing circuits capable of processing a sub-task included in a task; and a processor capable of processing the task using at least some of the one or more processing circuits, wherein the processor processes a designated task comprising one or more designated sub-tasks; ascertain a status in which tasks are being processed, and, based at least on the status, identify at least one designated subtask among the one or more designated subtasks whose processing is being delayed, using the at least some processing circuitry, process at least one designated sub-task for which processing is being delayed, using the processor to process at least one designated sub-task for which processing is delayed; a first processing result corresponding to the at least one designated subtask being delayed, and a second processing result corresponding to the at least one designated subtask being delayed, the processing processed using the processor satisfying a specified condition and an electronic device configured to apply one processing result as a processing result corresponding to at least one sub-task whose processing is being delayed.
Other embodiments are possible.

Description

A method for processing a task with delayed processing and an electronic device supporting the same

Various embodiments of the present disclosure relate to a method of processing a task whose processing is being delayed, and an electronic device supporting the same.

As technology is advanced, electronic devices are required to handle complex tasks. In addition, the electronic device is required to have excellent processing performance and to optimize current consumption.

In order to process a complex task, the electronic device processes one task in a plurality of sub-task units to process one task, and each sub-task is performed by at least one computing resource.

However, when each sub-task is performed by at least one computing resource, there is a problem in that the electronic device has a limitation in grasping the resource situation in real time and it is not possible to allocate a computing resource suitable for each sub-task due to the performance of the electronic device. . Due to this, a chain problem such as a delay in the processing speed of one job composed of each sub-job occurs.

According to various embodiments of the present disclosure, an electronic device may include one or more processing circuits capable of processing a sub-task included in a task; and a processor capable of processing the task using at least some of the one or more processing circuits, wherein the processor processes a designated task comprising one or more designated sub-tasks; ascertain a status in which tasks are being processed, and, based at least on the status, identify at least one designated subtask among the one or more designated subtasks whose processing is being delayed, using the at least some processing circuitry, process at least one designated sub-task for which processing is being delayed, using the processor to process at least one designated sub-task for which processing is delayed; a first processing result corresponding to the at least one designated subtask being delayed, and a second processing result corresponding to the at least one designated subtask being delayed, the processing processed using the processor satisfying a specified condition and an electronic device configured to apply one processing result as a processing result corresponding to at least one sub-task whose processing is delayed.

A method for processing a task whose processing is delayed according to various embodiments and an electronic device supporting the same can normalize the performance of a task by resolving a task performance delay that occurs in real time.

1 is a block diagram of an electronic device in a network environment, according to various embodiments of the present disclosure;
2 is an exemplary diagram illustrating a task and a sub-task according to various embodiments of the present disclosure;
3 is a diagram illustrating a flow of operations according to various embodiments of the present disclosure;
4 is a diagram illustrating a flow of operations according to various embodiments of the present disclosure;
5A and 5B are diagrams illustrating an example of detecting a worst node.
6 is a diagram illustrating a time for performing a node for each target.
7 is a diagram illustrating a flow of an operation of selecting a candidate target according to various embodiments of the present disclosure;

1 is a block diagram of an electronic device 101 in a network environment 100 according to various embodiments of the present disclosure. Referring to FIG. 1 , in a network environment 100 , an electronic device 101 communicates with the electronic device 102 through a first network 198 (eg, short-range wireless communication) or a second network 199 ( For example, it may communicate with the electronic device 104 or the server 108 through long-distance wireless communication. According to an embodiment, the electronic device 101 may communicate with the electronic device 104 through the server 108 . According to an embodiment, the electronic device 101 includes a processor 120 , a memory 130 , an input device 150 , a sound output device 155 , a display device 160 , an audio module 170 , and a sensor module ( 176 , interface 177 , haptic module 179 , camera module 180 , power management module 188 , battery 189 , communication module 190 , subscriber identification module 196 , and antenna module 197 . ) may be included. In some embodiments, at least one of these components (eg, the display device 160 or the camera module 180 ) may be omitted or another component may be added to the electronic device 101 . In some embodiments, for example, as in the case of a sensor module 176 (eg, a fingerprint sensor, an iris sensor, or an illuminance sensor) embedded in a display device 160 (eg, a display), some components It can be integrated and implemented.

The processor 120, for example, runs software (eg, the program 140) to execute at least one other component (eg, a hardware or software component) of the electronic device 101 connected to the processor 120 . It can control and perform various data processing and operations. The processor 120 loads and processes commands or data received from other components (eg, the sensor module 176 or the communication module 190 ) into the volatile memory 132 , and stores the result data in the non-volatile memory 134 . can be stored in According to an embodiment, the processor 120 is operated independently of the main processor 121 (eg, central processing unit or application processor), and additionally or alternatively, uses less power than the main processor 121, or Alternatively, the auxiliary processor 123 (eg, a graphic processing unit, an image signal processor, a sensor hub processor, or a communication processor) specialized for a specified function may be included. Here, the auxiliary processor 123 may be operated separately from or embedded in the main processor 121 .

In this case, the auxiliary processor 123 is, for example, on behalf of the main processor 121 while the main processor 121 is in an inactive (eg, sleep) state, or when the main processor 121 is active (eg, in a sleep) state. : While in the application execution) state, together with the main processor 121 , at least one of the components of the electronic device 101 (eg, the display device 160 , the sensor module 176 , or the communication module ( 190))) and related functions or states. According to one embodiment, the coprocessor 123 (eg, image signal processor or communication processor) is implemented as some component of another functionally related component (eg, camera module 180 or communication module 190). can be The memory 130 includes various data used by at least one component (eg, the processor 120 or the sensor module 176 ) of the electronic device 101 , for example, software (eg, the program 140 ). ) and input data or output data for commands related thereto. The memory 130 may include a volatile memory 132 or a non-volatile memory 134 .

The program 140 is software stored in the memory 130 , and may include, for example, an operating system 142 , middleware 144 , or an application 146 .

The input device 150 is a device for receiving commands or data to be used by a component (eg, the processor 120) of the electronic device 101 from the outside (eg, a user) of the electronic device 101, for example, For example, it may include a microphone, mouse, or keyboard.

The sound output device 155 is a device for outputting a sound signal to the outside of the electronic device 101, and includes, for example, a speaker used for general purposes such as multimedia playback or recording playback, and a receiver used exclusively for receiving calls. may include According to an embodiment, the receiver may be formed integrally with or separately from the speaker.

The display device 160 is a device for visually providing information to a user of the electronic device 101 , and may include, for example, a display, a hologram device, or a projector and a control circuit for controlling the corresponding device. According to an embodiment, the display device 160 may include a touch circuitry or a pressure sensor capable of measuring the intensity of the pressure applied to the touch.

The audio module 170 may interactively convert a sound and an electrical signal. According to an embodiment, the audio module 170 acquires a sound through the input device 150 , or an external electronic device (eg, a sound output device 155 ) connected to the electronic device 101 by wire or wirelessly. Sound may be output through the electronic device 102 (eg, a speaker or headphones).

The sensor module 176 may generate an electrical signal or data value corresponding to an internal operating state (eg, power or temperature) of the electronic device 101 or an external environmental state. The sensor module 176 may include, for example, a gesture sensor, a gyro sensor, a barometric pressure sensor, a magnetic sensor, an acceleration sensor, a grip sensor, a proximity sensor, a color sensor, an IR (infrared) sensor, a biometric sensor, a temperature sensor, a humidity sensor, Alternatively, it may include an illuminance sensor.

The interface 177 may support a designated protocol capable of connecting to an external electronic device (eg, the electronic device 102 ) in a wired or wireless manner. According to an embodiment, the interface 177 may include a high definition multimedia interface (HDMI), a universal serial bus (USB) interface, an SD card interface, or an audio interface.

The connection terminal 178 is a connector capable of physically connecting the electronic device 101 and an external electronic device (eg, the electronic device 102 ), for example, an HDMI connector, a USB connector, an SD card connector, or an audio connector. (eg a headphone connector).

The haptic module 179 may convert an electrical signal into a mechanical stimulus (eg, vibration or movement) or an electrical stimulus that the user can perceive through tactile or kinesthetic sense. The haptic module 179 may include, for example, a motor, a piezoelectric element, or an electrical stimulation device.

The camera module 180 may capture still images and moving images. According to an embodiment, the camera module 180 may include one or more lenses, an image sensor, an image signal processor, or a flash.

The power management module 188 is a module for managing power supplied to the electronic device 101 , and may be configured as, for example, at least a part of a power management integrated circuit (PMIC).

The battery 189 is a device for supplying power to at least one component of the electronic device 101 , and may include, for example, a non-rechargeable primary battery, a rechargeable secondary battery, or a fuel cell.

The communication module 190 establishes a wired or wireless communication channel between the electronic device 101 and an external electronic device (eg, the electronic device 102, the electronic device 104, or the server 108), and establishes the established communication channel. It can support performing communication through The communication module 190 may include one or more communication processors that support wired communication or wireless communication, which are operated independently of the processor 120 (eg, an application processor). According to one embodiment, the communication module 190 is a wireless communication module 192 (eg, a cellular communication module, a short-range wireless communication module, or a global navigation satellite system (GNSS) communication module) or a wired communication module 194 (eg, : including a local area network (LAN) communication module, or a power line communication module), and using a corresponding communication module among them communication network) or the second network 199 (eg, a cellular network, the Internet, or a telecommunication network such as a computer network (eg, LAN or WAN)). The above-described various types of communication modules 190 may be implemented as a single chip or as separate chips.

According to an embodiment, the wireless communication module 192 may use the user information stored in the subscriber identification module 196 to distinguish and authenticate the electronic device 101 in the communication network.

The antenna module 197 may include one or more antennas for externally transmitting or receiving a signal or power. According to an example, the communication module 190 (eg, the wireless communication module 192 ) may transmit a signal to or receive a signal from the external electronic device through an antenna suitable for a communication method.

Some of the components are connected to each other through a communication method between peripheral devices (eg, a bus, general purpose input/output (GPIO), serial peripheral interface (SPI), or mobile industry processor interface (MIPI)) to signal (eg commands or data) can be exchanged with each other.

According to an embodiment, the command or data may be transmitted or received between the electronic device 101 and the external electronic device 104 through the server 108 connected to the second network 199 . Each of the electronic devices 102 and 104 may be the same or a different type of device from the electronic device 101 . According to an embodiment, all or some of the operations performed by the electronic device 101 may be executed by one or a plurality of external electronic devices. According to an embodiment, when the electronic device 101 is to perform a function or service automatically or upon request, the electronic device 101 performs the function or service with it instead of or in addition to executing the function or service itself. At least some related functions may be requested from the external electronic device. Upon receiving the request, the external electronic device may execute the requested function or additional function, and may transmit the result to the electronic device 101 . The electronic device 101 may provide the requested function or service by processing the received result as it is or additionally. For this purpose, for example, cloud computing, distributed computing, or client-server computing technology may be used.

The electronic device according to various embodiments disclosed in this document may have various types of devices. The electronic device may include, for example, at least one of a portable communication device (eg, a smart phone), a computer device, a portable multimedia device, a portable medical device, a camera, a wearable device, and a home appliance device. The electronic device according to the embodiment of the present document is not limited to the above-described devices.

The various embodiments of this document and the terms used therein are not intended to limit the technology described in this document to a specific embodiment, but it should be understood to cover various modifications, equivalents, and/or substitutions of the embodiments. In connection with the description of the drawings, like reference numerals may be used for like components. The singular expression may include the plural expression unless the context clearly dictates otherwise. In this document, expressions such as “A or B”, “at least one of A and/or B”, “A, B or C” or “at least one of A, B and/or C” refer to all of the items listed together. Possible combinations may be included. Expressions such as "first", "second", "first" or "second" can modify the corresponding elements regardless of order or importance, and are used only to distinguish one element from another element. The components are not limited. When an (eg, first) component is referred to as being “(functionally or communicatively) connected” or “connected” to another (eg, second) component, that component is It may be directly connected to the component or may be connected through another component (eg, a third component).

As used herein, the term “module” includes a unit composed of hardware, software, or firmware, and may be used interchangeably with terms such as, for example, logic, logic block, component, or circuit. A module may be an integrally formed part or a minimum unit or a part of performing one or more functions. For example, the module may be configured as an application-specific integrated circuit (ASIC).

Various embodiments of the present document include instructions stored in a machine-readable storage media (eg, internal memory 136 or external memory 138) that can be read by a machine (eg, a computer). It may be implemented as software (eg, the program 140). The device is a device capable of calling a stored command from a storage medium and operating according to the called command, and may include the electronic device (eg, the electronic device 101 ) according to the disclosed embodiments. When the instruction is executed by a processor (eg, the processor 120 ), the processor may perform a function corresponding to the instruction by using other components directly or under the control of the processor. Instructions may include code generated or executed by a compiler or interpreter. The device-readable storage medium may be provided in the form of a non-transitory storage medium. Here, 'non-transitory' means that the storage medium does not include a signal and is tangible, and does not distinguish that data is semi-permanently or temporarily stored in the storage medium.

According to an example, the method according to various embodiments disclosed in this document may be included and provided in a computer program product. Computer program products may be traded between sellers and buyers as commodities. The computer program product may be distributed in the form of a machine-readable storage medium (eg, compact disc read only memory (CD-ROM)) or online through an application store (eg, Play Store™). In the case of online distribution, at least a portion of the computer program product may be temporarily stored or temporarily generated in a storage medium such as a memory of a server of a manufacturer, a server of an application store, or a relay server.

Each of the components (eg, a module or a program) according to various embodiments may be composed of a singular or a plurality of entities, and some sub-components of the aforementioned sub-components may be omitted, or other sub-components may be It may be further included in various embodiments. Alternatively or additionally, some components (eg, a module or a program) may be integrated into a single entity to perform the same or similar functions performed by each corresponding component prior to integration. According to various embodiments, operations performed by a module, program, or other component are sequentially, parallel, repetitively or heuristically executed, or at least some operations are executed in a different order, are omitted, or other operations are added. can be

Hereinafter, the present invention will be described in detail with reference to FIGS. 2 to 7 .

2 is an exemplary diagram illustrating a task and a sub-task according to various embodiments of the present disclosure; The task means an entire job to be processed, and may include a plurality of sub-tasks corresponding to a part of the overall job. In the detailed description of the present invention, tasks may be described as graphs, and sub-tasks may be described as nodes. Hereinafter, it will be described with graphs and nodes in the detailed description.

Referring to FIG. 2 , the graph 200 may include nodes 210 to 218 . The nodes 210 to 218 may perform respective roles constituting the overall task. Operations performed by each node may be different. Referring to FIG. 2 , it is assumed that the graph 200 shown in FIG. 2 is a graph related to video or image editing. Node 0 210 may perform an extract-related operation. Node 1 211 , node 2 212 , and node 3 213 may perform a scale-related operation. Node 4 214 may perform an operation related to cropping. Nodes 5 215 and 6 216 may perform operations related to noise filters. Node 7 217 may perform an operation related to edge enhancement. Node 8 218 may perform operations related to combine.

The graph 200 may include an input end and an output end, and the input end and the output end of the graph 200 may mean an initial input end and a final output end of the entire job. Each of the nodes may include an input terminal and an output terminal, and the nodes may include at least one input terminal and at least one output terminal. The input and output terminals of the nodes may be intermediate input and intermediate output from a graph point of view.

Referring to FIG. 2 , the input terminal 251 of the node 0 210 may be the initial input terminal of the graph 200 , and the output terminal 252 of the node 8 218 may be the final input terminal of the graph 200 . The output terminals 210a, 210b, and 210c of the node 0 210 may be three, and each of the output terminals 210a, 210b, 210c of the node 0 210 is the node 1 211 , the node 2 212 and the node Each of the three (213) input terminals may be. Each output of node 5 215 , node 6 216 , and node 7 217 may be connected to the inputs of node 8 218 . Just as the output of the node 0 210 is connected to the input of the node 1 211 , an order or a causal relationship may exist between the two nodes.

Each node may be processed by processing circuits of the electronic device (eg, the electronic device 101), and the processing circuits may be described as a target. The targets may include a part of the processor 120 of the electronic device (eg, the electronic device 101 ). In an embodiment, the target may include a central processing unit (CPU), an advanced SIMD (NEON or “MPE” media processing engine), a graphics processing unit (GPU), a digital signal processor (DSP), and vision acceleration hardware. In another embodiment, when the camera includes an image signal processor (ISP), the target may include an image signal processor included in the camera.

3 and 4 are diagrams illustrating a flow of operations according to various embodiments of the present disclosure.

Referring to FIG. 3 , in operation 301 , the processor 120 of the electronic device (eg, the electronic device 101 ) may control targets capable of processing nodes included in the graph to process the nodes included in the graph. . The processor 120 of the electronic device (eg, the electronic device 101 ) may check the states of nodes processed by the targets.

In operation 302, the processor 120 of the electronic device (eg, the electronic device 101) may determine a node whose processing is delayed. A node whose processing is delayed may include a worst node.

In operation 303, the processor 120 of the electronic device (eg, the electronic device 101) may select a candidate target to process the worst node.

In operation 304 , the processor 120 of the electronic device (eg, the electronic device 101 ) may apply the processing result of the target that has processed the worst node first as the result of the corresponding worst node. 3 is a view showing the overall operation of the present invention, detailed description will proceed with FIG.

Referring to FIG. 4 , communication between at least one software module required for task performance delay detection and normalization may be shown according to various embodiments of the present disclosure. Software modules according to various embodiments of the present disclosure include a master module (Master) 401, a resource manager module (Resource Manager) 402, a graph execution module (Graph Execution Module) 403, a worst node detection module (Worst) It may include a Node Detector 404 , a Candidate Target Preparer 405 , and a Node Performance Accelerator 406 . The processor 120 of the electronic device (eg, the electronic device 101) may include a part or all of at least one software module.

The master module (Master) 401 may include a scheduler and receive data from the scheduler. The data may include a schedule table for determining a target for performing each node constituting the graph.

The resource manager module (Resource Manager) 402 may allocate necessary resources to a target to perform each node. The resource may include a resource required when the target executes a node. Alternatively, the target may include resources that can be accessed when performing a node. For example, when a target for performing a specific node is a GPU, a resource allocated to the target may include a memory accessible to the GPU.

The graph execution module (Graph Execution Module) 403 may include a module for executing a graph.

The worst node detection module 404 may detect one or more worst nodes by analyzing the graph execution time information transmitted from the graph execution module 403 . According to various embodiments of the present disclosure, the worst node may include at least one node whose processing is delayed among nodes constituting the graph. The graph execution time information may include graph premise execution time and execution time information for each node for performing the graph N times. The graph execution time information may be transmitted from the graph execution module 403 every time the graph execution is finished N times.

The Candidate Target Preparer 405 selects a second target to be additionally added to the worst node, and requests the resource manager module 402 to allocate resources necessary for the operation of the second target to the second target. can As an embodiment, the candidate target preparation module 405 may request and receive the target list and priority for performing the worst node from the resource manager 402 . The candidate target preparation module 405 selects a target with the highest priority as a second target with reference to the target list, requests the resource manager 402 for a resource for performing the target, and allocates the resource to the target. can In another embodiment, the candidate target preparation module 405 may consider factors other than the priority information received from the resource manager 402 in selecting the second target.

The node performance accelerator module (Node Performance Accelerator) 406 communicates with the graph execution module 403 at the time of performing the worst node, and performs the corresponding worst node to the existing target and the second target that were performing the worst node, respectively. (Parallel execution) and the result of the target that is terminated first can be reflected as the output of the worst node.

Referring to FIG. 4 , in operation 411 , the master module 401 may receive a schedule table from a scheduler. In operation 412 , the master module 401 may request the resource manager module 402 to allocate a necessary resource to a target for performing each node. In operation 413 , the resource manager module 402 may transmit a response to the request to the master module 401 . In operation 414 , the master module 401 may request the graph execution module 403 to execute the graph, and in operation 415 , the graph execution module 403 may execute the graph. In operation 416 , the graph execution module 403 may notify the master module 401 that the graph execution is finished. In operation 417 , the master module 401 communicates with the graph execution module 403 to repeat the graph execution operation N times.

In operation 418 , the master module 401 may transmit graph execution time information to the worst node detection module 404 . In operation 419 , the worst node detection module 404 may detect one or more worst nodes by analyzing the transferred graph execution time information, and transmit information about the detected worst nodes to the node performance acceleration module 406 . . In operation 420 , the worst node detection module 404 may transmit information about the detected worst node to the candidate target preparation module 405 .

In operation 421, the candidate target preparation module 405 selects a second target to be additionally committed to the worst node, and tells the resource manager module 402 to allocate a resource necessary for the operation of the second target to the second target. you can request In operation 422 , the resource manager module 402 may transmit the allocated resource information to the candidate target preparation module 405 . In operation 423 , the candidate target preparation module 405 may transmit the received allocated resource information to the node performance acceleration module 406 .

In operation 424 , the node execution acceleration module 404 may request the graph execution module 403 to add the second target to the schedule table in order to cause the second target to perform the corresponding worst node (set flags). In operation 425 , the graph execution module 403 receiving this may transmit a standby signal to the master module 401 . In operation 426 , the master module 401 may request the graph execution module 403 to execute the graph, and in operation 427 , the graph execution module 403 may execute the graph. In operation 428 , the graph execution module 403 may notify the node performance acceleration module 406 that the execution of the worst node starts at a time point when the worst node is executed after the graph execution. Upon receiving this, the node execution acceleration module 406 may perform a corresponding worst node on each of the second target and the existing target. In operation 429, the node execution acceleration module 406 notifies the graph execution module 403 that the processing of the target has been completed for the target that has processed the worst node first, and also displays the processing result of the target that has been processed first The graph execution module 403 may be instructed to reflect the processing result of the corresponding worst node.

In operation 430 , the graph execution module 403 may notify the node execution acceleration module 406 that graph execution is finished. In operation 431 , the graph execution module 403 may notify the master module 401 that the graph execution is finished. In operation 432 , the master module 401 may communicate with the graph execution module 403 to repeat the graph execution operation N times. In operation 433 , the node execution acceleration module 406 may notify the graph execution module 403 that the second target will no longer perform the corresponding worst node (reset flags).

In operation 434 , the master module 401 may transmit graph execution time information to the worst node detection module 404 . In operation 435 , the worst node detection module 404 may analyze the transmitted graph execution time information to notify the graph execution module 403 that the worst node is not detected. In operation 436 , the graph execution module 403 receiving this may transmit a standby signal to the master module 401 .

5A and 5B are diagrams illustrating an example of detecting a worst node.

The worst node detection module may detect one or more worst nodes by analyzing the graph execution time information transmitted from the graph execution module. According to various embodiments of the present disclosure, the worst node may include at least one node whose processing is delayed among nodes constituting the graph. The graph execution time information may include graph premise execution time and execution time information for each node for performing the graph N times.

In the graph execution time information obtained by performing N (eg 5) times, the worst node detection module determines that the difference in execution time between the term having the lower graph execution time and the term having the upper graph execution time is the reference value based on the graph execution time. You can check if it is over. If the worst node detection module determines that the graph execution time gap between the upper term and the lower term exceeds the reference value, it may determine that the worst node is included. The lower term may mean a term in which a graph execution time is long. As an embodiment, the lower term may include a term corresponding to the lower 20% based on the graph execution time order. The upper term may include a term corresponding to the top 80% based on the graph execution time order. Referring to FIG. 5A , the lower term may include a second performed term having a required time of 7 ms. The upper term may include first, third, and fifth terms having a required time of 4 ms. Assuming that the reference value is 2 ms, the worst node detection module may determine that the worst node is included because the difference between the execution times of the upper term and the lower term is 3 ms.

According to various embodiments of the present disclosure, the worst node detection module compares the execution time of each node of the second performed term, which is the lower term, and the first performed term, which is the upper term, to determine the node with the largest difference as the worst node. have. Referring to FIG. 5A below, the worst node detection module may determine that the worst node is node 0.

According to various embodiments of the present disclosure, the worst node detection module may determine a node in which the execution time for each node exceeds a preset time limit for each node in the second performed term, which is a term corresponding to the lower 20%, as a worst node. . Referring to FIG. 5A below, the worst node detection module may determine that the worst node is node 0. When there are a plurality of terms corresponding to the lower 20%, the worst node detection module may determine a node having the largest number of nodes exceeding a preset time limit for each node as a worst node.

6 is a diagram illustrating a time for performing a node for each target.

The candidate target preparer may select a second target to be additionally input to the worst node and request the resource manager module to allocate resources necessary for the operation of the second target to the second target. As an embodiment, the candidate target preparation module may request and receive information about a target list capable of performing a worst node from the resource manager and information on the priority of the targets. The candidate target preparation module may select a target with the highest priority as the second target by referring to the target list, request a resource for performing the target from the resource manager, and allocate the resource to the target. As an example, the candidate target preparation module may check the target list including the target A, the target B, the target C, and the target D and the priority of each target from the resource manager. The priority of the targets may be designated for each node. Target D may be higher than target B in priority of targets capable of performing node 0 identified as a worst node. The candidate target preparation module may select target D as a candidate target capable of performing node 0 with reference to the priority.

In another embodiment, the candidate target preparation module may consider factors other than the priority information received from the resource manager when selecting the second target. Referring to FIG. 6 , FIG. 6 is a diagram illustrating a time for performing a node for each target. As another element, the candidate target preparation module may select a candidate target by referring to a time for performing a node for each target. The candidate target preparation module may identify a target that is in an idle state during a time in which node 0 determined as the worst node is performed, and the candidate target preparation module may select the idle target B as a candidate target.

According to various embodiments of the present disclosure, the candidate target preparation module may repeatedly add a target for generating a worst node to a blacklist, and select a candidate target by referring to the blacklist. This will be described in detail with reference to FIG. 7 .

7 is a diagram illustrating a flow of an operation of selecting a candidate target according to various embodiments of the present disclosure; Referring to FIG. 7 , the candidate target preparation module may receive graph execution time information, information about a worst node, and information about a candidate target priority. The candidate target preparation module may receive graph execution time information from the master module. The graph execution time information may include an entire graph execution time and/or an execution time for each node. The graph execution time information may be transmitted in operation 418 of FIG. 4 . The candidate target preparation module may receive information about the detected worst node from the worst node detection module. Information about the worst node may be transmitted in operation 420 of FIG. 4 . The candidate target preparation module may request and receive information about a target list capable of performing a worst node and priorities of targets from the resource manager.

According to various embodiments, it is assumed in FIG. 7 that the candidate target preparation module detects a worst node and selects at least one candidate target to be input to the corresponding worst node during previously performed terms. Referring to operation 701 , the candidate target preparation module may determine whether the worst node performed as the candidate target in the previous term (N-1) is a worst node also in this term (N).

As a result of the determination in operation 701 , if it is determined that the worst node detected in the previous term is also a worst node in this term, operation 702 may be performed. Referring to operation 702 , the candidate target preparation module may add a target that performed the worst node in the previous term to the blacklist of the corresponding worst node as a blacklist target. The blacklist target may include a target that has not been resolved even though it has been introduced to resolve the processing delay of the corresponding node. After adding in operation 702 , the process may proceed to operation 703 .

In operation 703 , the candidate target preparation module may set K, which is a value indicating a rank to be considered when selecting a target, to 1 . Setting K to 1 may include considering the candidate target of the 1st rank as the candidate target. After setting in operation 703 , operation 704 may be performed.

In operation 704 , the candidate target preparation module may determine whether the first-ranked candidate target is idle while the worst node is being performed. The candidate target preparation module may determine by referring to graph execution time information received from the master module.

As a result of the determination in operation 704 , when it is determined that the first-ranked candidate target is not in an idle state, operation 708 may be performed.

In operation 708 , the candidate target preparation module may add 1 to K, which is a value indicating a rank. Adding 1 to K may include considering a next-ranked candidate target as a candidate target. For example, it may include considering the second rank candidate target as a candidate target.

Proceeding to operation 709 , the candidate target preparation module may determine whether a second priority candidate target capable of performing the worst node exists with reference to the target list and priority information received from the resource manager. As a result of the determination in operation 709, when the candidate target preparation module determines that the second-ranked candidate target capable of performing the worst node exists, the process proceeds to operation 704 and the subsequent process may be repeated.

As a result of the determination in operation 709, when the candidate target preparation module determines that the second-ranked candidate target capable of performing the worst node does not exist, the process proceeds to operation 710 to select a candidate target for performing the worst node in the next term may not

If the candidate target preparation module determines in operation 704 that the first-ranked candidate target is in an idle state, operation 705 may be performed.

In operation 705 , it may be determined whether the first-ranked candidate target has been selected as a target for executing the corresponding worst node in previous terms.

As a result of the determination in operation 705, if it is determined that the first-ranked candidate target has never been selected as a target for executing the corresponding worst node in previous terms, the process proceeds to operation 707 and the candidate target preparation module selects the first-ranked candidate target as the next It can be selected as a candidate target to be performed in the term.

As a result of the determination in operation 705 , if it is determined that the first-ranked candidate target has been selected as a target for executing the corresponding worst node in previous terms, operation 706 may be performed. In operation 706 , it may be determined whether the number of times the first-ranked candidate target is added as a blacklist target to the blacklist of the corresponding worst node is equal to or greater than a reference number. As a result of the determination in operation 706, if the number of times is not equal to or greater than the reference number, in operation 707, the candidate target preparation module may select the first-ranked candidate target as a candidate target to be performed in the next term. As a result of the determination in operation 706 , if the reference number is greater than or equal to the reference number, operation 708 may be performed. In operation 708 , the candidate target preparation module may add 1 to K, which is a value indicating a rank. Proceeding to operation 709 , the candidate target preparation module may determine whether a second priority candidate target capable of performing the worst node exists with reference to the target list and priority information received from the resource manager. As a result of the determination in operation 709, when the candidate target preparation module determines that the second-ranked candidate target capable of performing the worst node exists, the process proceeds to operation 704 and the subsequent process may be repeated.

As a result of the determination in operation 709, when the candidate target preparation module determines that the second-ranked candidate target capable of performing the worst node does not exist, the process proceeds to operation 710 to select a candidate target for performing the worst node in the next term may not

101: electronic device
120: processor
130: memory

Claims (20)

In an electronic device,
one or more processing circuits capable of processing a sub-task included in the task; and
a processor capable of processing the task using at least some of the one or more processing circuits;
The processor is
process a designated task comprising one or more designated subtasks;
check a status in which the one or more designated subtasks are being processed, and check at least one designated subtask whose processing is delayed among the one or more designated subtasks, based at least on the status;
process, using the at least some processing circuitry, at least one designated subtask whose processing is being delayed;
processing, using the processor, at least one designated subtask whose processing is being delayed;
a first processing result corresponding to the at least one designated subtask for which the processing is being delayed, processed using the at least some processing circuitry, and the at least one designated subtask processed using the processor, for which the processing is being delayed. An electronic device configured to apply one processing result that satisfies a specified condition among the second processing results corresponding to , as a processing result corresponding to the at least one subtask whose processing is delayed. The method of claim 1,
The processor is
The electronic device is configured to identify at least one designated subtask whose processing is delayed among the one or more designated subtasks, based on at least one of a processing time of the designated task or a processing time of the one or more designated subtasks. The method of claim 1,
The processor is
an electronic device configured to identify at least one designated subtask whose processing is delayed among the one or more designated subtasks, based on the fact that the processing time of the one or more designated subtasks exceeds a time limit designated for each subtask . The method of claim 1,
The processor is
In processing the at least one designated subtask whose processing is delayed using the processor,
selecting at least some of the one or more processing circuits different from the at least some processing circuits;
an electronic device configured to process the at least one designated subtask whose processing is being delayed using the selected at least some processing circuitry. 5. The method of claim 4,
The processor is
an electronic device configured to select the other at least some processing circuits based on a priority of the specified processing circuitry. 5. The method of claim 4,
The processor is
an electronic device configured to select an idle processing circuit among the one or more processing circuits as the other at least some processing circuitry. 4. The method of claim 3,
The processor is
It is determined whether the processing of at least one designated sub-task whose processing is being delayed has been delayed before,
an electronic device configured to store, as a blacklist target of the at least one designated subtask whose processing is delayed, a processing circuit that has performed the at least one designated subtask whose processing has been delayed, when it is determined that the processing has been delayed. 8. The method of claim 7,
The processor is
an electronic device configured to select a processing circuit stored less than a reference number of times as a black list target of the at least one designated subtask whose processing is delayed as the processing circuit for processing the at least one designated subtask whose processing is delayed. The method of claim 1,
The processor is
and applying the earliest processed result among the first processing result and the second processing result as a processing result corresponding to the at least one sub task. processing, using the processor, a designated task including one or more designated sub-tasks;
checking a state in which the one or more designated sub-tasks are being processed using the processor;
identifying, using the processor, at least one designated subtask whose processing is being delayed from among the one or more designated subtasks, based on at least the state;
processing, using at least some processing circuitry, the at least one designated subtask whose processing is being delayed;
processing, using the processor, at least one designated subtask whose processing is being delayed;
a first processing result corresponding to the at least one designated subtask for which the processing is being delayed, processed using the at least some processing circuitry, and the at least one designated subtask processed using the processor, for which the processing is being delayed. and applying one processing result that satisfies a specified condition among second processing results corresponding to , as a processing result corresponding to at least one subtask whose processing is delayed. delete delete delete delete delete delete delete delete delete delete

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