KR102407210B1 - A multi-mode device and an operating method thereof - Google Patents

Abstract

A device according to an embodiment of the present invention may include a connector, a chassis type circuit, and a mode configuration circuit. A connector may connect the device with the chassis. A chassis type circuit may determine the type of chassis that contains the device. A mode configuration circuit may configure the device to use the first mode or the second mode in response to the type of chassis.

Description

A MULTI-MODE DEVICE AND AN OPERATING METHOD THEREOF

The present invention relates to a storage device, and more particularly, to a multi-mode device and an operating method thereof.

Conventional chassis are available in a variety of different models. For example, some chassis use Non-Volatile Memory express (NVMe) to communicate with devices. On the other hand, other chassis use NVMe over Fabrics (NVMeoF) to communicate with devices. Different models of chassis may require different models of devices designed to be compatible with these models. As a result, manufacturers of devices have to offer different models of devices. In addition, data centers using different models of these chassis must keep spare parts for the various devices in case the device fails. This means that data centers will have to store more spare parts than they would otherwise store.
There is still a need for a method to reduce the number of device types produced by manufacturers and stored by data centers.

The present invention is to solve the above technical problem, the present invention can provide a multi-mode apparatus and an operating method thereof.

A device according to an embodiment of the present invention may include a connector, a chassis type circuit, and a mode configuration circuit. The connector may connect the device with the chassis. The chassis type circuitry may determine the type of chassis that contains the device. The mode configuration circuit may configure the device to use the first mode or the second mode in response to the type of chassis.
A method of operating a device according to another embodiment of the present invention includes the steps of determining a type of a chassis in which the device is installed, and according to the type of the chassis, activating a first communication mechanism for the device and a second communication mechanism and configuring the device to be disabled.
An article according to another embodiment of the present invention may include a tangible storage medium for storing non-transitory instructions. The non-transitory instructions, when executed by the machine: determining the type of chassis in which the device is installed, and configuring the device to activate a first communication mechanism for the device and deactivate a second communication mechanism for the device according to the type of chassis. steps can be performed.

The multi-mode apparatus and method of operation thereof of the present invention can provide a single common apparatus and a platform of a common system that can be used in a plurality of products. Accordingly, it is possible to reduce production and storage costs of devices of various models.

1 shows a machine comprising an apparatus according to an embodiment of the present invention.
Fig. 2 shows the machine of Fig. 1 in further detail.
3 and 4 show the device of FIG. 1 operating in Non-Volatile Memory express (NVMe) or Non-Volatile Memory express over Fabrics (NVMeoF) mode.
Figure 5 shows the device of Figure 1 communicating with two hosts within a High Availability (HA) chassis.
6 is a flowchart exemplarily showing a procedure for self-configuring the apparatus of FIG. 1 according to an embodiment of the present invention.
7A and 7B are flowcharts exemplarily illustrating a procedure for self-configuring the device of FIG. 1 for an NVMe or NVMeoF protocol and an HA chassis or a non-HA chassis according to an embodiment of the present invention.

Reference will now be made in detail to specific embodiments of the inventive concept. Examples of specific embodiments of the inventive concept will be illustrated in the accompanying drawings. In the detailed description that follows, numerous specific details will be provided in order that a thorough understanding of the inventive concept may be provided. However, it should be understood that those skilled in the art may practice the concepts of the present invention without these detailed descriptions. In other instances, well-known or public methods, steps, configurations, circuits, and networks have not been described in detail so as not to unnecessarily obscure aspects of the embodiments of the present invention.
In this specification, the first and second, etc. may be used to describe various components, but it will be understood that these components are not limited by these terms. These terms are used to distinguish one component from another. For example, a first logic stage may be termed a second logic stage, and similarly, the second logical stage may be termed a first logic stage without departing from the scope of the inventive concept.
Terms used in the description of the inventive concept are used only for the purpose of describing specific embodiments, and are not intended to limit the inventive concept. Unless the context clearly dictates otherwise, the singular forms, when used in the description of the inventive concept and the appended claims, are to be understood as being intended to encompass the plural forms. It should also be understood that the term “and/or” as used herein indicates or includes all possible combinations of one or more of the related recitations. When the term “comprising” is used herein, it is intended to specify the presence of a described feature, number, step, operation, configuration, and/or component, and one or more other features, number, step, operation thereof. It should be further understood that it does not exclude the presence or addition of , components, parts, and/or groups. The illustrations of the components and features are not drawn to scale, and some components and features may be drawn by enlarging/reducing the drawings.
It is desirable for NVMeoF device suppliers to provide a single common device that can be used in multiple products, such as an NVMe chassis and an NVMeoF chassis. In addition, NVMe devices in non-HA (or single path I/O (Input/Output)) mode and HA (or multi-path I/O) mode with minimal change It is desirable to have a common system platform that can support both and NVMeoF devices.
A multi-mode NVMeoF device may support NVMe or NVMeoF by looking for information from a known location. If a multi-mode device is installed within an NVMe chassis or the chassis type is not determined, x4 lanes of Peripheral Component Interconnect express (PCIe) can be used for both data and control communication. The device is powered by a PCIe engine, enabling communication via a U.2 connector, for example. In this case, the device will disable the ethernet engine(s). And, all NVMe protocols and functions are supported or enabled.
When a multi-mode device is installed within the NVMeoF chassis, two of the PCIe lanes can be used for control communication. Depending on the design of the device, Ethernet ports supporting data communication may use other available PCIe lanes or SAS (Serial Attached Small Computer System Interface (SCSI)) pins.
Embodiments of the present invention enable multi-mode devices to push health status, Field Replaceable Unit (FRU) information, sensor information, and discovery services to a Baseboard Management Controller (BMC) or a local host processor. Multi-mode devices can also download NVMeoF device firmware upgrades.
Although a multi-mode device must support data communication and control communication with two (or potentially more) hosts, HA multi-path I/O support is also possible. This may require allocation of more communication paths (eg, additional Ethernet ports via additional SAS pins) or division of possible communication paths (eg allocation of different PCIe lanes for different purposes).
Embodiments of the present invention may support various designs. In some designs, a common multi-mode device may support two distinct modes (NVMe and NVMeoF). Moreover, in some designs, a multi-mode device in NVMe mode may operate like a conventional NVMe device. In one design, the multi-mode device may use some PCIe lanes for control communication and may use some PCIe lanes for Ethernet ports. In another design, the multi-mode device may use some PCIe lanes for control communication and may use SAS pins for Ethernet ports. In some designs, conventional PCIe software drivers may be used to manage PCIe communications.
1 shows a chassis comprising a device according to an embodiment of the present invention. 1 , a chassis 105 is shown. Without any limitation, the chassis 105 may be a desktop or laptop computer, a server (eg, a standalone server or a rack server), or advantages from embodiments of the present invention. Any desired chassis including any other device capable of having The chassis 105 may also include specialized portable computing devices, tablet computers, smart phones, and other computing devices. In addition, although the described embodiments of the present invention refer to storage devices such as ethernet solid state drives (eSSDs), the embodiments of the present invention may have any form having an advantage that can be obtained by separating data planes and control planes. It can also be applied to devices of
Notwithstanding the particular shape of the chassis 105 , the chassis 105 may include a processor 110 , memory 115 , Electrically Erasable Programmable Read-Only Memory (EEPROM) 120 , and a storage device 125 . . The processor 110 may be any type of processor (eg, Intel Xeon, Celeron, Itanium, Atom processor, AMD Opteron processor, ARM processor, etc.). Although FIG. 1 depicts a single processor, chassis 105 may include any number of processors. The memory 115 may include any type of memory (eg, flash memory, static random access memory (SRAM), persistent random access memory (PRAM), ferroelectric random access memory (FRAM), or magnetic random access memory (MRAM)) and It may also be NVRAM (Non-Volatile Random Access Memory, etc.). However, in general, the memory 115 may be a DRAM. Also, memory 115 may be any desired combination of various memory types.
The EEPROM 120 may store VPD (Vital, Product Data, 130). VPD 130 is data that storage device 125 can use to configure itself. For example, VPD 130 may store information about chassis 105 or information about a transport protocol to be used for communication with storage device 125 . Transport protocols to be used for communication with the storage device 125 may include, for example, Ethernet, Fiber Channel, InfiniBand, or NVMe, to name a few. VPD 130 may also include information regarding the transport subprotocols used. For example, if the VPD 130 specifies that an Ethernet transport protocol is to be used, the VPD 130 may store whether, among other possibilities, Remote Direct Memory Access (RDMA) over Converged Ethernet (RoCE) or iWarp will be used. can
1 shows that the VPD 130 is stored in the EEPROM 120, embodiments of the present invention may support the use of any other alternative storage media. For example, the EEPROM 120 may be replaced with an erasable programmable read only memory (EPROM) or flash memory, to name a few.
The storage device 125 may be any of a variety of storage devices. Examples of such devices may include Solid State Drives (SSDs). However, other storage types are also possible, such as hard disk drives or other long-term storage devices. Furthermore, memory 115 and storage device 125 may be combined. That is, embodiments of the present invention may not distinguish between the concepts of short-term storage and long-term storage. However, in the embodiments of the present invention, both may be managed within a single form factor. Also, the storage device 125 may be generalized to any device that may benefit from embodiments of the present invention. The use of storage device 125 is simplified for purposes described only.
Fig. 2 shows the chassis of Fig. 1 in further detail; Referring to FIG. 2 , a chassis 105 generally includes one or more processors 110 . Processors 110 include a controller 205 and clock 210 and are used to coordinate the operations of components of chassis 105 . Processors 110 may be coupled to memory 115 including, for example, random access memory (RAM), read-only memory (ROM), or other stateful medium. In addition, the processors 110 may be connected to the storage devices 125 and a network connector 215 (eg, an Ethernet connector or a wireless connector). In addition, the processors 110 may be connected to the bus 220 that may be connected to the user interface 225 and input/output interface ports that may be managed using the input/output engine 230 , among other components. can
3 and 4 show the device 125 of FIG. 1 operating in NVMe or NVMeoF mode. In FIG. 3 , the storage device 125 is shown to include a U.2 connector 305 , a PCIe Gen3 X4 chip 310 , storage 315 , a chassis type circuit 320 , and a mode configuration circuit 325 . became U.2 connector 305 is a special kind of connector that can be used on devices such as storage device 125 . With support for PCIe, SAS, and Serial AT Attachment (SATA) built in, the U.2 connector 305 can support a number of different interfaces. 3 and 4 illustrate the use of a U.2 connector 305, the U.2 connector 305 may be replaced with alternative connectors, which communicate in a manner consistent with embodiments of the present invention. They can be replaced if they can be supported. As U.2 connector 305 supports 4 lanes of PCIe communication and supports alternative communication channels such as SAS, the use of U.2 connector 305 has several advantages over other connectors.
The PCIe Gen3 X4 chip 310 is a chip that manages PCIe communications through the PCIe bus. Although a similar chip needs to be compatible with the communication methods provided by the connector, the PCIe Gen3 X4 chip 310 can be replaced with any similar chip capable of managing communications and is limited to using the PCIe bus. doesn't happen For example, a chip that does not manage PCIe communications may not work with the U.2 connector 305 . The combination has an advantage in that the combination of U.2 connector 305 and PCI Gen3 X4 chip 310 can have all the advantages of the four lanes of the PCIe bus available through U.2 connector 305 . have
Storage 315 may be in any desired storage format. For example, storage 315 may be a flash memory, or storage 315 may be a hard disk drive, among other possible examples. Embodiments of the present invention are not limited to a specific storage format. Of course, if storage device 125 is replaced with some other type of device, storage 315 may be replaced with some other function suitable for another type of device.
The chassis type circuit 320 may query the chassis 105 of FIG. 1 to determine the type of the chassis 105 of FIG. 1 . In one embodiment of the present invention, the chassis 105 of FIG. 1 may or may not be an HA chassis, and the chassis 105 of FIG. 1 may use the NVMe protocol to communicate with devices such as the storage device 125 . The NVMeoF protocol can be used. Thus, in this embodiment of the present invention, the chassis 105 of FIG. 1 may be any of four different types. Other embodiments of the present invention may also contemplate other possible types of chassis 105 of FIG. 1 .
Chassis type circuitry 320 may perform this query in any desired way. In an embodiment of the present invention, the chassis type circuit 320 may read information from the VPD 130 of FIG. 1 . The VPD 130 of FIG. 1 may specify the type of chassis 105 of FIG. 1 . In another embodiment of the present invention, the chassis type circuit 320 may access a signal on one or more pins of the U.2 connector 305 . This signal may specify the type of chassis 105 of FIG. 1 . For example, a low signal on one pin (eg, the E25 pin (DualPort En#) of the U.2 connector 305) can identify that the chassis 105 of FIG. 1 is an HA chassis. have. Here, a high signal on the corresponding pin can identify that the chassis 105 of FIG. 1 is not an HA chassis. The signals on the second pin may be used in parallel to specify whether the chassis 105 of FIG. 1 is using the NVMe protocol or the NVMeoF protocol. For example, these pins may be General Purpose Input/Output (GPIO) pins of the U.2 connector 305, which are not otherwise used. Also, these pins may not be pins in the U.2 connector 305 , although these pins may be located somewhere within the chassis 105 of FIG. 1 . The location of the pins is not critical as long as the storage device 125 can read the signals on the pins. Other embodiments of the present invention may include chassis type circuitry 320 that determines the type of chassis 105 of FIG. 1 in other ways.
In some embodiments of the present invention, the storage device 125 may be located in a legacy chassis. That is, the existing chassis is a chassis that is not designed to inform the storage device 125 of the type of the chassis directly or indirectly to the storage device 125 . When the chassis type circuit 320 does not determine the type of the chassis 105 of FIG. 1 , the chassis type circuit 320 defaults to a specific mode. For example, a specific mode, which is the default, configures the storage device 125 to use the NVMe protocol and may assume that the chassis 105 of FIG. 1 is not an HA chassis.
Once the chassis type circuit 320 determines the type of chassis 105 , the mode configuration circuit 325 can configure the storage device 125 to use the appropriate protocols and disable unnecessary protocols. For example, when the chassis type circuit 320 indicates that the chassis 105 is an NVMe chassis, the mode configuration circuit 325 may configure the storage device 125 to use the NVMe protocol.
In one embodiment of the present invention, using the NVMe protocol means that the PCIe lanes of the U.2 connector 305 are used in both the data plane and the control plane. If the chassis 105 of FIG. 1 is an HA chassis, the mode configuration circuit 325 may divide the PCIe lanes into two sets. One set is used to communicate with one host, and the other set is used to communicate with another host. For example, lanes 0 and 1 shown in PCIe X2 330 may be assigned to communicate with a first host, and lanes 2 and 3 shown in PCIe X2 335 may be assigned to communicate with a second host. can be allocated for Since the NVMe protocol does not use Ethernet, the mode configuration circuit 325 may “enable” the Ethernet ports on the U.2 connector 325 . If the chassis 105 of FIG. 1 is not an HA chassis, the mode configuration circuit 325 uses all four PCIe lanes for the data plane and the control plane, or (the other two PCIe lanes communicate with other hosts). (as reserved for ) only two PCIe lanes are available. More generally, embodiments of the present invention support using any number of lanes to communicate with any number of hosts. For example, if a connector supporting a given number of lanes (which may be four or more, such as U.2 connector 305) is used, then these lanes are used to communicate with various hosts in any assignment desired. can be For example, all lanes may be allocated to a single host within a non-HA chassis, or lanes may be allocated to communicate with various hosts equally or unevenly. In addition, all lanes may be allocated, or only a subset of the available lanes may be allocated.
In another embodiment of the present invention, using the NVMeoF protocol means that the PCIe lanes of the U.2 connector 305 are only used for the control plane. Ethernet ports are used for the data plane. When the chassis 105 of FIG. 1 is an HA chassis, the mode configuration circuit 325 may divide the PCIe lanes into two sets. One set is used to communicate with one host, and the other set is used to communicate with another host. For example, lanes 0 and 1 shown in PCIe X2 330 may be assigned to communicate with a first host, and lanes 2 and 3 shown in PCIe X2 335 may be assigned to communicate with a second host. can be allocated for However, data may be communicated through Ethernet ports, which may be formed through SAS pins on, for example, U.2 connector 305 . Different Ethernet ports may be formed on different SAS pins for different hosts. Accordingly, the Ethernet port 405 may be used to communicate data with a first host, and the Ethernet port 410 may be used to communicate data with a second host. Since the NVMeoF protocol does not use PCIe lanes for the data plane, the mode configuration circuitry 325 “remembers” the PCIe lanes on the U.2 connector 305 for data, even though the PCIe lanes are still used for the control plane. can be “disabled”. If the chassis 105 of FIG. 1 is not an HA chassis, the mode configuration circuit 325 either uses all four PCIe lanes for the control plane, or (as if the other two PCIe lanes are reserved for communicating with other hosts). ) can only use two PCIe lanes. Also, the mode configuration circuit 325 may set only one Ethernet port or set a plurality of Ethernet ports to communicate with one host. And, in theory, any number of SAS pins can be assigned to any Ethernet port.
The mode configuration circuit 325 may be implemented in any desired manner. A simple approach is that the mode configuration circuit 325 is configured as a demultiplexer. The information received from the chassis type circuit 320 may be a control signal to the demultiplexer. The control signal can then be used to select a specific destination for the signal (PCIe lanes or Ethernet ports). A more complex approach could be to include both NVMe protocol circuitry 340 and NVMeoF protocol circuitry 415 , and use mode configuration circuitry 325 to direct signals to appropriate circuitry. In this way, embodiments of the present invention may support any intermediary processing on the signals before they are sent to the appropriate pins of the U.2 connector 305 .
In general, although embodiments of the present invention that support hot plugging when a device is plugged into chassis 105 of FIG. 1 may determine the type of chassis 105 of FIG. 1 , Nevertheless, the chassis type circuit 320 determines the type of the chassis 105 of FIG. 1 upon boot up. That is, when the storage device 125 is powered up, the chassis type circuit 320 determines the type of the chassis 105 of FIG. 1 , and the mode configuration circuit 325 configures the storage device 125 . The storage device 125 then retains its configuration until the storage device 125 device is powered down or rebooted. However, in some embodiments of the present invention, if the chassis 105 of FIG. 1 changes its configuration, the chassis type circuit 320 may determine this fact. For example, to sense a change in signals on pins in the U.2 connector 305 , to periodically check the VPD 130 of FIG. 1 , or to identify a signal or a change in the VPD 130 of FIG. 1 . This may be determined by receiving a signal from some configuration (eg, BMC) of the chassis 105 of FIG. 1 . Then, the chassis type circuit 320 signals the mode configuration circuit 325 to change the mode of the storage device 125 . This may include rebooting the storage device 125 for the new mode to take effect.
4 , additional components are shown. Specifically, Ethernet 420, IP (Internet Protocol, 425), TCP (Transmission Control Protocol, 430), and RDMA (Remote Direct Memory Access, 435) are shown. Ethernet 420 , IP 425 , TCP 430 , RDMA 435 , and NVMeoF protocol 415 together constitute a fabric-attached engine. These components may be replaced or supplemented according to suitable implementations. For example, if it is desired to support protocols other than Ethernet (eg, InfiniBand or Fiber Channel), additional software may be used in place of or in addition to Ethernet 420 in the fabric-attached engine.
Figure 5 shows the device of Figure 1 communicating with two hosts within an HA chassis. In FIG. 5 , storage device 125 , PCIe X2 lanes 330 , 335 , and Ethernet ports 405 , 410 are shown. This data plane and control plane may communicate with the midplane 505 . The midplane 505 can then direct the data to the appropriate host. Accordingly, the host 510 may receive communications from the PCIe X2 lanes 330 and the Ethernet ports 405 . On the other hand, the host 515 may receive communications from the PCIe X2 lanes 335 and the Ethernet ports 410 .
5 shows a storage device 125 using the NVMeoF protocol 415 of FIG. 4 to communicate with two hosts in an HA chassis. If the storage device 125 had used the NVMe protocol 340 instead of the NVMeoF protocol 415 , the Ethernet ports 405 and 410 would not be shown. And, if the chassis is not an HA chassis, PCIe lanes ( 335) and the Ethernet ports 410 may be inactive or not shown in the drawing.
In addition to being self-configured and capable of supporting multiple modes, the storage device 125 of FIGS. 1-5 can also transmit valuable information to the system. For example, the storage device 125 may transmit information about its health state, Field-Replaceable Unit (FRU) information, sensor information, and/or discovery services. For example, the storage device 125 may report information about its health status (eg, how efficiently the storage device 125 is operating, etc.). This information may be global across the storage device 125 , or it may be more centralized. For example, for a particular region of storage 315 of storage device 125 of FIGS. 3 and 4 , storage device 125 may report that storage 315 is only “17.3% OK”. The FRU information may inform the chassis 105 of FIG. 1 about the status of all specific FRUs. For example, the FRU may be the EEPROM 120 of FIG. 1 , a switch board, a memory module, a processor, a BMC, or any other FRU. The sensor information may include, for example, information on a temperature sensor in the storage device 125 . The BMC can then use the information about the temperature sensor to adjust cooling in the chassis 105 of FIG. 1 . Discovery Services are disclosed in U.S. Provisional Patent Application No. US 62/394,726, filed September 14, 2016, and U.S. Patent Application No. 15/345,507, which claims priority thereto, which are incorporated herein by reference for all purposes. filed on November 7, 2016).
Also, the storage device 125 may support firmware updates. In embodiments of the present invention, the BMC in chassis 105 (or other chassis with which storage device 125 may communicate) may receive or download updated firmware. The BMC may then communicate with the storage device 125 , verify that the firmware update is compatible with the storage device 125 , and use the firmware update to upgrade the firmware in the storage device 125 . This firmware update may be executed as a background process. In particular, when the storage device 125 is operating using the NVMeoF protocol 415 of FIG. 4 , the firmware update may be performed using the control plane. Accordingly, any delays for applications using data on the storage device 125 are avoided.
6 is a flowchart exemplarily illustrating a procedure for self-configuring the device 125 of FIG. 1 according to an embodiment of the present invention. 6 , in S605 , the storage device 125 of FIG. 1 may determine the type of the chassis 105 of FIG. 1 . In some embodiments of the present invention, determining the type of chassis 105 includes determining whether the chassis 105 of FIG. 1 is an HA chassis, and/or determining whether the chassis 105 of FIG. 1 is a FIG. It may include determining whether to use the NVMe protocol 340 of 3 or the NVMeoF protocol 415 of FIG. 4 . As shown in S610 , among other possible examples, this determination may be performed by reading the type of chassis 105 of FIG. 1 from the VPD 130 of FIG. 1 . Alternatively, as shown in S615, this determination may be performed by accessing a signal from one or more pins (eg, GPIO pins) from the U.2 connector 305 of FIG. 3 . As a result, in S620 , the storage device 125 of FIG. 1 may be self-configuring. An example of this process is shown in more detail in FIGS. 7A and 7B below.
7A and 7B show the NVMe protocol 340 of FIG. 3 or the NVMeoF protocol 410 of FIG. 4, and the device 125 of FIG. 1 for an HA chassis or a non-HA chassis according to an embodiment of the present invention. - It is a flowchart showing the procedure for configuring by way of example. In FIG. 7A , in S705 , the storage device 125 of FIG. 1 may determine whether the chassis 105 of FIG. 1 is an HA chassis. In the case of an HA chassis, in S710 , the storage device 125 of FIG. 1 may determine whether the storage device 125 is an HA storage device. If the chassis 105 of FIG. 1 is an HA chassis but the storage device 125 of FIG. 1 is not an HA storage device, at S715 , the storage device 125 of FIG. 1 may report an alert. This is because single-port devices may not function properly within a dual-port chassis. After that, the processing ends.
On the other hand, when the storage device 125 of FIG. 1 operates in the chassis 105 of FIG. 1 , in S720 , the storage device 125 of FIG. 1 may determine the type of the chassis 105 of FIG. 1 . have. In the embodiment of the present invention shown in FIGS. 7A and 7B , the type of chassis is the NVMe protocol 340 of FIG. 3 or the NVMeoF protocol 415 of FIG. 4 . If the type of chassis 105 of FIG. 1 is not determined (eg, if the chassis 105 of FIG. 1 is an existing chassis that does not provide such information), then the NVMe protocol 340 of FIG. 3 is assumed .
When the chassis 105 of FIG. 1 uses the NVMeoF protocol 415 of FIG. 4 , in S725 of FIG. 7B , the storage device 125 of FIG. 1 serves as a control plane for communication with one host. or more) PCIe lanes. And in S730, the storage device 125 of FIG. 1 may activate one or more Ethernet ports as a data plane to communicate with a corresponding one host. In S735, for example, if the chassis 105 of FIG. 1 is an HA chassis, the storage device 125 of FIG. 1 activates two (or more) additional PCIe lanes as a control plane to communicate with the second host. can do. And, in S740 , the storage device 125 of FIG. 1 may activate one or more additional Ethernet ports as a data plane for communication with the corresponding second host. For example, Ethernet ports may operate through SAS pins on U.2 connector 305 of FIG. 3 . If the chassis 105 of FIG. 1 and the storage device 125 of FIG. 1 are not HA, S735 and S740 may be omitted as indicated by a dotted arrow 745 . Finally, at S750 , the storage device 125 of FIG. 1 may “disable” (by not activating) the use of lanes on the PCIe bus as a data plane on the storage device 125 of FIG. 1 .
On the other hand, when the chassis 105 of FIG. 1 uses the NVMe protocol 340 of FIG. 3 , in S755 , the storage device 125 of FIG. 1 uses both the data plane and the control plane in one host. It is possible to activate two (or more) lanes of the PCIe bus. In S760, for example, if the chassis 105 of FIG. 1 is an HA chassis, the storage device 125 of FIG. 1 uses two (or more) of the PCIe bus to use both the data plane and the control plane for the second host. ) can be activated. If the chassis 105 of FIG. 1 and the storage device 125 of FIG. 1 are not HA, S760 may be omitted as indicated by a dotted arrow 765 . Finally, in S770 , the storage device 125 of FIG. 1 may “disable” (by not activating) all Ethernet ports on the storage device 125 of FIG. 1 .
6 , 7A, 7B , some embodiments of the present invention are shown. However, by changing the order of blocks (or steps), omitting blocks, or including links not shown in the drawings, those skilled in the art will recognize that other embodiments of the present invention are also possible. All such variations of flow charts, whether explicitly described or not, are considered embodiments of the present invention.
The following description is intended to provide a brief and general description of a suitable machine (or machine) or machines in which some aspects of the inventive concept are implemented. The machine or machines are at least in part by instructions received from another machine, interaction with a virtual reality (VR) environment, biofeedback, or other input signals as well as input from conventional input devices such as a keyboard, mouse, etc. can be controlled. As used herein, the term “machine” is intended to broadly encompass a single machine, virtual machine, or a system coupled to communicate with machines, virtual machines, or devices operating together. Exemplary machines include personal computers, workstations, servers, portable computers, handheld devices, phones, tablets, as well as transport devices such as personal or public transport such as, for example, cars, trains, taxis, etc. computing devices, such as
The machine or machines may include embedded controllers such as programmable or non-programmable logic devices or arrays, application specific integrated circuits (ASICs), embedded computers, smart cards, and the like. The machine or machines may utilize one or more connections to one or more remote machines, such as through a network interface, modem, or other communication couplings. Machines may be connected to each other by means of physical and/or logical networks such as intranets, the Internet, local area networks (LANs), wide area networks (WANs), and the like. Those skilled in the art will appreciate that network communication utilizes a variety of wired and/or wireless near or far carriers and protocols including radio frequency (RF), satellite, microwave, IEEE 802.11, Bluetooth, optical, infrared, cable, laser, etc. will understand that
Embodiments of the inventive concept provide functions, procedures, data structures, applications that, when accessed by the machine, cause a machine to perform tasks or define abstract data types or low-level hardware contexts. may be described with reference to or cooperatively with associated data, including Associated data may include, for example, volatile and/or non-volatile memory such as RAM, ROM, etc., or other storage devices, and hard drives, floppy disks, optical storage, tapes, flash memory, memory sticks, digital video disks, etc. , may be stored in an associated storage medium including bio-storage and the like. The associated data may be transmitted in the form of packets, serial data, parallel data, transmission signals, etc., via transmission environments including physical and/or logical networks, and may be used in a compressed or encrypted format. Associated data may be used in a distributed environment and may be stored locally and/or remotely for machine access.
Embodiments of the inventive concept include a tangible, non-transitory machine-readable medium comprising instructions executable by one or more processors and causing the inventive inventive concept to be performed as described herein. can do.
Having the principles of the inventive concept described with reference to the illustrated embodiments, it is understood that the illustrated embodiments can be modified in arrangement and detail and combined in any necessary way without departing from these principles. will be understood Although the preceding description has focused on specific embodiments, other constructs are also contemplated. Specifically, notwithstanding descriptions such as "according to embodiments of the technical spirit of the present invention" or similar ones used herein, these phrases generally refer to possibilities of embodiments, and to implement the technical spirit of the present invention in specific implementations. It is not intended to be limited to example configurations. As used herein, these terms may refer to the same or different embodiments that are combinable into other embodiments.
The above-described embodiments are not to be construed as limiting the technical spirit of the present invention thereto. Although only a few embodiments have been described, those skilled in the art will fully appreciate that many modifications are possible to these embodiments without departing substantially from the novel descriptions and advantages of the present disclosure. Accordingly, all such modifications are intended to be included within the scope of the present invention as defined in the claims.
Embodiments of the inventive concept may be extended to the following statements without limitation.
Statement 1. An embodiment of the present invention includes an apparatus. The device is:
a connector connecting the device to a chassis;
a chassis type circuit for determining the type of chassis containing the device; and
and mode configuration circuitry configured to configure the device to use a first mode or a second mode in response to the type of chassis.
Statement 2. An embodiment of the invention comprises an apparatus according to statement 1,
The device further comprises storage for data.
Statement 3. An embodiment of the invention comprises a device according to statement 1,
The chassis type circuitry operates to determine the type of the chassis by reading Vital Product Data (VPD) from an address in an Electrically Erasable Programmable Read-Only Memory (EEPROM).
Statement 4. An embodiment of the invention comprises the device according to statement 1,
The chassis type circuitry is operative to determine the type of chassis from a signal on a pin on the connector.
Statement 5. An embodiment of the invention comprises an apparatus according to statement 4,
The pins on the connector include General Purpose Input/Output (GPIO) pins on the connector.
Statement 6. An embodiment of the invention comprises an apparatus according to statement 1,
The mode configuration circuit is operative to configure the device to use the first mode when the chassis type circuit fails to determine the type of the chassis.
Statement 7. An embodiment of the invention comprises an apparatus according to statement 1,
The first mode includes a Non-Volatile Memory express (NVMe) protocol for communication between the device and the chassis,
The second mode includes a Non-Volatile Memory express over Fabric (NVMeoF) protocol for communication between the device and the chassis.
Statement 8. An embodiment of the invention comprises the device according to statement 7,
The NVMeoF protocol includes logic for exchanging data between the device and the chassis using a protocol extracted from a set including Ethernet, InfiniBand, and Fiber Channel.
Statement 9. An embodiment of the invention comprises the device according to statement 7,
The connector supports a plurality of Peripheral Component Interconnect express (PCIe) lanes and Serial Attached Small computer system interface (SAS) pins.
Statement 10. An embodiment of the invention comprises the device according to statement 9,
The connector includes a U.2 connector.
Statement 11. An embodiment of the invention comprises the device according to statement 9,
When the type of chassis is NVMe, the mode configuration circuit uses the first two lanes of the PCIe lanes as a first data plane and a first control plane for a first host, and Ethernet via the SAS pins It works to disable the use of the port.
Statement 12. An embodiment of the invention comprises the device according to statement 9,
When the type of chassis is NVMeoF, the mode configuration circuit uses the first two lanes of the PCIe lanes as a first control plane for a first host, and uses a first set of SAS pins as a first data plane It operates to be used as the first Ethernet port for
Statement 13. An embodiment of the invention comprises the device according to statement 9,
The chassis type circuit is operative to determine whether the type of chassis is a High Availability (HA) chassis.
Statement 14. An embodiment of the invention comprises the device according to statement 13,
When the type of chassis is NVMe, the mode configuration circuit uses the second two lanes of the PCIe lanes as a second data plane and a second control plane for a second host, and Ethernet via the SAS pins It works to disable the use of the port.
Statement 15. An embodiment of the invention comprises the device according to statement 13,
When the type of chassis is NVMeoF, the mode configuration circuit uses the second two lanes of the PCIe lanes as a second control plane for a second host, and uses a second set of SAS pins as a second data plane It operates to be used as a second Ethernet port for
Statement 16. An embodiment of the present invention comprises a method comprising:
determining the type of chassis in which the device is installed; and
and configuring the device to activate a first communication mechanism and deactivate a second communication mechanism for the device according to the type of chassis.
Statement 17. An embodiment of the invention comprises a method according to statement 16,
Determining the type of chassis in which the device is installed includes accessing the type of chassis from a VPD in EEPROM.
Statement 18. An embodiment of the invention comprises a method according to statement 16,
Determining the type of chassis in which the device is installed includes accessing a signal from a pin on a connector associated with the device.
Statement 19. An embodiment of the present invention comprises a method according to statement 18,
Accessing a signal from a pin on a connector coupled with the device includes accessing the signal from a general purpose input/output (GPIO) pin on the connector coupled with the device.
Statement 20. An embodiment of the present invention comprises a method according to statement 16,
Determining the type of chassis in which the device is installed includes determining whether the type of chassis is an NVMe chassis or an NVMeoF chassis.
Statement 21. An embodiment of the invention comprises a method according to statement 20,
Determining whether the type of chassis is an NVMe chassis or an NVMeoF chassis includes, if the device fails to determine the type of the chassis, default setting the type of chassis to be the NVMe chassis do.
Statement 22. An embodiment of the present invention comprises a method according to statement 20,
According to the type of chassis, configuring the device to enable a first communication mechanism and deactivate a second communication mechanism for the device may include: if the type of chassis is the NVMe chassis;
enable the device to use two lanes in the PCIe bus as a first data plane and a first control plane for a first host, and disable the device from using an Ethernet port on the device for the first host including the steps of
Statement 23. An embodiment of the present invention comprises a method according to statement 22,
Determining the type of chassis in which the device is installed further includes determining whether the type of chassis is an HA chassis,
The method further includes determining whether the device is an HA device.
Statement 24. An embodiment of the present invention comprises a method according to statement 23,
According to the type of chassis, configuring the device to activate a first communication mechanism and deactivate a second communication mechanism for the device may include: if the type of chassis is the HA chassis and the device is an HA device If ,
activating a second two lanes in the PCIe bus as a second data plane and a second control plane for a second host.
Statement 25. An embodiment of the invention comprises a method according to statement 23,
The method further includes reporting an alert when the type of chassis is an HA chassis and the device is not an HA device.
Statement 26. An embodiment of the present invention comprises a method according to statement 20,
According to the type of chassis, configuring the device to enable a first communication mechanism and deactivate a second communication mechanism for the device may include: if the type of chassis is the NVMeoF chassis,
activating a first two lanes in the PCIe bus as a first control plane for a first host;
activating a first Ethernet port on the device as a first data plane for the first host; and
deactivating the lanes in the PCIe bus as the first data plane to the first host.
Statement 27. An embodiment of the present invention comprises a method according to statement 26,
Activating a first Ethernet port on the device as a first data plane to the first host includes using a first pair of SAS pins on a connector coupled to the device as the first Ethernet port.
Statement 28. An embodiment of the invention comprises a method according to statement 26,
Determining the type of chassis in which the device is installed includes determining whether the type of chassis is an HA chassis,
The method further includes determining whether the device is an HA device.
Statement 29. An embodiment of the present invention comprises a method according to statement 28,
According to the type of chassis, configuring the device to activate a first communication mechanism and deactivate a second communication mechanism for the device may include: if the type of chassis is an HA chassis and the device is an HA device case,
activating a second two lanes in the PCIe bus as a second control plane for a second host; and
activating a second Ethernet port on the device as a second data plane to the second host.
Statement 30. An embodiment of the invention comprises a method according to statement 29,
Activating a second Ethernet port on the device as a second data plane to the second host includes using a second pair of SAS pins on a connector coupled to the device as the second Ethernet port.
Statement 31. An embodiment of the invention comprises the method according to statement 28,
The method further includes reporting an alert when the type of chassis is an HA chassis and the device is not an HA device.
Statement 32. An embodiment of the present invention provides an apparatus comprising a tangible storage medium for storing Non-Transitory instructions,
When the non-transitory instructions are executed by the machine:
determining the type of chassis in which the device is installed; and
and configuring the device to activate a first communication mechanism and deactivate a second communication mechanism for the device according to the type of chassis.
Statement 33. An embodiment of the present invention comprises an apparatus according to statement 32,
Determining the type of chassis in which the device is installed includes accessing the type of chassis from a VPD in EEPROM.
Statement 34. An embodiment of the invention comprises an apparatus according to statement 32,
Determining the type of chassis in which the device is installed includes accessing a signal from a pin on a connector associated with the device.
Statement 35. An embodiment of the present invention comprises an apparatus according to statement 34,
Accessing a signal from a pin on a connector coupled to the device includes accessing the signal from a GPIO pin on the connector coupled to the device.
Statement 36. An embodiment of the present invention comprises an apparatus according to statement 32,
Determining the type of chassis in which the device is installed includes determining whether the type of chassis is an NVMe chassis or an NVMeoF chassis.
Statement 37. An embodiment of the present invention comprises an apparatus according to statement 36,
Determining whether the type of chassis is an NVMe chassis or an NVMeoF chassis includes, if the device fails to determine the type of the chassis, default setting the type of chassis to be the NVMe chassis do.
Statement 38. An embodiment of the present invention comprises an apparatus according to statement 36,
According to the type of chassis, configuring the device to enable a first communication mechanism and deactivate a second communication mechanism for the device may include: if the type of chassis is the NVMe chassis;
enable the device to use two lanes in the PCIe bus as a first data plane and a first control plane for a first host, and disable the device from using an Ethernet port on the device for the first host including the steps of
Statement 39. An embodiment of the present invention comprises an apparatus according to statement 38,
Determining the type of chassis in which the device is installed further includes determining whether the type of chassis is an HA chassis,
When the non-repository instructions are executed by the machine, they further perform the step of: determining whether the device is an HA device.
Statement 40. An embodiment of the present invention comprises an apparatus according to statement 39,
According to the type of chassis, configuring the device to activate a first communication mechanism and deactivate a second communication mechanism for the device may include: if the type of chassis is the HA chassis and the device is an HA device If ,
activating a second two lanes in the PCIe bus as a second data plane and a second control plane for a second host.
Statement 41. An embodiment of the present invention comprises an apparatus according to statement 39,
When the non-transitory instructions are executed by the machine:
If the type of chassis is an HA chassis and the device is not an HA device, the step of reporting an alert is further performed.
Statement 42. An embodiment of the present invention comprises an apparatus according to statement 36,
According to the type of chassis, configuring the device to enable a first communication mechanism and deactivate a second communication mechanism for the device may include: if the type of chassis is the NVMeoF chassis,
activating a first two lanes in the PCIe bus as a first control plane for a first host;
activating a first Ethernet port on the device as a first data plane for the first host; and
deactivating the lanes in the PCIe bus as the first data plane to the first host.
Statement 43. An embodiment of the present invention comprises an apparatus according to statement 42,
Activating a first Ethernet port on the device as a first data plane to the first host includes using a first pair of SAS pins on a connector coupled to the device as the first Ethernet port.
Statement 44. An embodiment of the present invention comprises an apparatus according to statement 42,
Determining the type of chassis in which the device is installed includes determining whether the type of chassis is an HA chassis,
When the non-repository instructions are executed by the machine, they further perform the step of: determining whether the device is an HA device.
Statement 45. An embodiment of the present invention comprises an apparatus according to statement 44,
According to the type of chassis, configuring the device to activate a first communication mechanism and deactivate a second communication mechanism for the device may include: if the type of chassis is an HA chassis and the device is an HA device case,
activating a second two lanes in the PCIe bus as a second control plane for a second host; and
activating a second Ethernet port on the device as a second data plane to the second host.
Statement 46. An embodiment of the present invention comprises an apparatus according to statement 45,
Activating a second Ethernet port on the device as a second data plane to the second host includes using a second pair of SAS pins on a connector coupled to the device as the second Ethernet port.
Statement 47. An embodiment of the present invention comprises an apparatus according to statement 44,
When the non-repository instructions are executed by the machine, further perform the step of: reporting an alert if the type of the chassis is an HA chassis and the device is not an HA device.
Consequently, in view of the various broad modifications to the embodiments described herein, this detailed description and accompanying material are intended to be illustrative only, and should not be construed as limiting the scope of the inventive concept. Accordingly, what is claimed as a concept of the invention are all modifications that may come within the scope and spirit of the following claims and their equivalents.

105: chassis 110: processor
115: memory 120: EEPROM
125: storage device 130: VPD
205: memory controller 210: clock
215: network connector 220: bus
225: user interface 230: input/output engine
305: U.2 connector 310: PCIe Gen3 X4 chip
315: storage 320: chassis type circuit
325: mode configuration circuit 330, 335: PCIe X2
340: NVMe 405, 410: Ethernet port
415: NVMeoF 420: Ethernet
425: IP 430: TCP
435: RDMA 505: Midplane
510, 515: host

Claims (10)

In the device:
a connector connecting the device to a component within a chassis;
a chassis type circuit for determining the type of chassis containing the device; and
mode configuration circuitry configured to configure the device to use a first mode or a second mode in response to the type of chassis;
the first mode includes a first transport protocol for communication between the device and the chassis;
the second mode includes a second transport protocol for communication between the device and the chassis; and
wherein the component performs an additional function in addition to determining the type of the chassis that contains the device. The method of claim 1,
and the chassis type circuitry is operative to determine the type of chassis from a signal on a pin on the connector. The method of claim 1,
and the chassis type circuitry is operative to determine from the component the type of the chassis that contains the device. The method of claim 1,
and the chassis type circuitry is operative to read the type of chassis from Vital Product Data (VPD). The method of claim 1,
The connector supports a plurality of Peripheral Component Interconnect Express (PCIe) lanes and Serial Attached Small Computer System Interface (SCSI) pins. 6. The method of claim 5,
based at least in part that the type of chassis is Non-Volatile Memory Express (NVMe), the mode configuration circuit uses two of the PCIe lanes as both a data plane and a control plane to a host; and a device operative to disable use of an Ethernet port through the SAS pins. 6. The method of claim 5,
Based at least in part on the type of chassis being Non-Volatile Memory Express over Fabric (NVMeoF), the mode configuration circuit uses two of the PCIe lanes as a control plane for a host, and SAS pins A device operative to use the set of as Ethernet ports to the data plane to the host. A method comprising:
determining the type of chassis in which the storage device is installed; and
based, at least in part, on the type of chassis being an NVMe chassis;
using two lanes in a PCIe bus as both a data plane and a control plane to a host and disabling an Ethernet port to the host;
the storage device is coupled to a component in the chassis using a connector, the component signals the storage device using at least one pin on the connector, and How to perform additional functions in addition to determining the type. 9. The method of claim 8,
Determining the type of chassis in which the storage device is installed includes accessing the signal from a pin on the connector. A method of operating an apparatus comprising a tangible non-transitory storage medium storing non-transitory instructions, the method comprising:
When the non-transitory instructions are executed by a machine:
determining the type of chassis in which the device is installed; and
causing the device to configure the device to activate a first communication mechanism and deactivate a second communication mechanism for the device according to the type of chassis;
The device is coupled to a component within the chassis using a connector, wherein the component performs an additional function in addition to determining the type of the chassis that contains the device.

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