KR102399541B1 - High speed delay-locked loop with built-in duty-cycle correction function - Google Patents

Abstract

The present invention relates to a high-speed digital delay locked loop circuit, which receives an input clock signal (CLK _IN ) and adjusts a delay amount of a delay line to adjust a phase between an input clock signal (CLK _IN ) and an output clock signal (CLK _OUT ) a digitally controlled delay line that reduces the error to within a preset delay resolution and corrects the duty cycle by adjusting the position of the falling edge of the clock signal; and a coarse time-to-digital converter that measures the phase difference between the input clock signal CLK _IN and the output clock signal CLK _OUT with coarse resolution in the delay locked loop locking process and generates a coarse delay code signal CDC. A high-speed digital delay locked loop circuit with built-in duty cycle correction is provided.

Description

High speed delay-locked loop with built-in duty-cycle correction function

The present invention relates to a high-speed digital delay locked loop circuit with a built-in clock duty cycle correction function. It relates to a high-speed digital delay-locked loop circuit capable of simultaneously performing high-frequency operation and duty cycle correction by repeatedly applying it to .

As the capacity of data to be sent and received increases, such as data for multimedia, high data transmission rates are required in various I/O interface applications. In particular, DDR5 SDRAM requires a performance level of up to 3.2GHz operating frequency and 6.4Gbps data transfer rate. In order to operate numerous analog and digital circuits integrated in the chip with synchronized clocks, a digital type delay-locked-loop (DLL) is widely used as a clocking circuit for SOC that eliminates the phase skew between input and output. do.

Memory interface or double sampling analog to digital converter (ADC), clock and data recovery (CDR) for double-data-rate (DDR) DRAM for high-speed interface implementation To implement double data rate (DDR) functionality using both the rising and falling edges of the output clock in applications such as A cycle correction (DCC) circuit is essential.

The existing time-to-digital converter (TDC)-based delay-locked loop circuits use a time-to-digital converter, so the locking speed is fast, but they do not include a duty cycle correction function, so they are not suitable for DDR applications. There were limits.

1 is a schematic block diagram of a circuit in which a duty cycle correction function according to the prior art is outside of a digital delay locked loop, and FIG. 2 is a schematic block diagram of a circuit in which a duty cycle correction function according to the prior art is included in a digital delay locked loop .

When the delay locked loop circuit and the duty cycle correction circuit are separately designed, a duty cycle correction function must be added by adding a duty cycle correction circuit to the output terminal of the delay locked loop circuit as shown in FIG. 1 . However, in this case, a phase error may occur between the output of the duty cycle correction circuit and the output of the delay locked loop circuit and the input of the delay locked loop circuit after the delay locked loop circuit is locked due to the time delay caused by the added duty cycle correction circuit. can

In order to solve this problem, as shown in FIG. 2 , a design has been mainly made by adding the duty cycle correction circuit to the front or rear end of the loop of the delay locked loop circuit. However, the structure according to FIG. 2 has a problem in that it is difficult to implement a high frequency because the time delay due to the added duty cycle correction circuit increases.

Korean Patent Registration No. 10-0670695

SUMMARY OF THE INVENTION The present invention is to overcome the above-described conventional problems, and an object of the present invention is to provide a high-speed digital delay locked loop circuit having a duty cycle correction function.

According to an exemplary embodiment of the present invention, a phase error between the input clock signal CLK _IN and the output clock signal CLK _OUT is preliminarily received by receiving the input clock signal CLK _IN and adjusting the delay amount of the delay line. a digitally controlled delay line that reduces the delay within the set delay resolution and corrects the duty cycle by adjusting the position of the falling edge of the clock signal; and a coarse time-to-digital converter that measures the phase difference between the input clock signal CLK _IN and the output clock signal CLK _OUT with coarse resolution in the delay locked loop locking process and generates a coarse delay code signal CDC. A high-speed digital delay locked loop circuit with built-in duty cycle correction is provided.

The digitally controlled delay line includes: a coarse delay line for adjusting the amount of delay by adjusting the number of delay cells used; a first half-fine delay line positioned in front of the coarse delay line and configured to adjust a delay amount with a relatively high resolution compared to the coarse delay line; and a second half-fine delay line positioned at a rear end of the coarse delay line and configured to adjust a delay amount with a relatively high resolution compared to the coarse delay line.

It further includes a DLL coarse shift register that receives and stores a coarse delay code signal CDC from the coarse time-to-digital converter and controls the operation of the coarse delay line according to the coarse delay code signal.

The coarse time-to-digital converter further includes a first vernier fine time-to-digital converter that measures a phase difference that is not measured, and encodes the measured fine delay to generate a fine delay code signal (FDC).

A fine delay code signal (FDC) received from the first vernier fine time-to-digital converter is stored, and fine for controlling fine delays of the first half-fine delay line and the second half-fine delay line of the digitally controlled delay line. and a DLL fine shift register for generating and applying a code signal F[15:0].

The first vernier fine time-to-digital converter uses two delay lines, and a delay cell used for each delay line measures each phase while narrowing the interval between two phases to be measured by (Δt).

The apparatus further includes a phase detector for tracking an error by comparing the phases of the input clock signal CLK _IN and the output clock signal CLK _OUT .

After locking the delay locked loop, the coarse time-to-digital converter measures the pulse width with coarse resolution during the duty cycle correction locking process, measures the position of the falling edge of the output clock signal CLK _OUT , and A coarse duty cycle correction code signal (CDCC) may be generated.

It further includes a DCC coarse shift register that receives the coarse duty cycle correction signal (CDCC) generated by the coarse time-to-digital converter and generates a control signal for controlling the coarse delay line of the digital control delay line.

The coarse time-to-digital converter measures the phase difference between the falling edge and the locking point, which cannot be measured, and a fine duty cycle correction code signal (FDCC[16:0]; Fine Duty Cycle Code) encoding the measured phase difference is obtained. It further includes a second vernier fine time-to-digital converter for generating.

DCC fine shift applied to the first half-fine delay line and the second half-fine delay line of the digitally controlled delay line by generating a fine duty cycle code signal (FD[15:0]) for controlling the fine duty cycle correction control the register. At this time, the role of the second vernier fine time-to-digital converter is changed to a DCC fine shift register and reused.

The apparatus further includes a timing controller receiving the output clock signal CLK _OUT and generating and outputting an enable signal for mode change.

The coarse delay line CDL includes a plurality of coarse delay units (CDUs).

The coarse delay unit (CDU) maintains the rising edge delay constant, but a digital falling edge shifter (DFES) capable of shifting the falling edge left and right according to the input digital code (C _DA , C _DB ) ) is included.

Each of the first and second half-fine delay lines includes a plurality of fine delay units (FDUs) and fine digital falling edge shifters connected to output terminals of the plurality of fine delay units.

For fine locking of duty cycle correction, the second vernier fine time-to-digital converter has a higher resolution than the first vernier fine time-to-digital converter.

The present invention can obtain a fast locking speed by repeatedly applying the time-to-digital converter-based sensing method to the digital delay locked loop and the duty cycle correction.

In addition, the delay line uses a delay cell with duty cycle correction, so that the delay line itself measures and corrects phase skew and duty cycle errors, eliminating the need for additional duty cycle correction circuitry within the delay locked loop, simplifying and simplifying the manufacturing process. Cost savings can be achieved.

1 is a schematic configuration diagram of a circuit in which a duty cycle correction circuit is added in addition to a digital delay locked loop circuit and a loop according to the prior art.
2 is a schematic block diagram of a circuit in which a duty cycle correction function according to the prior art is included in a digital delay locked loop.
3 is a schematic configuration diagram of a high-speed digital delay locked loop circuit incorporating a duty cycle correction function according to an embodiment of the present invention.
4 is a block diagram of a high-speed digital delay locked loop circuit with a built-in duty cycle correction function shown in FIG. 3 .
5 is a view showing the entire operation process of the high-speed digital delay locked loop circuit incorporating the duty cycle correction function according to the present invention.
6 is a diagram showing the configuration of a digital control delay line and a coarse time-to-digital converter.
7A is a diagram illustrating the configuration of a coarse delay unit (CDU) of a digitally controlled delay line, and FIG. 7B is a diagram illustrating an operation of the coarse delay unit.
8 is a diagram illustrating a configuration of a half-fine delay line (HFDL).
9A and 9B are diagrams illustrating an operation of a coarse time-to-digital converter when a phase difference is detected in a delay locked loop locking mode.
10 is a diagram showing the configuration of the first vernier fine TDC and the DLL fine shift register.
11 is a flowchart illustrating a duty cycle correction locking process.
12A is a diagram illustrating an operation of a coarse time-to-digital converter for pulse width detection, and FIG. 12B is a timing diagram and output code for pulse width detection.
13 is a diagram showing the configuration of a DCC coarse shift register.
14 is a diagram showing the configuration of the second vernier fine TDC and DCC fine shift registers.
15 is a diagram illustrating a process of controlling a falling edge of a DCC coarse shift register.
16 is a timing diagram of a second vernier fine TDC.
17 is a view showing a simulation result showing a locking process according to the present invention.

Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.

3 is a schematic configuration diagram of a high-speed digital delay locked loop circuit with a built-in duty cycle correction function according to an embodiment of the present invention, and FIG. 4 is a high-speed digital delay locked loop with a built-in duty cycle correction function shown in FIG. It is a schematic diagram of the circuit.

3 and 4, the high-speed digital delay fixed loop circuit 100 with a built-in duty cycle correction function according to an embodiment of the present invention includes a digitally controlled delay line (DCDL) 110, Coarse time-to-digital converter (CTDC) 120, DLL coarse shift register (DLL coarse shift register) 130, first vernier fine time-to-digital converter (Vernier fine TDC (DLL)) 140, DLL fine shift register 150, phase detector 160, DCC coarse shift register 170, second vernier fine time-to-digital converter (Vernier fine TDC) (DCC) 180 , a DCC fine shift register 190 and a timing controller 200 . DLL stands for delay-locked-loop, and DCC stands for duty cycle correction.

A digitally controlled delay line (DCDL) 110 receives an input clock signal (CLK _IN ), adjusts the delay amount of the delay line, an input clock signal (CLK _IN ) and an output clock signal (CLK _OUT ) It reduces the phase error or skew between the two within a preset delay resolution, and performs a function of correcting the duty cycle by adjusting the position of the falling edge of the clock signal.

The digitally controlled delay line 110 connects a coarse delay line (CDL) 115 , a first half fine delay line (HFDL) 111 , and a second half-fine delay line 112 . include

The coarse delay line 115 performs a function of adjusting the delay amount by adjusting the position of the falling edge of the clock signal.

The first half-fine delay line 111 is positioned at the front end of the coarse delay line 115 , and the second half-fine delay line 112 is positioned at the rear end of the coarse delay line 115 . The first and second half-fine delay lines 111 and 112 perform a function of adjusting the delay amount with a relatively high resolution compared to the coarse delay line 115 .

The coarse time-to-digital converter 120 converts the phase difference between the input clock signal CLK _IN and the output clock signal CLK _OUT to coarse resolution in the delay locked loop locking process. It measures and encodes the measured coarse delay to generate a coarse delay code signal (CDC; Coarse Delay Code).

In addition, in the duty cycle correction locking process, a pulse width, ie, a duty cycle, is measured with coarse resolution.

The DLL coarse shift register 130 inputs the coarse delay code signal CDC generated by encoding the coarse delay measured by the coarse time-to-digital converter 120 from the coarse time-to-digital converter 120 . take and save

The first vernier fine time-to-digital converter (Vernier fine TDC (DLL)) 140 measures the phase difference that was not measured by the coarse time-to-digital converter 120, and the measured fine A fine delay code signal (FDC) is generated by encoding the delay.

In this case, the first vernier fine time-to-digital converter uses two delay lines, and a delay cell used for each delay line has a delay difference Δt corresponding to the highest resolution to be measured. If each phase is measured while narrowing the interval between the two phases to be measured by (Δt), it is possible to measure the phase difference that the coarse time-to-digital converter cannot measure.

The DLL fine shift register 150 converts the fine delay code signal FDC generated by encoding the fine delay measured by the first vernier fine time-to-digital converter 140 to the first vernier fine time-to-digital converter 140 . It receives input from the converter 140 and stores it.

Then, after storing the stored fine delay code signal FDC[15:0], the fine code signal F for controlling the fine delay of the first half-fine delay line and the second half-fine delay line of the digital control delay line [15:0]) is created and authorized.

The phase detector 160 compares the phases of the input clock signal CLK _IN and the output clock signal CLK _OUT to track an error.

After the delay locked loop locking, the coarse time-to-digital converter 120 measures the pulse width with coarse resolution during the duty cycle correction locking process. That is, the position of the falling edge of the output clock signal CLK _OUT is measured, and a coarse duty cycle correction signal CDCC is generated for the measured falling edge position, and the generated coarse duty cycle correction signal is DCC applied to the coarse shift register 170 .

DCC coarse shift register (DCC coarse shift register) 170 receives a coarse duty cycle correction signal (CDCC) as an input to control a coarse delay line (Coarse delay line) of a digitally controlled delay line (DCDL) Generates a control signal.

The second vernier fine time-to-digital converter (Vernier fine TDC (DCC)) 180 has a falling edge and a locking point (ie, 50) that are not measured by the coarse time-to-digital converter 120 . % duty ratio), and generates a fine duty cycle correction code signal (FDCC[16:0]) based on the measured phase difference.

The DCC fine shift register 190 generates a fine duty cycle code signal FD[15:0] for controlling fine duty cycle correction, so that the first half-fine delay line of the digitally controlled delay line and to the second half-fine delay line.

The timing controller 200 receives the output clock signal CLK _OUT , generates and outputs an enable signal for mode conversion. That is, the timing controller 200 generates C _E (coarse enable signal), _FE (coarse enable signal), STORE, and _TE signals.

5 is a view showing the entire operation process of the high-speed digital delay locked loop circuit incorporating the duty cycle correction function according to the present invention. Referring to FIG. 5 , first, delay locked loop (DLL) locking is performed for 6 cycles, and duty cycle correction (DCC) locking is started 7 cycles after phase alignment.

In the delay-locked loop locking process of the first 6 cycles, it operates in 3 modes, 2 cycles each.

During the first two cycles, the phase difference is measured with coarse resolution.

During the next two cycles, the remaining phase difference, which could not be measured with the coarse resolution, is measured with the fine resolution, which is relatively high-resolution compared to the coarse resolution.

During the last two cycles, the time-to-digital code signal corresponding to the total phase difference value measured above is stored in the DLL coarse shift register and the DLL fine-sist register, and then the coarse delay line and the first and second halves of the digital control delay line are stored. Applied to fine delay lines, delay locked loop locking is performed.

After the 7th cycle, the phase skew is removed and delay-locked loop locking is completed.

From the 7th cycle, the duty cycle correction (DCC) locking process starts, and the 8th output clock changes TDC _EN back to high and activates the coarse time-to-digital converter that was used earlier, and then the pulse width with coarse resolution for the 9th cycle. measure

As the 10th cycle Apply Code (AC) turns high, the TDC code corresponding to the measured pulse width is applied to the coarse delay line (CDL).

Duty cycle correction in the 11th cycle After checking whether the coarse locking is properly completed, the FINE _EN signal becomes high from the 12th cycle if it is locked, and the duty cycle error that is not measured with the coarse resolution is measured with the fine resolution.

If all remaining duty cycle errors are measured with fine resolution, the AFC signal becomes 1 and the corresponding TDC code is applied to the two half-fine delay lines (HFDL), respectively, and duty cycle correction locking is completed.

Fine duty cycle error measurement takes a minimum of 3 cycles and a maximum of 9 cycles, and the total locking time can take up to 24 cycles.

After all locking is completed, signals such as C _E , F _E , TDC _EN , FINE _EN become 0 to stop all TDC operations and reduce power consumption due to unnecessary TDC operation.

6 is a diagram showing the configuration of a digital control delay line and a coarse time-to-digital converter, FIG. 7a is a diagram showing the configuration of a coarse delay unit (CDU) of a digital control delay line, and FIG. 7b is a diagram showing the operation of the coarse delay unit FIG. 8 is a diagram showing the configuration of a half-fine delay line HFDL.

The digitally controlled delay line 110 connects a coarse delay line (CDL) 115 , a first half fine delay line (HFDL) 111 , and a second half-fine delay line 112 . include

The coarse delay line (CDL) 115 includes a plurality of coarse delay units (CDUs). In this embodiment, the coarse delay line 115 is composed of 16 coarse delay units CDU#1 to CDU#16.

An operation according to a specific circuit and code of each coarse delay unit (CDU) is shown in FIG. 7 . FIG. 7 shows the configuration of the third coarse delay unit CDU#3 shown in FIG. 6 .

The coarse delay unit (CDU) shown in FIG. 7A is a delay cell that includes a circuit capable of shifting a falling edge with a digital code and has a constant rising edge delay at the same time.

Although the rising edge delay is kept constant, the falling edge can be shifted to the left or right according to the input digital code (C _DA , C _DB ), so it is called a digital falling edge shifter (DFES).

As shown in FIG. 7B , each coarse delay unit CDU has a fixed delay value t _CDU of 80 ps when digital codes C _DA and C _DB are initialized to 0 and 1, respectively.

If the C _DA code changes from 0 to 1, the current driving strength of the pull up path of the first stage and the pull down path of the second stage in a digital falling edge shifter (DFES) ), the delay of the falling edge is increased by 20ps while keeping the delay of the rising edge at 80ps(t _CDU ).

Conversely, when the C _DB code changes from 1 to 0, each driving force is increased, so the rising edge delay is maintained at 80ps (t _CDU ) and only the falling edge delay is reduced by 20ps. As such, each CDU can adjust its duty cycle by adjusting the position of the falling edge of the clock signal.

8 shows a configuration of a first half-fine delay line (HFDL) 111 and a second half-fine delay line 112 disposed at both ends of a coarse delay line (CDL) 115 . This is shown. Since the first half-fine delay line and the second half-fine delay line have the same structure, the first half-fine delay line will be described below.

The first half-fine delay line 111 includes a plurality of fine delay units (FDUs) 111a and a fine digital falling edge shifter (Fine DFES) 111b.

In the present embodiment, the first half-fine delay line 111 is composed of four fine delay units 111a, and the fine digital falling edge shifter is connected to the output terminal of the fine delay unit.

Each fine delay unit consists of 4 shunt capacitances, the first half-fine delay line has 16 shunt capacitance based delay units controlled by the code F[15:0], and the Adjust the amount of delay in the range of 40ps (2.5ps×16) as a resolution.

Since the first and second half-fine delay lines, ie, two half-fine delay lines, are used, the delay width by t _CDU (80 ps) can be adjusted, and the resolution becomes 5 ps.

There is a fine digital falling edge shifter (Fine _DFES ) at the output of the 4 fine delay units, and 8 FD codes can right shift the falling edge with a resolution of 2ps. A total of 16 F _D [15:0] codes are applied to two HFDLs at both ends of the coarse delay line, and the falling edge shifting is performed for a total range of 32 ps.

The delay of the falling edge is adjusted to a higher resolution (2ps) than the delay adjustment resolution of the rising edge (5ps), because the clock cycle is very short in the case of high frequencies. becomes significantly larger and eventually significantly affects the deterioration of jitter performance.

9A and 9B are diagrams illustrating an operation of a coarse time-to-digital converter when a phase difference is detected in a delay locked loop locking mode.

During the first 6cycles after the start of operation, it operates in a delay-locked loop locking (DLL locking) mode. The coarse delay line (CDL) shown in FIG. 6 receives a total of two signals of CDL _BEFORE or CLK _OUT as inputs. Initially, C[0 ] is initialized to '0' and the rest of C[15:1] is initialized to '1', so CDL _BEFORE is input to CDU#16, the last CDU of CDL, and the CLK _OUT signal is to CDU#1, the first CDU of CDL. is input Therefore, the initial delay of the digital delay control line DCDL from the input clock signal CLK _IN to the output clock signal CLK _OUT is the sum of two minimum delays of the half-fine delay line HFDL and one coarse delay unit delay. do.

t _I (Initial Delay) = HFDL _min *2 + t _CDU *1

When the _CE signal becomes high by the ^1st clock of CLK _OUT , the coarse time-to-digital converter operates in the phase measurement mode as shown in FIG. 9 .

FIG. 9a shows a coarse time-to-digital converter of FIG. 6 when the C _E signal input to each register is 1, C[0]='0', C[15:1]='1' It is a figure that simply expresses the operation of a digital converter.

The CLK _IN signal, CDL _BEFORE , D[1:15], and CDL _AFTER are all input after passing the MUX delay of the same value, and operate as in the timing diagram of FIG. 9B .

The output clock signal CLK _OUT is input to the first coarse delay unit CDU#1 and outputs multi-phase signals of D[1] to CDL _AFTER at intervals of 80ps(t _CDU ). The input clock signal CLK _IN is used as a clock signal of the flip-flop to measure the phase difference t _P between the input clock signal CLK _IN and the output clock signal CLK _OUT by a time-to-digital converter.

For example, in the case of FIG. 9B , there are 5 t _CDU delays between the output clock signal CLK _OUT and the input clock signal CLK _IN , so t _P becomes tCDU×5 + α. The coarse delay measured by the coarse time-to-digital converter (CTDC) is output as the TDC code Q[16:0], and is encoded back into the CDC[15:0] code by the NAND gate. At this time, the measured CDC[15:0] code is later stored in the DLL coarse shift register by the 6th output clock signal (6 ^th CLK _OUT ) when the STROE signal becomes 1, and then the final C[15:0] code becomes coarse. applied to the delay line CDL.

10 is a diagram showing the configuration of the first vernier fine TDC and DLL fine shift registers.

During the first two cycles of the delay locked loop locking process, when coarse delay measurement is completed with the coarse time-to-digital converter, for the next two cycles, the coarse time-to-digital converter is converted to a coarse time-to-digital converter using the first Vernier Fine TDC. Measure the unmeasured phase difference (α).

10 shows a first vernier fine TDC and a DLL fine shift register for storing fine TDC codes.

The first vernier fine time-to-digital converter 140 includes two delay lines, and a delay cell used for each delay line has a delay difference Δt corresponding to the highest resolution to be measured. If each phase is measured while the interval between the two phases to be measured is narrowed by Δt, the phase difference that has not been measured in the coarse time-to-digital converter can be output as a TDC code. The highest resolution of Fine Delay Line is 5ps, so Δt is 5ps.

The CDC[15:0] code from the coarse time-to-digital converter is applied to the 16:1 MUX of the first fine vernier time-to-digital converter to select the D[x] signal, and the input clock signal (CLK _IN ) D[x ] to obtain a fine TDC code FDC[15:0] by measuring the phase difference of the signal with the first vernier time-to-digital converter. When the Vernier Fine TDC is activated as the F _E signal becomes 1, the delay value corresponding to α is output as a TDC code.

After measuring up to the fine phase difference and outputting the FDC[15:0] code, the FDC[15:0] code is stored in the DLL fine shift register 150, and the generated F[15:0] code is generated after saving. It applies to the 1st and 2nd half-fine delay lines.

That is, when the TDC code of C[15:0] and F[15:0] is applied to the digital control delay line, the phase skew between the input clock signal CLK _IN and the output clock signal CLK _OUT is removed, phase alignment.

Since a phase skew may occur due to a supply voltage or temperature change after the delay locked loop locking, in order to avoid a lock fail state due to this, the delay locked loop operates as a closed loop.

After locking, in order to reduce power consumption, the operation of the coarse and fine time-to-digital converter is stopped, and the phase of the output clock signal (CLK _OUT ) and the input clock signal (CLK _IN ) is compared in the phase detector 160 and the voltage, temperature Trace errors caused by changes.

By using the HOLD/COMP signal output after comparing the phases of the two clock signals from the phase detector 160, the F[15:0] code is shifted and tracked in the DLL fine shift register.

11 is a flowchart illustrating a duty cycle correction locking process, FIG. 12A is a diagram illustrating an operation of a coarse time-to-digital converter for pulse width sensing, and FIG. 12B is a timing diagram and output code of pulse width sensing.

After the delay locked loop locking is completed, the duty cycle correction locking process is largely divided into a coarse locking process and a fine locking process.

<Course locking process>

When the delay locked loop locking is completed, the number of coarse delay units (CDUs) required for the delay line is determined. When the number of CDUs is 2X-1 or 2X, first, the position of the falling edge of the output clock signal CLK _OUT is coarse. Measured with a time-to-digital converter.

After measurement, when the TDC code signal (CDCC[16:0]) for the falling edge position is output, it is applied to the DCC coarse shift register 170 (1 ^st :apply code), and the falling edge is applied to the X-th coarse delay unit. move to After measuring once more with the coarse time-to-digital converter whether the falling edge is properly positioned on the X-th coarse delay unit, coarse locking is completed.

If the falling edge is not positioned properly, the code is shifted in the DCC coarse shift register to move the falling edge until the falling edge is positioned on the X-th coarse delay unit.

After locking the delay locked loop, the phases of the input clock signal CLK _IN and the output clock signal CLK _OUT are aligned, and the delay magnitude of the digital control delay line after locking is equal to one cycle of the clock. Accordingly, as in the timing diagram of FIG. 12B , the multi-phase on the digital control delay line measures the pulse width of the output clock signal CLK _OUT in only one cycle, and outputs the TDC code (CDCC[16:0]).

13 is a diagram showing the configuration of a DCC coarse shift register.

DCC coarse shift register (DCC coarse shift register) 170 receives a coarse duty cycle correction signal (CDCC) as an input to control a coarse delay line (Coarse delay line) of a digitally controlled delay line (DCDL) Generates a control signal.

The amount that one digital falling edge shifter (DFES) of the coarse delay unit can shift the falling edge is ±20ps (t _CDU /4), and the amount of each bit of the CDCC[16:0] code measured in the coarse time-to-digital converter is Since the interval is t _CDU (80ps), one bit of the CDCC[16:0] code must be applied to a total of 4 coarse delay units (CDUs) at once to control the falling edge at intervals of 80ps (20ps×4) .

The DCC coarse shift register of FIG. 13 is composed of 4 blocks of 4 bundles each of C _DA and C _DB in order to adjust the C _DA [15:0] and C _DB [15: 0] codes by grouping them 4 each.

Depending on how many coarse delay units are used in the delay locked loop locking process, the number of bits of the CDCC code to be input to each block varies. Therefore, C[15:0] is encoded as CC[8:0], entered as a control signal of the MUX of each block, and an appropriate CDCC code is selected. At this time, the selected CDCC code is used to set or reset C _DA and C _DB of each block, and the falling edge is shifted after the code is applied.

14 is a diagram showing the configuration of the second vernier fine TDC and DCC fine shift registers.

<Fine locking process>

After the coarse duty cycle correction locking, the second vernier fine time-to-digital converter (Vernier Fine TDC ( _DCC ) )) (180) is used.

In the case of duty cycle correction, the delay amount of the falling edge is adjusted with a higher resolution than the fine resolution in the delay locked loop. In particular, in the case of high-frequency operation, if the falling edge is not located exactly at the center of the clock cycle, an error occurs because the period is relatively short. This is because as the ratio increases, the duty cycle error increases significantly, and the jitter characteristics are also very poor.

Therefore, without reusing the first vernier fine TDC (DLL) used in the delay locked loop as if the coarse time-to-digital converter was reused, for fine locking of duty cycle correction, a higher resolution than the first vernier fine TDC was used. 2 Vernier fine time-to-digital converters are used.

The second vernier fine time-to-digital converter of FIG. 14 is configured with two different delay lines like the first vernier time-to-digital converter of FIG. 10 .

In this embodiment, each delay line is composed of 17 delay cells, and each delay cell is different from each other by 2ps(Δt), so the detection range of the second vernier fine time-to-digital converter corresponds to 32ps.

Because the detection range is narrowed while improving the fine resolution to 2ps, the fine detection range of the falling edge is less than one coarse duty cycle correction unit (32ps < 80ps).

Therefore, the process of locating the falling edge within the measurable range with the fine time-to-digital converter is prioritized, and the second vernier fine time-to-digital converter measures at once, and then completes the duty cycle correction fine locking.

15 is a diagram illustrating a process of controlling a falling edge of a DCC coarse shift register, and FIG. 16 is a timing diagram of a second vernier fine TDC.

15 shows a process of shifting the falling edge in the DCC coarse shift register until the falling edge of the output clock signal CLK _OUT falls within the measurable range of the second vernier fine time-to-digital converter.

If the falling edge is not within the fine detection range (32ps), control the C _DA ,C _DB code in the DCC coarse shift register to shift the falling edge to the right once every 3 cycles. Since the size of t _CDU is 80ps and the CDU moves the falling edge by 20ps, a maximum of 3 movements are required, and this takes 16 to 25 cycles for fine duty cycle compensation locking.

If the falling edge is within the detection range (32ps), the second vernier fine time-to-digital converter measures the phase difference between the falling edge and the 50% point (locking point), which is not measured in the coarse time-to-digital converter as shown in FIG. 16 This outputs the TDC code (FDCC[16:0]).

After measurement up to fine duty cycle correction, the FD[15:0] code of FIG. 14 is applied to the first and second half-fine delay lines of the digitally controlled delay line to complete duty cycle correction locking.

After all locking is finished, the DCC coarse shift register and DCC fine shift register also use the falling edge phase detector included in FIG. 14 as in the closed loop operation of the delay locked loop to measure the phase difference between the falling edge and the rising edge of the clock center. Compare and track. Accordingly, even after locking, even if the input duty cycle fluctuates or a duty cycle error occurs due to a change in voltage or temperature, it is possible to correct it.

17 is a view showing a simulation result showing a locking process according to the present invention.

What has been described above is only an exemplary embodiment of a high-speed digital delay locked loop circuit with a built-in duty cycle correction function according to the present invention, and the present invention is not limited to the above embodiment, but is claimed in the following claims As such, without departing from the gist of the present invention, it will be said that the technical spirit of the present invention exists to the extent that various modifications can be made by anyone with ordinary knowledge in the field to which the present invention belongs.

110: digital control delay line
120: coarse time-to-digital converter
130: DLL coarse shift register
140: first vernier fine time-to-digital converter
150 : DLL Fine Shift Register
160: phase detector
170: DCC coarse shift register
180: second vernier fine time-to-digital converter
190: DCC Fine Shift Register
200: timing controller

Claims (12)

In the high-speed digital delay locked loop circuit with built-in duty cycle correction function,
It receives the input clock signal CLK _IN , and adjusts the delay amount of the delay line to reduce the phase error between the input clock signal CLK _IN and the output clock signal CLK _OUT within the preset delay resolution. a digitally controlled delay line that adjusts the position of the falling edge to compensate for the duty cycle; and
A coarse time-to-digital converter that measures the phase difference between the input clock signal (CLK _IN ) and the output clock signal (CLK _OUT ) with coarse resolution in the delay locked loop locking process and generates a coarse delay code signal (CDC); includes,
The digital control delay line,
a coarse delay line for adjusting the amount of delay by adjusting the number of delay cells used;
a first half-fine delay line positioned in front of the coarse delay line and configured to adjust a delay amount with a relatively high resolution compared to the coarse delay line; and
A high-speed digital delay fixed loop circuit with a built-in duty cycle correction function comprising a; a second half-fine delay line positioned at a rear end of the coarse delay line and adjusting a delay amount with a relatively high resolution compared to the coarse delay line.
delete According to claim 1,
and a DLL coarse shift register that receives and stores a coarse delay code signal CDC from the coarse time-to-digital converter and controls the operation of the coarse delay line according to the coarse delay code signal; High-speed digital delay locked loop circuit with built-in cycle correction function.
According to claim 1,
A first vernier fine time-to-digital converter that measures the phase difference that was not measured by the coarse time-to-digital converter and encodes the measured fine delay to generate a fine delay code signal (FDC); further comprising A high-speed digital delay locked loop circuit with a built-in duty cycle correction function.
5. The method of claim 4,
A fine delay code signal (FDC) received from the first vernier fine time-to-digital converter is stored, and fine for controlling fine delays of the first half-fine delay line and the second half-fine delay line of the digitally controlled delay line. A high-speed digital delay locked loop circuit with a built-in duty cycle correction function, further comprising a DLL fine shift register that generates and applies a code signal (F[15:0]).
5. The method of claim 4,
The first vernier fine time-to-digital converter uses two delay lines, and the delay cell used for each delay line measures each phase while narrowing the interval between the two phases to be measured by (Δt) unit. High-speed digital delay locked loop circuit with built-in duty cycle correction function.
According to claim 1,
High-speed digital delay locked loop circuit with a built-in duty cycle correction function, characterized in that it further comprises a phase detector for tracking an error by comparing the phases of the input clock signal (CLK _IN ) and the output clock signal (CLK _OUT ).
According to claim 1,
After locking the delay locked loop, the coarse time-to-digital converter is reused in the duty cycle correction locking process to measure the pulse width with coarse resolution to measure the position of the falling edge of the output clock signal CLK _OUT , and the measured falling edge A high-speed digital delay locked loop circuit with built-in duty cycle correction, characterized in that it generates a coarse duty cycle correction signal (CDCC) for position.
9. The method of claim 8,
DCC coarse shift register receiving the coarse duty cycle correction signal (CDCC) generated by the coarse time-to-digital converter and generating a control signal for controlling the coarse delay line of the digital control delay line; characterized in that it further comprises High-speed digital delay-locked loop circuit with built-in duty cycle correction.
9. The method of claim 8,
The second vernier measures the phase difference between the falling edge and the locking point, which is not measured by the coarse time-to-digital converter, and generates a fine duty cycle correction code signal (FDCC[16:0]) encoding the measured phase difference. A high-speed digital delay locked loop circuit with a built-in duty cycle correction function, characterized in that it further comprises a fine time-to-digital converter.
9. The method of claim 8,
DCC fine shift applied to the first half-fine delay line and the second half-fine delay line of the digitally controlled delay line by generating a fine duty cycle code signal (FD[15:0]) for controlling the fine duty cycle correction A high-speed digital delay locked loop circuit with a built-in duty cycle correction function, characterized in that it further comprises a register.
According to claim 1,
The high-speed digital delay fixed loop circuit with a built-in duty cycle correction function, further comprising a timing controller receiving the output clock signal (CLK _OUT ) and generating and outputting an enable signal for mode conversion.

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