KR102397395B1 - Wide range lo generator and apparatus including the same - Google Patents

Abstract

According to an exemplary embodiment of the present disclosure, a local oscillator (LO) generator for providing a local oscillator signal to a mixer includes an input buffer for receiving an input oscillation signal and outputting a first internal oscillation signal, the frequency of the first internal oscillation signal and a frequency division circuit for outputting a second internal oscillation signal by division, and an output buffer for receiving the second internal oscillation signal and outputting a local oscillation signal, wherein the input buffer and the frequency division circuit are independent of the output buffer and may be configured to receive a power supply voltage.

Description

WIDE RANGE LO GENERATOR AND APPARATUS INCLUDING THE SAME

The technical idea of the present disclosure relates to wireless communication, and more particularly, to an LO (Local Oscillator) generator for generating a local oscillation signal and an apparatus including the same.

As non-limiting examples, a variety of wireless communication systems, such as a Code Division Multiple Access (CDMA) system, a Global System for Mobile Communications (GSM) system, a Wideband Code Division Multiple Access (WDCDMA) system, a Long Term Evolution (LTE) system, etc. A wireless communication device capable of supporting standards can provide a wide range of applications. In order to support various standards of a wireless communication system, a wireless communication device may include a transceiver capable of supporting a wideband, and the transceiver uses a local oscillator signal to provide a wide range of frequencies. It is possible to process a received signal according to a carrier having them. The amount of power consumed by the transceiver as well as the width of the transceiver's supportable band may be very important, for example, in a battery-operated portable terminal. Accordingly, there is a need for a transceiver that supports a wide bandwidth and at the same time consumes low power.

SUMMARY The present disclosure provides a local oscillator (LO) generator that provides a local oscillation signal having a wide range of frequencies in a wireless communication system, and an apparatus including the same.

In order to achieve the above object, an LO generator for providing a local oscillation signal to a mixer according to an aspect of the technical concept of the present disclosure includes an input buffer for receiving an input oscillation signal and outputting a first internal oscillation signal, a first a frequency division circuit for outputting a second internal oscillation signal by dividing the frequency of the internal oscillation signal, and an output buffer for receiving the second internal oscillation signal and outputting a local oscillation signal, the input buffer and the frequency division circuit comprising: It may be configured to receive the supply voltage independently of the output buffer.

According to an aspect of the technical concept of the present disclosure, an apparatus for wireless communication includes an LO generator for outputting a local oscillation signal by dividing a frequency of an input oscillation signal and receiving a first power supply voltage, a mixer for receiving the local oscillation signal, and a controller that controls the frequency of the input oscillation signal and the frequency division ratio of the LO generator based on the carrier frequency of the wireless communication, and controls to adjust the first power supply voltage based on the frequency of the input oscillation signal and the frequency division ratio of the LO generator may include

A frequency divider for dividing an oscillation signal of an oscillator according to an aspect of the present disclosure may include an injection-locked oscillator including a plurality of gated inverters, and each of the plurality of gated inverters includes: may include first and second PMOS transistors, first and second NMOS transistors, which are finFETs sequentially connected in series between a power supply voltage and a negative power supply voltage of An input signal of a next stage may be generated at the drains, an output signal of a previous stage may be applied to gates of the first PMOS transistor and the second NMOS transistor, and the gates of the second PMOS transistor and the first NMOS transistor An oscillation signal may be applied to the .

According to an LO generator and an apparatus including the same according to an exemplary embodiment of the present disclosure, a local oscillation signal having a wide range of frequencies can be generated, and power consumed to generate the local oscillation signal can be reduced.

1 shows a block diagram of a wireless communication system including a user equipment and a base station according to an exemplary embodiment of the present disclosure.
2A and 2B are block diagrams illustrating examples of the RX LO generator of FIG. 1 in accordance with example embodiments of the present disclosure.
3 is a block diagram illustrating an AC-coupled buffer according to an exemplary embodiment of the present disclosure.
4 is a block diagram illustrating an RX LO generator according to an exemplary embodiment of the present disclosure.
5A is a block diagram illustrating an example of the duty adjustment circuit of FIG. 4 according to an exemplary embodiment of the present disclosure, and FIG. 5B is a waveform diagram illustrating the signals of FIG. 5A according to an exemplary embodiment of the present disclosure.
6A is a block diagram illustrating an RX LO generator according to an exemplary embodiment of the present disclosure, and FIG. 6B is a block diagram illustrating an example of the output buffer of FIG. 6A according to an exemplary embodiment of the present disclosure.
7 is a circuit diagram illustrating a frequency divider according to an exemplary embodiment of the present disclosure.
8A is a circuit diagram illustrating a frequency divider according to an exemplary embodiment of the present disclosure, and FIG. 8B is a graph illustrating characteristics of the frequency divider in FIG. 8A according to an exemplary embodiment of the present disclosure.
9A is a block diagram illustrating a multiplexer according to an exemplary embodiment of the present disclosure, and FIG. 9B is a graph illustrating output power according to fan-out of the multiplexer according to an exemplary embodiment of the present disclosure.
10 is a block diagram illustrating an RX LO generator according to an exemplary embodiment of the present disclosure.
11 is a block diagram illustrating an RX LO generator according to an exemplary embodiment of the present disclosure.
12 is a flowchart illustrating a method of controlling the transceiver of FIG. 1 according to an exemplary embodiment of the present disclosure.
13 is a flowchart illustrating a method of controlling the transceiver of FIG. 1 according to an exemplary embodiment of the present disclosure;

1 shows a block diagram of a wireless communication system 5 including a user equipment 10 and a base station 20 according to an exemplary embodiment of the present disclosure.

The wireless communication system 5 may be, by way of non-limiting example, a Long Term Evolution (LTE) system, a Code Division Multiple Access (CDMA) system, a Global System for Mobile Communications (GSM) system, a Wireless Local Area Network (WLAN) system, or other It may be standard in any wireless communication system. Hereinafter, the wireless communication system 5 is mainly described with reference to the LTE system, but it will be understood that the exemplary embodiments of the present disclosure are not limited thereto.

A base station (BS) 20 may generally refer to a fixed station that communicates with user equipment and/or other base stations, and provides data and control information by communicating with user equipment and/or other base stations. can be exchanged for For example, the base station 20 is a Node B, an evolved-Node B (eNB), a sector, a site, a base transceiver system (BTS), an access pint (AP), a relay node, It may also be referred to as a remote radio head (RRH), a radio unit (RU), a small cell, and the like. In this specification, the base station 20 or cell is a generic meaning representing some area or function covered by a base station controller (BSC) in CDMA, Node-B in WCDMA, an eNB or a sector (site) in LTE, etc. It can be interpreted and can cover various coverage areas such as megacells, macrocells, microcells, picocells, femtocells and relay nodes, RRHs, RUs, and small cell communication ranges.

User Equipment (UE) 10 is a wireless communication device, which may be fixed or mobile, and may refer to various devices capable of transmitting and receiving data and/or control information by communicating with the base station 20 . . For example, the user equipment 10 may include a terminal equipment, a mobile station (MS), a mobile terminal (MT), a user terminal (UT), a subscriber station (SS), a wireless device, and a portable device. (handheld device), etc. may be referred to.

The wireless communication network between the user equipment 10 and the base station 20 may support multiple users to communicate by sharing available network resources. For example, in a wireless communication network, Code Division Multiple Access (CDMA), Frequency Division Multiple Access (FDMA), Time Division Multiple Access (TDMA), Orthogonal Frequency Division Multiple Access (OFDMA), Single Carrier Frequency Division Multiple (SC-FDMA), Access), OFDM-FDMA, OFDM-TDMA, OFDM-CDMA, and the like, information can be transmitted in various multiple access methods.

As shown in FIG. 1 , the user equipment 10 and the base station 20 may communicate with each other through an uplink (UL) and a downlink (DL). In the uplink (UL) and the downlink (DL), data may be transmitted by a carrier in a frequency channel, and carrier aggregation using a plurality of carriers simultaneously is an uplink (UL) or a downlink (DL). can also be used in The range of frequencies of carriers used in uplink (UL) and downlink (DL) may be determined by a standard of a wireless communication system, and in order to support various standards of a wireless communication system, the user equipment 10 and/or the base station 20 may include a transceiver capable of handling a carrier wave having a wide range of frequencies. For example, the user equipment 10 may include a transceiver 13 capable of processing a carrier wave having a wide range of frequencies in order to communicate with base stations that comply with different standards of a wireless communication system. Hereinafter, exemplary embodiments of the present disclosure will be mainly described with reference to the user equipment 10 for convenience of description, but the base station 20 may also include the transceiver and components for controlling the transceiver according to the exemplary embodiment of the present disclosure. It should be noted that possible

Referring to FIG. 1 , a user device 10 may include an antenna 11 , switches/duplexers 12 , a transceiver 13 , a controller 14 , and a Power Management Integrated Circuit (PMIC) 15 . there is. The switches/duplexers 12 may provide a signal received through the antenna 11 as an RX input signal RXin to the transceiver 13 , and receive a TX output signal TXout received from the transceiver 13 . It may be provided to the antenna 11 .

The transceiver 13 may generate an RX output signal RXout by processing the RX input signal RXin and provide it to the controller 14 , as shown in FIG. 1 , to process the RX output signal RXin To this end, it may include a low noise amplifier (LNA) 110 , an RX mixer 120 , a baseband filter 130 , an RX oscillator 140 , and an RX LO generator 150 . The low-noise amplifier 110 may amplify the RX input signal RXin, and the RX mixer 120 generates the RX baseband signal RXb from the RX local oscillation signal RX_LO and the output signal RXr of the low-noise amplifier 110 . ) can be created. The baseband filter 130 may generate the RX output signal RXout by removing unwanted images from the RX baseband signal RXb.

In addition, the transceiver 13 may generate the transmit output signal TXout by processing the TX input signal TXin received from the controller 14, and as shown in FIG. 1 , the TX input signal TXin For processing, it may include a TX mixer 210 , an RF filter 220 , a Power Amplifier (PA) 230 , a TX oscillator 240 , and a TX LO generator 250 . The TX mixer 210 may generate the TX RF signal TXr from the TX local oscillation signal TX_LO and the TX input signal TXin. The RF filter 220 may generate a TX filtered signal TXf by removing unwanted images from the TX RF signal TXr, and the power amplifier 230 may amplify the TX filtered signal TXf to output the TX A signal TXout may be generated.

The RX LO generator 150 and the TX LO generator 250 may respectively generate local oscillation signals RX_LO and TX_LO having the same frequency as the frequency of the carrier wave. For example, the RX LO generator 150 generates an RX local oscillation signal RX_LO based on the RX oscillation signal RX_O received from the RX oscillator 140 and the RX control signal C_RX received from the controller 14 . can create Similarly, the TX LO generator 250 generates a TX local oscillation signal TX_LO based on the TX oscillation signal TX_O received from the TX oscillator 240 and the TX control signal C_TX received from the controller 14 . can do.

Although, one RX mixer 120 and one RX LO generator 150 are illustrated in FIG. 1 to process the RX input signal RXin, exemplary embodiments of the present disclosure are not limited thereto, for example, a transceiver (13) may include a plurality of RX mixers and a plurality of RX LO generators for carrier aggregation. Similarly, the transceiver 13 may include a plurality of TX mixers and a plurality of TX LO generators for carrier aggregation.

The controller 14 may receive the reception output signal RXout from the transceiver 13 , and may provide the transmission input signal TXin to the transceiver 13 . The controller 14 may process the RX output signal RXout, and may generate the TX input signal TXin by processing data, and may be referred to as a data processor. Also, the controller 14 may generate control signals C_RX and C_TX for controlling the transceiver 13 , and may provide a DVS control signal C_DVS to the PMIC 15 . In some embodiments, the controller 14 may include hardware logic designed through logic synthesis, or a processor that executes software stored in a memory or the like.

In some embodiments, the controller 14 may obtain the carrier frequency of the downlink (DL) determined by the base station 20, and RX such that the RX local oscillation signal RX_LO has the same frequency as the carrier frequency. The RX LO generator 150 may be controlled through the control signal C_RX. Similarly, in some embodiments, the controller 14 may obtain the carrier frequency of the uplink (UL) determined by the base station 20, and the TX local oscillation signal TX_LO has the same frequency as the carrier frequency. It is possible to control the TX LO generator 250 through the TX control signal (C_TX) to have it.

Although not shown in FIG. 1 , in some embodiments, the RX oscillator 140 may receive an RX control signal C_RX, and the RX oscillator 140 generates an RX LO generator according to the RX control signal C_RX. The frequency of the RX oscillation signal RX_O that is the input oscillation signal of 150 may be adjusted. For example, the RX oscillator 140 may include at least one voltage controlled oscillator (VCO), and according to the RX control signal C_RX, a VCO may be selected or a frequency of an output signal of the VCO may be adjusted. Similarly, in some embodiments, TX oscillator 240 may also receive a TX control signal (C_TX).

In some embodiments, the controller 14 may adjust the power supply voltages V_RX and V_TX generated by the PMIC 15 through the DVS control signal C_DVS based on the obtained carrier frequency. For example, the controller 14 may decrease the RX power supply voltage V_RX when the frequency of the oscillation signal processed inside the RX LO generator 150 is relatively low, while in the RX LO generator 150 . When the frequency of the oscillation signal to be processed is relatively high, the RX power supply voltage V_RX may be increased. That is, the controller 14 may perform dynamic voltage scaling (DVS) according to the frequency of the internal oscillation signal of the RX LO generator 150 . Similarly, the controller 14 may adjust the TX power supply voltage V_TX. When the carrier frequency is low, the RX power supply voltage (V_RX) does not necessarily drop, and as will be described later with reference to FIG. 4 and the like, in some embodiments, for the RX oscillation signal (RX_LO) of the desired frequency, the RX oscillator ( Based on the frequency of the RX oscillation signal RX_O generated by 140 and the configuration of the RX LO generator 150 , the RX power supply voltage V_RX may be adjusted.

When the internal oscillation signals of relatively low frequencies are processed by the RX LO generator 150 and the TX LO generator 250 , the power supply voltages V_RX and V_TX fall, thereby the RX LO generator 150 and the TX LO generator 250 . ) can reduce power consumption. In addition, as will be described later with reference to FIG. 8B and the like, the adjustment of the power supply voltages V_RX and V_TX of the RX LO generator 150 and the TX LO generator 250 is performed by the RX LO generator 150 and the TX LO generator ( 250) may cause a change in the frequency tuning range of the frequency divider, and the changed frequency tuning range of the frequency divider is combined with frequencies of the oscillation signals RX_O and TX_O to generate local oscillation signals ( RX_LO, TX_LO) can extend the adjustable frequency range. In the following, exemplary embodiments of the present disclosure will be mainly described with reference to an RX LO generator 150 for processing a signal received over a downlink (DL), but exemplary embodiments of the present disclosure include a TX LO generator It will be understood that the same applies to (250).

2A and 2B are block diagrams illustrating examples of the RX LO generator 150 of FIG. 1 in accordance with example embodiments of the present disclosure. As described above with reference to FIG. 1 , the RX LO generators 500 and 500 ′ of FIGS. 2A and 2B may receive a variable power supply voltage V_RX. FIGS. 2A and 2B will be described above with reference to FIG. 1 , and overlapping descriptions of FIGS. 2A and 2B will be omitted.

Referring to FIG. 2A , the RX LO generator 500 may generate the RX local oscillation signal RX_LO from the RX oscillation signal RX_O according to the RX control signal C_RX, and the first and second power supply voltages V_RX1 , V_RX2 may be supplied with power from the RX power supply voltage V_RX. The RX LO generator 500 may include an input buffer 510 , a frequency division circuit 520 , and an output buffer 530 .

The input buffer 510 may receive the RX oscillation signal RX_O and output the first internal oscillation signal SIG_1 . For example, the input buffer 510 may include at least one inverter. The frequency divider circuit 520 may output the second internal oscillation signal SIG_2 by dividing the frequency of the first internal oscillation signal SIG_1 according to the RX control signal C_RX. That is, the frequency division ratio of the first internal oscillation signal SIG_1 may be determined by the RX control signal C_RX. The output buffer 530 may receive the second internal oscillation signal SIG_2 and output the RX local oscillation signal RX_LO. For example, the output buffer 530 may include at least one inverter.

As shown in FIG. 2A , the input buffer 510 and the frequency divider circuit 520 may receive the first power voltage V_RX1 through the first path 501 , and the output buffer 530 may provide the second The second power voltage V_RX2 may be received through the path 502 . That is, the input buffer 510 and the frequency division circuit 520 may receive the first power voltage V_RX1 independently of the output buffer 530 , and the first and second power voltages V_RX1 and V_RX2 are can be adjusted independently of each other. In some embodiments, the first power supply voltage V_RX1 may be adjusted based on the frequency of the RX oscillation signal RX_O, while the second power supply voltage V_RX2 may be fixed. For example, the supply voltage of a mixer (eg, 120 in FIG. 1 ) receiving the RX local oscillation signal RX_LO may be fixed and in order to meet the high voltage level of the RX local oscillation signal RX_LO required by the mixer, The second power voltage V_RX2 provided to the output buffer 530 may be fixed (eg, at the same level as the power voltage of the mixer). In this case, the output buffer 530 may include a structure (eg, the AC-coupled buffer 30 of FIG. 3 ) for processing the second internal oscillation signal SIG_2 having a variable high voltage level. Also, in some embodiments, both the first and second power supply voltages V_RX1 and V_RX2 may be adjusted based on the frequency of the RX oscillation signal RX_O.

Referring to FIG. 2B , the RX LO generator 500 ′ may receive an RX power supply voltage V_RX including first to third power supply voltages V_RX1 to V_RX3 , and an input buffer 510 ′, frequency division. circuitry 520' and an output buffer 530'.

The input buffer 510 ′ and the frequency divider circuit 520 ′ have power supply voltages V_RX3 , independently of the output buffer 530 ′, compared to the input buffer 510 and the frequency divider circuit 520 of FIG. 2A . In addition to receiving V_RX1), the power supply voltages V_RX3 and V_RX1 may be received independently of each other. For example, as shown in FIG. 2B , the input buffer 510' may receive the third power supply voltage V_RX3 through the third path 503', and the frequency divider circuit 520' may The first power supply voltage V_RX1 may be received through the first path 501 ′, and the output buffer 530 ′ may receive the second power supply voltage V_RX2 through the second path 502 ′. In some embodiments, at least one of the first to third power supply voltages V_RX1 to V_RX3 may be adjusted based on the frequency of the RX oscillation signal RX_O. Hereinafter, the RX LO generators described with reference to the drawings include an input buffer, a frequency divider circuit, and an output buffer for receiving a power supply voltage independently of each other, as shown in FIG. 2B , but exemplary embodiments of the present disclosure include The present invention is not limited thereto, and as shown in FIG. 2A , it will be understood that the RX LO generator described below may include an input buffer and a frequency divider circuit that receive the same power supply voltage.

3 is a block diagram illustrating an AC-coupled buffer 30 according to an exemplary embodiment of the present disclosure. Hereinafter, FIG. 3 will be described with reference to FIGS. 2A and 2B.

As described above with reference to FIGS. 2A and 2B , at least one of the components of the RX LO generator 500 or 500 ′ may receive a power supply voltage independently of the other components. For example, in the RX LO generator 500 of FIG. 2A , the second power supply voltage V_RX2 supplied to the output buffer 530 is fixed and the first power supply voltage V_RX1 supplied to the frequency divider circuit 520 is When adjusted, the high voltage level of the second internal oscillation signal SIG_2 may vary. When the high voltage level of the oscillation signal fluctuates, a circuit that receives the oscillation signal may not recognize the transition or duty cycle of the oscillation signal as being valid. Accordingly, the output buffer 530 may include a structure for effectively processing the second internal oscillation signal SIG_2 having a varying high voltage level, and in some embodiments, the output buffer 530 may include the second internal oscillation signal SIG_2. An AC-coupled buffer 30 for AC coupling the internal oscillation signal SIG_2 may be included.

Referring to FIG. 3 , the AC-coupled buffer 30 may include an inverter INV, a feedback resistor R and a capacitor C, and an AC-coupled self-biased inverter. It may also be referred to as a buffer. 3 , the feedback resistor R may have both ends respectively connected to the input terminal and the output terminal of the inverter INV, and the capacitor C is the first connected to the input terminal of the AC-coupled buffer 30 . and a second terminal connected to the input terminal of the inverter INV. Accordingly, the AC-coupled buffer 30 may output the output oscillation signal OUT by effectively recognizing the transition of the input signal IN despite a change in the high voltage level of the input oscillation signal IN.

4 is a block diagram illustrating an RX LO generator 500a according to an exemplary embodiment of the present disclosure. As shown in FIG. 4 , the RX LO generator 500a includes an input buffer 510a that receives the third power supply voltage V_RX3 , a frequency divider circuit 520a that receives the first power supply voltage V_RX1 , and a second power supply voltage V_RX3 . It may include an output buffer 530a that receives the power supply voltage V_RX2.

Referring to FIG. 4 , the frequency divider circuit 520a includes first to fourth frequency dividers 521a to 524a receiving the first internal oscillation signal SIG_1 , a selection circuit 525a , and a duty adjustment circuit 526a . may include As described above with reference to FIG. 1 , the RX oscillation signal RX_O may have a predetermined frequency range, and in some embodiments, the first internal oscillation signal SIG_1 output from the input buffer 510a is RX It may have the same frequency as the oscillation signal RX_O. The number and/or frequency division ratios of the first to fourth frequency dividers 521a to 524a included in the frequency divider circuit 520a may be determined according to the frequency range and carrier frequency range of the RX oscillation signal RX_O. there is. For example, as shown in FIG. 4 , each of the first to fourth frequency dividers 521a to 524a may have an assigned frequency range of the first internal oscillation signal SIG_1, and its frequency division ratio Accordingly, the frequency of the first internal oscillation signal SIG_1 may be divided.

The selection circuit 525a may receive a plurality of oscillation signals output from the first to fourth frequency dividers 521a to 524a and select one of the plurality of oscillation signals according to the RX control signal C_RX. there is. In some embodiments, the output signal S_50 of the selection circuit 525a may be an oscillation signal selected from among a plurality of oscillation signals, or an oscillation signal obtained by processing (eg, frequency division) the selected oscillation signal.

The duty control circuit 526a may generate the second internal oscillation signal SIG_2 by adjusting the phase of the output signal S_50 of the selection circuit 525a. For example, the duty cycle of the output signal S_50 of the selection circuit 525a may be different from the duty cycle required by the mixer (eg, 140 of FIG. 1 ) receiving the RX local oscillation signal RX_LO. Accordingly, the duty adjustment circuit 526a may adjust the phase of the output signal S_50 of the selection circuit 525a. Details of the duty adjustment circuit 526a will be described later with reference to FIGS. 5A and 5B .

The first to fourth frequency dividers 521a to 524a may receive the first power supply voltage V_RX1 , and the first power supply voltage V_RX1 is the frequency of the RX oscillation signal RX_O (or the first internal oscillation signal). (frequency of SIG_1)). For example, the first internal oscillation signal SIG_1 having a frequency range of 3610 MHz to 5380 MHz is sequentially processed by the first frequency divider 521a, the selection circuit 525a, and the duty control circuit 526a. Assuming that, as the frequency of the first internal oscillation signal SIG_1 is closer to 3610 MHz, the first power supply voltage V_RX1 provided to the first frequency divider 521a may decrease, while the first internal oscillation signal SIG_1 may decrease. As the frequency of the signal SIG_1 approaches 5380 MHz, the first power voltage V_RX1 may increase. Accordingly, power consumption consumed by the first frequency divider 521a may be reduced compared to the case where the fixed first power voltage V_RX1 is used.

5A is a block diagram illustrating an example of the duty adjustment circuit 526a of FIG. 4 according to an exemplary embodiment of the present disclosure, and FIG. 5B is a waveform diagram illustrating the signals of FIG. 5A according to an exemplary embodiment of the present disclosure. As described above with reference to FIG. 4 , the duty adjustment circuit 526a ′ of FIG. 5A may output the second internal oscillation signal SIG_2 by adjusting the phase of the output signal S_50 of the selection circuit 525a. . 5A and 5B will be described below with reference to FIG. 4 .

The output signal S_50 of the selection circuit 525a may have a duty cycle of 50%. For example, as shown in FIGS. 5A and 5B , the output signal S_50 of the selection circuit 525a includes signals LOIP_50 and LOIM_50 for the I-channel and signals LOQP_50 for the Q-channel, LOQM_50), and signals LOIP_50 and LOIM_50 for the I-channel and signals LOQP_50 and LOQM_50 for the Q-channel may have a duty cycle of 50%. Also, as shown in FIG. 5B , there may be a 25% phase difference between the signal LOIP_50 for the I-channel and the signal LOQP_50 for the Q-channel corresponding to each other.

The second internal oscillation signal SIG_2 may have a duty cycle of 25%. For example, as described above with reference to FIG. 4 , the passive mixer may require an RX local oscillation signal RX_LO having a duty cycle of 25%, and accordingly, the second internal oscillation signal SIG_2 may have a 25% duty cycle. It may have a duty cycle. As shown in FIG. 5B , the second internal oscillation signal SIG_2 has a duty of 25% corresponding to the signals LOIP_50 and LOIM_50 for the I-channel and the signals LOQP_50 and LOQM_50 for the Q-channel. Signals having a cycle (LOIP_25, LOIM_25, LOQP_25, LOQM_25) may be included.

5A , to generate four signals (LOIP_25, LOIM_25, LOQP_25, LOQM_25) having a duty cycle of 25% from four signals (LOIP_50, LOIM_50, LOQP_50, LOQM_50) having a duty cycle of 50% To this end, the duty adjustment circuit 526a' may include four AND gates. The inputs of the four AND gates may be interconnected as shown in FIG. 5A .

6A is a block diagram illustrating an RX LO generator 500b according to an exemplary embodiment of the present disclosure, and FIG. 6B is a block diagram illustrating an example output buffer 530b of FIG. 6A according to an exemplary embodiment of the present disclosure. am.

Referring to FIG. 6A , similar to the RX LO generator 500a of FIG. 4 , the RX LO generator 500b of FIG. 6A may include an input buffer 510b, a frequency divider circuit 520b and an output buffer 530b. The frequency divider circuit 520b may include first to fourth frequency dividers 521b to 524b and a selection circuit 525b. The output buffer 530b may include an AC-coupled buffer 531b and a duty adjustment circuit 532b. Compared with the RX LO generator 500a of FIG. 4 , the duty adjustment circuit 532b in the output buffer 530b of FIG. 6A may be included in the output buffer 530b. As shown in FIG. 6A , the input buffer 510b may receive the third power supply voltage V_RX3, and the frequency divider circuit 520b may receive the first power supply voltage V_RX1, and the output buffer ( 530b may receive the second power supply voltage V_RX2.

Referring to FIG. 6B , similar to the duty adjustment circuit 526a ′ of FIG. 5B , the output buffer 530b ′ includes four signals LOIP_50 , LOIM_50 , LOQP_50 , LOQM_50 having a duty cycle of 50%. The second internal oscillation signal SIG_2 may be received, and an RX local oscillation signal RX_LO including four signals LOIP_25 , LOIM_25 , LOQP_25 , and LOQM_25 having a 25% duty cycle may be output.

The AC-coupled buffer 531b' may AC-couple each of the four signals LOIP_50, LOIM_50, LOQP_50, LOQM_50, and the output signals of the AC-coupled buffer 531b' are applied to the duty adjustment circuit ( 532b'). Duty adjustment circuit 532b' may include four NAND gates and four inverters, and consequently may operate similarly to duty adjustment circuit 526a' of FIG. 5B including four AND gates.

7 is a circuit diagram illustrating a frequency divider 70 according to an exemplary embodiment of the present disclosure. Specifically, FIG. 7 shows an exemplary circuit diagram of a divide-by-two frequency divider 70 that outputs the output oscillation signal OUT by dividing the frequency of the input oscillation signal IN by two.

As described above with reference to FIG. 4 and the like, the frequency division circuit 520a of the RX LO generator 500a may include a plurality of frequency dividers, and as described above with reference to FIG. 5B and the like, the differential oscillation signals are As used, the divide-by-two frequency divider 70 can receive the differential signals IN, /IN and output the differential signals OUT, /OUT, referred to as a divide-by-two differential frequency divider. it might be Referring to FIG. 7 , the frequency division by 2 frequency divider 70 may include gated inverters 71 to 74 and latches 75 and 76 . In addition, the latches 75 and 76 may be implemented in various ways, as shown in FIG. 7 as a non-limiting example, n-latch 76a, p-latch 76b, CMOS latch 76c, etc. this can be used

8A is a circuit diagram illustrating a frequency divider 80 according to an exemplary embodiment of the present disclosure, and FIG. 8B is a graph illustrating characteristics of the frequency divider 80 in FIG. 8A according to an exemplary embodiment of the present disclosure. . Specifically, FIG. 8A shows (2n+1) division- which outputs the output oscillation signal OUT by dividing the input oscillation signal IN by (2n+1) when n is 1 or a prime number. by-(2n+1)) shows an exemplary circuit diagram of a frequency divider 80, and FIG. 8B is a (2n+1) divider frequency divider (2n+1) at different power supply voltages (ie, 0.7V and 0.8V), respectively. 80) is a graph showing the power of the input oscillation signal IN according to the frequency of the input oscillation signal IN.

Referring to FIG. 8A , a (2n+1) division frequency divider 80 may include a plurality of gated inverters 81 to 86 and a plurality of latches 87 to 89 . The number of gated inverters and a plurality of latches included in the (2n+1) division frequency divider 80 may be determined according to a frequency division ratio. For example, the number of serially connected gated inverters or the number of latches may be equal to (2n+1), and may be referred to as the number of stages of the (2n+1) frequency divider 80 . The (2n+1) divide-by-frequency divider 80 may be referred to as an injection-locked oscillator and may include (2n+1) stages.

One stage of the (2n+1) frequency divider 80 may include two gated inverters (eg, 81 and 84) for a differential signal. The gated inverter 81 includes first and second PMOS transistors P1 sequentially connected in series between a positive supply voltage (or a power supply voltage) and a negative supply voltage (or a ground voltage), as shown in FIG. 8A . , P2) and first and second NMOS transistors N1 and N2. The output signal of the previous stage, that is, the output oscillation signal OUT output from the gated inverter 83 is the first PMOS transistor P1 having a source to which a positive supply voltage is applied from the gated inverter 81 and the negative A supply voltage of may be applied to the gates of the second NMOS transistor N2 having a source to which it is applied, in this specification, the first PMOS transistor P1 and the second NMOS transistor N2 are tail transistors In addition, the input oscillation signal IN is to be applied to the gates of the second PMOS transistor P2 and the first NMOS transistor N1 each having drains from which the output signal of the gated inverter 81 is output. In this specification, the second PMOS transistor P2 and the first NMOS transistor N1 may be referred to as cascade transistors.

When the input oscillation signal IN and the output oscillation signal OUT output from the previous stage are applied to the gated inverter 81 differently as shown in FIG. 8A , that is, the input oscillation signal IN is When the gates are applied and the output oscillation signal OUT is applied to the gates of the cascode transistors, as the semiconductor process is miniaturized, the bandwidth may be limited. In particular, when the transistors included in the (2n+1) frequency divider 80 are Finfet, the influence of the body bias on the channel may be reduced differently from the planar transistor. For example, when the input oscillation signal IN is applied to the gates of the tail transistors, an additional capacitance between the cascode transistors may increase the load capacitance of the gated inverter. Accordingly, the output pole frequency may be reduced, the size of the injection current generated by the input oscillation signal IN may be limited, and as a result, the bandwidth may be limited. On the other hand, as shown in FIG. 8A , in the gated inverter 81 , the input oscillation signal IN is applied to the gates of the cascode transistors and the output oscillation signal OUT is applied to the gates of the tail transistors. In this case, since injection current is generated in the cascode transistors, only the load capacitance due to the latch 87 may dominate, and consequently the load capacitance may decrease.

Referring to FIG. 8B , the (2n+1) division frequency divider 80 of FIG. 8A may have a different frequency tuning range according to a power supply voltage. That is, the natural frequency of the injection-locked oscillator may vary according to the magnitude of the power supply voltage. For example, in the graph of FIG. 8B , a frequency representing the lowest power of the input oscillation signal IN at a given power supply voltage may represent a natural frequency of the (2n+1) frequency division frequency divider 80 . Accordingly, as shown in FIG. 8B , the (2n+1) division frequency divider 80 may have a higher natural frequency when a power supply voltage of 0.8V is applied than when a power supply voltage of 0.7V is applied. and, as a result, can have a higher frequency adjustment range.

According to an exemplary embodiment of the present disclosure, the power supply voltage supplied to the frequency divider circuit (eg, 520a in FIG. 4 ) may be adjusted, and the power supply voltage supplied to the frequency divider included in the frequency divider circuit may also be adjusted. there is. Accordingly, not only power consumed in the frequency division circuit is reduced, but also due to the frequency divider having a varying frequency adjustment range as described above with reference to FIG. 8B, the frequency range supported by the frequency division circuit may also vary. can As a result, the frequency division circuit may expand the supportable frequency range, thereby improving the efficiency of the frequency division operation.

9A is a block diagram illustrating a multiplexer according to an exemplary embodiment of the present disclosure, and FIG. 9B is a graph illustrating output power according to fan-out of the multiplexer according to an exemplary embodiment of the present disclosure. Specifically, FIG. 9A shows a 2:1 multiplexer 90 as an example of a multiplexer included in the above-described selection circuit (eg, 525a in FIG. 4 ), and FIG. 9B shows a fan-out of a multiplexer including a gated inverter. It is a graph showing the output power.

Referring to FIG. 9A , the 2:1 multiplexer 90 may include gated inverters 91 and 92 . The first gated inverter 91 may receive the first input signal IN1 and may invert the first input signal IN1 or float the output according to the differential selection signals SEL and /SEL. there is. Similarly, the second gated inverter 92 may receive the second input signal IN2 , and invert the second input signal IN2 or output the second input signal IN2 according to the differential selection signals SEL and /SEL. can be floated. When the multiplexer includes pass gates for passing or blocking the first and second input signals IN1 and IN2 according to the differential selection signals SEL and /SEL, different from that shown in FIG. 9A . A 2:1 multiplexer 90 including gated inverters 91 , 92 may provide a relatively high bandwidth, while bandwidth may be limited due to the additional parasitic element of the pass gate. . In some embodiments, the inverter 93 of FIG. 9A may be omitted.

Referring to FIG. 9B , the output power of the multiplexer including gated inverters may vary according to fan-out when a signal oscillating at a relatively high frequency is input. That is, as shown in FIG. 9B , the output power of the multiplexer may decrease as the fan-out increases, and as a result, as the fan-out decreases, it may be advantageous for a signal oscillating at a high frequency. Accordingly, as will be described below with reference to FIGS. 10 and 11 , in some embodiments, a selection circuit (eg, 525a of FIG. 4 ) that selects one of oscillation signals output by a plurality of frequency dividers is hierarchical. It may include a plurality of 2:1 multiplexers arranged as Also, in some embodiments, the selection circuit may include a multiplexer (eg, 90 in FIG. 9A ) including a plurality of gated inverters.

10 is a block diagram illustrating an RX LO generator 500c according to an exemplary embodiment of the present disclosure. Similar to the RX LO generator 500a of FIG. 4 , the RX LO generator 500c of FIG. 10 may include an input buffer 510c , a frequency divider circuit 520c , and an output buffer 530c . Hereinafter, content overlapping with the description of FIG. 4 among the description of FIG. 10 will be omitted.

Referring to FIG. 10 , the frequency divider circuit 520c may include first to fourth frequency dividers 521c to 524c , a selection circuit 525c , and a duty adjustment circuit 526c . As shown in FIG. 10 , at least one of the division ratios of the first to fourth frequency dividers 521c to 524c of FIG. 10 includes the first to fourth frequency dividers 521a to 524a and may be different. That is, the third and fourth frequency dividers 523a and 524a of FIG. 4 have frequency division ratios of 4 and 6, respectively, while the third and fourth frequency dividers 523c and 524c of FIG. 10 are It may have frequency division ratios of division by 2 and division by 3, respectively. As will be described later, the third frequency divider 523c of FIG. 10 may form a frequency division ratio of 4 divisions together with the fifth frequency divider 525c_4 included in the selection circuit 525c, as shown in FIG. The fourth frequency divider 524c may form a frequency division ratio of 6 along with the fifth frequency divider 525c_4 included in the selection circuit 525c. The third and fourth frequency dividers 523c and 524c of FIG. 10 may share the fifth frequency divider 525c_4 , and accordingly, the area and power consumption of the frequency divider circuit 520c may be reduced.

The selection circuit 525c may include first to third 2:1 multiplexers 525c_1 , 525c_2 , 525c_3 , and a fifth frequency division disposed between the second and third 2:1 multiplexers 525c_2 and 525c_3 . A period 525c_4 may be included. 10 , the selection circuit 525c selects one of the four oscillation signals received from the first to fourth frequency dividers 521c to 524c, hierarchically arranged first to fourth frequency dividers 521c to 524c. A third 2:1 multiplexer 525c_1 , 525c_2 , and 525c_3 may be included. The first to third 2:1 multiplexers 525c_1 , 525c_2 , and 525c_3 may select one of four oscillation signals according to the RX control signal C_RX. In some embodiments, each of the first to third 2:1 multiplexers 525c_1 , 525c_2 , and 525c_3 may include gated inverters, as described above with reference to FIG. 9A .

11 is a block diagram illustrating an RX LO generator 500d according to an exemplary embodiment of the present disclosure. Similar to the RX LO generator 500c of FIG. 10 , the RX LO generator 500d of FIG. 11 may include an input buffer 510d, a frequency divider circuit 520d, and an output buffer 530d, and may include a frequency divider circuit. The 520d may include first to fourth frequency dividers 521d to 524d, a selection circuit 525d, and a duty adjustment circuit 526c. Hereinafter, content that overlaps with the description of FIG. 10 among the description of FIG. 11 will be omitted.

Referring to FIG. 11 , the frequency divider circuit 520d includes first to fifth switches 521d-1 to 521d-1 to independently cut off the power supplied to the first to fifth frequency dividers 521d to 524d and 525d_4. 525d-1). For example, the first switch 521d - 1 may block the first power voltage V_RX1 from being provided to the first frequency divider 521d. The first to fifth switches 521d-1 to 525d-5 may be controlled by the RX control signal C_RX, and the first to fifth frequency dividers 521d to 521d to 525d-5 may control power according to the RX control signal C_RX. 524d, 525d_4) can be supplied or cut off. In some embodiments, the first to fifth switches 521d - 1 to 525d - 1 may include PMOS transistors having a source to which the first power voltage V_RX1 is applied.

In some embodiments, the first to fourth switches 521d-1 to 525d-4 of the first group G1 include the first to fourth frequency dividers 521d to 524d of the first group G1. It may be controlled by the RX control signal C_RX to cut off power to three frequency dividers that output three oscillation signals that are not selected by the selection circuit 525d among the four output oscillation signals. . In addition, the fifth switch 525d-1 also cuts off the power supplied to the fifth frequency divider 525d_4 when the oscillation signal output by the second 2:1 multiplexer 525d_2 is not selected, the RX control signal ( C_RX). For example, when the frequency divider circuit 520d outputs the second internal oscillation signal SIG_2 by dividing the frequency of the first internal oscillation signal SIG_1 by two, the first switch 521d-1 sets the first frequency The divider 521d may be closed so that the first power supply voltage V_RX1 is provided, while the second to fifth switches 522d-1 to 525d-1 are connected to the second to fifth frequency dividers 521d to 524d, The first power voltage V_RX1 may be opened to 525d_4 to be cut off. Accordingly, the power consumed by the second to fifth frequency dividers 521d to 524d and 525d_4 can be eliminated, and as a result, the frequency divider circuit 520d and the RX LO generator including the same (eg, in FIG. 1 ) 150) may reduce power consumption.

Although in the example of FIG. 11 , the first to fifth frequency dividers 521d to 524d and 525d_4 supply the first power voltage V_RX1 to the first to fifth switches 521d-1 to 525d-1. Although illustrated as being blocked by The supply voltage V_RX1 may be cut off.

12 is a flowchart illustrating a method of controlling the transceiver 13 of FIG. 1 according to an exemplary embodiment of the present disclosure. For example, the method of FIG. 12 may be performed by the controller 14 of FIG. 1 , and may be referred to as an operation method of the controller 14 . Hereinafter, FIG. 12 will be described with reference to FIG. 1 .

12 , in step S11, an operation of obtaining a carrier frequency may be performed. For example, the controller 14 may acquire the frequency of at least one carrier used for downlink (DL) from the base station 20 . For example, the base station 20 may provide the user equipment 10 with information on at least one frequency channel used in downlink (DL) to transmit data to the user equipment 10 , The controller 14 of (10) may recognize the center frequency of the frequency channel as a carrier frequency.

In operation S12, an operation of controlling the frequency and frequency division ratio of the RX oscillation signal RX_O may be performed. For example, based on the obtained carrier frequency, the controller 14 divides the frequency of the RX oscillation signal RX_O and the RX LO generator 150 so that the RX local oscillation signal RX_LO has the same frequency as the carrier frequency. You can decide the rain. Then, the controller 14 activates/deactivates at least one VCO included in the RX oscillator 140 through the RX control signal C_RX or controls the frequency of the oscillation signal output from the VCO, thereby generating the RX LO generator ( 150) may control the frequency of the RX oscillation signal RX_O. Also, the controller 14 may control the frequency division ratio of the RX LO generator 150 through the RX control signal C_RX. Accordingly, the RX local oscillation signal RX_LO output by the RX LO generator 150 may have the same frequency as the carrier frequency.

In step S13 , an operation of scaling the RX power supply voltage V_RX may be performed. For example, the controller 14 may determine the level of the RX power supply voltage V_RX provided to the RX LO generator 150 based on the frequency of the RX oscillation signal RX_O determined in step S12 . The controller 14 may generate the DVS control signal C_DVS based on the determined magnitude of the RX power supply voltage V_RX, and the PMIC 15 may generate the RX power supply voltage V_RX based on the DVS control signal C_DVS. You can adjust the size. Accordingly, power unnecessarily consumed in the RX oscillation signal RX_O of a relatively low frequency may be removed, and as a result, power consumption of the RX LO generator 150 may be reduced.

13 is a flowchart illustrating a method of controlling the transceiver 13 of FIG. 1 according to an exemplary embodiment of the present disclosure. For example, the method of FIG. 13 may be performed by the controller 14 of FIG. 1 , and may be referred to as an operation method of the controller 14 . In some embodiments, FIG. 13 may be a method of controlling a transceiver including the RX LO generator 500d of FIG. 11 . Hereinafter, FIG. 13 will be described assuming that the controller 14 of FIG. 1 controls the RX LO generator 500d of FIG. 11 .

Referring to FIG. 13 , in step S21, an operation of obtaining a carrier frequency may be performed. For example, similar to step S11 of FIG. 12 , the controller 14 may obtain a frequency of at least one carrier used for downlink (DL) from the base station 20 . For example, the base station 20 may provide the user equipment 10 with information on at least one frequency channel used in downlink (DL) to transmit data to the user equipment 10 , The controller 14 of (10) may recognize the center frequency of the frequency channel as a carrier frequency.

In operation S22, an operation of controlling the frequency and frequency division ratio of the RX oscillation signal RX_O may be performed. For example, similar to step S12 of FIG. 12 , the controller 14, based on the obtained carrier frequency, configures the RX oscillation signal RX_O and A frequency division ratio of the RX LO generator 500d may be determined. Then, the controller 14 activates/deactivates at least one VCO included in the RX oscillator 140 through the RX control signal C_RX or controls the frequency of the oscillation signal output from the VCO, thereby generating the RX LO generator ( The frequency of the RX oscillation signal RX_O provided to 500d) may be controlled. Also, the controller 14 may control the frequency division ratio of the RX LO generator 500d through the RX control signal C_RX. Accordingly, the RX local oscillation signal RX_LO output from the RX LO generator 500d may have the same frequency as the carrier frequency.

In step S23 , an operation of selectively cutting off power supplied to the first to fifth frequency dividers 521d to 524d and 525d_4 of the RX LO generator 500d may be performed. For example, the controller 14 controls the RX local oscillation signal RX_LO of the first to fifth frequency dividers 521d to 524d and 525d_4 based on the frequency division ratio of the RX LO generator 500d determined in step S22. It can recognize things that are not used in creation. The controller 14 cuts off power supplied to those not used for generation of the RX local oscillation signal RX_LO among the first to fifth frequency dividers 521d to 524d and 525d_4, the RX control signal C_RX ) through at least one of the switches 521d-1 to 525d-1 may be opened. Accordingly, power consumed by an unused frequency divider may be removed, and as a result, power consumed by the RX LO generator 500d may be reduced.

In some embodiments, the method of controlling the transceiver 13 of FIG. 1 described above with reference to FIGS. 12 and 13 may be combined. That is, when the frequency division ratio of the RX oscillation signal RX_O and the RX LO generator 150 is determined, the RX power supply voltage V_RX supplied to the RX LO generator 150 may be scaled, and Power supplied to at least one not used among a plurality of frequency dividers included may be cut off.

Exemplary embodiments have been disclosed in the drawings and specification as described above. Although embodiments have been described using specific terms in the present specification, these are used only for the purpose of explaining the technical spirit of the present disclosure and not used to limit the meaning or scope of the present disclosure described in the claims. . Therefore, it will be understood by those skilled in the art that various modifications and equivalent other embodiments are possible therefrom. Accordingly, the true technical protection scope of the present disclosure should be defined by the technical spirit of the appended claims.

Claims (10)

A local oscillator (LO) generator for providing a local oscillating signal to a mixer, comprising:
an input buffer configured to generate a first internal oscillation signal based on the input oscillation signal;
a frequency division circuit for outputting a second internal oscillation signal by dividing the frequency of the first internal oscillation signal; and
an output buffer configured to generate the local oscillation signal based on the second internal oscillation signal;
at least one of the input buffer and the frequency division circuit is configured to receive a power supply voltage adjusted according to the frequency of the local oscillation signal independently of the output buffer;
the output buffer is configured to receive a fixed supply voltage;
The frequency division circuit is
a plurality of first frequency dividers independently dividing the frequency of the first internal oscillation signal and generating a plurality of output signals, respectively; and
a selection circuit for outputting one of the plurality of output signals as the second internal oscillation signal;
wherein the selection circuit comprises at least one 2:1 multiplexer arranged hierarchically. The method according to claim 1,
and the input buffer and the frequency division circuit are configured to receive power supply voltages independently of each other. The method according to claim 1,
and the output buffer comprises an AC-coupled buffer for AC coupling the second internal oscillation signal. 4. The method according to claim 3,
The AC-coupled buffer,
inverter;
a feedback resistor having both ends respectively connected to an input terminal and an output terminal of the inverter; and
and a capacitor having a first end for receiving the second internal oscillation signal and a second end connected to an input end of the inverter. The method according to claim 1,
and said input buffer and said frequency division circuit are each configured to receive a variable supply voltage. The method according to claim 1,
the at least one 2:1 multiplexer comprises a plurality of 2:1 multiplexers;
and the selection circuit further comprises at least one second frequency divider coupled between at least two of the plurality of 2:1 multiplexers. The method according to claim 1,
and said at least one 2:1 multiplexer comprises two gated inverters. The method according to claim 1,
The frequency divider circuit comprises at least one first switch capable of cutting off power supplied to at least one of the plurality of first frequency dividers. The method according to claim 1,
At least one first frequency divider of the plurality of first frequency dividers includes an injection-locked oscillator including a plurality of gated inverters,
Each of the plurality of gated inverters,
a first PMOS transistor and a second PMOS transistor, a first NMOS transistor and a second NMOS transistor, sequentially connected in series between a positive supply voltage and a negative supply voltage;
an input signal of a next stage is generated in drains of the second PMOS transistor and the first NMOS transistor;
an output signal of a previous stage is applied to gates of the first PMOS transistor and the second NMOS transistor;
and the first internal oscillation signal is applied to gates of the second PMOS transistor and the first NMOS transistor. A device for wireless communication, comprising:
generating a first internal oscillation signal based on an input oscillation signal, generating a second internal oscillation signal by dividing a frequency of the first internal oscillation signal, and generating a local oscillation signal based on the second internal oscillation signal; , an LO generator to receive the first supply voltage;
a mixer for receiving the local oscillation signal; and
Control the frequency of the input oscillation signal and the frequency division ratio of the LO generator based on the carrier frequency of the wireless communication, and the first power supply voltage based on the frequency of the input oscillation signal and the frequency division ratio of the LO generator a controller for controlling the regulating;
the LO generator includes a frequency division circuit configured to generate the second internal oscillation signal by dividing the first internal oscillation signal;
The frequency division circuit is
a plurality of first frequency dividers independently dividing the frequency of the first internal oscillation signal and generating a plurality of output signals, respectively; and
a selection circuit for outputting one of the plurality of output signals as the second internal oscillation signal;
The selection circuit comprises at least one 2:1 multiplexer arranged hierarchically.

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