KR102392938B1 - System and method for estimating and compensating direct current offset in an ultra-low power receiver - Google Patents

Abstract

A method for estimating a DC offset of an ultra-low power receiver is disclosed. A DC offset estimation method according to an embodiment includes receiving a signal from an output of an AD converter of a receiver, and estimating a DC offset compensation parameter in a plurality of sections for a plurality of stages by using the received signal do. The received signal includes a correlated variable DC component for at least one of an in-phase side and a quadrature side of the receiver. The estimating of the DC offset compensation parameter may include calculating a DC offset compensation parameter in a magnitude estimation section for the plurality of stages, and calculating a DC offset compensation parameter in a sign estimation section for the plurality of stages. include

Description

SYSTEM AND METHOD FOR ESTIMATING AND COMPENSATING DIRECT CURRENT OFFSET IN AN ULTRA-LOW POWER RECEIVER

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to estimation of a direct current offset, and more particularly, to a method and system for estimating and compensating for a direct current offset of an ultra-low power receiver.

Most wireless receivers include an analog front end. DC offset is an important factor in radio receivers with analog front end. DC offset is mainly due to local oscillator leakage and component mismatch. For example, DC offset occurs due to local oscillator leakage self mixing, transmit leakage self mixing, and strong interference magnetic mixing.

DC offset occurs in front of the analog receiver where the local oscillator signal is mixed with the input radio frequency (RF) signal. The DC offset needs to be removed before demodulation of the baseband signal for reliable communication. In the case of an ultra-low power sliding intermediate frequency (IF) non-coherent receiver, the packet error rate (PER) performance degradation by 6 dB to 7 dB due to DC offset ( degradation) is observed.

In particular, when the gain in the baseband stage is high, the removal of the DC offset is very important because a small DC offset can be amplified due to the high gain. If the DC offset is not removed, the performance of the receiver may be severely degraded. Accordingly, there is a need for a method for compensating for a DC offset of an ultra-low power receiver.

There are several methods for compensating for DC offset. AC coupling or high pass filtering is one of effective methods for removing time-invariant DC offset. Alternatively, the time-invariant DC offset of the in-phase arm and the quadrature arm may be corrected, stored in a memory, and then input to the subtraction circuit. However, since conventional methods for compensating for a DC offset involve separate processing of an in-phase component and a quadrature component of the receiver, additional hardware may be required and it may take more time.

According to one side, a method for estimating a correlated DC offset of an ultra-low power receiver is provided. A method of estimating a correlated DC offset of an ultra-low power receiver comprises: a signal at the output of an analog to digital converter (AD converter) of the receiver, the signal being variable correlated to at least one of an in-phase side and a quadrature side of the receiver including a DC component; and estimating a DC offset compensation parameter in a plurality of sections for a plurality of stages using the received signal, wherein the step of estimating the DC offset compensation parameter includes: , calculating a DC offset compensation parameter in a magnitude estimation interval for the plurality of stages; and calculating a DC offset compensation parameter in a sign estimation section for the plurality of stages.

In one embodiment, the received signal may be the output of an envelope detector of a non-coherent receiver. In another embodiment, the received signal may be an envelope of an in-phase component and a quadrature component of a coherent receiver.

In an embodiment, the correlated variable DC component may include a value approximate to the DC offset values of the in-phase side and the quadrature side.

In one embodiment, the plurality of stages may include a noise only stage and a signal and noise stage.

In an embodiment, the calculating of the DC offset compensation parameter in the magnitude estimation interval for the plurality of stages includes, for the signal and noise stages, zero of the received signal during a predefined time window. The method may include calculating a DC offset compensation parameter in the magnitude estimation section by using the value.

In an embodiment, the calculating of the DC offset compensation parameter in the sign estimation interval for the plurality of stages includes: the DC offset in the magnitude estimation interval with respect to at least one of the noise confinement stage and the signal and noise stage allocating one of a positive sign or a negative sign to a compensation parameter, obtaining a DC offset compensation parameter in the code estimation section based on compensation for the DC offset according to the assigned sign, the DC analyzing the effect of the compensation for the offset on the sign estimation interval; and re-assigning the sign of the DC offset parameter based on the analysis.

In an embodiment, the method of estimating the DC offset may further include compensating for the DC offset based on the reassigned sign.

In an embodiment, the analyzing may include comparing a value of the DC offset compensation parameter in the magnitude estimation section with a value of the DC offset compensation parameter in the sign estimation section.

In an embodiment, the step of reassigning the sign includes maintaining the assigned sign when a DC offset compensation parameter in the magnitude estimation section is greater than a DC offset compensation parameter in the code estimation section can do. In addition, the step of reassigning the code may include inverting the assigned code when the DC offset compensation parameter in the magnitude estimation section is smaller than the DC offset compensation parameter in the code estimation section. .

According to another aspect, a method for estimating a DC offset of an ultra-low power receiver is provided. A method for estimating a DC offset of an ultra-low power receiver, comprising: receiving a signal at an output of an AD converter of the receiver, the signal including a variable DC component with respect to at least one of an in-phase side and a quadrature side of the receiver , and estimating a DC offset compensation parameter in a plurality of sections with respect to a plurality of stages by using the received signal, wherein the estimating of the DC offset compensation parameter includes, for the plurality of stages, a first calculating a magnitude of a DC offset using the received signal in a section, calculating a magnitude of a DC offset using the received signal in a second section, and calculating the magnitude of the DC offset calculated in the first section and the second section calculating a DC offset compensation parameter in the in-phase side based on the magnitude of the DC offset calculated in the second section, and calculating the DC offset magnitude using the received signal in the third section, and in the first section The method may include calculating a DC offset compensation parameter at the orthogonal side based on the calculated magnitude of the DC offset and the magnitude of the DC offset calculated in the third section.

In an embodiment, the DC offset compensation parameter in the in-phase side includes a magnitude and a sign of a DC offset in the in-phase side, and the DC offset compensation parameter in the orthogonal side is a value of the DC offset in the quadrature side. May include size and sign.

In one embodiment, the plurality of stages may include a noise confinement stage and a signal and noise stage.

In an embodiment, the method of estimating the DC offset may further include compensating for the DC offset based on the estimated DC offset compensation parameter.

According to another aspect, a system for estimating a correlated DC offset of an ultra-low power receiver is provided. A system for estimating a correlated DC offset of an ultra-low power receiver, comprising: a processor; and a memory coupled to the processor and storing a plurality of modules executed by the processor, the plurality of modules comprising: a signal at an output of an AD converter of the receiver, the signal being in-phase and quadrature of the receiver a receiving module for receiving - including a correlated variable DC component with respect to at least one of the phase sides; and an estimation module for estimating a DC offset compensation parameter in a plurality of sections for a plurality of stages by using the received signal and the estimation module may calculate a DC offset compensation parameter in a magnitude estimation section for the plurality of stages, and calculate a DC offset compensation parameter in a sign estimation section for the plurality of stages.

In one embodiment, when the estimation module estimates the DC offset compensation parameter in the plurality of sections with respect to the plurality of stages, for at least one of the noise confinement stage and the signal and noise stage, in the magnitude estimation section assigning either a positive sign or a negative sign to the DC offset compensation parameter of An effect of the compensation for the DC offset on the code estimation section may be analyzed, and the sign of the DC offset parameter may be reallocated based on the analysis.

In an embodiment, when the estimation module analyzes the effect of the compensation on the sign estimation section, the value of the DC offset compensation parameter in the magnitude estimation section and the value of the DC offset compensation parameter in the sign estimation section can be compared

In an embodiment, the estimation module may maintain the assigned code when reallocating the code, if the DC offset compensation parameter in the magnitude estimation section is greater than the DC offset compensation parameter in the code estimation section there is. Also, when reassigning the code, if the DC offset compensation parameter in the magnitude estimation section is smaller than the DC offset compensation parameter in the code estimation section, the estimation module may invert the assigned code.

1 shows a network implementation of a system for estimating a DC offset of an ultra-low power receiver and compensating for a DC offset according to an embodiment.
2 shows details of a system for estimating a correlated DC offset of an ultra-low power receiver according to an embodiment.
3 shows an architecture for implementing a system for estimating a DC offset of an ultra-low power receiver and compensating for a DC offset according to an embodiment.
4 shows a timing diagram for a process for estimating and compensating for a DC offset according to one embodiment.
5 shows a state diagram for a DC offset estimation and compensation process in accordance with one embodiment.
6 shows details of a receiver architecture for estimating a DC offset according to an embodiment.
7 shows details of a system for estimating a DC offset of an ultra-low power receiver according to an embodiment.
8 illustrates a process for estimating a DC offset in a plurality of sections according to an embodiment.
9 is a flowchart of a method for estimating a correlated DC offset of an ultra-low power receiver according to an embodiment.
10 is a flowchart illustrating a method of estimating a DC offset of an ultra-low power receiver according to an embodiment.
11 graphically illustrates a DC offset estimation and compensation process in accordance with one embodiment.
12 illustrates a packet error rate in the absence of DC offset compensation.
13 illustrates a packet error rate when DC offset estimation and compensation are applied according to an embodiment.
14 and 15 illustrate an effect of a correlation coefficient on a packet error rate when estimating a DC offset according to an embodiment.
16 illustrates a packet error rate when DC offset estimation and compensation are applied according to an embodiment.
17 illustrates a packet error rate when DC offset compensation is applied according to a conventional method.
18 illustrates a computing environment implementing a method and system for estimating and compensating for a DC offset of an ultra-low power receiver in accordance with one embodiment.

Hereinafter, embodiments will be described in detail with reference to the accompanying drawings. However, the scope of rights is not limited or limited by these embodiments. Like reference numerals in each figure indicate like elements.

The terms used in the description below have been selected as general and universal in the related technical field, but there may be other terms depending on the development and/or change of technology, customs, preferences of technicians, and the like. Therefore, the terms used in the description below should not be construed as limiting the technical idea, but as illustrative terms for describing the embodiments.

Also, in specific cases, there are terms arbitrarily selected by the applicant, and in this case, the meaning will be described in detail in the corresponding description. Therefore, the terms used in the description below should be understood based on the meaning of the term and the content throughout the specification, rather than the simple name of the term.

In one embodiment, a method and system for estimating a DC offset in an ultra-low power receiver may be implemented. The ultra-low power receiver may include a coherent receiver or a non-coherent receiver. In one embodiment, a method and system for compensating for a DC offset based on an ultra-low power estimated DC offset may also be implemented. A signal may be received from an output of an analog to digital converter (ADC) of the ultra-low power receiver. The received signal may include variable DC components of a plurality of arms of the receiver. A DC offset parameter may be estimated in a plurality of sections for a plurality of stages using the received signal.

Referring to FIG. 1 , the relationship between the network 100 , the transmitter 110 , and the receivers 120 and 130 is illustrated. The receivers 120 and 130 may communicate with the transmitter 110 through the network 100 . The network 100 may be a wired network or a wireless network. The receivers 120 and 130 may include a system for estimating a DC offset compensation parameter of the receivers 120 and 130 .

2, details of a system 200 for estimating a correlated DC offset of an ultra-low power receiver in accordance with one embodiment are shown. In one embodiment, the system 200 may include at least one processor 210 , an input/output interface 220 , and a memory 230 .

The at least one processor 210 may process signals based on a microprocessor, microcomputer, microcontroller, digital signal processor, central processing unit, state machine, logic circuitry, and/or instructions. It may be implemented by any device capable of. The at least one processor 210 is configured to fetch and execute computer readable instructions stored in the memory 230 .

Input/output interface 220 may facilitate communication with various types of networks and protocols. For example, various networks may include a wired network such as a local area network (LAN), a cable, and a wireless network such as a wireless local area network (WLAN), a wireless telephone, or a satellite. The input/output interface 220 may include one or more ports for connection with a server or other device.

One or more modules 240 may be stored in the memory 230 . Module 240 may be configured to perform a particular task or function or implement an abstract data type. For example, modules 240 may include routines, programs, objects, components, data structures, and the like. In one embodiment, the module 240 may include a receiving module 241 and an estimation module 242 . Module 240 may include programs or instructions that supplement the applications and functions of system 200 .

Data 250 may be stored in the memory 230 . Data 250 may include data received, processed data, and generated data by one or more modules 240 . In one embodiment, data 250 may include database 251 and auxiliary data 252 . The auxiliary data 252 may include data generated as a result of the execution of one or more modules 240 .

Referring to FIG. 3 , a receiver architecture 300 for estimating a DC offset of an ultra-low power receiver according to an embodiment is illustrated. The receiver architecture 300 may include an ultra-low power receiver (eg, a non-coherent energy detection receiver). The DC offset of the ultra-low power receiver may be estimated using a signal received from the output of the ADC 310 . An output of an envelope detector may be utilized to estimate the DC offset compensation parameter. A system for estimating and compensating for a DC offset can also be implemented in a coherent receiver. In one embodiment, the in-phase and quadrature-side outputs of the coherent receiver may pass through an envelope detector before being provided to the DC offset estimation block.

The receiver architecture 300 may include a low noise amplifier (LNA) 320 , a local oscillator 330 , and a phase shifter 340 . The receiver architecture 300 may also include a low pass filter (LPF) 351 , 352 and a programmable gain amplifier (PGA) 361 , 362 . Receiver architecture 300 may also include Digital to Analog Converter (DAC) 371 , 372 and quantum electrodynamics (QED) 380 . The receiver architecture 300 may also include an in-phase DC offset estimator 391 and a quadrature DC offset estimator 392 .

2 and 3 together, the receiving module 241 of the system 200 of FIG. 2 is configured to receive a signal from the ADC 310 . The received signal includes variable DC components of a plurality of sides of the ultra-low power receiver. The plurality of sides includes an in-phase side and an orthogonal side. The in-phase and quadrature sides are affected by DC offset. The DC offset is generated after the PGA (361, 362) stage and before the QED (380) stage, and the DC offset is dependent on the gain of the PGA (361, 362).

Estimation module 242 of system 200 of FIG. 2 may estimate a correlated DC offset of an ultra-low power receiver (eg, an ultra-low power receiver of receiver architecture 300 ). The correlated DC offset refers to a DC offset of a value approximately equal to the DC offset values for the in-phase side and the quadrature side. The DC offset may have an arbitrary positive or negative value among Gaussian normal distributions according to the gain setting of the PGA.

Referring to FIG. 4, a timing diagram for estimation and compensation of a DC offset is shown. The timing diagram of FIG. 4 shows a time sequence in which the DC offset estimation and compensation system interacts with other modules of the receiver architecture 300 during a plurality of stages. For example, 0 to 12 μs is a DC offset estimation section, and 12 to 20 μs is a DC offset compensation section. Also shown in the timing diagram is a noise only stage and a signal and noise stage.

5, a process for estimating and compensating for a DC offset is shown in accordance with one embodiment. The plurality of stages includes a noise confinement stage before packets are detected and a signal and noise stage after packets are detected. The plurality of sections include an offset magnitude estimation phase and an offset sign estimation phase. The process of estimating the DC offset may be performed, for example, by the estimation module 242 of the system 200 of FIG. 2 .

In the noise confinement stage, automatic gain control (AGC) freezes the gain of the PGA, and a DC offset according to the PGA gain affects the noise confinement samples received by the receiving module 241 . The DC offset estimation and compensation cycle as shown in FIG. 5 is started by the DC offset estimation Enable (DCOE Enable) signal from the Rx FSM. DC offset estimation (DCOE_N) and DC offset compensation (DCOC_N) are performed during the noise confinement stage.

In the signal and noise stage, when a packet is detected and the automatic gain control operation is complete, the AGC's gain freezing indicates that another round of DC offset estimation and compensation should be performed. do. Since a change in the gain of the PGA may cause a change in the DC offset, it is necessary to perform estimation and compensation of the DC offset again after the change in the gain of the PGA is completed. Accordingly, DC offset estimation (DCOE_S) and DC offset compensation (DCOC_S) are performed again during the signal and noise stage. Whenever a gain change of the PGA is reported from the Rx FSM, estimation and compensation of the DC offset may be performed again.

Referring to FIG. 6 , additional components of a receiver architecture 300 for estimating a DC offset are shown. The receiver architecture 300 includes a receiver finite state machine (Rx FSM) 610 for enabling DC offset estimation, an analog front end 620 , a DC offset estimator 630 , and a DC offset register 640 . ) may be further included. In one embodiment, the DC offset estimator 630 may be the estimation module 242 of the system 200 of FIG. 2 .

Continuing to refer to FIG. 6 , when DC offset estimation is requested, the Rx FSM 610 transmits a DCOE Enable signal to the DC offset estimator 630 . The DCOE Enable signal may be used to activate or deactivate the DC offset estimation of the DC offset estimator 630 . The DC offset estimator 630 may receive the digitized QED signal from the ADC 310 to estimate the DC offset.

The DC offset estimator 630 may estimate the final DC offset value by recursively applying the DC offset intermediate value to the DC offset compensation in a continuous section. The DC offset intermediate value in the continuous section may be stored in the DC offset register 640 and transmitted to the Rx FSM 610 using the DC offset estimation Available (DCOE Available) signal. The final DC offset value may also be stored in the DC offset register 640 and transmitted to the Rx FSM 610 using the DCOE Available signal. In addition, the Rx FSM 610 may transmit a command signal to the analog front end 620 to perform DC offset compensation and a baseband process.

A signal y(n) received from the output of the ADC 310 may be expressed as in Equation 1 when additive white Gaussian noise (AWGN) exists.

는 시간 n에서의 데이터 부분,

는 시간 n에서의 잡음 부분,

는 각각 동상 변 및 직교상 변에서 발생되는 직류 오프셋을 의미한다.here,

is the data part at time n,

is the noise part at time n,

denotes a DC offset generated at the in-phase side and the quadrature side, respectively.

In addition, if the variable DC offset component input from the DC offset register 640 as shown in FIG. 6 is included in Equation 1, it can be expressed as Equation 2 .

는 각 패킷의 시작 시의 PGA의 초기 이득 설정에 기초하여 패킷 내에서 변화하는 PGA의 이득에 대한 함수이다.here,

is a function of the gain of the PGA that varies within a packet based on the initial gain setting of the PGA at the beginning of each packet.

이다. 따라서, 이 경우 y(n)은 수학식 3과 같이 표현될 수 있다.In the absence of a data signal, i.e. in the case of a noise confinement stage,

am. Therefore, in this case, y(n) may be expressed as in Equation 3.

는 AWGN 만이 존재하는 상태에서 추정된다.Therefore, in the noise confinement stage

is estimated in a state where only AWGN exists.

이다. 따라서, 예를 들어 수신 모듈(241)에 의해 수신되는 데이터 부분이 함께 고려되어야 한다.

인 곳은 오프-칩 신호가 전송되는 경우, 즉 진폭이 0 인 신호가 전송되는 경우로서, 이러한 신호는 신호 및 잡음 스테이지 내에서 데이터 신호의 크기가 없는 경우라는 점에서 직류 오프셋 추정에 이용될 수 있다. 신호 및 잡음 스테이지에서 직류 오프셋 파라미터를 추정하기 위해서, 넌코히런트 수신기를 위한 프리앰블(preamble)은 신호 및 잡음 스테이지의 통상적인 수신 프로세스 지속시간 내에서 충분한 수의 0 값을 이용하도록 설계되는 것이 바람직하다.For signal and noise stages,

am. Thus, for example, the data portion received by the receiving module 241 should be considered together.

Where is the case where an off-chip signal is transmitted, that is, a signal with zero amplitude is transmitted, and this signal can be used for DC offset estimation in that there is no magnitude of the data signal in the signal and noise stage. there is. In order to estimate the DC offset parameter in the signal and noise stage, the preamble for the non-coherent receiver is preferably designed to use a sufficient number of zero values within the typical receive process duration of the signal and noise stage. .

Hereinafter, calculations performed to estimate the DC offset when there is a strong correlation between the in-phase DC offset and the quadrature DC offset will be described.

로 가정되고, 동상/직교상(I/Q) 상관 계수

는 1 로 가정된다. 이 경우 y(n)은 수학식 4와 같이 표현될 수 있다.If there is a strong correlation between the in-phase DC offset and the quadrature DC offset, the DC offset is

is assumed, and the in-phase/quadrature (I/Q) correlation coefficient

is assumed to be 1. In this case, y(n) may be expressed as in Equation (4).

이다. 따라서, 이 경우 y(n)은 수학식 5와 같이 표현될 수 있다.For the noise-limited stage,

am. Accordingly, in this case, y(n) may be expressed as in Equation 5.

In an embodiment, the estimation module 242 may estimate a DC offset in a plurality of sections with respect to a plurality of stages. The plurality of stages may include a noise confinement stage and a signal and noise stage. The plurality of sections may include an offset magnitude estimation section and an offset code estimation section.

First, the estimation module 242 is configured to estimate a DC offset in a plurality of intervals for the noise confinement stage.

동안의 직류 오프셋의 크기

는 수학식 6과 같이 표현될 수 있다.In the offset magnitude estimation section, the magnitude of the DC offset is estimated. The estimation module 242 averages the signal received by the reception module 241 over a predefined time window. An exemplary time window is shown in FIG. 4 . For example, the length of the time window may be defined as N, and the time window

The magnitude of the DC offset during

can be expressed as in Equation (6).

According to Equation 6, the estimation module 242 estimates only the offset magnitude among the DC offset parameters. The estimation module 242 may transmit the estimated offset size to the DC offset register 640 to estimate the offset sign.

In the offset sign estimation interval, the estimation module 242 assigns either a positive sign or a negative sign to the offset magnitude estimated in the offset magnitude estimation interval for at least one of the noise confinement stage and the signal and noise stage. After either a positive sign or a negative sign is assigned, the estimation module 242 estimates a DC offset based on the assigned sign. The estimation module 242 analyzes the effect of the assigned code on the DC offset magnitude in the offset code estimation section. The estimation module 242 retains or re-assigns the assigned sign based on the analysis result.

가 아날로그 베이스밴드에 감산(subtraction)으로 적용된다. 오프셋 부호 추정 구간에서 추정 모듈(242)은 후속하는(subsequent) 타임 윈도우에서 오프셋 크기 추정을 다시 수행한다. 예를 들어, 후속하는 타임 윈도우

에서 수신 모듈(241)에 의해 수신된 신호의 평균을 낸다. 타임 윈도우

동안의 직류 오프셋의 크기

은 수학식 7과 같이 표현될 수 있다.The process for estimating the sign of the DC offset is described in more detail below. The size of the DC offset estimated in the offset size estimation section

is applied as a subtraction to the analog baseband. In the offset sign estimation interval, the estimation module 242 performs offset magnitude estimation again in a subsequent time window. For example, the following time window

The signal received by the receiving module 241 is averaged. time window

The magnitude of the DC offset during

can be expressed as in Equation 7.

및

를 비교함으로써 할당된 부호의 영향을 분석한다. 추정 모듈(242)에 의해 오프셋 크기의 증가가 식별된(identified) 경우, 즉 비교의 결과가

<

인 경우, 이는 할당된 부호가 실제로 적용되어야 하는 부호와 반대의 부호라는 사실을 나타낸다. 따라서, 직류 오프셋에 할당된 부호는 반전될 필요가 있다.The estimation module 242 is

and

Analyze the influence of the assigned sign by comparing . If an increase in the offset magnitude is identified by the estimation module 242, i.e. the result of the comparison is

<

, this indicates the fact that the assigned code is the opposite of the code to be actually applied. Accordingly, the sign assigned to the DC offset needs to be inverted.

>

인 경우, 이는 할당된 부호가 실제로 적용되어야 하는 부호와 동일한 부호라는 사실을 나타낸다. 따라서, 직류 오프셋에 할당된 부호는 유지된다.Also, if a significant decrease in the offset magnitude is identified by the estimation module 242, i.e. the result of the comparison is

>

, this indicates the fact that the assigned code is the same code as the code to be actually applied. Accordingly, the sign assigned to the DC offset is maintained.

The estimation module 242 is also configured to estimate a DC offset at the plurality of intervals during the signal and noise stage.

The estimation module 242 measures the DC offset after the AGC gain is fixed after the packet is detected. For example, the DC offset measurement is initiated by the DCOE Enable signal from the Rx FSM 610 . A signal received by the receiving module 241 may be expressed as Equation (8).

일 때) 상기 수신된 신호는 잡음에 의한 직류 오프셋 만을 포함한다. 즉, 이 경우 수신된 신호 내에 데이터 신호는 존재하지 않는다. 예를 들어,

일 때 수신된 신호

을

이라 하면, 추정 모듈(242)은

을 이용하여 잡음 한정 스테이지에서와 유사한 방식으로 직류 오프셋을 추정할 수 있다. 직류 오프셋을 추정하기 위한 프로세스가 이하에서 단계 별로 상세하게 설명된다.For amplitude-shift keying (ASK) and On-Off keying (OOK) modulation, when the amplitude of the signal is zero (i.e.,

), the received signal includes only a DC offset caused by noise. That is, in this case, there is no data signal in the received signal. for example,

signal received when

second

If , the estimation module 242 is

can be used to estimate the DC offset in a similar way as in the noise confinement stage. The process for estimating the DC offset is described in detail step by step below.

동안에 수신된

의 N 개의 샘플로부터

의 N⁺ 개의 샘플을 추정할 수 있다. 여기서,

는 AGC의 이득이 고정된 후 Rx FSM(610)으로부터 DCOE Enable 신호가 수신되는 때를 나타낸다.Step 1. Estimation module 242 sets the time window

received during

from N samples of

of N ⁺ samples can be estimated. here,

indicates when the DCOE Enable signal is received from the Rx FSM 610 after the gain of the AGC is fixed.

을 이용하여 직류 오프셋의 크기를 추정한다. 직류 오프셋의 크기

는 수학식 9와 같이 표현될 수 있다.Step 2. Estimation module 242

is used to estimate the magnitude of the DC offset. DC offset size

can be expressed as in Equation (9).

를 감산으로 적용한다. 직류 오프셋의 크기

가 타임 윈도우

에 적용될 수 있다.Step 3. The estimation module 242 determines the magnitude of the DC offset on the in-phase side and the quadrature side of the analog front end.

is applied as a subtraction. DC offset size

autumn time window

can be applied to

에서 직류 오프셋의 크기

를 추정한다.Step 4. Estimation module 242 sets the time window

the magnitude of the DC offset in

to estimate

인 경우), 타임 윈도우

에 적용된 직류 오프셋에 할당된 부호가 잘못되었다는 표시로 식별되고, 따라서

이후에는 반전된 부호가 재할당되어 직류 오프셋이 적용된다. 그 밖의 경우, 할당된 부호가 올바르다는 표시로 식별되고, 따라서 직류 오프셋 부호가 그대로 유지된다. 이러한 방식으로,

및

간의 비교에 기초하여 직류 오프셋 부호가 유지 또는 재할당될 수 있다.Step 5. If the DC offset magnitude is increased (i.e.,

), time window

identified as an indication that the sign assigned to the DC offset applied to

After that, the inverted sign is reassigned and a DC offset is applied. In other cases, it is identified as an indication that the assigned code is correct, and thus the DC offset code is maintained as it is. In this way,

and

A DC offset code may be maintained or reassigned based on the comparison between the two.

In one embodiment, system 200 may be configured to compensate for DC offset in receiver architecture 300 . After the DC offset is estimated, the DC offset compensation process may be initiated by the system 200 and the DC offset estimate may be passed to the DC offset register 640 using a serial peripheral interface (SPI) protocol. The DC offset estimate is then applied subtractively to the analog baseband to compensate for the DC offset of the receiver architecture 300 .

Referring to FIG. 7 , details of a system 700 for estimating a DC offset of an ultra-low power receiver according to another embodiment are shown. System 700 may be configured to compensate for a direct current offset of receiver architecture 300 shown in FIG. 3 . Like the system 200 of FIG. 2 , the system 700 may include a processor 710 , an interface 720 , and a memory 730 . One or more modules 740 may be stored in the memory 730 . In one embodiment, module 740 may include a receiving module 741 and an estimation module 742 .

Data 750 may be stored in the memory 730 . Data 750 may include data received, processed data, and generated data by one or more modules 740 . In one embodiment, data 750 may include database 751 and auxiliary data 752 . The auxiliary data 752 may include data generated as a result of the execution of one or more modules 740 .

The estimation module 742 may estimate a DC offset in a plurality of sections with respect to a plurality of stages. The plurality of stages may include a noise confinement stage and a signal and noise stage. The plurality of sections may include a first section, a second section, and a third section, which will be described in more detail below.

First, the estimation module 742 is configured to estimate the DC offset in a plurality of intervals during the noise confinement stage. A signal y(n) received by the reception module 741 may be expressed as Equation (10).

In the first interval, the estimation module 742 calculates the magnitude of the DC offset from the signal received by the reception module 741 .

In the second section, the estimation module 742 calculates the magnitude of the DC offset from the received signal, and estimates the magnitude and sign of the DC offset of the in-phase side based on the DC offset magnitude calculated in the first section and the second section do.

In the third section, the estimation module 742 calculates the magnitude of the DC offset from the received signal, and calculates the magnitude and sign of the DC offset of the orthogonal side based on the DC offset magnitude calculated in the first section and the third section. estimate

에 직류 오프셋 추정기(630)를 작동시킨다(enable). 직류 오프셋 추정기(630)는 수신된 신호로부터 N개의 샘플을 수집한다. 수집되는 샘플의 개수 N은 추정의 정확도를 확보하기 위한 최소의 개수로 선택될 수 있다.The operation of the system 700 will be described with reference to FIG. 6 . Rx receiver 610 is time

To enable the DC offset estimator 630 (enable). The DC offset estimator 630 collects N samples from the received signal. The number N of samples to be collected may be selected as the minimum number to ensure accuracy of estimation.

동안 직류 오프셋의 크기를 추정한다. 추정되는 직류 오프셋의 크기는 수학식 11과 같이 표현될 수 있다.In the first interval, the estimating module 742 sets the time window

While estimating the magnitude of the DC offset. The size of the estimated DC offset may be expressed as in Equation (11).

Also, Equation 11 can be approximated as Equation 12.

로 주어진다. 따라서, 후속하는 타임 윈도우

동안 수신 모듈(741)에 의해 수신되는 신호는 수학식 13과 같이 표현될 수 있다.In the second section, the estimation module 742 estimates the in-phase component of the DC offset. In the second section, the DC offset compensation for the orthogonal component is input as a value of 0, and all the magnitudes of the DC offset estimated in the first section are subtracted from the in-phase side. The complex representation of the variable DC offset applied to the analog front end is

is given as Thus, the subsequent time window

A signal received by the receiving module 741 during the operation may be expressed as in Equation 13.

Also, Equation 13 can be expressed as Equation 14.

By averaging the influence of the noise part, it can be expressed as Equation (15).

Accordingly, the in-phase component of the DC offset estimated by the estimation module 742 may be expressed as Equation (16).

동안 가변 직류 오프셋

을 아날로그 전단에 적용하여 직류 오프셋의 직교상 성분을 추정한다. 제3 구간에서 수신된 신호

은 수학식 17과 같이 표현될 수 있다.In the third interval, the estimation module 742 sets the time window

Variable DC offset while

is applied to the analog front end to estimate the orthogonal component of the DC offset. signal received in section 3

can be expressed as in Equation 17.

Also, Equation 17 can be expressed as Equation 18.

By averaging the influence of the noise part, it can be expressed as Equation (19).

Accordingly, the orthogonal component of the DC offset estimated by the estimation module 742 may be expressed as Equation (20).

을 얻을 수 있다.As a result, the estimation module 742 calculates the DC offset from the in-phase component and the quadrature component (Equations 16 and 20) of the DC offset.

can get

Alternatively, in the second section, a variable DC offset as in Equation 21 may be applied to the front end of the analog.

In this case, the in-phase component and the quadrature component of the DC offset estimated in the second section and the third section can be expressed as Equations 22 and 23, respectively.

The estimation module 742 is also configured to estimate a DC offset at the plurality of intervals during the signal and noise stage. The estimation module 742 measures the DC offset after the AGC gain is fixed after the packet is detected. For example, the DC offset measurement is initiated by the DCOE Enable signal from the Rx FSM 610 . The signal received by the receiving module 741 may be expressed as Equation 24.

일 때) 상기 수신된 신호는 잡음에 의한 직류 오프셋 만을 포함한다. 즉, 이 경우 수신된 신호 내에 데이터 신호는 존재하지 않는다. 예를 들어,

일 때 수신된 신호

을

이라 하면, 추정 모듈(742)은

을 이용하여 잡음 한정 스테이지에서와 유사한 방식으로 직류 오프셋을 추정할 수 있다. 추정 모듈(742)에 의해 직류 오프셋을 추정하기 위한 프로세스가 이하에서 도 8을 참조하여 단계 별로 상세하게 설명된다.For ASK and OOK modulation, when the amplitude of the signal is zero (i.e.,

), the received signal includes only a DC offset caused by noise. That is, in this case, there is no data signal in the received signal. for example,

signal received when

second

If , the estimation module 742 is

can be used to estimate the DC offset in a similar way as in the noise confinement stage. A process for estimating the DC offset by the estimation module 742 is described in detail step by step with reference to FIG. 8 below.

동안에 수신된

의 N 개의 샘플로부터

의 N⁺ 개의 샘플을 추정할 수 있다. 여기서,

는 AGC의 이득이 고정된 후 Rx FSM(610)으로부터 DCOE Enable 신호가 수신되는 때를 나타낸다.Step 1. Estimating module 742 sets the time window

received during

from N samples of

of N ⁺ samples can be estimated. here,

indicates when the DCOE Enable signal is received from the Rx FSM 610 after the gain of the AGC is fixed.

을 이용하여 타임 윈도우

동안의 직류 오프셋의 크기

를 추정한다. 직류 오프셋의 크기

는 수학식 25와 같이 표현될 수 있다.Step 2. Estimating module 742

time window using

The magnitude of the DC offset during

to estimate DC offset size

can be expressed as in Equation 25.

를 추정한다. 직류 오프셋의 동상 성분

를 추정하기 위하여 타임 윈도우

동안 동상 변에 직류 오프셋

가 감산으로 적용된다. 추정 모듈(742)에 의해 추정되는

는 수학식 26과 같이 표현될 수 있다.Step 3. Estimation module 742 provides an in-phase component of the DC offset

to estimate In-phase component of DC offset

time window to estimate

DC offset to the in-phase side while

is applied as a subtraction. estimated by the estimation module 742 .

can be expressed as in Equation 26.

를 추정한다. 직류 오프셋의 직교상 성분

를 추정하기 위하여 타임 윈도우

동안 직교상 변에 직류 오프셋

가 감산으로 적용된다. 추정 모듈(742)에 의해 추정되는

는 수학식 27과 같이 표현될 수 있다.Step 4. Estimation module 742 determines the orthogonal component of the DC offset

to estimate Quadrature component of DC offset

time window to estimate

DC offset on the quadrature side while

is applied as a subtraction. estimated by the estimation module 742 .

can be expressed as in Equation 27.

동안 직류 오프셋을 보상하기 위하여 직류 오프셋

를 감산으로 적용한다.Step 5. Estimation module 742 time window until new input is received from Rx FSM 610

DC offset to compensate for DC offset during

is applied as a subtraction.

Alternatively, in the second section, a variable DC offset as in Equation 28 may be applied to the analog front end.

In this case, the in-phase component and the quadrature component of the DC offset estimated in the second section and the third section can be expressed as Equations 29 and 30, respectively.

In the noise confinement stage, the DC offset register 640 is initialized to a value of zero. The DC offset estimator 630 uses all samples in a plurality of sections for the estimation process in the noise confinement stage, and uses the zero value of the preamble for the estimation process in the signal and noise stages.

In one embodiment, system 700 may be configured to compensate for DC offset in receiver architecture 300 . After the DC offset is estimated, the DC offset compensation process may be initiated by the system 700 and the DC offset estimate may be passed to the DC offset register 640 using the SPI protocol. The DC offset estimate is then applied subtractively to the analog baseband to compensate for the DC offset of the receiver architecture 300 .

Referring to FIG. 9 , a flowchart of a method for estimating a correlated DC offset of an ultra-low power receiver according to an embodiment is shown. The method of FIG. 9 may be performed, for example, by the system 200 of FIG. 2 . The method of FIG. 9 may be used to compensate for a DC offset based on the estimated DC offset.

In step 910, the DC offset estimation method includes receiving a signal from an output of an ADC of an ultra-low power receiver. The received signal includes a correlated variable DC component for a plurality of sides of the ultra-low power receiver. The plurality of sides includes an in-phase side and an orthogonal side. In one embodiment, receiving the signal may be performed by the receiving module 241 of the system 200 .

In operation 920, the DC offset estimation method includes estimating a DC offset compensation parameter in a plurality of sections for a plurality of stages by using the received signal. In one embodiment, estimating the DC offset compensation parameter may be performed by the estimation module 242 of the system 200 .

Referring to FIG. 10, a flowchart of a method of estimating a DC offset of an ultra-low power receiver according to another embodiment is shown. The method of FIG. 10 may be performed, for example, by the system 700 of FIG. 7 . The method of FIG. 10 may be used to compensate for a DC offset based on the estimated DC offset.

In step 1010, the DC offset estimation method includes receiving a signal from an output of an ADC of an ultra-low power receiver. The received signal includes variable DC components for a plurality of sides of the ultra-low power receiver. The plurality of sides includes an in-phase side and an orthogonal side. In one embodiment, receiving the signal may be performed by the receiving module 741 of the system 700 .

In operation 1020, the DC offset estimation method includes estimating a DC offset compensation parameter in a plurality of sections for a plurality of stages by using the received signal. In one embodiment, estimating the DC offset compensation parameter may be performed by the estimation module 742 of the system 700 .

In step 1030, the DC offset estimation method includes subtracting the estimated DC offset compensation parameter to compensate for the DC offset of the ultra-low power receiver.

11-15 graphically illustrate exemplary results according to the method of FIG. 8 performed by the system 200 of FIG. 2 in accordance with one embodiment.

Referring to FIG. 11 , a DC offset compensation process is illustrated by way of example. The output of the AD converter for 0 μs to 4 μs shows a DC offset magnitude of about 110 mV. The sign of the DC offset cannot be discerned from the output of the AD converter. The magnitude of the DC offset is estimated, and the estimated magnitude of the DC offset is transmitted to the analog compensation circuit to compensate for the DC offset. The analog compensation circuit assumes that the sign of the DC offset is a positive sign and applies the estimated DC offset magnitude as a subtraction. That is, -110 mV may be applied to compensate the DC offset for 4 μs to 8 μs by the analog compensation circuit. Considering the output of the AD converter for 4 μs to 8 μs, it is identified that the sign of the actual DC offset was a negative sign. The analog compensation circuit applies the DC offset compensation of the correct sign by reallocating the sign of the DC offset. As a result, the DC offset is remarkably reduced after 8 μs.

12 and 13, PER versus signal to noise ratio (SNR) at the receiver antenna is shown. 12 shows the PER performance of the ultra-low power receiver in the absence of compensation of the DC offset. 13 shows a result in which the DC offset of the ultra-low power receiver is removed to a negligible level by compensating for the DC offset by the method of FIG. 9 . Comparing FIGS. 12 and 13 , it is shown that the performance gain according to the method of FIG. 9 compensating for a DC offset is 6 dB to 8 dB.

에 따른 SNR 에 대한 PER 이 도시된다.

인 경우, 직류 오프셋은 효과적으로 보상되고 PER 성능은 직류 오프셋이 없는 경우와 동일하게 유지된다.

인 경우,

인 경우에 비한 1% PER 의 갭은 1 dB 이하이다.Referring to FIG. 14 , in-phase/orthogonal correlation coefficients

The PER for SNR according to is shown.

, the DC offset is effectively compensated and the PER performance remains the same as without DC offset.

If ,

The gap of 1% PER compared to the case of is less than 1 dB.

에 따른 SNR 에 대한 PER 이 도시된다.

인 경우, 직류 오프셋은 효과적으로 보상되고 PER 성능은 직류 오프셋이 없는 경우와 동일하게 유지된다.

인 경우,

인 경우에 비한 1% PER 의 갭은 1 dB 이하이다.15 , in-phase/orthogonal correlation coefficients

The PER for SNR according to is shown.

, the DC offset is effectively compensated and the PER performance remains the same as without DC offset.

If ,

The gap of 1% PER compared to the case of is less than 1 dB.

16 and 17 graphically illustrate exemplary results according to the method of FIG. 10 performed by the system 700 of FIG. 7 in accordance with one embodiment.

16 and 17, PER versus SNR at the receiver antenna is shown. FIG. 16 shows a result in which the DC offset of the ultra-low power receiver is removed to a negligible level by compensating for the DC offset by the method of FIG. 10 . 17 shows PER when DC offset compensation is applied according to a conventional method.

18 illustrates a computing environment 1800 implementing a method and system for estimating and compensating for a DC offset of an ultra-low power receiver in accordance with one embodiment. Computing environment 1800 includes at least one Processing Unit (PU) 1810 having a Control Unit 1811 and an Arithmetic and Logic Unit (ALU) 1812 . do. The computing environment 1800 also includes a memory 1820 , a storage unit 1830 , a plurality of network devices 1840 , and an input/output device 1850 . The processing unit 1810 is configured to process instructions of the algorithm. The processing unit 1810 may receive a command from the control unit 1811 to perform a process. Further, the processing unit 1810 may be assisted by the arithmetic logic operation unit 1812 to perform a logical operation or an arithmetic operation included in the instruction.

The overall computing environment 1800 may be comprised of a plurality of homogeneous and/or heterogeneous cores, a plurality of different types of central processing units (CPUs), and a media accelerator. . The processing unit 1810 may be located on a single chip or may be located across multiple chips.

Algorithms, including instructions and codes necessary for implementation, are stored in memory 1820 and/or storage 1830 . Upon execution of the algorithm, instructions are fetched from memory 1820 and/or storage 1830 and executed by processing unit 1810 .

Any network device 1840 or external input/output device required for implementation may be coupled to computing environment 1800 via input/output device 1850 .

The embodiments described above may be implemented by a hardware component, a software component, and/or a combination of a hardware component and a software component. For example, the apparatus, methods and components described in the embodiments may include, for example, a processor, a controller, an arithmetic logic unit (ALU), a digital signal processor, a microcomputer, a field programmable gate (FPGA) array), a programmable logic unit (PLU), a microprocessor, or any other device capable of executing and responding to instructions, may be implemented using one or more general purpose or special purpose computers. The processing device may execute an operating system (OS) and one or more software applications running on the operating system. A processing device may also access, store, manipulate, process, and generate data in response to execution of the software. For convenience of understanding, although one processing device is sometimes described as being used, one of ordinary skill in the art will recognize that the processing device includes a plurality of processing elements and/or a plurality of types of processing elements. It can be seen that can include For example, the processing device may include a plurality of processors or one processor and one controller. Other processing configurations are also possible, such as parallel processors.

Software may comprise a computer program, code, instructions, or a combination of one or more thereof, which configures a processing device to operate as desired or is independently or collectively processed You can command the device. The software and/or data may be any kind of machine, component, physical device, virtual equipment, computer storage medium or apparatus, to be interpreted by or to provide instructions or data to the processing device. , or may be permanently or temporarily embody in a transmitted signal wave. The software may be distributed over networked computer systems and stored or executed in a distributed manner. Software and data may be stored in one or more computer-readable recording media.

The method according to the embodiment may be implemented in the form of program instructions that can be executed through various computer means and recorded in a computer-readable medium. The computer-readable medium may include program instructions, data files, data structures, etc. alone or in combination. The program instructions recorded on the medium may be specially designed and configured for the embodiment, or may be known and available to those skilled in the art of computer software. Examples of the computer-readable recording medium include magnetic media such as hard disks, floppy disks and magnetic tapes, optical media such as CD-ROMs and DVDs, and magnetic such as floppy disks. - includes magneto-optical media, and hardware devices specially configured to store and execute program instructions, such as ROM, RAM, flash memory, and the like. Examples of program instructions include not only machine language codes such as those generated by a compiler, but also high-level language codes that can be executed by a computer using an interpreter or the like. The hardware devices described above may be configured to operate as one or more software modules to perform the operations of the embodiments, and vice versa.

As described above, although the embodiments have been described with reference to the limited embodiments and drawings, various modifications and variations are possible from the above description by those skilled in the art. For example, the described techniques are performed in an order different from the described method, and/or the described components of the system, structure, apparatus, circuit, etc. are combined or combined in a different form than the described method, or other components Or substituted or substituted by equivalents may achieve an appropriate result. Therefore, other implementations, other embodiments, and equivalents to the claims are also within the scope of the following claims.

Claims (20)

A method for estimating a correlated DC offset of an ultra-low power receiver, the method comprising:
receiving a signal at the output of an analog to digital converter (AD converter) of the receiver, the signal comprising a correlated variable DC component for at least one of an in-phase side and a quadrature side of the receiver; and
estimating a DC offset compensation parameter in a plurality of sections for a plurality of stages using the received signal
including,
The plurality of stages,
a noise only stage provided before the packet is detected and a signal and noise stage provided after the packet is detected;
The step of estimating the DC offset compensation parameter comprises:
calculating a DC offset compensation parameter in a magnitude estimation section for the plurality of stages; and
Calculating a DC offset compensation parameter in a sign estimation section for the plurality of stages
Including, DC offset estimation method. According to claim 1,
The received signal is an output of an envelope detector of a non-coherent receiver. According to claim 1,
wherein the received signal is an envelope of an in-phase component and a quadrature component of a coherent receiver. According to claim 1,
The correlated variable direct current component is
Including a value determined from a Gaussian normal distribution according to the gain setting of the PGA,
DC offset estimation method. delete According to claim 1,
Calculating a DC offset compensation parameter in the magnitude estimation section for the plurality of stages includes:
calculating, for the signal and noise stage, a DC offset compensation parameter in the magnitude estimation interval using a zero value of the received signal during a predefined time window;
DC offset estimation method. According to claim 1,
Calculating a DC offset compensation parameter in the sign estimation section for the plurality of stages includes:
For at least one of the noise confinement stage and the signal and noise stage:
allocating one of a positive sign or a negative sign to the DC offset compensation parameter in the magnitude estimation section;
obtaining a DC offset compensation parameter in the code estimation section based on compensation for the DC offset according to the assigned code;
analyzing an effect of the compensation for the DC offset on the code estimation section; and
re-assigning the sign of the DC offset compensation parameter based on the analysis
Including, DC offset estimation method. 8. The method of claim 7,
The method further comprising compensating for the DC offset based on the reassigned sign. 8. The method of claim 7,
The analyzing step is
and comparing the value of the DC offset compensation parameter in the magnitude estimation section with the value of the DC offset compensation parameter in the sign estimation section. 8. The method of claim 7,
The step of reassigning the code is
and maintaining the assigned sign when the DC offset compensation parameter in the magnitude estimation section is greater than the DC offset compensation parameter in the code estimation section. 8. The method of claim 7,
The step of reassigning the code is
and inverting the assigned sign when the DC offset compensation parameter in the magnitude estimation section is smaller than the DC offset compensation parameter in the code estimation section. A method for estimating a DC offset of an ultra-low power receiver, the method comprising:
receiving a signal at an output of an AD converter of the receiver, the signal including a variable DC component for at least one of an in-phase side and a quadrature side of the receiver; and
estimating a DC offset compensation parameter in a plurality of sections for a plurality of stages using the received signal
including,
The step of estimating the DC offset compensation parameter comprises:
For the plurality of stages:
calculating a magnitude of a DC offset using the received signal in a first section;
A DC offset magnitude is calculated using the received signal in a second section, and the DC offset in the in-phase side is calculated based on the DC offset value calculated in the first section and the DC offset value calculated in the second section. calculating an offset compensation parameter; and
In a third section, a DC offset magnitude is calculated using the received signal, and based on the magnitude of the DC offset calculated in the first section and the magnitude of the DC offset calculated in the third section, in the orthogonal side calculating a DC offset compensation parameter;
DC offset estimation method comprising a. 13. The method of claim 12,
The DC offset compensation parameter in the in-phase side includes a magnitude and a sign of the DC offset in the in-phase side,
The DC offset compensation parameter at the orthogonal side includes a magnitude and a sign of a DC offset at the orthogonal side. 13. The method of claim 12,
wherein the plurality of stages includes a noise confinement stage and a signal and noise stage. 13. The method of claim 12,
Compensating for the DC offset based on the estimated DC offset compensation parameter. A system for estimating a correlated DC offset of an ultra-low power receiver, comprising:
processor; and
a memory coupled to the processor and storing a plurality of modules executed by the processor;
The plurality of modules,
a receiving module for receiving a signal at the output of the AD converter of the receiver, the signal including a correlated variable DC component for at least one of an in-phase side and a quadrature side of the receiver; and
An estimation module for estimating a DC offset compensation parameter in a plurality of sections for a plurality of stages using the received signal
including,
The plurality of stages,
a noise only stage provided before the packet is detected and a signal and noise stage provided after the packet is detected;
The estimation module is
calculating a DC offset compensation parameter in a magnitude estimation section for the plurality of stages;
calculating a DC offset compensation parameter in a sign estimation section for the plurality of stages,
DC offset estimation system. 17. The method of claim 16,
When the estimation module estimates the DC offset compensation parameter in the plurality of sections with respect to the plurality of stages,
For at least one of the noise confinement stage and the signal and noise stage:
Allocating one of a positive sign or a negative sign to the DC offset compensation parameter in the magnitude estimation section,
obtaining a DC offset compensation parameter in the code estimation section based on compensation for the DC offset according to the assigned code;
analyzing the effect of the compensation for the DC offset on the code estimation section,
reallocating the sign of the DC offset compensation parameter based on the analysis,
DC offset estimation system. 18. The method of claim 17,
When the estimation module analyzes the effect of the compensation on the sign estimation section,
Comparing the value of the DC offset compensation parameter in the magnitude estimation section and the DC offset compensation parameter in the sign estimation section,
DC offset estimation system. 18. The method of claim 17,
When the estimation module reallocates the sign,
maintaining the assigned sign when the DC offset compensation parameter in the magnitude estimation section is greater than the DC offset compensation parameter in the code estimation section;
DC offset estimation system. 18. The method of claim 17,
When the estimation module reallocates the sign,
inverting the assigned sign when the DC offset compensation parameter in the magnitude estimation section is smaller than the DC offset compensation parameter in the code estimation section;
DC offset estimation system.

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