KR102390076B1 - Method of manufacturing a semiconductor device and a semiconductor device - Google Patents

Abstract

In a method of manufacturing a semiconductor device, a single crystal oxide layer is formed over a substrate. After the single crystal oxide layer is formed, an isolation structure for forming an active region is formed. A gate structure is formed over the single crystal oxide layer in the active region. A source/drain structure is formed.

Description

The manufacturing method of a semiconductor device, and a semiconductor device TECHNICAL FIELD

Related applications

This application claims priority to U.S. Provisional Patent Application No. 62/738,595, filed September 28, 2018, the disclosure of which is incorporated herein by reference in its entirety.

Conventional complementary metal-oxide-semiconductor (CMOS) technology often uses metal-oxide-semiconductor field effect transistors (MOSFETs) and bipolar junction transistors. : BJTs) are implemented to fabricate a single integrated-circuit (IC) chip at approximately the same level of fabrication. In advanced IC chips, transistors are arranged on multiple layers.

BRIEF DESCRIPTION OF THE DRAWINGS The present disclosure is best understood from the following detailed description when read in conjunction with the accompanying drawings. It is emphasized that, in accordance with standard practice in the industry, various features are used for illustrative purposes only and not drawn to scale. Indeed, the dimensions of various features may be arbitrarily increased or decreased for clarity of description.
1 illustrates one of various stages of manufacturing a semiconductor FET device in accordance with an embodiment of the present disclosure;
2 depicts one of various stages of manufacturing a semiconductor FET device in accordance with an embodiment of the present disclosure;
3 depicts one of various stages of manufacturing a semiconductor FET device in accordance with an embodiment of the present disclosure;
4 depicts one of various stages of manufacturing a semiconductor FET device in accordance with an embodiment of the present disclosure;
5 depicts one of various stages of manufacturing a semiconductor FET device in accordance with an embodiment of the present disclosure.
6 depicts one of various stages of manufacturing a semiconductor FET device in accordance with an embodiment of the present disclosure.
7 depicts one of various stages of manufacturing a semiconductor FET device in accordance with an embodiment of the present disclosure;
8 depicts one of various stages of manufacturing a semiconductor FET device in accordance with an embodiment of the present disclosure.
9 depicts one of various stages of manufacturing a semiconductor FET device in accordance with an embodiment of the present disclosure.
10 depicts one of various stages of manufacturing a semiconductor FET device in accordance with an embodiment of the present disclosure.
11 depicts one of various stages of manufacturing a semiconductor FET device in accordance with an embodiment of the present disclosure.
12 depicts one of various stages of manufacturing a semiconductor FET device in accordance with an embodiment of the present disclosure.
13A and 13B illustrate one of various stages of manufacturing a semiconductor FET device in accordance with an embodiment of the present disclosure;
14 depicts one of various stages of manufacturing a semiconductor FET device according to another embodiment of the present disclosure.
15 depicts one of various stages of manufacturing a semiconductor FET device in accordance with another embodiment of the present disclosure.
16 depicts one of various stages of manufacturing a semiconductor FET device according to another embodiment of the present disclosure.
17 depicts one of various stages of manufacturing a semiconductor FET device according to another embodiment of the present disclosure.
18 depicts one of various stages of manufacturing a semiconductor FET device according to another embodiment of the present disclosure.
19 depicts one of various stages of manufacturing a semiconductor FET device in accordance with another embodiment of the present disclosure.
20 depicts one of various stages of manufacturing a semiconductor FET device in accordance with another embodiment of the present disclosure.
21 depicts one of various stages of manufacturing a semiconductor FET device in accordance with another embodiment of the present disclosure.
22 depicts one of various stages of manufacturing a semiconductor FET device in accordance with another embodiment of the present disclosure.
23 depicts one of various stages of manufacturing a semiconductor FET device in accordance with another embodiment of the present disclosure.
24 depicts one of various stages of manufacturing a semiconductor FET device in accordance with another embodiment of the present disclosure.
25 depicts one of various stages of manufacturing a semiconductor FET device in accordance with another embodiment of the present disclosure.
26 depicts one of various stages of manufacturing a semiconductor FET device in accordance with another embodiment of the present disclosure.
27 depicts one of various stages of manufacturing a semiconductor FET device in accordance with another embodiment of the present disclosure.
28 depicts one of various stages of manufacturing a semiconductor FET device in accordance with another embodiment of the present disclosure.
29 depicts one of various stages of manufacturing a semiconductor FET device in accordance with another embodiment of the present disclosure.
30 depicts one of various stages of manufacturing a semiconductor FET device in accordance with another embodiment of the present disclosure.
31 depicts one of various stages of manufacturing a semiconductor FET device according to another embodiment of the present disclosure.
32 depicts one of various stages of manufacturing a semiconductor FET device in accordance with another embodiment of the present disclosure.
33 depicts one of various stages of manufacturing a semiconductor FET device in accordance with another embodiment of the present disclosure.
34 illustrates one of various stages of manufacturing a semiconductor FET device in accordance with another embodiment of the present disclosure.
35 depicts one of various stages of manufacturing a semiconductor FET device in accordance with another embodiment of the present disclosure.
36A depicts one of various stages of manufacturing a semiconductor FET device in accordance with another embodiment of the present disclosure. 36B depicts one of various stages of manufacturing a semiconductor FET device in accordance with another embodiment of the present disclosure.
37 illustrates a cross-sectional view of a semiconductor FET device in accordance with an embodiment of the present disclosure.

It should be understood that the following disclosure provides many different embodiments or examples for implementing different features of the invention. Specific embodiments or examples of components and devices are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, the dimensions of an element are not limited to the disclosed ranges or values, and may depend on process conditions and/or desired characteristics of the device. Moreover, in the description that follows, the formation of a first feature over or on a second feature may include embodiments in which the first and second features are formed in direct contact, wherein the additional features are formed in direct contact with the first and second features. It may also include embodiments that may be formed between portions, such that the first and second features may not be in direct contact. Various features may be arbitrarily drawn to different scales for purposes of simplicity and clarity.

Also, spatially relative terms such as "below", "below", "lower", "above", "upper" and the like refer to one element or to another element(s) or feature(s) as shown in the figures. It may be used herein for easy description to describe the relationship of features. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The apparatus may be otherwise oriented (rotated 90 degrees or at other orientations), and spatially relative descriptors used herein may likewise be interpreted accordingly. Furthermore, the term “made of” may mean “comprising” or “consisting of”. In the present disclosure, the phrase “one of A, B and C” means “A, B and/or C” (A, B, C, A and B, A and C, B and C, or A, B and C), and not one element from A, one element from B and one element from C, unless stated otherwise.

In a transistor manufacturing process in a back-end of line, there is a main process for forming a high quality crystalline semiconductor layer for a channel of a transistor over an amorphous layer such as a silicon oxide layer. A method for manufacturing a crystalline semiconductor on a silicon oxide layer includes the steps of: (a) growing a semiconductor film in an amorphous state followed by high-temperature annealing; and (b) growing the semiconductor layer by using the crystalline seed grown from the crystalline Si substrate. All of these methods have a thermal budget limitation in method (a), for example below 450°C, and in method (b) the crystalline seed layer needs to pass through multiple metal layers and an interlayer dielectric layer. Because there is, it may not be suitable for the post-processing process.

The present disclosure provides a method for forming a high quality crystalline semiconductor layer on an amorphous (amorphous) dielectric layer. The present disclosure also provides a self-aligned method for fabricating a transistor in a region where a polycrystalline or amorphous semiconductor layer is converted into a crystalline layer having a high degree of crystallinity.

In the following embodiments, materials, configurations, dimensions, and/or processes of one embodiment may be used in other embodiments unless otherwise described, and detailed descriptions thereof may be omitted.

1-13A illustrate various stages of manufacturing a semiconductor FET device in accordance with an embodiment of the present disclosure. It is understood that additional operations may be provided before, during, and after the operations illustrated by FIGS. 1-13A , and that some of the operations described below may be replaced or eliminated for additional embodiments of the method. . The order of actions/processes may be interchangeable. Also, in the present disclosure, source and drain are used interchangeably and source/drain refers to at least one of source and drain.

1 , a substrate 10 is provided. In some embodiments, the substrate 10 includes a single crystal semiconductor layer on at least a surface portion thereof. Substrate 10 may include single crystal semiconductor materials such as, but not limited to, Si, Ge, SiGe, GaAs, InSb, GaP, GaSb, InAlAs, InGaAs, GaSbP, GaAsSb, and InP. In certain embodiments, the substrate 10 is made of crystalline Si, SiGe, or Ge. Substrate 10 may include one or more buffer layers (not shown) within its surface region in some embodiments. The buffer layer may serve to gradually change the lattice constant from that of the substrate to that of the source/drain region. The buffer layer is formed from an epitaxially grown single crystal semiconductor material such as, but not limited to, Si, Ge, GeSn, SiGe, GaAs, InSb, GaP, GaSb, InAlAs, InGaAs, GaSbP, GaAsSb, GaN, GaP, and InP. it might be In a particular embodiment, the substrate 10 includes a silicon germanium (SiGe) buffer layer epitaxially grown on the silicon substrate 10 . The germanium concentration of the SiGe buffer layer may increase from 30 atomic % germanium for the bottom buffer layer to 70 atomic % germanium for the top buffer layer.

Also, as shown in FIG. 1 , one or more dielectric layers 20 are formed over the substrate 10 . In some embodiments, one or more electronic devices, such as transistors, memory (eg, dynamic random access memory (DRAM), static RAM, magnetic MRAM, and/or phase change RAM), are attached to the substrate 10 . One or more dielectric layers 20 are formed thereon and cover the electronic device. Also, one or more metal interconnect structures are embedded in the dielectric layer 20 . The dielectric material for the dielectric layer 20 may include silicon oxide, silicon nitride, silicon oxynitride (LPCVD) formed by low pressure chemical vapor deposition (LPCVD), plasma-CVD or flowable CVD, or any other suitable deposition method. SiON), SiCN, fluorine doped silicate glass (FSG), or low-k dielectric materials. An annealing operation may be performed after formation of the dielectric layer 20 . In some embodiments, a planarization operation, such as a chemical mechanical polishing (CMP) method and/or an etch-back method, is performed to flatten the surface of the dielectric layer 20 .

With continued reference to FIG. 1 , a semiconductor layer 30 as a channel semiconductor material is formed over the dielectric layer 20 . Semiconductor materials for semiconductor layer 30 include, in some embodiments, Si, Ge, SiGe, GaAs, InSb, GaP, GaSb, InAlAs, InGaAs, GaSbP, GaAsSb, and InP. In certain embodiments, the semiconductor layer 30 is made of Si, SiGe, or Ge.

In some embodiments, the semiconductor layer 30 is formed by CVD, ALD, or any other suitable deposition method. In some embodiments, the deposition is performed at a temperature of less than about 450°C. In some embodiments, the deposition is performed at a temperature of about 25° C. or higher. In some embodiments, Si ₂ H ₆ gas is used as the source gas of Si, and Ge ₂ H ₆ is used as the source gas of Ge. In certain embodiments, GeH ₄ and/or SiH ₄ are used instead of or in addition to Ge ₂ H ₆ and/or Si ₂ H ₆ . In some embodiments, semiconductor layer 30 is amorphous or crystalline. In some embodiments, semiconductor layer 30 is suitably doped with impurities such as P, As, Sb and/or B. Impurities are doped in-situ during film formation, or doped by ion implantation or plasma doping after the semiconductor layer 30 is formed. The thickness of the semiconductor layer 30 ranges from about 5 nm to about 500 nm in some embodiments, and from about 10 nm to about 50 nm in other embodiments.

Next, as shown in FIG. 2 , a seed layer 40 is formed over the semiconductor layer 30 . In some embodiments, a seed layer is not formed under the semiconductor layer 30 . In some embodiments, the seed layer 40 is crystalline in the as-deposited state or is made of a metal oxide by low temperature annealing at about 300°C to about 450°C. In a particular embodiment, the seed layer 40 is made of magnesium oxide (MgO). In some embodiments, the MgO seed layer 40 is monocrystalline. In another embodiment, the MgO seed layer 40 is polycrystalline or has multiple domains of single crystal. The seed layer 40 may be formed by CVD, atomic layer deposition (ALD), physical vapor deposition including sputtering, or any other suitable deposition method. The thickness of the seed layer 40 ranges from about 1 nm to about 100 nm in some embodiments, and from about 2 nm to about 20 nm in other embodiments. In certain embodiments, the thickness of the seed layer 40 ranges from about 1 nm to about 10 nm. In another embodiment, HfO ₂ , La ₂ Hf ₂ O ₇ , Y ₂ O ₃ , SrTiO ₃ and HfZrO ₂ are used as the seed layer 40 .

Next, as shown in FIG. 3 , seed layer 40 is patterned into patterned seed layer 45 using one or more lithography and etching operations. Lithographic operations include ultraviolet (UV) lithography, deep UV (DUV) lithography, extreme UV (EUV) lithography, electron beam (e-beam) lithography, and etching operations include plasma dry etching. The patterned seed layer 45 corresponds to the gate electrode of the FET formed thereafter. Accordingly, the width W1 of the patterned seed layer 45 corresponds to the gate length of the FET, and the patterned seed layer 45 has a shape corresponding to the gate electrode of the FET. In some embodiments, the patterned seed layer 45 has a line shape. The width W1 ranges from about 5 nm to about 500 nm in some embodiments, and in other embodiments from about 20 nm to about 200 nm.

Next, as shown in Figs. 4 to 7, a crystallization process for crystallizing the semiconductor layer 30 is performed. The crystallization process includes thermal annealing. In some embodiments, the thermal annealing comprises a laser annealing process using a nanosecond laser transparent to the seed layer. In another embodiment, the thermal annealing comprises a low temperature annealing at a temperature in the range of about 350°C to 450°C.

5 and 6, the semiconductor layer 30 begins to crystallize the bottom (corresponding to the channel region of the subsequently formed FET) of the patterned seed layer as a crystal template. By continuing the thermal annealing process, the crystallized portion 35 of the semiconductor layer 30 expands laterally into the source/drain region as shown in FIG. 7 . In some embodiments, the entire semiconductor layer 30 is crystalline.

Next, as shown in FIG. 8 , sidewall spacers 50 are formed on opposite sides of the patterned seed layer 45 . A blanket layer of insulating material for the sidewall spacers 50 is conformally formed by using CVD or other suitable method. The blanket layer is conformally deposited to have substantially the same thickness on a vertical surface, such as a sidewall, a horizontal surface, and an upper portion of the patterned seed layer 45 . In some embodiments, the blanket layer is deposited to a thickness ranging from about 2 nm to about 30 nm. In one embodiment, the insulating material of the blanket layer is different from the material of the patterned seed layer 45 and is made of a silicon nitride based material, such as silicon nitride, SiON, SiOCN or SiCN and combinations thereof. In some embodiments, the blanket layer (sidewall spacers 50) is made of silicon nitride. The sidewall spacers 50 are formed on opposite sides of the patterned seed layer 45 by anisotropic etching, as shown in FIG. 8 . The patterned seed layer 45 functions as a dummy gate electrode in the gate replacement technique.

Next, as shown in Fig. 9, a source region and a drain region are formed. In some embodiments, source/drain region 60 includes one or more epitaxial semiconductor layers. Source/drain epitaxial layer 60 includes one or more layers of Si, SiP, SiC and SiCP for n-channel FETs or Si, SiGe, Ge for p-channel FETs. For P-channel FETs, boron (B) may also be contained in the source/drain regions. The source/drain epitaxial layer 50 is formed by an epitaxial growth method using CVD, ALD, or MBE. In some embodiments, the source/drain regions of the crystallized semiconductor layer 35 are recessed by etching, and then the source/drain epitaxial layer 60 is a recessed source of the crystallized semiconductor layer 35 ). /forms above the drain area. In another embodiment, one or more ion implantation processes are performed to introduce impurities into the source/drain regions of the crystallized semiconductor layer 35 .

Next, a first interlayer dielectric (ILD) layer 65 is formed over the source/drain epitaxial layer 60 and the patterned seed layer 45 . The material for the first ILD layer 65 includes a compound comprising Si, O, C and/or H, such as silicon oxide, SiCOH and SiOC. An organic material such as a polymer may be used for the first ILD layer 65 . After the first ILD layer 65 is formed, a planarization operation such as CMP is performed to expose an upper portion of the patterned seed layer 45 , as shown in FIG. 10 . In some embodiments, the patterned seed layer 45 functions as a CMP stop layer. In some embodiments, before the first ILD layer 65 is formed, a contact etch stop layer, such as a silicon nitride layer or a silicon oxynitride layer, is formed.

Next, the patterned seed layer 45 is removed, thereby forming a gate space 47 as shown in FIG. 11 . The patterned seed layer 45 may be removed using plasma dry etching and/or wet etching.

After the patterned seed layer 45 is removed, a gate dielectric layer 70 and a gate electrode 75 are formed in the gate space 47 , as shown in FIG. 12 . In some embodiments, gate dielectric layer 70 includes one or more layers of dielectric material, such as silicon oxide, silicon nitride, or a high-k dielectric material, other suitable dielectric material, and/or combinations thereof. Examples of high-k dielectric materials include HfO ₂ , HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, zirconium oxide, aluminum oxide, titanium oxide, hafnium dioxide-alumina (HfO ₂ —Al ₂ O ₃ ) alloys, other suitable high-k dielectric materials, and/or combinations thereof. In some embodiments, the gate dielectric layer 70 includes an interfacial layer formed between the channel layer 35 and the dielectric material using chemical oxidation. Gate dielectric layer 70 may be formed by CVD, ALD, or any suitable method. In one embodiment, the gate dielectric layer 70 is formed using a highly conformal deposition process such as ALD to ensure formation of a gate dielectric layer having a uniform thickness around each channel layer. The thickness of the gate dielectric layer 70 ranges from about 1 nm to about 10 nm in one embodiment.

Thereafter, a gate electrode layer 75 is formed on the gate dielectric layer 70 . The gate electrode layer 75 may be made of aluminum, copper, titanium, tantalum, tungsten, cobalt, molybdenum, tantalum nitride, nickel silicide, cobalt silicide, TiN, WN, TiAl, TiAlN, TaCN, TaC, TaSiN, a metal alloy, other suitable material; and/or one or more layers of conductive material, such as combinations thereof. The gate electrode layer 75 may be formed by CVD, ALD, electrolytic plating, or other suitable method. A metal for the gate dielectric layer 70 and the gate electrode layer 75 is also deposited over the top surface of the first ILD layer 65 . The material for the gate dielectric layer formed over the ILD layer 65 is then planarized using, for example, CMP until the top surface of the ILD layer 65 is exposed. In some embodiments, after the planarization operation, the metal gate electrode layer 77 is recessed and a cap insulating layer (not shown) is formed over the recessed gate electrode layer. The cap insulating layer includes one or more layers of a silicon nitride based material, such as silicon nitride. The cap insulating layer may be formed by depositing an insulating material followed by a planarization operation.

In certain embodiments of the present disclosure, one or more work function tuning layers (not shown) are interposed between the gate dielectric layer 70 and the gate electrode layer 75 . The work function adjusting layer is made of a conductive material such as a single layer of TiN, TaN, TaAlC, TiC, TaC, Co, Al, TiAl, HfTi, TiSi, TaSi or TiAlC, or multiple layers of two or more of these materials. For n-channel FETs, at least one of TaN, TaAlC, TiN, TiC, Co, TiAl, HfTi, TiSi and TaSi is used as the work function tuning layer, for p-channel FETs, TiAlC, Al, TiAl, TaN, At least one of TaAlC, TiN, TiC and Co is used as the work function adjusting layer. The work function tuning layer may be formed by ALD, PVD, CVD, e-beam deposition, or other suitable process. Further, the work function tuning layer may be formed separately for n-channel FETs and p-channel FETs, which may use different metal layers.

Also, as shown in FIG. 13A , a second ILD layer 80 is formed over the first ILD layer 65 and conductive contacts passing through the second ILD layer 80 or the second and first ILD layers. 85 is formed to contact the gate electrode 75 and the source/drain epitaxial layer 60 . Contact openings are formed in the first and/or second ILD layers. One or more layers of a conductive material are formed in and over the contact openings, followed by a planarization operation, such as a CMP operation, followed by performing a planarization operation, as shown in FIG. A contact 85 is formed. In some embodiments, conductive contact 85 includes a liner layer and a body layer. The liner layer is a barrier layer and/or an adhesive (adhesive) layer. In some embodiments, a Ti layer is formed on the source/drain epitaxial layer 55 and a TiN or TaN layer is formed on the Ti layer as a liner layer. The body layer comprises one or more layers of Co, Ni, W, Ti, Ta, Cu and Al, or any other suitable material.

It is understood that FETs undergo additional CMOS processes to form various features such as contacts/vias, interconnect metal layers, dielectric layers, passivation layers, and the like.

In another embodiment, as shown in FIG. 13A , the crystallization process stops when crystallized portions 35 form in essential regions, such as channel regions and source/drain regions. Accordingly, there is a portion of the non-crystallized semiconductor layer 30 that is amorphous or polycrystalline.

14-23 illustrate various stages of manufacturing a semiconductor FET device in accordance with an embodiment of the present disclosure. It is understood that additional operations may be provided before, during, and after the operations illustrated by FIGS. 14-23 , and that some of the operations described below may be replaced or eliminated for additional embodiments of the method. . The order of actions/processes may be interchangeable.

Similar to FIGS. 1 and 2 , a seed layer 40 is formed over the semiconductor layer 30 . Next, as shown in FIG. 14 , the seed layer 40 is patterned into a plurality of patterned seed layers 45 using one or more lithography and etching operations. The lithography operation includes UV lithography, DUV lithography, EUV lithography, e-beam lithography, and the etching operation includes plasma dry etching. The patterned seed layer 45 corresponds to the gate electrode of the FET formed thereafter. In some embodiments, the patterned seed layer 45 has a line shape. The width of the patterned seed layer 45 ranges from about 5 nm to about 500 nm in some embodiments, and from about 20 nm to about 200 nm in other embodiments.

Next, as shown in Figs. 15 to 18, a crystallization process for crystallizing the semiconductor layer 30 is performed. The crystallization process includes thermal annealing. In some embodiments, the thermal annealing comprises a laser annealing process using a nanosecond laser transparent to the seed layer. In another embodiment, the thermal annealing comprises a low temperature annealing at a temperature in the range of about 350°C to 450°C.

16 and 17, the semiconductor layer 30 begins to crystallize the bottom (corresponding to the channel region of the subsequently formed FET) of the patterned seed layer 45 as a crystal template. By continuing the thermal annealing process, the crystallized portion 35 of the semiconductor layer 30 expands laterally into the source/drain region as shown in FIG. 17 .

As shown in FIG. 18 , each front portion of the crystallized semiconductor layer 35 encounters an adjacent front portion of the crystallized semiconductor layer 35 , creating a grain boundary 37 .

Next, as shown in FIG. 19 , sidewall spacers 50 are formed on opposite sides of the patterned seed layer 45 . A blanket layer of insulating material for the sidewall spacers 50 is conformally formed by using CVD or other suitable method. The blanket layer is conformally deposited to have substantially the same thickness on a vertical surface, such as a sidewall, a horizontal surface, and an upper portion of the patterned seed layer 45 . In some embodiments, the blanket layer is deposited to a thickness ranging from about 2 nm to about 30 nm. In one embodiment, the insulating material of the blanket layer is different from the material of the patterned seed layer 45 and is made of a silicon nitride based material, such as silicon nitride, SiON, SiOCN or SiCN and combinations thereof. In some embodiments, the blanket layer (sidewall spacers 50) is made of silicon nitride. The sidewall spacers 50 are formed on opposite sides of the patterned seed layer 45 by anisotropic etching, as shown in FIG. 8 . The patterned seed layer 45 functions as a dummy gate electrode in the gate replacement technique.

Next, as shown in Fig. 20, a source region and a drain region are formed. In some embodiments, source/drain region 60 includes one or more epitaxial semiconductor layers. Source/drain epitaxial layer 60 includes one or more layers of Si, SiP, SiC and SiCP for n-channel FETs or Si, SiGe, Ge for p-channel FETs. For P-channel FETs, boron (B) may also be contained in the source/drain regions. The source/drain epitaxial layer 50 is formed by an epitaxial growth method using CVD, ALD, or MBE. In some embodiments, the source/drain regions of the crystallized semiconductor layer 35 are recessed by etching, and then the source/drain epitaxial layer 60 is a recessed source of the crystallized semiconductor layer 35 ). /forms above the drain area. In another embodiment, one or more ion implantation processes are performed to introduce impurities into the source/drain regions of the crystallized semiconductor layer 35 . In some embodiments, source/drain epitaxial layer 60 completely fills the space between adjacent dummy gate electrodes (patterned seed layer 45), and in other embodiments, source/drain epitaxial layer 60 only partially fills the space between adjacent dummy gate electrodes.

Next, a first interlayer dielectric (ILD) layer 65 is formed over the source/drain epitaxial layer 60 and the patterned seed layer 45 . The material for the first ILD layer 65 includes a compound comprising Si, O, C and/or H, such as silicon oxide, SiCOH and SiOC. An organic material such as a polymer may be used for the first ILD layer 65 . After the first ILD layer 65 is formed, a planarization operation such as CMP is performed to expose an upper portion of the patterned seed layer 45 as shown in FIG. 21 . In some embodiments, the patterned seed layer 45 functions as a CMP stop layer. In some embodiments, before the first ILD layer 65 is formed, a contact etch stop layer, such as a silicon nitride layer or a silicon oxynitride layer, is formed.

Next, the patterned seed layer 45 is removed, thereby forming a gate space 47 as shown in FIG. 22 . The patterned seed layer 45 may be removed using plasma dry etching and/or wet etching.

After the patterned seed layer 45 is removed, a gate dielectric layer 70 and a gate electrode 75 are formed in each gate space 47 , as shown in FIG. 23 . In some embodiments, gate dielectric layer 70 includes one or more layers of dielectric material, such as silicon oxide, silicon nitride, or a high-k dielectric material, other suitable dielectric material, and/or combinations thereof. Examples of high-k dielectric materials include HfO ₂ , HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, zirconium oxide, aluminum oxide, titanium oxide, hafnium dioxide-alumina (HfO ₂ —Al ₂ O ₃ ) alloys, other suitable high-k dielectric materials, and/or combinations thereof. In some embodiments, the gate dielectric layer 70 includes an interfacial layer formed between the channel layer 35 and the dielectric material using chemical oxidation. Gate dielectric layer 70 may be formed by CVD, ALD, or any suitable method. In one embodiment, the gate dielectric layer 70 is formed using a highly conformal deposition process such as ALD to ensure formation of a gate dielectric layer having a uniform thickness around each channel layer. The thickness of the gate dielectric layer 70 ranges from about 1 nm to about 10 nm in one embodiment.

Thereafter, a gate electrode layer 75 is formed on the gate dielectric layer 70 . The gate electrode layer 75 may be made of aluminum, copper, titanium, tantalum, tungsten, cobalt, molybdenum, tantalum nitride, nickel silicide, cobalt silicide, TiN, WN, TiAl, TiAlN, TaCN, TaC, TaSiN, a metal alloy, other suitable material; and/or one or more layers of conductive material, such as combinations thereof. The gate electrode layer 75 may be formed by CVD, ALD, electrolytic plating, or other suitable method. A metal for the gate dielectric layer 70 and the gate electrode layer 75 is also deposited over the top surface of the first ILD layer 65 . The material for the gate dielectric layer formed over the ILD layer 65 is then planarized using, for example, CMP until the top surface of the ILD layer 65 is exposed. In some embodiments, after the planarization operation, the metal gate electrode layer 77 is recessed and a cap insulating layer (not shown) is formed over the recessed gate electrode layer. The cap insulating layer includes one or more layers of a silicon nitride based material, such as silicon nitride. The cap insulating layer may be formed by depositing an insulating material followed by a planarization operation.

In certain embodiments of the present disclosure, one or more work function tuning layers (not shown) are interposed between the gate dielectric layer 70 and the gate electrode layer 75 . The work function adjusting layer is made of a conductive material such as a single layer of TiN, TaN, TaAlC, TiC, TaC, Co, Al, TiAl, HfTi, TiSi, TaSi or TiAlC, or multiple layers of two or more of these materials. For n-channel FETs, at least one of TaN, TaAlC, TiN, TiC, Co, TiAl, HfTi, TiSi and TaSi is used as the work function tuning layer, for p-channel FETs, TiAlC, Al, TiAl, TaN, At least one of TaAlC, TiN, TiC and Co is used as the work function adjusting layer. The work function tuning layer may be formed by ALD, PVD, CVD, e-beam deposition, or other suitable process. Further, the work function tuning layer may be formed separately for n-channel FETs and p-channel FETs, which may use different metal layers.

Also similar to FIG. 13A , a second ILD layer is formed over the first ILD layer, and conductive contacts passing through the second ILD layer or the second and first ILD layers contact the gate electrode and the source/drain epitaxial layer. formed to do

In another embodiment, the crystallization process stops before each front portion of the crystallized semiconductor layer 35 encounters an adjacent front portion of the crystallized semiconductor layer 35 . In this case, a portion of the non-crystallized semiconductor layer 30 remains between adjacent FETs.

It is understood that FETs undergo additional CMOS processes to form various features such as contacts/vias, interconnect metal layers, dielectric layers, passivation layers, and the like.

24-36A illustrate various stages of manufacturing a semiconductor FET device in accordance with an embodiment of the present disclosure. It is understood that additional operations may be provided before, during, and after the operations illustrated by FIGS. 24-36A , and that some of the operations described below may be replaced or eliminated for additional embodiments of the method. . The order of actions/processes may be interchangeable.

Similar to FIG. 1 , a semiconductor layer 30 is formed over the dielectric layer 20 disposed over the substrate 10 , as shown in FIG. 25 . Next, similar to FIG. 2 , a seed layer 40 is formed over the semiconductor layer 30 as shown in FIG. 25 . In some embodiments, the seed layer 40 is crystalline in the as-deposited state or is made of a metal oxide by low temperature annealing at about 350°C to about 450°C. In a particular embodiment, the seed layer 40 is made of magnesium oxide (MgO). In some embodiments, the MgO seed layer 40 is monocrystalline. In another embodiment, the MgO seed layer 40 is polycrystalline or has multiple domains of single crystal. The seed layer 40 may be formed by CVD, atomic layer deposition (ALD), physical vapor deposition including sputtering, or any other suitable deposition method. The thickness of the seed layer 40 ranges from about 1 nm to about 100 nm in some embodiments, and from about 2 nm to about 20 nm in other embodiments. In certain embodiments, the thickness of the seed layer 40 ranges from about 1 nm to about 10 nm.

Next, as shown in FIG. 26 , a dummy gate layer 90 is formed over the seed layer 45 . In some embodiments, dummy gate layer 90 is made of polysilicon or amorphous silicon. Other semiconductor or dielectric materials that can be selectively removed with respect to the ILD layer and sidewall spacers may also be used. The thickness of the dummy gate layer 90 is in a range from about 50 nm to about 500 nm in some embodiments, and in a range from about 100 nm to about 200 nm in other embodiments. The dummy gate layer 90 may be formed by CVD, atomic layer deposition (ALD), physical vapor deposition including sputtering, or any other suitable deposition method.

Next, as shown in Figure 27, dummy gate layer 90 and seed layer 40 are formed using one or more lithography and etching operations, a plurality of patterned dummy gate layer 95 and patterned seed layer. It is patterned with (45). The lithography operation includes UV lithography, DUV lithography, EUV lithography, e-beam lithography, and the etching operation includes plasma dry etching. The patterned dummy gate layer 95 and the patterned seed layer 45 correspond to the gate electrode of the FET formed thereafter. In some embodiments, the patterned dummy gate layer 95 and the patterned seed layer 45 have a line shape. The width of the patterned dummy gate layer 95 and the patterned seed layer 45 ranges from about 5 nm to about 500 nm in some embodiments, and from about 20 nm to about 200 nm in other embodiments.

Next, as shown in Figs. 28 to 31, a crystallization process for crystallizing the semiconductor layer 30 is performed. The crystallization process includes thermal annealing. In some embodiments, the thermal annealing comprises a laser annealing process using a nanosecond laser transparent to the seed layer. In another embodiment, the thermal annealing comprises a low temperature annealing at a temperature in the range of about 350°C to 450°C.

29 and 30, the semiconductor layer 30 begins to crystallize the bottom (corresponding to the channel region of the subsequently formed FET) of the patterned seed layer 45 as a crystal template. By continuing the thermal annealing process, the crystallized portion 35 of the semiconductor layer 30 expands laterally into the source/drain region as shown in FIG. 30 .

As shown in FIG. 31 , each front portion of the crystallized semiconductor layer 35 encounters an adjacent front portion of the crystallized semiconductor layer 35 , creating a grain boundary 37 .

Next, as shown in FIG. 32 , sidewall spacers 50 are formed on opposite sides of the patterned dummy gate layer 95 and the patterned seed layer 45 . A blanket layer of insulating material for the sidewall spacers 50 is conformally formed by using CVD or other suitable method. The blanket layer is conformally deposited to have substantially the same thickness on a vertical surface, such as a sidewall, a horizontal surface, and an upper portion of the patterned dummy gate layer 95 and the patterned seed layer 45 . In some embodiments, the blanket layer is deposited to a thickness ranging from about 2 nm to about 30 nm. In one embodiment, the insulating material of the blanket layer is different from the material of the patterned dummy gate layer 95 and the patterned seed layer 45, and is silicon, such as silicon nitride, SiON, SiOCN or SiCN, and combinations thereof. It is made of a nitride-based material. In some embodiments, the blanket layer (sidewall spacers 50) is made of silicon nitride. The sidewall spacers 50 are formed on opposite sides of the patterned dummy gate layer 95 and the patterned seed layer 45 by anisotropic etching, as shown in FIG. 8 . The patterned dummy gate layer 95 and the patterned seed layer 45 function as a dummy gate electrode in the gate replacement technique.

Next, as shown in Fig. 33, a source region and a drain region are formed. In some embodiments, source/drain region 60 includes one or more epitaxial semiconductor layers. Source/drain epitaxial layer 60 includes one or more layers of Si, SiP, SiC and SiCP for n-channel FETs or Si, SiGe, Ge for p-channel FETs. For P-channel FETs, boron (B) may also be contained in the source/drain regions. The source/drain epitaxial layer 50 is formed by an epitaxial growth method using CVD, ALD, or MBE. In some embodiments, the source/drain regions of the crystallized semiconductor layer 35 are recessed by etching, and then the source/drain epitaxial layer 60 is a recessed source of the crystallized semiconductor layer 35 ). /forms above the drain area. In another embodiment, one or more ion implantation processes are performed to introduce impurities into the source/drain regions of the crystallized semiconductor layer 35 . In some embodiments, source/drain epitaxial layer 60 completely fills the space between adjacent dummy gate electrodes (patterned dummy gate layer 95 and patterned seed layer 45), and in other embodiments, The source/drain epitaxial layer 60 only partially fills the space between adjacent dummy gate electrodes.

Next, a first interlayer dielectric (ILD) layer 65 is formed over the source/drain epitaxial layer 60 and the patterned dummy gate layer 95 and the patterned seed layer 45 . The material for the first ILD layer 65 includes a compound comprising Si, O, C and/or H, such as silicon oxide, SiCOH and SiOC. An organic material such as a polymer may be used for the first ILD layer 65 . After the first ILD layer 65 is formed, a planarization operation such as CMP is performed to expose the upper portion of the patterned dummy gate layer 95 and the patterned seed layer 45, as shown in FIG. will become In some embodiments, the patterned dummy gate layer 95 functions as a CMP stop layer. In some embodiments, before the first ILD layer 65 is formed, a contact etch stop layer, such as a silicon nitride layer or a silicon oxynitride layer, is formed.

Next, the patterned dummy gate layer 95 and the patterned seed layer 45 are removed, thereby forming a gate space 47 as shown in FIG. 22 . The patterned dummy gate layer 95 and the patterned seed layer 45 may be removed using plasma dry etching and/or wet etching. When the patterned dummy gate layer 95 is polysilicon or amorphous silicon, a wet etchant such as tetramethylammonium hydroxide (TMAH) solution may be used to selectively remove the dummy gate electrode layer. The patterned seed layer 45 is then removed using plasma dry etching and/or wet etching.

After the patterned dummy gate layer 95 and the patterned seed layer 45 are removed, a gate dielectric layer 70 and a gate electrode 75 are placed in each gate space 47, as shown in FIG. 36A. is formed In some embodiments, gate dielectric layer 70 includes one or more layers of dielectric material, such as silicon oxide, silicon nitride, or a high-k dielectric material, other suitable dielectric material, and/or combinations thereof. Examples of high-k dielectric materials include HfO ₂ , HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, zirconium oxide, aluminum oxide, titanium oxide, hafnium dioxide-alumina (HfO ₂ —Al ₂ O ₃ ) alloys, other suitable high-k dielectric materials, and/or combinations thereof. In some embodiments, the gate dielectric layer 70 includes an interfacial layer formed between the channel layer 35 and the dielectric material using chemical oxidation. Gate dielectric layer 70 may be formed by CVD, ALD, or any suitable method. In one embodiment, the gate dielectric layer 70 is formed using a highly conformal deposition process such as ALD to ensure formation of a gate dielectric layer having a uniform thickness around each channel layer. The thickness of the gate dielectric layer 70 ranges from about 1 nm to about 10 nm in one embodiment.

Thereafter, a gate electrode layer 75 is formed on the gate dielectric layer 70 . The gate electrode layer 75 may be made of aluminum, copper, titanium, tantalum, tungsten, cobalt, molybdenum, tantalum nitride, nickel silicide, cobalt silicide, TiN, WN, TiAl, TiAlN, TaCN, TaC, TaSiN, a metal alloy, other suitable material; and/or one or more layers of conductive material, such as combinations thereof. The gate electrode layer 75 may be formed by CVD, ALD, electrolytic plating, or other suitable method. A metal for the gate dielectric layer 70 and the gate electrode layer 75 is also deposited over the top surface of the first ILD layer 65 . The material for the gate dielectric layer formed over the ILD layer 65 is then planarized using, for example, CMP until the top surface of the ILD layer 65 is exposed. In some embodiments, after the planarization operation, the metal gate electrode layer 77 is recessed and a cap insulating layer (not shown) is formed over the recessed gate electrode layer. The cap insulating layer includes one or more layers of a silicon nitride based material, such as silicon nitride. The cap insulating layer may be formed by depositing an insulating material followed by a planarization operation.

In certain embodiments of the present disclosure, one or more work function tuning layers (not shown) are interposed between the gate dielectric layer 70 and the gate electrode layer 75 . The work function adjusting layer is made of a conductive material such as a single layer of TiN, TaN, TaAlC, TiC, TaC, Co, Al, TiAl, HfTi, TiSi, TaSi or TiAlC, or multiple layers of two or more of these materials. For n-channel FETs, at least one of TaN, TaAlC, TiN, TiC, Co, TiAl, HfTi, TiSi and TaSi is used as the work function tuning layer, for p-channel FETs, TiAlC, Al, TiAl, TaN, At least one of TaAlC, TiN, TiC and Co is used as the work function adjusting layer. The work function tuning layer may be formed by ALD, PVD, CVD, e-beam deposition, or other suitable process. Further, the work function tuning layer may be formed separately for n-channel FETs and p-channel FETs, which may use different metal layers.

Also similar to FIG. 13A , a second ILD layer is formed over the first ILD layer, and conductive contacts passing through the second ILD layer or the second and first ILD layers contact the gate electrode and the source/drain epitaxial layer. formed to do As shown in Figure 13A, the fabricated FET is a thin film transistor (TFT) in some embodiments.

In another embodiment, the crystallization process stops before each front portion of the crystallized semiconductor layer 35 encounters an adjacent front portion of the crystallized semiconductor layer 35 . In this case, a portion of the non-crystallized semiconductor layer 30 remains between adjacent FETs, as shown in FIG. 36B .

It is understood that FETs undergo additional CMOS processes to form various features such as contacts/vias, interconnect metal layers, dielectric layers, passivation layers, and the like.

37 illustrates a cross-sectional view of a semiconductor device according to an embodiment of the present disclosure. As shown in FIG. 37 , an underlayer device 100 is formed over a substrate. The lower layer device 100 may include one or more fin field effect transistors (FinFETs), gate-all-around FETs (GAA FETs), planar FETs, vertical FETs, or any other electronic device. includes 37 also shows the top layer device 200 disposed over the bottom layer device 100 . In some embodiments, one or more ILD layers, metallization layers, and/or via contacts are disposed between the bottom layer device 100 and the top layer device 200 . In some embodiments, top layer device 200 includes one or more FETs fabricated by the aforementioned embodiments of the present disclosure.

The various embodiments or examples described herein provide a number of advantages over the prior art. For example, in the present disclosure, a crystallization process of the amorphous semiconductor layer is performed using a patterned seed layer formed on the amorphous semiconductor layer (top seed layer). Since the crystallization of the amorphous semiconductor layer starts from the bottom of the patterned seed layer and the patterned seed layer is used as the dummy gate, as the channel region of the FET, the initially crystallized portion with higher crystalline quality (closer to the seed layer) ) can be used. In other words, the most crystalline portion can be used as the channel region in a self-aligned manner. Further, by using the seed layer as a dummy gate for the gate replacement process, it is possible to suppress the increase in the operation steps for manufacturing the semiconductor device. The operation of the present disclosure is compatible with post-processing processes of semiconductor manufacturing.

Not all advantages are necessarily described herein, no particular advantage is required for all embodiments or examples, and it will be understood that other embodiments or examples may provide different advantages.

According to an aspect of the present disclosure, in a method of manufacturing a semiconductor device, a semiconductor layer is formed on a dielectric layer disposed over a substrate. A seed layer is formed on the semiconductor layer. The seed layer is patterned with a patterned seed layer. A crystallization operation is performed on the semiconductor layer using the patterned seed layer as a seed of crystallization, thereby forming a crystallized semiconductor layer. In one or more of the above and below embodiments, the seed layer is MgO. In one or more of the above and below embodiments, the semiconductor layer is amorphous or polycrystalline. In one or more of the above and below embodiments, the semiconductor layer is one of Si, SiGe, and Ge. In one or more of the above and below embodiments, the thickness of the seed layer is in the range of 1 nm to 10 nm. In one or more of the above and below embodiments, the thickness of the semiconductor layer is in the range of 10 nm to 50 nm. In one or more of the above and below embodiments, the crystallization operation comprises thermal annealing or laser annealing at a temperature of 350°C to 450°C. In one or more of the above and below embodiments, sidewall spacers are formed on opposite sides of the patterned seed layer. A source/drain structure is formed. An interlayer dielectric (ILD) layer is formed over the sidewall spacers, the patterned seed layer, and the source/drain structures. After the ILD layer is formed, the patterned seed layer is removed, thereby forming a gate space. A gate dielectric layer and a gate electrode layer are formed in the gate space.

According to another aspect of the present disclosure, in a method of manufacturing a semiconductor device, a semiconductor layer is formed on a dielectric layer disposed over a substrate. A seed layer is formed on the semiconductor layer. The seed layer is patterned with a patterned seed layer. A crystallization operation is performed on the semiconductor layer using the patterned seed layer as a seed of crystallization, thereby forming a crystallized semiconductor layer. In one or more of the above and below embodiments, the seed layer is MgO. In one or more of the above and below embodiments, the semiconductor layer is amorphous or polycrystalline of one of Si, SiGe, and Ge. In one or more of the above and below embodiments, the crystallization operation comprises thermal annealing or laser annealing at a temperature of 350°C to 450°C. In one or more of the above and below embodiments, sidewall spacers are formed on opposite sides of the patterned seed layer. A source/drain structure is formed. An interlayer dielectric (ILD) layer is formed over the sidewall spacers, the patterned seed layer, and the source/drain structures. After the ILD layer is formed, the patterned seed layer is removed, thereby forming a gate space. A gate dielectric layer and a gate electrode layer are formed in each gate space. In one or more of the above and below embodiments, the crystallization operation comprises: a front portion of the crystallized semiconductor layer under one of the seed layers adjacent one of the seed layers and a front portion of the crystallized semiconductor layer under the other of the seed layers , thereby forming a grain boundary. In one or more of the above and below embodiments, the crystallization operation comprises: a front portion of the crystallized semiconductor layer under one of the seed layers adjacent one of the seed layers and a front portion of the crystallized semiconductor layer under the other of the seed layers Stopped before encountering

According to another aspect of the present disclosure, in a method of manufacturing a semiconductor device, a semiconductor layer is formed on a dielectric layer disposed over a substrate. A seed layer is formed on the semiconductor layer. A dummy gate layer is formed on the seed layer. The dummy gate layer and the seed layer are formed of the patterned dummy gate layer and the patterned seed layer. A crystallization operation is performed on the semiconductor layer using the patterned seed layer as a seed of crystallization, thereby forming a crystallized semiconductor layer. In one or more of the above and below embodiments, the dummy gate layer is amorphous or polycrystalline of one of Si, SiGe, and Ge. In one or more of the above and below embodiments, the thickness of the dummy gate layer is in the range of 50 nm to 200 nm. In one or more of the above and below embodiments, the seed layer is MgO. In one or more of the above and below embodiments, sidewall spacers are formed on opposite sides of the patterned dummy gate layer and the patterned seed layer. A source/drain structure is formed. An interlayer dielectric (ILD) layer is formed over the sidewall spacers, the patterned dummy gate layer, and the source/drain structures. After the ILD layer is formed, the patterned dummy gate layer and the patterned seed layer are removed, thereby forming a gate space. A gate dielectric layer and a gate electrode layer are formed in the gate space.

According to an aspect of the present disclosure, a semiconductor device includes a channel formed as part of a semiconductor layer disposed on a dielectric layer, a gate dielectric layer disposed over the channel, a gate electrode layer disposed over the gate dielectric layer, disposed on opposite sides of the gate electrode layer. sidewall spacers, and a source and a drain. The semiconductor layer includes a crystalline portion and an amorphous portion as a channel. In one or more of the above and below embodiments, the semiconductor device further comprises one or more transistors covered by a dielectric layer. In one or more of the above and below embodiments, the one or more transistors comprise finned field effect transistors. In one or more of the above and below embodiments, the semiconductor layer is made of one of Si, SiGe, and Ge. In one or more of the above and below embodiments, the thickness of the semiconductor layer is in the range of 10 nm to 50 nm.

According to another aspect of the present disclosure, a semiconductor device includes an electronic device disposed on a substrate, one or more dielectric layers disposed over the electronic device, and a thin film transistor disposed on a top layer of the one or more dielectric layers. Each thin film transistor includes a channel formed as part of a semiconductor layer disposed on a topmost layer, a gate dielectric layer disposed over the channel, a gate electrode layer disposed over the gate dielectric layer, sidewall spacers disposed on opposite sides of the gate electrode layer, and a source and Includes drain. The semiconductor layer is single crystal, and a grain boundary exists between the semiconductor layer of one of the thin film transistors and the semiconductor layer of the other of the thin film transistors adjacent to one of the thin film transistors. In one or more of the above and below embodiments, the electronic device is a transistor. In one or more of the above and below embodiments, the transistor is one of a fin field effect transistor and a gate-all-around transistor. In one or more of the above and below embodiments, the semiconductor layer is made of one of Si, SiGe, and Ge. In one or more of the above or below embodiments, the top layer is made of silicon oxide. In one or more of the above and below embodiments, the thickness of the semiconductor layer is in the range of 10 nm to 50 nm. In one or more of the above and below embodiments, the source and drain include epitaxial semiconductor layers. In one or more of the above and below embodiments, the epitaxial semiconductor layer is in contact with one of the sidewall spacers of one of the thin film transistors and one of the sidewall spacers of the other of the thin film transistors.

According to another aspect of the present disclosure, a semiconductor device includes an electronic device disposed on a substrate, one or more dielectric layers disposed over the electronic device, and a thin film transistor disposed on a top layer of the one or more dielectric layers. Each thin film transistor includes a channel formed as part of a semiconductor layer disposed on a topmost layer, a gate dielectric layer disposed over the channel, a gate electrode layer disposed over the gate dielectric layer, sidewall spacers disposed on opposite sides of the gate electrode layer, and a source and Includes drain. The channel is single crystal, and an amorphous semiconductor layer made of the same material as the semiconductor layer exists between the semiconductor layer of one of the thin film transistors and the semiconductor layer of the other of the thin film transistors adjacent to one of the thin film transistors. In one or more of the above and below embodiments, the electronic device is a transistor. In one or more of the above and below embodiments, the transistor is one of a fin field effect transistor and a gate-all-around transistor. In one or more of the above and below embodiments, the semiconductor layer is made of one of Si, SiGe, and Ge. In one or more of the above and below embodiments, the thickness of the semiconductor layer is in the range of 10 nm to 50 nm. In one or more of the above and below embodiments, the source and drain include epitaxial semiconductor layers. In one or more of the above and below embodiments, the epitaxial semiconductor layer is in contact with one of the sidewall spacers of one of the thin film transistors and one of the sidewall spacers of the other of the thin film transistors.

The foregoing has outlined the features of a number of embodiments or examples in order that those skilled in the art may better understand aspects of the present invention. Those skilled in the art will recognize that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments or examples introduced herein. have to understand Those skilled in the art will also recognize that such equivalent constructions do not depart from the spirit and scope of the present invention, and that they may make various changes, substitutions, and modifications herein without departing from the spirit and scope of the present invention. Should be.

<Note>

1. A method of manufacturing a semiconductor device, comprising:

forming a semiconductor layer on the dielectric layer disposed over the substrate;

forming a seed layer on the semiconductor layer;

patterning the seed layer into a patterned seed layer; and

performing a crystallization operation on the semiconductor layer using the patterned seed layer as a seed of crystallization, thereby forming a crystallized semiconductor layer;

A method of manufacturing a semiconductor device comprising a.

2. The method of claim 1, wherein the seed layer is MgO.

3. The method of claim 1, wherein the semiconductor layer is amorphous or polycrystalline.

4. The method of claim 3, wherein the semiconductor layer is one of Si, SiGe and Ge.

5. The method of claim 1, wherein the thickness of the seed layer is in the range of 1 nm to 10 nm.

6. The method according to claim 1, wherein the thickness of the semiconductor layer is in the range of 10 nm to 50 nm.

7. The method of claim 1, wherein the crystallizing operation comprises thermal annealing or laser annealing at a temperature of 350°C to 450°C.

8. Item 1,

forming sidewall spacers on opposite sides of the patterned seed layer;

forming a source/drain structure;

forming an interlayer dielectric (ILD) layer over the sidewall spacers, the patterned seed layer, and the source/drain structures;

after the ILD layer is formed, removing the patterned seed layer, thereby forming a gate space; and

and forming a gate dielectric layer and a gate electrode layer in the gate space.

9. A method of manufacturing a semiconductor device, comprising:

forming an amorphous or polycrystalline semiconductor layer on the dielectric layer disposed over the substrate;

forming a seed layer on the semiconductor layer;

patterning the seed layer into a plurality of patterned seed layers; and

performing a crystallization operation on the semiconductor layer using the patterned seed layer as a seed of crystallization, thereby forming a plurality of single crystalline semiconductor layers over the dielectric layer;

A method of manufacturing a semiconductor device comprising a.

10. The method of claim 9, wherein the seed layer is MgO.

11. The method of manufacturing a semiconductor device according to claim 9, wherein the semiconductor layer is an amorphous or polycrystalline one of Si, SiGe and Ge.

12. The method of claim 9, wherein the crystallizing operation comprises thermal annealing or laser annealing at a temperature of 350°C to 450°C.

13. Item 9,

forming sidewall spacers on opposite sides of the patterned seed layer;

forming a source/drain structure;

forming an interlayer dielectric (ILD) layer over the sidewall spacers, the patterned seed layer, and the source/drain structures;

after the ILD layer is formed, removing the patterned seed layer, thereby forming a gate space; and

and forming a gate dielectric layer and a gate electrode layer within each of the gate spaces.

14. The method of clause 9, wherein the crystallization operation comprises: a front portion of a crystallized semiconductor layer under one of the seed layers adjacent to one of the seed layers; A method of manufacturing a semiconductor device, which is performed so as to encounter the front portion and thereby form a grain boundary.

15. The method of clause 9, wherein the crystallization operation comprises: a front portion of the crystallized semiconductor layer under one of the seed layers adjacent to one of the seed layers of the crystallized semiconductor layer under the other of the seed layers. A method of manufacturing a semiconductor device, wherein it is stopped before encountering the front part.

16. A semiconductor device comprising:

an electronic device disposed on the substrate;

one or more dielectric layers disposed over the electronic device; and

a thin film transistor disposed on the uppermost layer of the one or more dielectric layers

including,

Each of the thin film transistors,

a channel formed as part of a semiconductor layer disposed on the top layer;

a gate dielectric layer disposed over the channel;

a gate electrode layer disposed over the gate dielectric layer;

sidewall spacers disposed on opposite sides of the gate electrode layer; and

comprising a source and a drain;

The channel is a single crystal,

wherein a grain boundary exists between the semiconductor layer of one of the thin film transistors and the semiconductor layer of the other thin film transistor of the thin film transistor adjacent to the one of the thin film transistors. a semiconductor device.

17. The semiconductor device of clause 16, wherein the electronic device is a transistor.

18. The semiconductor device of clause 17, wherein the transistor is one of a fin field effect transistor and a gate-all-around transistor.

19. The semiconductor device of clause 16, wherein the semiconductor layer is made of one of Si, SiGe and Ge.

20. The semiconductor device of clause 16, wherein the top layer is made of silicon oxide.

Claims (10)

A method of manufacturing a semiconductor device, comprising:
forming a semiconductor layer on a dielectric layer disposed over the substrate;
forming a seed layer on the semiconductor layer;
patterning the seed layer into a patterned seed layer;
performing a crystallization operation on the semiconductor layer using the patterned seed layer as a seed of crystallization, thereby forming a crystallized semiconductor layer;
forming sidewall spacers on opposite sides of the patterned seed layer;
forming a source/drain structure;
forming an interlayer dielectric (ILD) layer over the sidewall spacers, the patterned seed layer, and the source/drain structures;
after the ILD layer is formed, removing the patterned seed layer, thereby forming a gate space; and
forming a gate dielectric layer and a gate electrode layer in the gate space;
A method of manufacturing a semiconductor device comprising a. The method of claim 1 , wherein the seed layer is MgO. The method of claim 1 , wherein the semiconductor layer is amorphous or polycrystalline. 4. The method of claim 3, wherein the semiconductor layer is one of Si, SiGe, and Ge. The method of claim 1 , wherein the thickness of the seed layer is in the range of 1 nm to 10 nm. The method of claim 1 , wherein the thickness of the semiconductor layer is in the range of 10 nm to 50 nm. The method of claim 1 , wherein the crystallization operation comprises thermal annealing or laser annealing at a temperature of 350°C to 450°C. delete A method of manufacturing a semiconductor device, comprising:
forming an amorphous or polycrystalline semiconductor layer on the dielectric layer disposed over the substrate;
forming a seed layer on the semiconductor layer;
patterning the seed layer into a plurality of patterned seed layers;
performing a crystallization operation on the semiconductor layer using the patterned seed layers as seeds of crystallization, thereby forming a plurality of single crystalline semiconductor layers over the dielectric layer;
forming sidewall spacers on opposite sides of the patterned seed layers;
forming a source/drain structure;
forming an interlayer dielectric (ILD) layer over the sidewall spacers, the patterned seed layers, and the source/drain structure;
after the ILD layer is formed, removing the patterned seed layers, thereby forming gate spaces; and
forming a gate dielectric layer and a gate electrode layer in each of the gate spaces;
A method of manufacturing a semiconductor device comprising a. A method of manufacturing a semiconductor device, comprising:
forming a semiconductor layer on the dielectric layer disposed over the substrate;
forming a seed layer on the semiconductor layer;
forming a dummy gate layer on the seed layer;
patterning the dummy gate layer and the seed layer into a patterned dummy gate layer and a patterned seed layer;
performing a crystallization operation on the semiconductor layer using the patterned seed layer as a seed of crystallization, thereby forming a crystallized semiconductor layer;
forming sidewall spacers on opposite sides of the patterned dummy gate layer and the patterned seed layer;
forming a source/drain structure;
forming an interlayer dielectric (ILD) layer over the sidewall spacers, the patterned dummy gate layer, and the source/drain structure;
after the ILD layer is formed, removing the patterned dummy gate layer and the patterned seed layer, thereby forming a gate space; and
forming a gate dielectric layer and a gate electrode layer in the gate space;
A method of manufacturing a semiconductor device comprising a.

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