KR102377788B1 - Analog-to-digital conversion apparatus and method for performing conversion in voltage domain and time domain - Google Patents

Abstract

A plurality of comparison voltages are generated by comparing a plurality of sampling signals extracted from a plurality of analog input signals with a reference voltage, and the plurality of comparison voltages are compared from the highest bit to the setting bit of the digital output signal to generate a first output signal. An analog-to-digital conversion device is provided that controls the clock signals corrected by a plurality of comparison voltages to be compared from the next bit to the least significant bit of the set bit to generate a second output signal.

Description

Analog-to-digital conversion device and method for performing conversion in voltage domain and time domain {ANALOG-TO-DIGITAL CONVERSION APPARATUS AND METHOD FOR PERFORMING CONVERSION IN VOLTAGE DOMAIN AND TIME DOMAIN}

The present invention relates to an analog-to-digital conversion device and method for performing conversion in the voltage domain and time domain, and more specifically, to an analog-to-digital conversion device and method for converting an analog signal into a digital signal.

A conventional differential Successive Approximation Register (SAR) analog-to-digital converter (ADC) has a resolution of 8 to 10 bits, and is usually lower than that of Flash ADC and Sigma-delta ADC. The level of sampling frequency and power consumption is shown.

Accordingly, when a low applied voltage is used to reduce the power consumption of the analog-to-digital converter, the voltage of 1 least significant bit (LSB) of the analog-to-digital converter is also reduced. On the other hand, since the noise inside the analog-to-digital converter circuit does not increase or decrease depending on the applied voltage, there is a disadvantage in deteriorating the resolution of the comparator.

Therefore, there is a need for a method to improve the resolution of the analog-to-digital converter at low applied voltage.

The technical problem to be solved by the present invention is to provide an analog-to-digital conversion device and method that converts some bits of a digital signal output by converting an analog signal into the voltage domain and converts some other bits into the time domain.

One aspect of the present invention includes a preprocessor that extracts each sampling signal from a plurality of analog input signals and compares each of the plurality of sampling signals with a preset reference voltage to generate a plurality of comparison voltages; a voltage comparator that compares the magnitudes of the plurality of comparison voltages; a time comparison unit that sets a plurality of delay times according to the magnitude of the plurality of comparison voltages, and corrects and compares preset clock signals according to the plurality of delay times; and controlling the voltage comparator so that a first output signal is generated by comparing the plurality of comparison voltages from the most significant bit of the digital output signal to the setting bit representing the bit of the preset digit, and the plurality of corrected clock signals are It may include a control unit that controls the time comparison unit to generate a second output signal by comparing the bit from the next bit of the set bit to the lowest bit.

In addition, the time comparator includes a voltage control delayer that sets a delay time of the clock signal according to the magnitude of a first comparison voltage and a second comparison voltage generated by comparing the plurality of sampling signals with the reference voltage; and a phase detector that compares a plurality of clock signals each corrected by the plurality of delay times.

In addition, the phase detector includes a first voltage control delay provided such that the first comparison voltage is input as a first input and the second comparison voltage is input as a second input, and the first comparison voltage is input as a second input. The second output signal can be generated according to the comparison result by comparing the waveforms of different clock signals output from a second voltage control delay device that is input and the second comparison voltage is input to the first input. there is.

In addition, the control unit controls the voltage comparator to perform comparison of the plurality of comparison voltages according to a first preset time interval, and compares the first voltage by a preset multiplier for the first time interval. The time comparison unit may be controlled to compare a plurality of clock signals each corrected by the plurality of delay times according to a second time interval that is set to be faster than the time interval.

In addition, the pre-processing unit includes a sampling switch that generates the sampling signal by fixing the values of the plurality of analog input signals appearing at an arbitrary point in time for a time interval according to a preset conversion time; and a plurality of capacitance elements representing different capacitances are provided, charging the plurality of capacitance elements according to the sampling signal and the reference voltage, and generating a comparison voltage using each capacitance element according to a preset time interval. It may include an internal converter;

Another aspect of the present invention is an analog-to-digital conversion method of an analog-to-digital conversion device that performs conversion in the voltage domain and the time domain, wherein the preprocessor extracts each sampling signal from a plurality of analog input signals, and Generating a plurality of comparison voltages by comparing each sampling signal with a preset reference voltage; Controlling the voltage comparison unit so that a first output signal is generated by comparing the plurality of comparison voltages from the most significant bit of the digital output signal to the setting bit representing the bit of the preset digit; Controlling the time comparison unit so that the control unit sets a plurality of delay times according to the magnitude of the plurality of comparison voltages and corrects each preset clock signal; and controlling the time comparison unit so that the control unit compares the plurality of corrected clock signals from the next bit to the least significant bit of the setting bit to generate a second output signal.

In addition, the step of controlling the clock signal to be corrected includes the voltage control delay delay time of the clock signal according to the magnitude of the first comparison voltage and the second comparison voltage generated by comparing the plurality of sampling signals with the reference voltage. Setting up; and comparing, by a phase detector, a plurality of clock signals each corrected by the plurality of delay times.

In addition, the step of comparing the plurality of corrected clock signals includes: a first voltage control delay provided to input the first comparison voltage as a first input and input the second comparison voltage as a second input; 1 A comparison voltage is input to the second input, and the waveforms of different clock signals output from the second voltage control delay are provided to input the second comparison voltage to the first input, and according to the comparison result, the A second output signal can be generated.

In addition, the control unit controls the voltage comparator to perform comparison of the plurality of comparison voltages according to a first preset time interval, and compares the first voltage by a preset multiplier for the first time interval. The time comparison unit may be controlled to compare a plurality of clock signals each corrected by the plurality of delay times according to a second time interval that is set to be faster than the time interval.

In addition, in the step of extracting the sampling signal and generating a comparison voltage, the sampling switch fixes the values of the plurality of analog input signals appearing at a random point in time for a time interval according to a preset conversion time to produce the sampling signal. generating a; and a plurality of capacitance elements in which internal converters exhibit different capacities are provided, charging the plurality of capacitance elements according to the sampling signal and the reference voltage, and comparing the capacitance elements using each capacitance element according to a preset time interval. It may include generating a voltage.

According to one aspect of the present invention described above, by providing an analog-to-digital conversion device and method for performing conversion in the voltage domain and the time domain, some bits of the digital signal output by converting the analog signal are converted in the voltage domain and , some other bits can be converted in the time domain.

1 is a schematic diagram of an analog-to-digital conversion device according to an embodiment of the present invention.
Figure 2 is a schematic diagram showing one embodiment of the preprocessing unit of Figure 1.
Figure 3 is a schematic diagram showing one embodiment of the voltage comparison unit of Figure 1.
Figure 4 is a schematic diagram showing one embodiment of the time comparison unit of Figure 1.
Figure 5 is a schematic diagram showing one embodiment of the voltage controlled delay of Figure 4.
Figure 6 is a schematic diagram showing one embodiment of the phase detector of Figure 4.
Figure 7 is a flowchart of an analog-to-digital conversion method according to an embodiment of the present invention.

The detailed description of the present invention described below refers to the accompanying drawings, which show by way of example specific embodiments in which the present invention may be practiced. These embodiments are described in sufficient detail to enable those skilled in the art to practice the invention. It should be understood that the various embodiments of the present invention are different from one another but are not necessarily mutually exclusive. For example, specific shapes, structures and characteristics described herein may be implemented in one embodiment without departing from the spirit and scope of the invention. Additionally, it should be understood that the location or arrangement of individual components within each disclosed embodiment may be changed without departing from the spirit and scope of the invention. Accordingly, the detailed description that follows is not intended to be taken in a limiting sense, and the scope of the invention is limited only by the appended claims, together with all equivalents to what those claims assert, if properly described. Similar reference numbers in the drawings refer to identical or similar functions across various aspects.

Hereinafter, preferred embodiments of the present invention will be described in more detail with reference to the drawings.

1 is a schematic diagram of an analog-to-digital conversion device according to an embodiment of the present invention.

The analog-to-digital conversion device 1 may include a preprocessor 100, a voltage comparator 200, a time comparator 300, and a control unit 400.

Additionally, the analog-to-digital conversion device 1 may be implemented with more components than those shown in FIG. 1 or may be implemented with fewer components. Alternatively, the analog-to-digital conversion device 1 may have at least two components provided in the analog-to-digital conversion device 1 integrated into one component, so that one component may perform a complex function. Hereinafter, the above-described components will be described in detail.

The preprocessor 100 can extract each sampling signal from a plurality of analog input signals, and the preprocessor 100 can generate a plurality of comparison voltages by comparing each of the plurality of sampling signals with a preset reference voltage. You can.

For this purpose, the preprocessor 100 may include a sampling switch 110 and an internal converter 120.

The sampling switch 110 may generate a sampling signal by fixing the values of a plurality of analog input signals that appear at an arbitrary point in time for a time interval according to a preset conversion time.

Here, the conversion time may be set as a time interval during which a digital output signal is generated according to the analog input signal input to the preprocessor 100 at any time.

In one embodiment, a plurality of analog input signals can be set to V_IN_P and V_IN_N.

In this case, the sampling switch 110 can fix the voltage input according to V_IN_P at an arbitrary point in time for a time interval according to the conversion time, and the sampling switch 110 can fix the voltage input according to V_IN_N at an arbitrary point in time. It can be fixed for a time interval depending on the conversion time.

As such, the sampling switch 110 may be a Sample and Hold switch (S/H Switch) that is provided to fix the level of the input signal for a certain time interval.

The internal converter 120 may be provided with a plurality of capacitive elements representing different capacities. Accordingly, the internal converter 120 can charge a plurality of capacitive elements according to the sampling signal and the reference voltage, and the internal converter ( 120) can generate a comparison voltage using each capacitive element according to a preset time interval.

In one embodiment, the internal converter 120 may be provided with capacitive elements of 256C, 128C, 64C, 32C, 16C, 8C, 4C, 2C, C, and C, respectively, for a plurality of analog input signals. At this time, the upper electrode of each capacitive element may be connected to an analog input signal, and the lower electrode of each capacitive element may be connected to any one of VDD, V_cm, and GND.

Here, V_cm may be an electrode provided to charge a plurality of capacitive elements. Accordingly, V_cm may be provided to appear as the potential of a reference voltage set to charge a plurality of capacitive elements.

In addition, VDD and GND may be electrodes that output either a high signal or a low signal according to the size comparison of the comparison voltage performed by the voltage comparator 200. Accordingly, VDD and GND are high signals. Alternatively, it may be arranged to appear at a potential set for a Low signal.

At this time, VDD and GND may be set to represent different signals. For example, VDD may be set to 5V, indicating a high signal, and GND may be set to 0V, indicating a low signal.

In this case, the internal converter 120 may be connected to V_cm so that a plurality of capacitive elements are charged by a sampling signal based on a preset clock signal, and at this time, the maximum chargeable value is determined according to the size of the plurality of capacitive elements. The voltage can be set as the difference between the sampling signal and the reference voltage.

Here, the clock signal may refer to a signal that is set to repeat a high signal and a low signal according to a preset time interval. At this time, the internal converter 120 may generate a plurality of signals when the clock signal is a low signal. The capacitive element may be set to charge.

Accordingly, the internal converter 120 may be set to connect the lower electrode of the first capacitor with the largest capacity to VDD based on the clock signal, and the internal converter 120 may be configured to connect the lower electrode of the first capacitor with the largest capacity to VDD. The lower electrodes of a plurality of capacitance elements, from the first capacitance element to the ninth capacitance element with the smallest capacity, can be set to be connected to GND. In this case, a comparison voltage may be generated on the upper electrodes of the plurality of capacitive elements.

At this time, the voltage comparator 200 may compare a plurality of comparison voltages (V_DAC_N and V_DAC_P) generated according to a plurality of analog input signals (V_IN_P and V_IN_N), and the internal converter 120 may compare the plurality of comparison voltages. Depending on the result, a high signal or a low signal may be connected to the lower electrode of the first capacitive element.

Here, when the clock signal is a high signal, the internal converter 120 may be set to determine the signal connected to the lower electrode of the capacitive element as a high signal or a low signal according to a plurality of comparison voltages.

Subsequently, based on the clock signal, the internal converter 120 may maintain the high signal or low signal connected to the lower electrode of the first capacitive element, and the internal converter 120 may maintain the state in which the lower electrode of the second capacitive element is connected. It can be set to be connected to VDD, and the internal converter 120 can be set to connect the lower electrodes of a plurality of capacitive elements from the third to the ninth capacitor to GND. In this case, a comparison voltage different from a previously generated comparison voltage may be generated at the top electrode of the plurality of capacitive elements.

At this time, the voltage comparator 200 may compare a plurality of comparison voltages generated according to a plurality of analog input signals, and the internal converter 120 may compare the lower electrode of the second capacitive element according to the comparison result of the plurality of comparison voltages. A high signal or a low signal can be connected to.

In the internal converter 120, this process may be repeated by the control unit 400, and accordingly, based on the clock signal of the internal converter 120, the capacitors are sequentially connected to the lower electrode of the capacitive element starting from the first capacitive element. A signal can be determined.

As such, the internal converter 120 may use a Capacitance Digital-to-Analog Converter (CDAC), which is provided to convert a digital signal into an analog signal using a capacitive element.

The voltage comparator 200 may compare the magnitudes of a plurality of comparison voltages.

In one embodiment, the voltage comparator 200 may receive a plurality of comparison voltages (V_DAC_P and V_DAC_N) based on a clock signal.

Accordingly, the voltage comparator 200 may output the first output signal as a High signal when the size of V_DAC_P among the plurality of comparison voltages (V_DAC_P and V_DAC_N) is greater than the size of V_DAC_N.

Additionally, the voltage comparator 200 may output the first output signal as a Low signal when the size of V_DAC_P among the plurality of comparison voltages (V_DAC_P and V_DAC_N) is smaller than the size of V_DAC_N.

As such, the voltage comparator 200 may use a Double-Tail Dynamic comparator that receives different signals and compares them.

The time comparator 300 can set a plurality of delay times according to the magnitude of a plurality of comparison voltages, and the time comparator 300 can respectively correct and compare preset clock signals according to the plurality of delay times. .

To this end, the time comparator 300 may include a voltage-controlled delayer 310 and a phase detector 330.

The voltage control delayer 310 may set the delay time of the clock signal according to the magnitude of the first comparison voltage and the second comparison voltage generated by comparing a plurality of sampling signals with a reference voltage.

At this time, the voltage control delay 310 may be provided with an inverter in which an arbitrary threshold voltage is set. Accordingly, the voltage control delay 310 operates when the voltage input to the inverter exceeds the threshold voltage. It can be arranged so that a low signal is output.

In one embodiment, the voltage control delay 310 is provided such that the first comparison voltage (V_DAC_P) is input to the first input (V_IN1) and the second comparison voltage (V_DAC_N) is input to the second input (V_IN2). A first voltage control delay and a second voltage control delay are provided so that the first comparison voltage (V_DAC_P) is input to the second input (V_IN2) and the second comparison voltage (V_DAC_N) is input to the first input (V_IN1). It can be.

In this case, the signal output from the first voltage controlled delay may be input to the first input (IN1) of the phase detector 330, and the signal output from the second voltage controlled delay may be input to the first input (IN1) of the phase detector 330. It can be input as the second input (IN2).

As such, the voltage-controlled delay line 310 may use a VCDL (Voltage-Controlled Delay Line) whose delay time is controlled to vary depending on the magnitude of the input voltage.

The phase detector 330 may compare a plurality of clock signals each corrected by a plurality of delay times. At this time, the phase detector 330 may generate an output signal that appears as a high signal or a low signal depending on the comparison result of the plurality of clock signals.

In one embodiment, the phase detector 330 is configured such that the first comparison voltage (V_DAC_P) is input to the first input (V_IN1) and the second comparison voltage (V_DAC_N) is input to the second input (V_IN2). Outputs from the voltage control delay and the second voltage control delay, respectively, are provided so that the first comparison voltage (V_DAC_P) is input to the second input (V_IN2) and the second comparison voltage (V_DAC_N) is input to the first input (V_IN1) The waveforms of different clock signals can be compared, and the phase detector 330 can generate a second output signal according to the comparison result.

At this time, the phase detector 330 may receive the signal output from the first voltage control delay as the first input (IN1), and the phase detector 330 may receive the signal output from the second voltage control delay as the second input. Input can be received through input (IN2).

In this case, the phase detector 330 may be set to output a high signal when the signal input to the first input (IN1) is faster than the signal input to the second input (IN2).

Meanwhile, the phase detector 330 may be set so that when the signal input to the first input IN1 or the second input IN2 is maintained, the output signal is also maintained.

As such, the phase detector 330 may use a Binary PD (Binary Phase Detector) that receives different signals, compares them, and outputs a binary signal according to the comparison result.

The control unit 400 may control the voltage comparison unit 200 so that a first output signal is generated by comparing a plurality of comparison voltages from the most significant bit of the digital output signal to a setting bit representing a bit of a preset digit, The control unit 400 may control the time comparator 300 so that the delay time is compared from the next bit of the setting bit to the least significant bit to generate a second output signal.

In one embodiment, the analog-to-digital conversion device 1 may be arranged to generate a 10-bit digital output signal for an analog input signal, and in this case, the control unit 400 controls the most significant bit (MSB: Seven bits including the Most Significant bit can be controlled to be generated as an output signal by the voltage comparison unit 200, and the control unit 400 can control three bits from the eighth bit to the least significant bit (LSB: Least Significant bit). Bits can be controlled to be generated as output signals by the time comparison unit 300.

Accordingly, the first output signal may refer to 7 bits generated by the voltage comparator 200, and the second output signal may refer to 3 bits generated by the time comparator 300. .

Meanwhile, the control unit 400 sets a time interval at which the voltage comparator 200 sets the value of each bit of the first output signal to be generated and the time comparison unit 300 generates the value of each bit of the second output signal. The set time interval can be controlled differently.

In one embodiment, the control unit 400 may control the voltage comparison unit to perform comparison of a plurality of comparison voltages according to a preset first time interval, and the control unit 400 may control the voltage comparison unit to perform comparison of a plurality of comparison voltages according to a preset first time interval. The time comparator 300 can be controlled to perform comparison of a plurality of clock signals each corrected by a plurality of delay times according to a second time interval that is set to be faster than the first time interval by a multiplier set in . .

In this case, the first time interval can be set to appear 3 times the time interval relative to the second time interval, or the second time interval may be set to appear 1/3 the time interval relative to the first time interval. It can be set to:

As such, the control unit 400 may be a SAR Logic designed to control a differential Successive Approximation Register (SAR) that sequentially performs comparison of arbitrary values from the most significant bit.

Through these components, the analog-to-digital conversion device (1) can operate at a low applied voltage of 0.6V. Additionally, the analog-to-digital conversion device (1) operates at a low applied voltage. This may result in improved noise characteristics.

Figure 2 is a schematic diagram showing one embodiment of the preprocessing unit of Figure 1.

The preprocessor 100 can extract each sampling signal from a plurality of analog input signals, and the preprocessor 100 can generate a plurality of comparison voltages by comparing each of the plurality of sampling signals with a preset reference voltage. You can.

The sampling switch 110 may generate a sampling signal by fixing the values of a plurality of analog input signals that appear at an arbitrary point in time for a time interval according to a preset conversion time.

At this time, a plurality of analog input signals input to the sampling switch 110 may be set to V_IN_P and V_IN_N.

The internal converter 120 may be provided with a plurality of capacitive elements representing different capacities. Accordingly, the internal converter 120 can charge a plurality of capacitive elements according to the sampling signal and the reference voltage, and the internal converter ( 120) can generate a comparison voltage using each capacitive element according to a preset time interval.

At this time, the internal converter 120 may be provided with capacitive elements of 256C, 128C, 64C, 32C, 16C, 8C, 4C, 2C, C, and C for a plurality of analog input signals, respectively. At this time, the upper electrode of each capacitive element may be connected to an analog input signal, and the lower electrode of each capacitive element may be connected to any one of VDD, V_cm, and GND.

In this case, the internal converter 120 may be connected to V_cm so that a plurality of capacitive elements are charged by a sampling signal based on a preset clock signal, and at this time, the maximum chargeable value is determined according to the size of the plurality of capacitive elements. The voltage can be set as the difference between the sampling signal and the reference voltage.

Accordingly, the internal converter 120 may be set to connect the lower electrode of the first capacitor with the largest capacity to VDD based on the clock signal, and the internal converter 120 may be configured to connect the lower electrode of the first capacitor with the largest capacity to VDD. The lower electrodes of a plurality of capacitance elements, from the first capacitance element to the ninth capacitance element with the smallest capacity, can be set to be connected to GND. In this case, a comparison voltage may be generated on the upper electrodes of the plurality of capacitive elements.

At this time, the voltage comparator 200 may compare a plurality of comparison voltages (V_DAC_N and V_DAC_P) generated according to a plurality of analog input signals (V_IN_P and V_IN_N), and the internal converter 120 may compare the plurality of comparison voltages. Depending on the result, a high signal or a low signal may be connected to the lower electrode of the first capacitive element.

Subsequently, based on the clock signal, the internal converter 120 may maintain the high signal or low signal connected to the lower electrode of the first capacitive element, and the internal converter 120 may maintain the state in which the lower electrode of the second capacitive element is connected. It can be set to be connected to VDD, and the internal converter 120 can be set to connect the lower electrodes of a plurality of capacitive elements from the third to the ninth capacitor to GND. In this case, a comparison voltage different from a previously generated comparison voltage may be generated at the top electrode of the plurality of capacitive elements.

At this time, the voltage comparator 200 may compare a plurality of comparison voltages generated according to a plurality of analog input signals, and the internal converter 120 may compare the lower electrode of the second capacitive element according to the comparison result of the plurality of comparison voltages. A high signal or a low signal can be connected to.

In the internal converter 120, this process may be repeated by the control unit 400, and accordingly, based on the clock signal of the internal converter 120, the capacitors are sequentially connected to the lower electrode of the capacitive element starting from the first capacitive element. A signal can be determined.

Figure 3 is a schematic diagram showing one embodiment of the voltage comparison unit of Figure 1.

The voltage comparator 200 may compare the magnitudes of a plurality of comparison voltages. At this time, the voltage comparator 200 may receive a plurality of comparison voltages (V_DAC_P and V_DAC_N) based on the clock signal.

In this regard, the voltage comparator 200 may charge the voltages of the fp node and fn node to VDD by the M3 transistor and the M4 transistor when the negative value (Not_CLK) of the clock signal is a low signal. In this case, the voltage comparator 200 may output a Low signal.

Meanwhile, in the voltage comparator 200, when the negative value (Not_CLK) of the clock signal is a high signal, the Mtail1 transistor and the Mtail2 transistor may be energized, and the M3 transistor and M4 transistor may be blocked.

Accordingly, the voltage comparison unit 200 may generate a difference in the amount of voltage change between the fp node and the fn node depending on the first comparison voltage (V_DAC_P) and the second comparison voltage (V_DAC_N), and the voltage comparison unit 200 may generate a difference in the amount of voltage change between the fp node and the fn node. The difference in voltage change between the node and the fn node can be output through a cross-coupled inverter that includes the M6 transistor, M7 transistor, M9 transistor, and M10 transistor.

For example, when the first comparison voltage (V_DAC_P) is greater than the second comparison voltage (V_DAC_N), the voltage comparator 200 may reduce the fn node voltage faster than the fp node voltage, and accordingly, Accordingly, the voltage comparison unit 200 increases the size of the current flowing in the M5 transistor compared to the size of the current flowing in the M8 transistor, so the output (OUT) by the cross-coupled inverter may appear as a high signal, and the output may be negative. The value (Not_OUT) may appear as a Low signal.

In this Double-Tail Dynamic comparator, the VDD line is divided into two stages and connected to each stage, so it can operate at a lower applied voltage.

Figure 4 is a schematic diagram showing one embodiment of the time comparison unit of Figure 1.

The time comparator 300 can set a plurality of delay times according to the magnitude of a plurality of comparison voltages, and the time comparator 300 can respectively correct and compare preset clock signals according to the plurality of delay times. .

To this end, the time comparator 300 may include a voltage-controlled delayer 310 and a phase detector 330.

The voltage control delayer 310 may set the delay time of the clock signal according to the magnitude of the first comparison voltage and the second comparison voltage generated by comparing a plurality of sampling signals with a reference voltage.

At this time, the voltage control delay 310 is provided so that the first comparison voltage (V_DAC_P) is input to the first input (V_IN1) and the second comparison voltage (V_DAC_N) is input to the second input (V_IN2). The control delay and the first comparison voltage (V_DAC_P) are input to the second input (V_IN2), and the second comparison voltage (V_DAC_N) is input to the first input (V_IN1). It may be provided with a second voltage control delay. .

Additionally, the phase detector 330 may compare a plurality of clock signals each corrected by a plurality of delay times.

Figure 5 is a schematic diagram showing one embodiment of the voltage controlled delay of Figure 4.

The voltage control delayer 310 may set the delay time of the clock signal according to the magnitude of the first comparison voltage (V_DAC_P) and the second comparison voltage (V_DAC_N) generated by comparing a plurality of sampling signals with a reference voltage.

At this time, the voltage control delay 310 is provided so that the first comparison voltage (V_DAC_P) is input to the first input (V_IN1) and the second comparison voltage (V_DAC_N) is input to the second input (V_IN2). The control delay and the first comparison voltage (V_DAC_P) are input to the second input (V_IN2), and the second comparison voltage (V_DAC_N) is input to the first input (V_IN1). It may be provided with a second voltage control delay. .

In this case, the signal output from the first voltage control delay may be input to the first input (IN1) of the phase detector 330, and the signal output from the second voltage control delay may be input to the first input (IN1) of the phase detector 330. It can be input as the second input (IN2).

In this regard, the change in delay time of the voltage-controlled delayer 310 can be expressed using Equations 1 to 8 below.

In Equations 1 to 8, t_d is the time interval until the voltage V_OUT output from the voltage control delay 310 reaches the threshold voltage of the inverter of the voltage control delay 310. It can mean, and I_SS can mean the current flowing in the inverter of the voltage control delay 310 in the steady-state.

Additionally, C_L may mean the size of the capacitance element set in the equivalent circuit corresponding to one stage of the circuit of the voltage controlled delay 310.

Meanwhile, t_d_diff is the time when the voltage (V_OUT) output from the voltage control delay 310, which receives a plurality of comparison signals, which are differential signals, reaches the threshold voltage of the inverter of the voltage control delay 310. It may mean a time interval, and Delta_V_IN may mean the difference between a plurality of comparison voltages. Additionally, g_m may refer to the mutual conductance of the transistor set in the equivalent circuit corresponding to one stage of the circuit of the voltage controlled delay 310.

Additionally, Gain may refer to the voltage-time gain of the voltage control delay 310. Accordingly, Gain_N may mean the voltage-time gain that appears from the voltage control delay 310 when an arbitrary number of N stages are provided in the circuit of the voltage control delay 310. there is.

In this regard, Delta_V_out^2 may refer to the change rate of the voltage (V_OUT) output from the voltage control delay 310 due to noise, alpha may refer to a constant set in advance, and kT may refer to the temperature. It can mean.

Additionally, slew rate may refer to a variable representing the response speed of the voltage control delay device 310.

Accordingly, the change in delay time of the clock signal passing through one stage of the circuit of the voltage-controlled delayer 310 can be expressed as Delta_t_d in Equation 7, where the The change in delay time of the clock signal passing through N stages can be expressed as Delta_t_d_N in Equation 8.

Meanwhile, the input noise of the voltage controlled delay 310 may be expressed as shown in Equation 9 below.

Here, Delta_V_noise may mean the input noise of the voltage control delay 310.

In this way, the voltage control delay 310 can have the effect of reducing the influence of input noise by root_N times depending on the number of stages of the voltage control delay 310 circuit.

For example, if the voltage control delay 310 circuit has 5 stages, the influence of input noise can be reduced by 5 times.

Figure 6 is a schematic diagram showing one embodiment of the phase detector of Figure 4.

The phase detector 330 may compare a plurality of clock signals each corrected by a plurality of delay times. At this time, the phase detector 330 may generate an output signal that appears as a high signal or a low signal depending on the comparison result of the plurality of clock signals.

The phase detector 330 includes a first voltage control delay and a first comparison voltage (V_DAC_P) provided to input the first comparison voltage (V_DAC_P) to the first input (V_IN1) and the second comparison voltage (V_DAC_N) to be input to the second input (V_IN2) 1 Different clock signals output from a second voltage control delay device provided such that the comparison voltage (V_DAC_P) is input to the second input (V_IN2) and the second comparison voltage (V_DAC_N) is input to the first input (V_IN1) The waveforms of can be compared, and the phase detector 330 can generate a second output signal according to the comparison result.

At this time, the phase detector 330 may receive the signal output from the first voltage control delay as the first input (IN1), and the phase detector 330 may receive the signal output from the second voltage control delay as the second input. Input can be received through input (IN2).

In this case, the phase detector 330 may be set to output a high signal when the signal input to the first input (IN1) is faster than the signal input to the second input (IN2).

Meanwhile, the phase detector 330 may be set so that when the signal input to the first input (IN1) or the second input (IN2) is maintained, the output signal is also maintained.

Figure 7 is a flowchart of an analog-to-digital conversion method according to an embodiment of the present invention.

The analog-to-digital conversion method according to an embodiment of the present invention is carried out on substantially the same configuration as the analog-to-digital conversion device 1 shown in FIG. 1, and therefore has the same configuration as the analog-to-digital conversion device 1 of FIG. The same reference numerals will be assigned to elements, and repeated descriptions will be omitted.

The analog-to-digital conversion method includes the steps of extracting a sampling signal and generating a comparison voltage (600), controlling the first output signal to be generated (610), controlling the clock signal to be corrected (620), and controlling the second output signal to be corrected (620). A step 630 of controlling an output signal to be generated may be included.

In the step 600 of extracting a sampling signal and generating a comparison voltage, the preprocessor 100 extracts each sampling signal from a plurality of analog input signals and compares each of the plurality of sampling signals with a preset reference voltage. This may be a step of generating a plurality of comparison voltages.

In the step 610 of controlling the first output signal to be generated, the control unit 400 compares a plurality of comparison voltages from the most significant bit of the digital output signal to the setting bit indicating the bit of the preset digit to generate the first output signal. This may be a step of controlling the voltage comparator 200 to generate voltage.

In the step 620 of controlling the clock signal to be corrected, the control unit 400 sets a plurality of delay times according to the magnitude of the plurality of comparison voltages and controls the time comparator 300 so that each of the preset clock signals is corrected. This may be a step.

In the control step 630 to generate a second output signal, the control unit 400 compares the plurality of corrected clock signals from the next bit to the least significant bit of the set bit to generate a second output signal. ) may be a control step.

Although the above has been described with reference to embodiments, those skilled in the art will understand that various modifications and changes can be made to the present invention without departing from the spirit and scope of the present invention as set forth in the following patent claims. You will be able to.

1: Analog-to-digital conversion device
100: Preprocessing unit
110: sampling switch
130: internal converter
200: voltage comparison unit
300: Time comparison unit
310: Voltage controlled delayer
330: phase detector
400: Control unit

Claims (10)

a preprocessor that extracts each sampling signal from a plurality of analog input signals and compares each of the plurality of sampling signals with a preset reference voltage to generate a plurality of comparison voltages;
a voltage comparator that compares the magnitudes of the plurality of comparison voltages;
a time comparison unit that sets a plurality of delay times according to the magnitude of the plurality of comparison voltages, and corrects and compares preset clock signals according to the plurality of delay times; and
The voltage comparator is controlled to generate a first output signal by comparing the plurality of comparison voltages from the most significant bit of the digital output signal to the setting bit representing the bit of the preset digit, and the plurality of corrected clock signals are compared to the setting bit. An analog-to-digital conversion device comprising: a control unit that controls the time comparison unit to generate a second output signal by comparing bits from the next bit to the least significant bit.
The method of claim 1, wherein the time comparison unit,
a voltage control delayer that sets a delay time of the clock signal according to the magnitude of a first comparison voltage and a second comparison voltage generated by comparing the plurality of sampling signals with the reference voltage; and
An analog-to-digital conversion device comprising a phase detector that compares a plurality of clock signals each corrected by the plurality of delay times.
The method of claim 2, wherein the phase detector is:
A first voltage control delay provided to input the first comparison voltage as a first input and input the second comparison voltage as a second input, and to input the first comparison voltage as a second input, and to input the second comparison voltage as a second input. An analog-to-digital conversion device that compares the waveforms of different clock signals output from a second voltage control delay device provided to input a voltage as a first input, and generates the second output signal according to the comparison result.
The method of claim 1, wherein the control unit:
Controls the voltage comparator to perform comparison of the plurality of comparison voltages according to a preset first time interval, and sets the voltage comparator to be faster than the first time interval by a preset multiplier for the first time interval. An analog-to-digital conversion device that controls the time comparator to perform comparison of a plurality of clock signals each corrected by the plurality of delay times according to a second time interval.
The method of claim 1, wherein the preprocessing unit,
a sampling switch that generates the sampling signal by fixing the values of the plurality of analog input signals appearing at an arbitrary point in time for a time interval according to a preset conversion time; and
A plurality of capacitance elements representing different capacitances are provided, the plurality of capacitance elements are charged according to the sampling signal and the reference voltage, and a comparison voltage is generated using each capacitance element according to a preset time interval. An analog-to-digital conversion device comprising an internal converter.
In the analog-to-digital conversion method of an analog-to-digital conversion device that performs conversion in the voltage domain and time domain,
A preprocessor extracting each sampling signal from a plurality of analog input signals and comparing each of the plurality of sampling signals with a preset reference voltage to generate a plurality of comparison voltages;
Controlling the voltage comparison unit so that the plurality of comparison voltages are compared from the most significant bit of the digital output signal to the setting bit representing the bit of the preset digit to generate a first output signal;
Controlling the time comparison unit, by the control unit, to correct each preset clock signal using a plurality of delay times set according to the magnitudes of the plurality of comparison voltages; and
The control unit controls the time comparison unit to generate a second output signal by comparing the plurality of corrected clock signals from the next bit to the least significant bit of the setting bit.
The method of claim 6, wherein controlling the clock signal to be corrected comprises:
setting, by a voltage control delayer, a delay time of the clock signal according to the magnitude of a first comparison voltage and a second comparison voltage generated by comparing the plurality of sampling signals with the reference voltage; and
Comprising a phase detector comparing a plurality of clock signals each corrected by the plurality of delay times.
The method of claim 7, wherein comparing the plurality of corrected clock signals comprises:
A first voltage control delay provided to input the first comparison voltage as a first input and input the second comparison voltage as a second input, and to input the first comparison voltage as a second input, and to input the second comparison voltage as a second input. An analog-to-digital conversion method that compares the waveforms of different clock signals output from a second voltage control delay device provided to input a voltage as a first input, and generates the second output signal according to the comparison result.
The method of claim 6, wherein the control unit,
Controls the voltage comparator to perform comparison of the plurality of comparison voltages according to a preset first time interval, and sets the voltage comparator to be faster than the first time interval by a preset multiplier for the first time interval. An analog-to-digital conversion method that controls the time comparator to perform comparison of a plurality of clock signals each corrected by the plurality of delay times according to a second time interval.
The method of claim 6, wherein extracting the sampling signal and generating a comparison voltage comprises:
A sampling switch generating the sampling signal by fixing the values of the plurality of analog input signals that appear at a random point in time for a time interval according to a preset conversion time; and
An internal converter having a plurality of capacitance elements representing different capacitances charged according to the sampling signal and the reference voltage generates a comparison voltage using each capacitance element according to a preset time interval. Analog-digital conversion method.

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