KR102374841B1 - Variable voltage generation circuit and memory device including the same - Google Patents

Abstract

The variable voltage generating circuit includes a first amplifying circuit and a second amplifying circuit. The first amplifying circuit is configured to provide a first amplification circuit according to a change in the operating temperature based on a reference voltage, a first feedback voltage, a temperature-variable voltage that varies according to the operating temperature, and a temperature-fixed voltage that is fixed regardless of the operating temperature. and generate a first output voltage varying in a voltage range, and generate the first feedback voltage based on the first output voltage. The second amplifier circuit is configured to operate in a second voltage range greater than the first voltage range according to a change in the operating temperature based on the first feedback voltage, the second feedback voltage, the temperature-varying voltage and the temperature-fixed voltage. and generate a varying second output voltage and generate the second feedback voltage based on the second output voltage.

Description

VARIABLE VOLTAGE GENERATION CIRCUIT AND MEMORY DEVICE INCLUDING THE SAME

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit, and more particularly, to a variable voltage generator circuit for generating a voltage that varies according to temperature, and a memory device including the same.

Recently, as semiconductor integrated circuits such as memory devices are highly integrated and high-speed, operating characteristics of semiconductor integrated circuits tend to be sensitively changed with respect to changes in operating temperature. In order to prevent malfunction of the semiconductor integrated circuit and improve performance, it is necessary to precisely control the operation of the semiconductor integrated circuit according to the change in operating temperature.

SUMMARY OF THE INVENTION One object of the present invention to solve the above problems is to provide a variable voltage generating circuit having a wide output voltage range with respect to an operating temperature range.

Another object of the present invention is to provide a memory device including a variable voltage generating circuit having a wide output voltage range with respect to an operating temperature range.

In order to achieve the above object, a variable voltage generating circuit according to embodiments of the present invention includes a first amplifying circuit and a second amplifying circuit. The first amplifying circuit is configured to provide a first amplification circuit according to a change in the operating temperature based on a reference voltage, a first feedback voltage, a temperature-variable voltage that varies according to the operating temperature, and a temperature-fixed voltage that is fixed regardless of the operating temperature. and generate a first output voltage varying in a voltage range, and generate the first feedback voltage based on the first output voltage. The second amplifier circuit is configured to operate in a second voltage range greater than the first voltage range according to a change in the operating temperature based on the first feedback voltage, the second feedback voltage, the temperature-varying voltage and the temperature-fixed voltage. and generate a varying second output voltage and generate the second feedback voltage based on the second output voltage.

In an exemplary embodiment, the first amplifier circuit comprises a differential input terminal pair for receiving the reference voltage and the first feedback voltage, and the second amplifier circuit comprises the first feedback voltage and the second feedback voltage. It may include a differential input terminal pair for receiving.

In an exemplary embodiment, each of the first amplification circuit and the second amplification circuit may further include a differential input terminal pair for receiving the temperature-variable voltage and the temperature-fixed voltage.

In an exemplary embodiment, the first amplifying circuit generates a first voltage offset corresponding to a difference between the reference voltage and the first feedback voltage based on the temperature-varying voltage, and the second amplifying circuit comprises the A second voltage offset corresponding to a difference between the first feedback voltage and the second feedback voltage may be generated based on the temperature-varying voltage.

In an exemplary embodiment, the first voltage range may be proportional to the first voltage offset, and the second voltage range may be proportional to a sum of the first voltage offset and the second voltage offset.

In an exemplary embodiment, the first amplifier circuit and the second amplifier circuit may have the same configuration, and the second voltage range may be twice the first voltage range.

In an exemplary embodiment, the first amplifying circuit is a first differential amplifier providing a first amplified voltage based on the reference voltage, the first feedback voltage, the temperature-variable voltage, and the temperature-fixed voltage. and a first output circuit providing the first output voltage and the first feedback voltage proportional to the first output voltage based on the first amplified voltage.

In an exemplary embodiment, the first differential difference amplifier comprises: a current mirror coupled to an output node pair generating the first amplified voltage, coupled to the output node pair and receiving the reference voltage and the first feedback voltage a first pair of input transistors coupled to the pair of output nodes and receiving the temperature-varying voltage and the temperature-fixed voltage, a first current source coupled to the first pair of input transistors and the second and a second current source coupled to the pair of input transistors.

In an exemplary embodiment, the second current source may adjust the first voltage range by adjusting a tail current supplied to the second input transistor pair in response to a temperature coefficient signal.

In an exemplary embodiment, the second amplification circuit is a second differential providing a second amplification voltage based on the first feedback voltage, the second feedback voltage, the temperature-variable voltage, and the temperature-fixed voltage. and a second output circuit configured to provide the second output voltage and the second feedback voltage proportional to the second output voltage based on a difference amplifier and the second amplified voltage.

In an exemplary embodiment, the second differential difference amplifier comprises: a current mirror coupled to an output node pair generating the second amplified voltage, coupled to the output node pair, the first feedback voltage and the second feedback voltage a first pair of input transistors receiving and a second current source coupled to the second pair of input transistors.

In an exemplary embodiment, the second current source may adjust the second voltage range by adjusting a tail current supplied to the second input transistor pair in response to a temperature coefficient signal.

In an exemplary embodiment, the variable voltage generating circuit is configured to configure the second voltage range according to a change in the operating temperature based on the second feedback voltage, the third feedback voltage, the temperature-variable voltage and the temperature-fixed voltage. The apparatus may further include a third amplifying circuit configured to generate a third output voltage that varies in a larger third voltage range, and to generate the third feedback voltage based on the third output voltage.

In an exemplary embodiment, the first amplifier circuit comprises a differential input terminal pair for receiving the reference voltage and the first feedback voltage, and the second amplifier circuit comprises the first feedback voltage and the second feedback voltage. and a differential input terminal pair for receiving , and the third amplifier circuit may include a differential input terminal pair for receiving the second feedback voltage and the third feedback voltage.

In an exemplary embodiment, the first amplifying circuit, the second amplifying circuit and the third amplifying circuit have the same configuration, the second voltage range is twice the first voltage range, and the third voltage range may be three times the first voltage range.

In order to achieve the above object, a variable voltage generating circuit according to embodiments of the present invention includes first to nth amplification circuits. The first amplifying circuit is configured to provide a first amplification circuit according to a change in the operating temperature based on a reference voltage, a first feedback voltage, a temperature-variable voltage that varies according to the operating temperature, and a temperature-fixed voltage that is fixed regardless of the operating temperature. and generate a first output voltage varying in a voltage range, and generate the first feedback voltage based on the first output voltage. The k-th amplifier circuit (k is a natural number of 2 or more and n or less) is configured to perform a second operation according to a change in the operating temperature based on a k-1 th feedback voltage, a k-th feedback voltage, the temperature-variable voltage, and the temperature-fixed voltage. A k-th output voltage that varies in a k-th voltage range greater than a k-1 voltage range is generated, and the k-th feedback voltage is generated based on the k-th output voltage.

In an exemplary embodiment, the first amplification circuit includes a differential input terminal pair for receiving the reference voltage and the first feedback voltage, and the kth amplifier circuit comprises the k-1th feedback voltage and the kth feedback voltage. and a differential input terminal pair for receiving a feedback voltage.

In an exemplary embodiment, the first to nth amplifier circuits may have the same configuration, and the kth voltage range may be k times the first voltage range.

In an exemplary embodiment, the variable voltage generating circuit may further include a selector for selecting and outputting one of the first to nth output voltages.

In order to achieve the above object, a memory device according to embodiments of the present invention includes first to nth amplification circuits and a memory cell array. The first amplifying circuit is configured to provide a first amplification circuit according to a change in the operating temperature based on a reference voltage, a first feedback voltage, a temperature-variable voltage that varies according to the operating temperature, and a temperature-fixed voltage that is fixed regardless of the operating temperature. and generate a first output voltage varying in a voltage range, and generate the first feedback voltage based on the first output voltage. The k-th amplifier circuit (k is a natural number of 2 or more and n or less) is configured to perform a second operation according to a change in the operating temperature based on a k-1 th feedback voltage, a k-th feedback voltage, the temperature-variable voltage, and the temperature-fixed voltage. A k-th output voltage that varies in a k-th voltage range greater than a k-1 voltage range is generated, and the k-th feedback voltage is generated based on the k-th output voltage. The memory cell array is driven based on at least one of the first to nth output voltages.

The variable voltage generating circuit according to the embodiments of the present invention expands the range of the output voltage with respect to the operating temperature range through a plurality of feedback operations using a plurality of amplification circuits having a voltage offset according to the temperature, and provides linearity. can improve

Memory devices according to embodiments of the present invention may have improved performance by precisely controlling operating characteristics of the memory device according to changes in operating temperature using the output voltage of the variable voltage generating circuit.

1 is a block diagram illustrating a variable voltage generating circuit according to embodiments of the present invention.
FIG. 2 is a diagram illustrating an example of a temperature-variable voltage and a temperature-fixed voltage provided to the variable voltage generating circuit of FIG. 1 .
3 is a diagram illustrating an example of a voltage range according to a temperature change of the variable voltage generator circuit of FIG. 1 .
FIG. 4 is a diagram illustrating another example of a temperature-variable voltage and a temperature-fixed voltage provided to the variable voltage generating circuit of FIG. 1 .
5 is a diagram illustrating another example of a voltage range according to a temperature change of the variable voltage generator circuit of FIG. 1 .
6 is a diagram illustrating an embodiment of a first amplifying circuit included in the variable voltage generating circuit of FIG. 1 .
7 is a diagram illustrating an embodiment of a second amplification circuit included in the variable voltage generator circuit of FIG. 1 .
8 is a diagram illustrating an embodiment of a third amplification circuit included in the variable voltage generator circuit of FIG. 1 .
9 is a diagram illustrating an embodiment of a first differential difference amplifier included in the first amplifier circuit of FIG. 6 .
FIG. 10 is a diagram for explaining control of a first output voltage of the first differential amplifier of FIG. 9 according to a temperature coefficient;
11 is a diagram illustrating a tail current of a second current source included in the first differential amplifier of FIG. 9 according to a temperature coefficient;
12 is a diagram illustrating an embodiment of a second differential amplifier included in the second amplifier circuit of FIG. 7 .
13 is a diagram illustrating an embodiment of a third differential difference amplifier included in the third amplifier circuit of FIG. 8 .
14 is a block diagram illustrating a variable voltage generating circuit according to embodiments of the present invention.
15 is a block diagram illustrating a digital thermometer according to embodiments of the present invention.
16 is a circuit diagram illustrating an example of a temperature sensor included in the digital thermometer of FIG. 15 .
17 is a block diagram illustrating a clock generator according to embodiments of the present invention.
18 is a diagram illustrating an example of a voltage controlled oscillator included in the clock generator of FIG. 17 .
19 is a diagram illustrating an example of an inverter included in the voltage controlled oscillator of FIG. 18 .
20 is a block diagram illustrating a memory device according to embodiments of the present invention.
21, 22, 23, and 24 are diagrams illustrating examples of a memory cell array included in the nonvolatile memory device of FIG. 20 .
25 is a block diagram illustrating a solid state disk or solid state drive (SSD) according to embodiments of the present invention.
26 is a block diagram illustrating an embedded multimedia card (eMMC) according to embodiments of the present invention.
27 is a block diagram illustrating a universal flash storage (USF) according to embodiments of the present invention.
28 is a block diagram illustrating a mobile device according to embodiments of the present invention.

With respect to the embodiments of the present invention disclosed in the text, specific structural or functional descriptions are only exemplified for the purpose of describing the embodiments of the present invention, and the embodiments of the present invention may be embodied in various forms and the text It should not be construed as being limited to the embodiments described in .

Since the present invention can have various changes and can have various forms, specific embodiments are illustrated in the drawings and described in detail in the text. However, this is not intended to limit the present invention to the specific disclosed form, it should be understood to include all modifications, equivalents and substitutes included in the spirit and scope of the present invention.

Terms such as first, second, etc. may be used to describe various elements, but the elements should not be limited by the terms. The above terms may be used for the purpose of distinguishing one component from another. For example, without departing from the scope of the present invention, a first component may be referred to as a second component, and similarly, a second component may also be referred to as a first component.

When an element is referred to as being “connected” or “connected” to another element, it is understood that it may be directly connected or connected to the other element, but other elements may exist in between. it should be On the other hand, when it is said that a certain element is "directly connected" or "directly connected" to another element, it should be understood that the other element does not exist in the middle. Other expressions describing the relationship between elements, such as "between" and "immediately between" or "neighboring to" and "directly adjacent to", etc., should be interpreted similarly.

The terms used in the present application are only used to describe specific embodiments, and are not intended to limit the present invention. The singular expression includes the plural expression unless the context clearly dictates otherwise. In the present application, terms such as “comprise” or “have” are intended to designate that the described feature, number, step, operation, component, part, or combination thereof exists, but is not limited to one or more other features or numbers. , it is to be understood that it does not preclude the possibility of the existence or addition of steps, operations, components, parts, or combinations thereof.

Unless defined otherwise, all terms used herein, including technical and scientific terms, have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs. Terms such as those defined in commonly used dictionaries should be interpreted to have meanings consistent with the context of the related art, and are not to be interpreted in an ideal or excessively formal meaning unless explicitly defined in the present application. .

Hereinafter, preferred embodiments of the present invention will be described in more detail with reference to the accompanying drawings. The same reference numerals are used for the same components in the drawings, and repeated descriptions of the same components are omitted.

1 is a block diagram illustrating a variable voltage generating circuit according to embodiments of the present invention.

Referring to FIG. 1 , the variable voltage generating circuit 100 includes first to nth amplification circuits AMP1 to AMPn.

The first amplifier circuit AMP1 includes a reference voltage VREF, a first feedback voltage VFB1, a temperature-varying voltage VNTC that varies according to an operating temperature, and a fixed temperature-fixed voltage VZTC regardless of the operating temperature. ), a first output voltage VO1 that changes in the first voltage range VR1 is generated according to a change in the operating temperature. The first amplifier circuit AMP1 generates a first feedback voltage VFB1 based on the first output voltage VO1 .

The k-th amplifier circuit AMPk (k is a natural number of 2 or more and n or less) includes a k-1th feedback voltage VFBk-1, a kth feedback voltage VFBk, a temperature-variable voltage VNTC, and a temperature-fixed voltage. Based on (VZTC), a kth output voltage VOk that varies in a kth voltage range VRk greater than the k−1th voltage range VRk−1 is generated according to a change in the operating temperature. The kth amplifier circuit AMPk generates the kth feedback voltage VFBk based on the kth output voltage VOk.

In other words, the second amplifying circuit AMP2 changes the operating temperature based on the first feedback voltage VFB1 , the second feedback voltage VFB2 , the temperature-variable voltage VNTC and the temperature-fixed voltage VZTC. Accordingly, the second output voltage VO2 that changes in the second voltage range VR2 greater than the first voltage range VR1 is generated, and the second feedback voltage VFB2 is generated based on the second output voltage VO2. Occurs. The third amplifying circuit AMP is configured to perform a first operation according to a change in the operating temperature based on the second feedback voltage VFB2 , the third feedback voltage VFB3 , the temperature-variable voltage VNTC and the temperature-fixed voltage VZTC. The third output voltage VO3 that is changed in the third voltage range VR3 greater than the second voltage range VR2 is generated, and the third feedback voltage VFB3 is generated based on the third output voltage VO3 . In this way, the n-th amplifier circuit AMPn is based on the n-1 th feedback voltage VFBn-1, the n th feedback voltage VFBn, the temperature-variable voltage VNTC, and the temperature-fixed voltage VZTC. to generate an n-th output voltage VOn that changes in an n-th voltage range VRn greater than an n-1 voltage range VRn-1 according to a change in the operating temperature, and Based on the n-th feedback voltage VFBn is generated.

As will be described later, each of the amplification circuits AMP1 to AMPn has a voltage offset according to temperature. According to embodiments of the present invention, the feedback voltage VFBk-1 of the amplifying circuit AMPk-1 of the preceding stage is provided as a reference voltage of the amplifying circuit AMPk of the subsequent stage. By performing differential amplification using the feedback voltage VFBk-1 of the amplification circuit AMPk-1 of the previous stage, the voltage offset can be accumulated as it goes to the amplification circuit of the rear stage. It is possible to extend the range of the output voltage for the range.

Conventionally, the amplified voltage is used by amplifying the temperature-varying voltage (VNTC) using a single variable gain amplifier to extend the temperature range and improve linearity. However, as will be described later with reference to FIG. 11 , when the current is monotonically increased using one variable gain amplifier, linearity is not guaranteed.

The variable voltage generating circuit 100 according to the embodiments of the present invention provides an output voltage for a range of operating temperature through a plurality of feedback operations using a plurality of amplification circuits AMP1 to AMPn having a voltage offset according to temperature. It is possible to extend the range of , and improve the linearity.

2 is a diagram illustrating an example of a temperature-variable voltage and a temperature-fixed voltage provided to the variable voltage generating circuit of FIG. 1 , and FIG. 3 is an example of a voltage range according to a temperature change of the variable voltage generator circuit of FIG. 1 It is a drawing showing

Referring to FIG. 2 , the temperature-varying voltage VNTC may have a voltage level that varies according to an operating temperature. For example, the temperature-varying voltage VNTC may increase as the operating temperature increases. That is, as shown in FIG. 2 , the temperature-varying voltage VNTC has a first voltage level VLc at a first temperature Tc, and a second temperature Th at a second temperature Th higher than the first temperature Tc. The second voltage level VLh may be higher than the first voltage level VLc. In one embodiment, the temperature-varying voltage VNTC may be provided using an on-chip sensor integrated with the variable voltage generating circuit 100 as shown in FIG. 16 . In another embodiment, the temperature-varying voltage VNTC may be provided using a separate temperature sensor chip.

The temperature-fixed voltage VZTC may have a fixed voltage level regardless of the operating temperature. 2 illustrates an example in which the temperature-fixed voltage VZTC is fixed to the first voltage level VLc, the fixed voltage level of the temperature-fixed voltage VZTC may be variously determined. In one embodiment, the temperature-locked voltage VZTC may be provided using a bandgap reference circuit.

Referring to FIG. 3 , the first to nth output voltages VO1 to VOn respectively provided by the first to nth amplifier circuits AMP1 to AMPn of FIG. 1 may increase as the operating temperature increases. For example, the first to nth output voltages VO1 to VOn have the reference voltage level VL0 at the first temperature Tc, and the reference voltage level VL0 at the second temperature Th higher than the first temperature Tc. Each of the voltage levels VL1 to VLn may be higher than the voltage level VL0.

As shown in FIG. 3 , the voltage range VRk of the output voltage VOk provided from the amplification circuit AMPk of the rear stage (k is a natural number greater than or equal to 2 and less than or equal to n) is the amplification circuit AMPk-1 of the previous stage. It may be wider than the voltage range VRk-1 of the provided output voltage VOk-1. That is, the voltage range VR1 = VL0 to VL1 of the first output voltage VO1 may be narrower than the voltage range VR2 = VL0 to VL2 of the second output voltage VO2, and the voltage of the second output voltage VO2 The range VR2=VL0~VL2 may be narrower than the voltage range VR3=VL0~VL3 of the third output voltage VO3, and in this way, the voltage range VRn=VL0~ of the nth output voltage VOn VLn) may be the widest.

As described above, the variable voltage generating circuit 100 according to the embodiments of the present invention is adjusted to the operating temperature range through a plurality of feedback operations using the plurality of amplification circuits AMP1 to AMPn having a voltage offset according to the temperature. It is possible to extend the range of output voltage and improve linearity.

4 is a diagram illustrating another example of a temperature-variable voltage and a temperature-fixed voltage provided to the variable voltage generator circuit of FIG. 1 , and FIG. 5 is another example of a voltage range according to a temperature change of the variable voltage generator circuit of FIG. 1 It is a drawing showing

Referring to FIG. 4 , the temperature-varying voltage VNTC may have a voltage level that varies according to an operating temperature. For example, the temperature-varying voltage VNTC may decrease as the operating temperature increases. That is, as shown in FIG. 4 , the temperature-varying voltage VNTC has a first voltage level VLc at a first temperature Tc and a second temperature Th at a second temperature Th higher than the first temperature Tc. The second voltage level VLh may be lower than the first voltage level VLc. In one embodiment, the temperature-varying voltage VNTC may be provided using an on-chip sensor integrated with the variable voltage generating circuit 100 as shown in FIG. 16 . In another embodiment, the temperature-varying voltage VNTC may be provided using a separate temperature sensor chip.

The temperature-fixed voltage VZTC may have a fixed voltage level regardless of the operating temperature. 4 illustrates an example in which the temperature-fixed voltage VZTC is fixed to the first voltage level VLc, the fixed voltage level of the temperature-fixed voltage VZTC may be variously determined. In one embodiment, the temperature-locked voltage VZTC may be provided using a bandgap reference circuit.

Referring to FIG. 5 , the first to nth output voltages VO1 to VOn respectively provided from the first to nth amplifier circuits AMP1 to AMPn of FIG. 1 may decrease as the operating temperature increases. For example, the first to nth output voltages VO1 to VOn have the reference voltage level VL0 at the first temperature Tc, and the reference voltage level VL0 at the second temperature Th higher than the first temperature Tc. Each of the voltage levels VL1 to VLn may be lower than the voltage level VL0.

As shown in Fig. 5, the voltage range VRk of the output voltage VOk provided from the amplifying circuit AMPk of the rear stage (k is a natural number greater than or equal to 2 and less than or equal to n) is the amplification circuit AMPk-1 of the preceding stage. It may be wider than the voltage range VRk-1 of the provided output voltage VOk-1. That is, the voltage range VR1 = VL0 to VL1 of the first output voltage VO1 may be narrower than the voltage range VR2 = VL0 to VL2 of the second output voltage VO2, and the voltage of the second output voltage VO2 The range VR2=VL0~VL2 may be narrower than the voltage range VR3=VL0~VL3 of the third output voltage VO3, and in this way, the voltage range VRn=VL0~ of the nth output voltage VOn VLn) may be the widest.

As described above, the variable voltage generating circuit 100 according to the embodiments of the present invention is adjusted to the operating temperature range through a plurality of feedback operations using the plurality of amplification circuits AMP1 to AMPn having a voltage offset according to the temperature. It is possible to extend the range of output voltage and improve linearity.

6 is a diagram illustrating an embodiment of a first amplifying circuit included in the variable voltage generating circuit of FIG. 1 .

Referring to FIG. 6 , the first amplifier circuit AMP1 may include a first differential difference amplifier (DDA1) 110 and a first output circuit 115 .

The first differential difference amplifier 110 provides a first amplified voltage VA1 based on the reference voltage VREF, the first feedback voltage VFB1, the temperature-varying voltage VNTC, and the temperature-fixed voltage VZTC. can do. The first differential amplifier 110 receives a temperature-varying voltage VNTC through a first input terminal IN1 , receives a temperature-fixed voltage VZTC through a second input terminal IN2 , and a third input The reference voltage VREF may be received through the terminal IN3 , and the first feedback voltage VFB1 may be received through the fourth input terminal IN4 . The first input terminal IN1 and the second input terminal IN2 that receive the temperature-variable voltage VNTC and the temperature-fixed voltage VZTC form one differential input terminal pair, and the reference voltage VREF and the second input terminal IN2 The third input terminal IN3 and the fourth input terminal IN4 receiving one feedback voltage VFB1 may form another differential input terminal pair.

Using these two differential input terminal pairs, as expressed in Equation 1, the first amplifier circuit AMP1 is a temperature-based voltage-varying voltage VNTC based on the reference voltage VREF and the first feedback voltage ( A first voltage offset OFF1 corresponding to the difference VFB1 may be generated.

The first output circuit 115 may provide a first output voltage VO1 based on the first amplified voltage VA1 and a first feedback voltage VFB1 proportional to the first output voltage VO1 . The first output circuit 115 includes an output amplifying transistor TO connected between the power supply voltage VDD and the output node NO, and a first resistor R1 connected in series between the output node NO and the ground voltage VSS. ) and a second resistor R2. The first output voltage VO1 is provided through the output node NO, and is expressed in Equation 2 by dividing the first output voltage VO1 using the first resistor R1 and the second resistor R2. A first feedback voltage VFB1 as shown in FIG.

The reference voltage VREF may have a fixed voltage level regardless of the operating temperature. In this case, in Equation 1, the amount of change of the first feedback voltage VFB1 according to the change of the operating temperature corresponds to the amount of change of the first voltage offset OFF1. Meanwhile, the first feedback voltage VFB1 and the first output voltage VO1 may be proportional to each other as expressed in Equation 2, and as a result, the first voltage range VR1 of the first output voltage VO1 is It may be proportional to the first voltage offset OFF1 .

7 is a diagram illustrating an embodiment of a second amplification circuit included in the variable voltage generator circuit of FIG. 1 .

Referring to FIG. 7 , the second amplifier circuit AMP2 may include a second differential amplifier DDA2 120 and a second output circuit 125 .

The second differential amplifier 120 is configured to generate a second amplified voltage VA2 based on the first feedback voltage VFB1 , the second feedback voltage VFB2 , the temperature-variable voltage VNTC and the temperature-fixed voltage VZTC. can provide The second differential amplifier 120 receives the temperature-varying voltage VNTC through the first input terminal IN1 , receives the temperature-fixed voltage VZTC through the second input terminal IN2 , and a third input The first feedback voltage VFB1 may be received through the terminal IN3 , and the second feedback voltage VFB2 may be received through the fourth input terminal IN4 . The first input terminal IN1 and the second input terminal IN2 that receive the temperature-variable voltage VNTC and the temperature-fixed voltage VZTC form one differential input terminal pair, and the first feedback voltage VFB1 and the third input terminal IN3 and the fourth input terminal IN4 receiving the second feedback voltage VFB2 may form another differential input terminal pair. While the first differential amplifier 110 included in the first amplifier circuit AMP1 of FIG. 6 receives the reference voltage VREF to the third terminal IN3, the second amplifier circuit AMP2 of FIG. The second differential amplifier 120 included in , receives the first feedback voltage VFB1 provided from the first amplifier circuit AMP1 to the third terminal IN3 .

Using these two differential input terminal pairs, as expressed in Equation 3, the second amplifying circuit AMP2 is a temperature-based first feedback voltage VFB1 and a second feedback voltage VNTC. A second voltage offset OFF2 corresponding to the difference in voltage VFB2 may be generated.

The second output circuit 125 may provide a second output voltage VO2 based on the second amplified voltage VA2 and a second feedback voltage VFB2 proportional to the second output voltage VO2 . The second output circuit 125 includes an output amplifying transistor TO connected between the power supply voltage VDD and the output node NO, and a first resistor R1 connected in series between the output node NO and the ground voltage VSS. ) and a second resistor R2. The second output voltage VO2 is provided through the output node NO, and is expressed in Equation 2 by dividing the second output voltage VO2 using the first resistor R1 and the second resistor R2. The second feedback voltage VFB1 as shown in FIG.

The reference voltage VREF may have a fixed voltage level regardless of the operating temperature. In this case, in Equation 3, the change amount of the second feedback voltage VFB2 according to the change of the operating temperature corresponds to the change amount of the sum of the first voltage offset OFF1 and the second voltage offset OFF2. Meanwhile, the second feedback voltage VFB2 and the second output voltage VO2 may be proportional to each other as expressed in Equation 4, and as a result, the second voltage range VR2 of the second output voltage VO2 is It may be proportional to the sum of the first voltage offset OFF1 and the second voltage offset OFF2 .

Meanwhile, the first amplification circuit AMP1 and the second amplification circuit AMP2 may have the same configuration. In this case, the first voltage offset OFF1 and the second voltage offset OFF2 may be the same, and Equation 3 may be expressed as Equation 5.

Referring to Equations 1 and 5, when the first amplifier circuit AMP1 and the second amplifier circuit AMP2 have the same configuration, the second voltage range VR2 of the second output voltage VO2 is the first It can be seen that the output voltage VO1 is twice the first voltage range VR1.

8 is a diagram illustrating an embodiment of a third amplification circuit included in the variable voltage generator circuit of FIG. 1 .

Referring to FIG. 8 , the third amplifier circuit AMP3 may include a third differential amplifier DDA2 130 and a third output circuit 135 .

The third differential amplifier 130 is configured to generate a third amplified voltage VA3 based on the second feedback voltage VFB2 , the third feedback voltage VFB3 , the temperature-varying voltage VNTC and the temperature-fixed voltage VZTC. can provide The third differential amplifier 130 receives the temperature-varying voltage VNTC through the first input terminal IN1 , receives the temperature-fixed voltage VZTC through the second input terminal IN2 , and a third input The second feedback voltage VFB2 may be received through the terminal IN3 , and the third feedback voltage VFB3 may be received through the fourth input terminal IN4 . The first input terminal IN1 and the second input terminal IN2 that receive the temperature-variable voltage VNTC and the temperature-fixed voltage VZTC form one differential input terminal pair, and the second feedback voltage VFB2 and the third input terminal IN3 and the fourth input terminal IN4 receiving the third feedback voltage VFB3 may form another differential input terminal pair. While the second differential amplifier 120 included in the second amplifier circuit AMP2 of FIG. 7 receives the first feedback voltage VFB1 to the third terminal IN3, the third amplifier circuit ( The third differential amplifier 130 included in AMP3 receives the second feedback voltage VFB2 provided from the second amplifier circuit AMP2 to the third terminal IN3 .

Using these two differential input terminal pairs, as expressed in Equation 6, the third amplifying circuit AMP3 provides a second feedback voltage VFB2 and a third feedback based on the temperature-varying voltage VNTC. A third voltage offset OFF3 corresponding to the difference in voltage VFB3 may be generated.

The third output circuit 135 may provide the third output voltage VO3 and the third feedback voltage VFB3 proportional to the second output voltage VO3 based on the third amplified voltage VA3 . The third output circuit 135 includes an output amplifying transistor TO connected between the power supply voltage VDD and the output node NO, and a first resistor R1 connected in series between the output node NO and the ground voltage VSS. ) and a second resistor R2. The third output voltage VO2 is provided through the output node NO, and is expressed in Equation 7 by dividing the third output voltage VO3 using the first resistor R1 and the second resistor R2. A third feedback voltage VFB1 as shown in FIG.

The reference voltage VREF may have a fixed voltage level regardless of the operating temperature. In this case, in Equation 6, the change amount of the third feedback voltage VFB3 according to the change of the operating temperature corresponds to the change amount of the sum of the first voltage offset OFF1, the second voltage offset OFF2, and the third voltage offset OFF3 do. Meanwhile, the third feedback voltage VFB3 and the third output voltage VO3 may be proportional to each other as expressed in Equation 7, and as a result, the third voltage range VR3 of the third output voltage VO3 is It may be proportional to the sum of the first voltage offset OFF1 , the second voltage offset OFF2 , and the third voltage offset OFF3 .

Meanwhile, the first amplification circuit AMP1 , the second amplification circuit AMP2 , and the third amplification circuit AMP3 may have the same configuration. In this case, the first voltage offset OFF1 , the second voltage offset OFF2 , and the third voltage offset OFF3 may be the same, and Equation 6 may be expressed as Equation 8 .

Referring to Equations 1 and 8, when the first amplifier circuit AMP1, the second amplifier circuit AMP2, and the third amplifier circuit AMP3 have the same configuration, the third output voltage VO3 is It can be seen that the third voltage range VR3 is three times the first voltage range VR1 of the first output voltage VO1 .

In the above, an embodiment in which the voltage range according to the change in operating temperature is sequentially extended using three amplification circuits has been described. However, those skilled in the art can further extend the voltage range using any number of amplification circuits. You will understand that you can.

9 is a diagram illustrating an embodiment of a first differential difference amplifier included in the first amplifier circuit of FIG. 6 . FIG. 10 is a diagram for explaining control of a first output voltage of the first differential amplifier of FIG. 9 according to a temperature coefficient, and FIG. 11 is a second current source included in the first differential amplifier of FIG. 9 according to a temperature coefficient. A diagram showing the tail current of

Referring to FIG. 9 , the first differential amplifier 110 includes a current mirror 111 , a first input transistor pair 112 , a second input transistor pair 113 , a first current source CS11 , and a second current source. (CS12). For example, the current mirror 111 may include P-type metal oxide semiconductor (PMOS) transistors MP11 and MP12, and a first input transistor pair 112 and a second input transistor pair ( The 113 may include N-type metal oxide semiconductor (NMOS) transistors MN11 , MN12 , MN13 , and MN14 .

The current mirror 111 may be coupled to the output node pair N1 and N2 that generates the first amplified voltage VA1 . The first input transistor pair 112 is coupled to the output node pair N1 , N2 and may receive a reference voltage VREF and a first feedback voltage VFB1 . The second input transistor pair 113 is coupled to the output node pair N1 and N2 and may receive a temperature-varying voltage VNTC and a temperature-fixed voltage VZTC. The first current source CS11 may be coupled to the first input transistor pair 112 to provide a tail current or a bias current to the first input transistor pair 112 , and the second current source CS12 may be coupled to the first input transistor pair 112 . It may be coupled to the two input transistor pair 113 to provide a tail current to the second input transistor pair 113 .

The first current source CS11 may supply a tail current to the first input transistor pair 112 in response to the bias signal VBS. The second current source CS12 may adjust the first output voltage VO1 and the first voltage range VR1 by adjusting the tail current supplied to the second input transistor pair 113 in response to the temperature coefficient signal TC. . In this case, Equation 1 may be expressed as Equation 9.

In Equation 9, the constant K is a constant proportional to the control value of the temperature coefficient signal TC. For example, the second current source CS12 may have a structure in which the tail current increases as the constant K increases. In this case, as the control value of the temperature coefficient signal TC increases, the first output voltage VO1 The first voltage range VR1 may increase. 10 , when the temperature coefficient signal TC has the intermediate control value TCi, the voltage range VR1 of the first output voltage VO1 for the temperature range Tc to Th is VL0 to VLi is relatively small, and when the temperature coefficient signal TC has the maximum control value TCm, the voltage range VR1 of the first output voltage VO1 for the temperature range Tc to Th has a maximum as VL0 to VLm. can be As described above, the voltage range VR1 of the first output voltage VO1 may be increased by increasing the control value of the temperature coefficient signal TC to increase the tail current of the second current source CS12 .

However, increasing the first voltage range VR1 of the first output voltage VO1 by increasing the tail current of the second current source CS12 has a certain limit. As illustrated in FIG. 11 , when the temperature coefficient signal TC monotonically increases the increasing tail current, when the temperature coefficient signal TC exceeds a constant control value TC1 , a problem occurs in that the linearity is broken.

According to embodiments of the present invention, it is possible to extend the range of the output voltage with respect to the operating temperature range and improve the linearity through a plurality of feedback operations using a plurality of amplification circuits.

12 is a diagram illustrating an embodiment of a second differential amplifier included in the second amplifier circuit of FIG. 7 .

Referring to FIG. 12 , the second differential amplifier 120 includes a current mirror 121 , a first input transistor pair 122 , a second input transistor pair 123 , a first current source CS21 , and a second current source. (CS22). For example, the current mirror 121 may include P-type metal oxide semiconductor (PMOS) transistors MP21 and MP22, and include a first input transistor pair 122 and a second input transistor pair ( 123 may include N-type metal oxide semiconductor (NMOS) transistors MN21 , MN22 , MN23 , and MN24 .

The current mirror 121 may be coupled to the output node pair N1 and N2 that generates the second amplified voltage VA2 . The first input transistor pair 122 may be coupled to the output node pair N1 and N2 and receive a first feedback voltage VFB1 and a second feedback voltage VFB2. The second input transistor pair 123 is coupled to the output node pair N1 and N2 and may receive a temperature-varying voltage VNTC and a temperature-fixed voltage VZTC. The first input transistor pair 112 of the first differential difference amplifier 110 of FIG. 9 receives the reference voltage VREF and the first feedback voltage VFB1 to perform differential amplification, while the second input transistor pair 112 of FIG. The first input transistor pair 122 of the differential difference amplifier 120 receives the first feedback voltage VFB1 and the second feedback voltage VFB2 to perform differential amplification. Through such a continuous feedback operation, the second amplification circuit AMP2 including the second differential amplifier 120 has a second voltage range that is wider than the first voltage range VR1 of the first output voltage VO1 . A second output voltage VO2 having VR2 may be generated.

The first current source CS21 may be coupled to the first input transistor pair 122 to provide a tail current to the first input transistor pair 122 , and the second current source CS22 may be coupled to the second input transistor pair 123 . may be coupled to provide a tail current to the second input transistor pair 123 .

The first current source CS21 may supply a tail current to the first input transistor pair 122 in response to the bias signal VBS. As described with reference to FIG. 10 , the second current source CS22 controls the tail current supplied to the second input transistor pair 123 in response to the temperature coefficient signal TC to increase the second output voltage VO2 . 2 Voltage range (VR2) can be adjusted.

13 is a diagram illustrating an embodiment of a third differential difference amplifier included in the third amplifier circuit of FIG. 8 .

Referring to FIG. 13 , the third differential amplifier 130 includes a current mirror 131 , a first input transistor pair 132 , a second input transistor pair 133 , a first current source CS31 , and a second current source. (CS32) may be included. For example, the current mirror 131 may include P-type metal oxide semiconductor (PMOS) transistors MP31 and MP32, and include a first input transistor pair 132 and a second input transistor pair ( The 133 may include N-type metal oxide semiconductor (NMOS) transistors MN31, MN32, MN33, and MN34.

The current mirror 131 may be coupled to the output node pair N1 and N2 that generates the third amplified voltage VA3 . The first input transistor pair 132 may be coupled to the output node pair N1 and N2 and receive a second feedback voltage VFB2 and a third feedback voltage VFB3 . The second input transistor pair 133 is coupled to the output node pair N1 and N2 and may receive a temperature-varying voltage VNTC and a temperature-fixed voltage VZTC. The first input transistor pair 122 of the second differential difference amplifier 120 of FIG. 12 receives the first feedback voltage VFB1 and the second feedback voltage VFB2 to perform differential amplification, while the The first input transistor pair 132 of the third differential amplifier 130 receives the second feedback voltage VFB2 and the third feedback voltage VFB3 to perform differential amplification. Through such a continuous feedback operation, the third amplification circuit AMP3 including the third differential amplifier 130 has a third voltage range that is wider than the second voltage range VR2 of the second output voltage VO2 . A third output voltage VO3 having VR3 may be generated.

The first current source CS31 may be coupled to the first input transistor pair 132 to provide a tail current to the first input transistor pair 132 , and the second current source CS32 may be coupled to the second input transistor pair 133 . may be coupled to provide a tail current to the second input transistor pair 133 .

The first current source CS31 may supply a tail current to the first input transistor pair 122 in response to the bias signal VBS. As described with reference to FIG. 10 , the second current source CS32 controls the tail current supplied to the second input transistor pair 133 in response to the temperature coefficient signal TC to increase the third output voltage VO3 . 3 Voltage range (VR3) can be adjusted.

14 is a block diagram illustrating a variable voltage generating circuit according to embodiments of the present invention.

Referring to FIG. 14 , the variable voltage generating circuit 100 may include first to nth amplification circuits AMP1 to AMPn and a selector MUX.

The first amplifier circuit AMP1 includes a reference voltage VREF, a first feedback voltage VFB1, a temperature-varying voltage VNTC that varies according to an operating temperature, and a fixed temperature-fixed voltage VZTC regardless of the operating temperature. ), a first output voltage VO1 that changes in the first voltage range VR1 is generated according to a change in the operating temperature. The first amplifier circuit AMP1 generates a first feedback voltage VFB1 based on the first output voltage VO1 .

The k-th amplifier circuit AMPk (k is a natural number of 2 or more and n or less) includes a k-1th feedback voltage VFBk-1, a kth feedback voltage VFBk, a temperature-variable voltage VNTC, and a temperature-fixed voltage. Based on (VZTC), a kth output voltage VOk that varies in a kth voltage range VRk greater than the k−1th voltage range VRk−1 is generated according to a change in the operating temperature. The kth amplifier circuit AMPk generates the kth feedback voltage VFBk based on the kth output voltage VOk.

In other words, the second amplifying circuit AMP2 changes the operating temperature based on the first feedback voltage VFB1 , the second feedback voltage VFB2 , the temperature-variable voltage VNTC and the temperature-fixed voltage VZTC. Accordingly, the second output voltage VO2 that changes in the second voltage range VR2 greater than the first voltage range VR1 is generated, and the second feedback voltage VFB2 is generated based on the second output voltage VO2. Occurs. The third amplifying circuit AMP is configured to perform a first operation according to a change in the operating temperature based on the second feedback voltage VFB2 , the third feedback voltage VFB3 , the temperature-variable voltage VNTC and the temperature-fixed voltage VZTC. The third output voltage VO3 that is changed in the third voltage range VR3 greater than the second voltage range VR2 is generated, and the third feedback voltage VFB3 is generated based on the third output voltage VO3 . In this way, the n-th amplifier circuit AMPn is based on the n-1 th feedback voltage VFBn-1, the n th feedback voltage VFBn, the temperature-variable voltage VNTC, and the temperature-fixed voltage VZTC. to generate an n-th output voltage VOn that changes in an n-th voltage range VRn greater than an n-1 voltage range VRn-1 according to a change in the operating temperature, and Based on the n-th feedback voltage VFBn is generated.

The selector MUX may select one of the first to nth output voltages VO1 to VOn in response to the selection signal SEL and output the selection voltage VOs. An output voltage having an appropriate voltage range for a temperature range is selected according to the characteristics of the device and/or system including the variable voltage generating circuit 101, and the operating characteristics according to the operating temperature of the device and/or system are efficiently selected. can be controlled

15 is a block diagram illustrating a digital thermometer according to embodiments of the present invention.

Referring to FIG. 15 , the digital thermometer 300 may include a temperature sensor (SEN) 310 , a variable voltage generating circuit (VVGC) 330 , and an analog-to-digital converter (ADC) 350 .

The temperature sensor 310 may generate a temperature-varying voltage VNTC that changes according to the surrounding temperature. In one embodiment, the temperature sensor 310 may be an on-chip sensor integrated with the variable voltage generating circuit 330 as shown in FIG. 16 . In another embodiment, the temperature sensor 310 may be a separate temperature sensor chip formed independently of the variable voltage generating circuit 330 .

The variable voltage generator circuit 330 includes a plurality of amplification circuits according to embodiments of the present invention. As described above, the variable voltage generating circuit 330 provides an output voltage VOn having an extended output voltage range and improved linearity with respect to an operating temperature range through a plurality of feedback operations using a plurality of amplification circuits. can do.

The analog-to-digital converter 350 may convert the output voltage VOn of the variable voltage generating circuit 330 into a digital signal DGT indicating the ambient temperature. The configuration of the analog-to-digital converter 350 may be implemented in various ways, and the digital signal DGT may include a plurality of bits.

The digital thermometer 300 according to embodiments of the present invention can measure the ambient temperature more precisely by using the output voltage VOn having an extended voltage range and improved linearity.

16 is a circuit diagram illustrating an example of a temperature sensor included in the digital thermometer of FIG. 15 .

The temperature sensor 310 includes first and second PMOS transistors M1 and M2, a feedback amplifier AMP, a resistor R, and first and second bipolar transistors coupled as shown in FIG. 16 . It may be implemented including (B1, B2). The voltage dVBE across both ends of the resistor R can be expressed as in Equation 10 below.

In Equation 10, Is1 and Is2 are reverse saturation currents of the first and second bipolar transistors B1 and B2, respectively, and Ic1 and Ic2 are the first and second bipolar transistors B1 and B2, respectively. ), n is a gain ratio of the first and second bipolar transistors B1 and B2, and VT is a temperature voltage and is proportional to the absolute temperature. In Equation 10, since Ln(n) is a constant, the voltage dVBE applied to both ends of the resistor R and the current I2 flowing through the resistor R have characteristics proportional to the temperature change. As such, the temperature sensor 310 may provide a temperature-varying voltage VNTC based on the voltage dVBE proportional to the temperature.

17 is a block diagram illustrating a clock generator according to embodiments of the present invention.

Referring to FIG. 17 , the clock generator 500 may include a temperature sensor (SEN) 510 , a variable voltage generator circuit (VVGC), and a voltage controlled oscillator (VCO) 550 .

The temperature sensor 510 may generate a temperature-varying voltage VNTC that changes according to the surrounding temperature. In one embodiment, the temperature sensor 510 may be an on-chip sensor integrated with the variable voltage generating circuit 530 as shown in FIG. 16 . In another embodiment, the temperature sensor 510 may be a separate temperature sensor chip formed independently of the variable voltage generating circuit 530 .

The variable voltage generator circuit 530 includes a plurality of amplification circuits according to embodiments of the present invention. As described above, the variable voltage generating circuit 530 provides an output voltage VOn having an extended output voltage range and improved linearity with respect to an operating temperature range through a plurality of feedback operations using a plurality of amplifier circuits. can do.

The voltage controlled oscillator 550 may generate a clock signal CK having a frequency that varies according to temperature based on the output voltage VOn of the variable voltage generator circuit 530 .

The clock generator 500 according to embodiments of the present invention can more precisely control the frequency of the clock signal CK according to the ambient temperature by using the output voltage VOn having an extended voltage range and improved linearity. there is.

18 is a diagram illustrating an example of a voltage-controlled oscillator included in the clock generator of FIG. 17 , and FIG. 19 is a diagram illustrating an example of an inverter included in the voltage-controlled oscillator of FIG. 18 .

In an embodiment, the voltage controlled oscillator 550 may be implemented including a ring oscillator as shown in FIG. 18 . The ring oscillator may include a cascaded NAND logic gate 551 and a plurality of inverters 552 , 553 , 554 , 555 . The output of the last inverter 555 is fed back to the NAND logic gate 551 , and the ring oscillator may be enabled in response to the sensing enable signal ENS applied to the NAND logic gate 551 .

The NAND logic gate 551 and the inverters 552 , 553 , 554 , and 555 have an operating speed according to an operating temperature, and thus the frequency of the clock signal CK may vary according to the operating temperature.

Referring to FIG. 19 , the inverter 552a includes a first PMOS transistor MP1, a first NMOS transistor MN1, and a first PMOS transistor MP1 cascoded between a power supply voltage VDD and a ground voltage VSS. 2 NMOS transistors MN2 may be included. The signal IN of the previous stage is applied to the gates of the first PMOS transistor MP1 and the first NMOS transistor MN1 , and the inverted signal OUT is outputted to the rear stage. The output voltage VOn of the variable voltage generating circuit 530 that varies according to temperature is applied to the gate of the second NMOS transistor MN2. For example, as the temperature increases, the output of the variable voltage generating circuit 530 is increased. As the voltage level of the voltage VOn increases, a sinking current flowing through the second NMOS transistor MN2 increases, thereby increasing the operating speed of the inverter 552a. As a result, the frequency of the clock signal CK output from the voltage controlled oscillator 550 may increase in proportion to the temperature.

Above, the digital thermometer 300 and the clock generator 500 using the variable voltage generating circuit according to embodiments of the present invention have been described with reference to FIGS. 15 to 19 . The configuration of the digital thermometer 300 and the clock generator 500 is not limited to the configuration shown in FIGS. 15 to 19 and may be variously modified. In addition, the variable voltage generating circuit according to the embodiments of the present invention may be applied to any device and/or system capable of using a voltage having a voltage level that changes with respect to a temperature change, as well as a digital thermometer and a clock generator.

20 is a block diagram illustrating a memory device according to embodiments of the present invention.

Referring to FIG. 20 , the nonvolatile memory device 900 includes a memory cell array 910 , a page buffer circuit 920 , a row decoder 930 , a voltage generator 940 , an input/output buffer circuit 960 , and a control circuit. (950). In one embodiment, the memory device 900 may be a flash memory device. In another embodiment, the memory device 900 may include any non-volatile memory, such as phase change random access memory (PRAM), resistance random access memory (RRAM), magneto-resistive random access memory (MRAM), ferroelectric random access memory (FRAM), or the like. It may be a volatile memory device. In another embodiment, the memory device 800 may be a volatile memory device such as a dynamic random access memory (DRAM), a static random access memory (SRAM), or the like.

The memory cell array 910 includes a plurality of memory cells respectively connected to a plurality of word lines and a plurality of bit lines. 21 to 24 , the plurality of memory cells may be NAND flash memory cells, NOR flash memory cells, or resistive memory cells, and are arranged in a two-dimensional array structure or a three-dimensional vertical array structure. can be

In an embodiment, the plurality of memory cells may be single-level cells (SLCs) each storing one data bit or multi-level cells (MLCs) storing a plurality of data bits. there is.

Each multi-level cell can store N-bit data by being programmed into one of 2N states (N is a natural number equal to or greater than 2). In the case of a multi-level cell, various program methods such as a shadow program method, a reprogram method, or an on-chip buffered program method may be applied as a programming method in the write mode.

The page buffer circuit 920 is connected to the plurality of bit lines and stores write data to be programmed in the memory cell array 910 or read data sensed from the memory cell array 910 . That is, the page buffer circuit 920 may operate as a write driver or a sense amplifier according to an operation mode of the memory device 900 . For example, the page buffer circuit 920 may operate as a write driver in a write mode and as a sense amplifier in a read mode. The input/output buffer circuit 960 may receive data to be written into the memory cell array 910 from an external memory controller, and transmit data read from the memory cell array 910 to the memory controller.

The row decoder 930 may be connected to the plurality of word lines and select at least one of the plurality of word lines in response to a row address. The voltage generator 940 may generate word line voltages such as a program voltage, a pass voltage, a verify voltage, an erase voltage, and a read voltage under the control of the control circuit 1950 . The control circuit 950 includes a page buffer circuit 920 , a row decoder 930 , a voltage generator 940 , and an input/output buffer circuit 960 to perform data storage, erasing, and reading operations on the memory cell array 1910 . can be controlled

The memory device 900 includes a variable voltage generation circuit (VVGC) 951 . Although the variable voltage generator circuit 951 is illustrated as being included in the control circuit 951 in FIG. 20 , the variable voltage generator circuit 951 may be disposed in various positions. The variable voltage generator circuit 951 includes a plurality of amplification circuits according to embodiments of the present invention. As described above, the variable voltage generating circuit 951 provides an output voltage VOn having an extended output voltage range and improved linearity with respect to an operating temperature range through a plurality of feedback operations using a plurality of amplification circuits. can do. By using the output voltage Von, operating characteristics such as an operation timing and a voltage level of the memory device 900 may be precisely controlled according to a change in temperature.

21 , 22 , 23 and 24 are diagrams illustrating examples of a memory cell array included in the nonvolatile memory device of FIG. 20 .

21 is a circuit diagram illustrating an example of a memory cell array included in a NOR-type flash memory device, FIG. 22 is a circuit diagram illustrating an example of a memory cell array included in a NAND-type flash memory device, and FIG. 23 is a vertical flash A circuit diagram illustrating an example of a memory cell array included in a memory device, and FIG. 24 is a circuit diagram illustrating an example of a memory cell array included in a resistive memory device.

Referring to FIG. 21 , the memory cell array 910a may include a plurality of memory cells MC1 . The memory cells MC1 arranged in the same column may be arranged in parallel between one of the bit lines BL(1), ..., BL(m) and the common source line CSL, and arranged in the same row. The memory cells MC1 may be commonly connected to one of the word lines WL(1), WL(2), ..., WL(n). For example, the memory cells arranged in the first column may be disposed in parallel between the first bit line WL( 1 ) and the common source line CSL. Gate electrodes of the memory cells arranged in the first row may be commonly connected to the first word line WL( 1 ). The memory cells MC1 may be controlled according to the level of a voltage applied to the word lines WL(1), ..., WL(n). The NOR-type flash memory device including the memory cell array 1910a performs write and read operations in units of bytes or words, and can perform erase operations in units of blocks 1912a. there is.

Referring to FIG. 22 , the memory cell array 910b may include string select transistors SST, ground select transistors GST, and memory cells MC2 . The string select transistors SST may be connected to the bit lines BL(1), ..., BL(m), and the ground select transistors GST may be connected to the common source line CSL. The memory cells MC2 arranged in the same column may be arranged in series between one of the bit lines BL(1), ..., BL(m) and the common source line CSL, and arranged in the same row. The memory cells MC2 may be commonly connected to one of the word lines WL(1), WL(2), WL(3), ..., WL(n-1), WL(n). . That is, the memory cells MC2 may be connected in series between the string select transistors SST and the ground select transistor GST, and between the string select line SSL and the ground select line GSL, there are 16 and 32 memory cells. A plurality of word lines, such as or 64, may be arranged.

The string select transistors SST are connected to the string select line SSL to be controlled according to a level of a voltage applied from the string select line SSL, and the ground select transistors GST are connected to the ground select line GSL. connected, and may be controlled according to a level of a voltage applied from the ground selection line GSL. The memory cells MC2 may be controlled according to the level of a voltage applied to the word lines WL(1), ..., WL(n).

The NAND-type flash memory device including the memory cell array 910b may perform a write operation and a read operation in units of pages 911b and may perform an erase operation in units of blocks 912b. Meanwhile, according to an embodiment, each of the page buffers may be connected to one even-numbered bit line and one odd-numbered bit line. In this case, the even-numbered bit lines form an even-numbered page, the odd-numbered bit lines form an odd-numbered page, and a write operation on the memory cells MC2 may be sequentially performed alternately between the even-numbered pages and the odd-numbered pages.

Referring to FIG. 23 , the memory cell array 910c may include a plurality of strings 913c having a vertical structure. A plurality of strings 913c may be formed along the second direction to form a string column, and the plurality of string columns may be formed along the third direction to form a string array. The plurality of strings 913c are ground select transistors GSTV that are disposed in series along the first direction between the bit lines BL(1), ..., BL(m) and the common source line CSL. , memory cells MC3 and string select transistors SSTV may be included, respectively.

The ground select transistors GSTV are respectively connected to the ground select lines GSL11, GSL12, ..., GSLi1, GSLi2, and the string select transistors SSTV are the string select lines SSL11, SSL12, ..., SSLi1 , SSLi2) can be connected respectively. The memory cells MC3 arranged on the same layer may be commonly connected to one of the word lines WL(1), WL(2), ..., WL(n-1), WL(n). The ground selection lines GSL11, ..., GSLi2 and the string selection lines SSL11, ..., SSLi2 may extend in the second direction and may be formed in plurality along the third direction. The word lines WL(1), ..., WL(n) may extend in the second direction and may be formed in plurality in the first direction and the third direction. The bit lines BL(1), ..., BL(m) may extend in the third direction and may be formed in plurality along the second direction. The memory cells MC3 may be controlled according to the levels of voltages applied to the word lines WL(1), ..., WL(n).

Since the vertical flash memory device including the memory cell array 910c includes NAND flash memory cells, write and read operations are performed in units of pages and erase operations are performed in units of blocks, similar to the NAND flash memory device. .

According to an embodiment, two string select transistors included in one string 913c are connected to one string select line, and two ground select transistors included in one string are connected to one ground select line. may be Also, according to an embodiment, one string may be implemented including one string select transistor and one ground select transistor.

Referring to FIG. 24 , the memory cell array 910d includes a plurality of memory cells MC disposed in a region where a plurality of word lines WL0 to WLn and a plurality of bit lines BL0 to BLm intersect. do. Each memory cell MC may include a cell transistor CT and a resistive element CR as shown in FIG. 24 .

The cell transistor CT and the resistive element CR of each memory cell MC may be connected between each of the bit lines BL0 to BLm and the source line SL. The plurality of memory cells MC may be commonly connected to the same source line SL. Meanwhile, the memory cell array 910d may be divided into two or more cell regions, and a different source line SL may be connected to each cell region.

25 is a block diagram illustrating a solid state disk or solid state drive (SSD) according to embodiments of the present invention.

Referring to FIG. 25 , the SSD 1000 includes a plurality of nonvolatile memory devices 1100 and an SSD controller 1200 .

The nonvolatile memory devices 1100 may optionally be implemented to receive an external high voltage (VPP). The nonvolatile memory devices 1100 may include the aforementioned vertical NAND flash memory devices.

The SSD controller 1200 is connected to the nonvolatile memory devices 1100 through a plurality of channels CH1 to CH4. The SSD controller 1200 includes at least one processor 1210 , a buffer memory 1220 , an error correction circuit 1230 , a host interface 1250 , and a nonvolatile memory interface 1260 .

The buffer memory 1220 may temporarily store data necessary for driving the memory controller 1200 . Also, the buffer memory 1220 may buffer data to be used for a fine program operation when a write request is made. Although the buffer memory 1220 in FIG. 25 exists inside the SSD controller 1200, it will not necessarily be limited thereto. The buffer memory may exist separately outside the SSD controller 1200 .

The error correction circuit 1230 calculates an error correction code value of data to be programmed in a write operation, performs error correction on data read in a read operation based on the error correction code value, and performs an error correction in the data recovery operation of the nonvolatile memory device 1100 ), it is possible to correct errors in the recovered data. Although not shown, a code memory for storing code data required for driving the memory controller 1200 may be further included. The code memory may be implemented as a non-volatile memory device.

The host interface 1250 may provide an interface function with an external device. The nonvolatile memory interface 1260 may provide an interface function with the nonvolatile memory device 1100 .

The SSD 1000 includes a variable voltage generating circuit (not shown), and the variable voltage generating circuit may be disposed at various positions within the SSD 1000 . The variable voltage generating circuit includes a plurality of amplifying circuits according to embodiments of the present invention. As described above, the variable voltage generating circuit may provide an output voltage having an extended output voltage range and improved linearity with respect to an operating temperature range through a plurality of feedback operations using a plurality of amplification circuits. By using such an output voltage, operation characteristics such as an operation timing and a voltage level of the SSD 1000 may be precisely controlled according to a change in temperature.

26 is a block diagram illustrating an embedded multimedia card (eMMC) according to embodiments of the present invention.

Referring to FIG. 26 , the eMMC 2000 may include at least one NAND flash memory device 2100 and a controller 2200 .

The memory controller 2200 is connected to the NAND flash memory device 2100 through a plurality of channels. The memory controller 2200 includes at least one controller core 2210 , a host interface 2250 , and a NAND interface 2260 . At least one controller core 2210 controls the overall operation of the eMMC (2000). The host interface 2250 performs interfacing between the controller 2210 and the host. The NAND interface 2260 interfaces the NAND flash memory device 2100 and the controller 2200 .

In an embodiment, the host interface 2250 may be a parallel interface (eg, an MMC interface). In another embodiment, the host interface 2250 of the eMMC 2000 may be a serial interface (eg, UHS-II, UFS interface).

The eMMC 2000 receives power supply voltages Vcc and Vccq from the host. Here, the first power voltage (Vcc, for example, 3.3V) is provided to the NAND flash memory device 2100 and the NAND interface 2260 , and the second power voltage (Vccq, for example, 1.8V/3.3V) is provided to the controller 2200 . In an embodiment, the eMMC 2000 may optionally receive an external high voltage (Vpp).

The eMMC 2000 includes a variable voltage generating circuit (not shown), and the variable voltage generating circuit may be disposed at various positions within the eMMC 2000 . The variable voltage generating circuit includes a plurality of amplifying circuits according to embodiments of the present invention. As described above, the variable voltage generating circuit may provide an output voltage having an extended output voltage range and improved linearity with respect to an operating temperature range through a plurality of feedback operations using a plurality of amplification circuits. By using such an output voltage, operation characteristics such as an operation timing and a voltage level of the eMMC 2000 may be precisely controlled according to a change in temperature.

27 is a block diagram illustrating a universal flash storage (USF) according to embodiments of the present invention.

Referring to FIG. 27 , the UFS system 3000 may include a UFS host 3100 , UFS devices 3200 and 3300 , an embedded UFS device 3400 , and a removable UFS card 3500 . The UFS host 3100 may be an application processor of a mobile device. Each of the UFS host 3100 , the UFS devices 3200 and 3300 , the embedded UFS device 3400 , and the removable UFS card 3500 may communicate with external devices through the UFS protocol.

At least one of the UFS host 3100 , the UFS devices 3200 and 3300 , the embedded UFS device 3400 , and the removable UFS card 3500 may include a variable voltage generating circuit (not shown). The variable voltage generating circuit includes a plurality of amplifying circuits according to embodiments of the present invention, and as described above, the variable voltage generating circuit is extended with respect to the operating temperature range through a plurality of feedback operations using the plurality of amplifying circuits. It is possible to provide an output voltage with an improved range of output voltages and improved linearity.

Meanwhile, the embedded UFS device 3400 and the removable UFS card 3500 may communicate using a protocol other than the UFS protocol. The UFS host 3100 and the removable UFS card 3500 may communicate using various card protocols (eg, UFDs, MMC, secure digital (SD), mini SD, Micro SD, etc.).

28 is a block diagram illustrating a mobile device according to embodiments of the present invention.

Referring to FIG. 28 , the mobile device 4000 includes an application processor 4100 , a communication module 4200 , a display/touch module 4300 , a storage device 4400 , and a mobile RAM 4500 .

The application processor 4100 controls the overall operation of the mobile device 4000 . The communication module 4200 may be implemented to control wired/wireless communication with the outside. The display/touch module 4300 may be implemented to display data processed by the application processor 4100 or to receive data from a touch panel. The storage device 4400 may be implemented to store user data. The storage device 4400 may be an eMMC, SSD, or UFS device.

The mobile RAM 4500 may be implemented to temporarily store data necessary for a processing operation of the mobile device 4000 .

At least one of the application processor 4100 , the communication module 4200 , the display/touch module 4300 , the storage device 4400 , and the mobile RAM 4500 may include a variable voltage generation circuit (not shown). The variable voltage generating circuit includes a plurality of amplifying circuits according to embodiments of the present invention, and as described above, the variable voltage generating circuit is extended with respect to the operating temperature range through a plurality of feedback operations using the plurality of amplifying circuits. It is possible to provide an output voltage with an improved range of output voltages and improved linearity.

A memory device or a storage device according to an embodiment of the present invention may be mounted using various types of packages. In an embodiment, the memory system or storage device according to an embodiment of the present invention is a PoP (Package on Package), Ball grid arrays (BGAs), Chip scale packages (CSPs), Plastic Leaded Chip Carrier (PLCC), Plastic Dual In -Line Package(PDIP), Die in Waffle Pack, Die in Wafer Form, Chip On Board(COB), Ceramic Dual In-Line Package(CERDIP), Plastic Metric Quad Flat Pack(MQFP), Thin Quad Flatpack(TQFP), Small Outline(SOIC), Shrink Small Outline Package(SSOP), Thin Small Outline(TSOP), Thin Quad Flatpack(TQFP), System In Package(SIP), Multi Chip Package(MCP), Wafer-level Fabricated Package(WFP) , Wafer-Level Processed Stack Package (WSP), etc. may be used to be mounted.

As described above, the variable voltage generating circuit according to embodiments of the present invention expands the output voltage range with respect to the operating temperature range through a plurality of feedback operations using a plurality of amplifying circuits having a voltage offset according to the temperature. and improve linearity. A device and/or system including the variable voltage generating circuit may have improved performance by precisely controlling the operating characteristics of the device and/or system according to a change in operating temperature using an output voltage of the variable voltage generating circuit. there is.

The variable voltage generating circuit according to the embodiments of the present invention may be usefully applied to devices and systems requiring operation control according to temperature changes. Memory cards, solid state drives (SSDs), computers, laptops, cellular phones, smart phones, MP3 players, and PDAs that operate at high speed and require power reduction. (Personal Digital Assistants; PDA), PMP (Portable Multimedia Player; PMP), digital TV, digital camera, portable game console (portable game console) can be more usefully applied to electronic devices.

Although the present invention has been described above with reference to preferred embodiments, those skilled in the art can variously modify and change the present invention without departing from the spirit and scope of the present invention as set forth in the claims below. you will understand that you can

AMP1-AMPn: Amplification circuits
VO1~Von: output voltages
VR1 to VRn: voltage ranges
VFB1 to VFBn: feedback voltages
VNTC: temperature-varying voltage
VZTC: temperature-fixed voltage
VREF: reference voltage
DDA: Differential Difference Amplifier

Claims (10)

A first voltage varying in a first voltage range according to a change in the operating temperature based on a reference voltage, a first feedback voltage, a temperature-varying voltage that varies according to the operating temperature and a temperature-fixed voltage that is fixed irrespective of the operating temperature a first amplifier circuit that generates an output voltage and generates the first feedback voltage based on the first output voltage; and
A second output voltage varying in a second voltage range greater than the first voltage range according to a change in the operating temperature based on the first feedback voltage, the second feedback voltage, the temperature-varying voltage, and the temperature-fixed voltage and a second amplifying circuit for generating the second feedback voltage based on the second output voltage,
wherein the first amplification circuit comprises a first differential difference amplifier and a first output circuit;
The first differential difference amplifier is
a first pair of differential input terminals receiving the reference voltage and the first feedback voltage; and
a second differential input terminal pair for receiving the temperature-varying voltage and the temperature-fixed voltage;
The first differential difference amplifier provides a first amplified voltage, and the first output circuit provides the first output voltage based on the first amplified voltage. According to claim 1,
and the second amplification circuit includes a differential input terminal pair for receiving the first feedback voltage and the second feedback voltage. delete 3. The method of claim 2,
the first amplifying circuit generates a first voltage offset corresponding to a difference between the reference voltage and the first feedback voltage based on the temperature-varying voltage;
and the second amplifying circuit generates a second voltage offset corresponding to a difference between the first feedback voltage and the second feedback voltage based on the temperature-varying voltage. 5. The method of claim 4,
the first voltage range is proportional to the first voltage offset;
and the second voltage range is proportional to a sum of the first voltage offset and the second voltage offset. According to claim 1,
The variable voltage generating circuit according to claim 1, wherein the first amplifying circuit and the second amplifying circuit have the same configuration, and the second voltage range is twice the first voltage range. The method of claim 1, wherein the first output circuit comprises:
The variable voltage generating circuit of claim 1 , further providing the first feedback voltage proportional to the first output voltage. 8. The method of claim 7,
The second amplification circuit,
a second differential difference amplifier configured to provide a second amplified voltage based on the first feedback voltage, the second feedback voltage, the temperature-varying voltage, and the temperature-fixed voltage; and
and a second output circuit providing the second output voltage and the second feedback voltage proportional to the second output voltage based on the second amplified voltage. A first voltage varying in a first voltage range according to a change in the operating temperature based on a reference voltage, a first feedback voltage, a temperature-varying voltage that varies according to the operating temperature and a temperature-fixed voltage that is fixed irrespective of the operating temperature a first amplifier circuit that generates an output voltage and generates the first feedback voltage based on the first output voltage; and
The kth amplifying circuit (k is a natural number of 2 or more and n or less) is a kth according to a change in the operating temperature based on the k-1th feedback voltage, the kth feedback voltage, the temperature-variable voltage, and the temperature-fixed voltage. 2nd to nth amplifier circuits for generating a kth output voltage that varies in a kth voltage range greater than a -1 voltage range, and generating the kth feedback voltage based on the kth output voltage,
wherein the first amplification circuit comprises a first differential difference amplifier and a first output circuit;
The first differential difference amplifier is
a first pair of differential input terminals receiving the reference voltage and the first feedback voltage; and
a second differential input terminal pair for receiving the temperature-varying voltage and the temperature-fixed voltage;
The first differential difference amplifier provides a first amplified voltage, and the first output circuit provides the first output voltage based on the first amplified voltage. 10. The method of claim 9,
The kth amplifier circuit comprises a differential input terminal pair for receiving the k-1th feedback voltage and the kth feedback voltage.

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