KR102374046B1 - Flash memory device - Google Patents

Abstract

A flash memory device according to the present technology includes main bit lines crossing a memory cell area and a page buffer area, dummy bit lines arranged outside the main bit lines in parallel with the main bit lines; Main cell strings connected between a bit line and a common source line, dummy cell strings connected between the dummy bit line and the common source line, and between the main bit lines and the dummy bit lines, the common A conductive line including a first conductive line short electrically connected to a source line and a second conductive line short circuit electrically connected to the page buffer region, and a slit for cutting the dummy bit lines along a straight line perpendicular to the main bit line may include Each of the dummy bit lines may include a first dummy bit line short connected to the dummy cell string and a second dummy bit line short that is separated from the first dummy bit line short by the slit, wherein the first dummy bit The line short circuit may be disposed in a diagonal direction from the second conductive line short circuit.

Description

Flash memory device {FLASH MEMORY DEVICE}

The present invention relates to a flash memory device.

A flash memory device is a memory device in which stored data is maintained even when power supply is cut off. Recently, as the degree of integration of a two-dimensional flash memory device has reached its limit, a three-dimensional flash memory device in which a plurality of memory cells are vertically stacked on a silicon substrate has been variously proposed.

SUMMARY Embodiments of the present invention provide a flash memory device capable of preventing current leakage.

In a flash memory device according to an embodiment of the present invention, main bit lines crossing a memory cell area and a page buffer area, and dummy bit lines arranged in parallel with the main bit lines outside the main bit lines and main cell strings connected between the main bit line and a common source line, dummy cell strings connected between the dummy bit line and the common source line, and between the main bit lines and the dummy bit lines. a conductive line disposed and comprising a first conductive line short electrically connected to the common source line and a second conductive line short circuit electrically connected to the page buffer region; and the dummy bit line along a straight line perpendicular to the main bit line It may include a slit for cutting them. Each of the dummy bit lines may include a first dummy bit line short connected to the dummy cell string and a second dummy bit line short that is separated from the first dummy bit line short by the slit, wherein the first dummy bit The line short circuit may be disposed in a diagonal direction from the second conductive line short circuit.

According to the present technology, current leakage can be prevented and reliability of the flash memory device can be improved.

1 is a block diagram illustrating a flash memory device according to an embodiment of the present invention.
2 is a layout diagram illustrating a main bit line, a dummy bit line, a conductive line, and a common source line of a flash memory device according to an embodiment of the present invention.
3 is a perspective view illustrating a main cell string.
FIG. 4 is a circuit diagram of the main cell string shown in FIG. 3 .
5 is a circuit diagram of a dummy cell string.
6 is a page buffer circuit diagram of a high voltage page buffer area.
7 is a diagram illustrating an erase process of a flash memory device according to the present invention.

Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.

1 is a block diagram illustrating a flash memory device according to an embodiment of the present invention.

Referring to FIG. 1 , the flash memory device may include a memory cell area CELL and page buffer areas PB_HV and PB_LV. A plurality of memory blocks BLK0 to BLKn may be formed in the memory cell region CELL, and each of the memory blocks BLK0 to BLKn may include a plurality of cell strings (not shown). . The configuration of the cell string will be described later with reference to FIGS. 3 to 4 .

A plurality of page buffers (not shown) may be formed in the page buffer areas PB_HV and PB_LV. The page buffers may temporarily store data to be stored in the memory cells of the cell string or sense data stored in the memory cells of the cell string according to the operation mode. The page buffers may operate as a write driver circuit in a program operation mode, and may operate as a sense amplifier circuit in a read operation mode. A single bit line or bit line pairs may be respectively connected to the page buffers.

The page buffer regions PB_HV and PB_LV may include a high voltage page buffer region PB_HV in which a high voltage transistor operating at a high voltage is disposed and a low voltage page buffer region PB_LV in which a low voltage transistor operating at a low voltage is disposed.

2 is a layout diagram illustrating bit lines BL, dummy bit lines DBL, a conductive line ML, and a common source line CSL of a flash memory device according to an embodiment of the present invention.

Referring to FIG. 2 , the bit lines BL are arranged in parallel in a direction crossing the memory cell region CELL and the page buffer regions PB_HV and PB_LV. Although not shown, the bit lines BL may be respectively connected to cell strings (not shown) formed in the memory cell region CELL.

During the photoresist exposure process for forming the bit lines BL, the photoresist line pattern disposed inside has a uniform line width CD due to the optical proximity effect, but the photoresist line pattern disposed on both left and right edges has a non-uniform line width. When a bit line is formed using such a photoresist line pattern, the line width of the bit line at both edges becomes larger than the line width of the inner bit line. In order to improve the line width non-uniformity of the bit lines, dummy bit lines DBL that are not used to transmit valid data are disposed at both left and right outer sides of the bit lines BL.

The dummy bit lines DBL may cross the memory cell area CELL and the page buffer areas PB_HV and PB_LV in a direction parallel to the bit lines BL on the same layer as the bit lines BL. The dummy bit lines DBL may be formed on both left and right sides of the bit lines BL by the number (eg, 16) of memory cells included in a single string, respectively.

Meanwhile, although not shown, a plurality of dummy cell strings may be formed on both left and right edges of the cell strings in the memory cell region CEL, and the dummy bit lines DBL are respectively provided to the dummy cell strings. can be connected The configuration of the dummy cell string will be described later with reference to FIG. 5 .

Hereinafter, a bit line BL will be defined as a main bit line as a relative concept of the dummy bit line DBL, and a cell string will be defined as a main cell string as a relative concept of a dummy cell string.

3 is a perspective view illustrating a main cell string, and FIG. 4 is a circuit diagram of the main cell string shown in FIG. 3 .

3 and 4 , a pipe gate PG having a recess portion is formed on a semiconductor substrate (not shown), and a pipe channel layer PC is formed in the recess portion of the pipe gate PG. A pair of vertical channel layers SP1 and SP2 may be formed on the pipe channel layer PC. The vertical channel layers SP1 and SP2 may be formed of polysilicon. Among the pair of vertical channel layers, an upper portion of the first vertical channel layer SP1 is connected to the common source line CSL, and an upper portion of the second vertical channel layer SP2 is connected to the main bit line BL.

A plurality of conductive layers SSL, WL0 to WLk are formed to surround the first vertical channel layer SP1 at different heights of the first vertical channel layer SP1 , and the second vertical channel layer SP2 is formed with each other at different heights. A plurality of conductive layers DSL, WLn to WLk+1 may be formed to surround the second vertical channel layer SP2 at different heights. A multilayer film (not shown) including a charge storage film may be formed on the surfaces of the vertical channel layers SP1 and SP2 and the pipe channel layer PC. The multilayer film is also located between the vertical channel layers SP1 and SP2 and the conductive films DSL, WLn to WLk+1, SSL, WL0 to WLk, and also between the pipe channel layer PC and the pipe gate PG. can do.

The uppermost conductive layer surrounding the first vertical channel layer SP1 becomes the source select line SSL, and the conductive layers under the source select line SSL become the word lines WL0 to WLk. In addition, the uppermost conductive layer surrounding the second vertical channel layer SP2 becomes the drain select line DSL, and the conductive layers under the drain select line DSL become the word lines WLn to WLk+1. In other words, first conductive layers SSL, WL0 to WLk and second conductive layers DSL, WLn to WLk+1 are stacked on different regions of the semiconductor substrate, and the first conductive layers SSL and WL0 A first vertical channel layer SP1 penetrating through to WLk is vertically connected between the common source line CSL and the pipe channel layer PC, and connects the second conductive layers DSL and WLn to WLk+1. A penetrating second vertical channel layer SP2 is vertically connected between the main bit line BL and the pipe channel layer PC.

The source select transistor SST is formed in a portion where the source select line SSL surrounds the first vertical channel layer SP1 , and in a portion where the word lines WL0 to WLk surround the first vertical channel layer SP1 , Memory cells C0 to Ck are respectively formed. The drain select transistor DST is formed in a portion where the drain select line DSL surrounds the second vertical channel layer SP2 , and the word lines WLn to WLk+1 surround the second vertical channel layer SP2 . In the portion, memory cells Cn to Ck+1 are respectively formed.

With the above structure, the U-shaped channel layer comprising the pipe channel layer PC and the first and second vertical channel layers SP1 and SP2 formed on the pipe channel layer PC, the main bit line BL, and the A drain select transistor DST vertically connected between the pipe channel layer PC, the memory cells Cn to Ck+1, and a source vertically connected to the substrate between the common source line CSL and the pipe channel layer PC It may include a selection transistor SST and memory cells C0 to Ck. Data input from the page buffer may be stored in the memory cells C0 to Ck and Cn to Ck+1 included in the main cell string ST.

5 is a diagram for describing a dummy cell string DST.

Referring to FIG. 5 , the dummy cell string DST will be described with reference to FIGS. 3 and 4 except that the drain select transistor DST is connected to the dummy bit line DBL instead of the main bit line BL. It has substantially the same structure as the main cell string ST. That is, the dummy cell string DST includes the drain select transistor DST vertically connected to the substrate between the dummy bit line DBL and the pipe channel layer, the dummy cells Dn to Dk+1, and the common source line CSL. and a source select transistor SST and dummy cells D0 to Dk vertically connected to the substrate between the pipe channel layer. The dummy cells D0 to Dk and Dn to Dk+1 included in the dummy cell string DST are not used for effective storage of data.

6 is a page buffer circuit diagram of the high voltage page buffer region PB_HV.

Referring to FIG. 6 , the page buffer PB may include the high voltage transistor NM1 in the high voltage page buffer region PB_HV. The high voltage transistor NM1 may be used to separate the main bit line BL from a transistor (not shown) formed in the low voltage page buffer region PB_LV. The high voltage transistor NM1 may electrically connect the main bit line BL to the transistor formed in the low voltage page buffer region PB_LV in response to the blocking control signal BLSLT. In order to prevent the high erase bias voltage applied to the main bit line BL from being transferred to the transistor formed in the low voltage page buffer region PB_LV during the erase operation, the blocking control signal ( BLSLT), a low-level signal, for example, a voltage of 0V may be used.

Referring back to FIG. 2 , in the memory cell region CELL, the common source line CSL includes the main bit lines BL and It may be disposed in a direction substantially perpendicular to the dummy bit lines DBL.

In addition, in the layer in which the main bit lines BL and the dummy bit lines DBL are disposed, the main bit lines BL and the dummy bit lines are disposed between the main bit lines BL and the dummy bit lines DBL. The conductive lines ML may be disposed in a direction parallel to the DBLs. That is, the main bit lines BL, the dummy bit lines DBL, and the conductive line ML cross the memory cell region CELL and the page buffer regions PB_HV and PB_LV and may be disposed in parallel with each other. For simplicity of the drawing, although only one conductive line ML is illustrated in FIG. 2 , there may be two or more conductive lines ML.

The conductive line ML may be cut by a cutting process in the page buffer region, more specifically, in the high voltage page buffer region PB_HV, to have the cut portion CUT1 . That is, the conductive line ML may include a first conductive line short ML1 and a second conductive line short ML2 separated by the cutting part CUT1 .

The first conductive line short ML1 is disposed across the memory cell region CELL and the high voltage page buffer region PB_HV, and is electrically connected to the common source line CSL in the memory cell region CELL through the contact CNT1 . can be connected The first conductive line short circuit ML1 may be electrically connected to a predetermined voltage source (not shown) providing a common source voltage, and may transmit the common source voltage provided from the voltage source to the common source line CSL.

The second conductive line short ML2 is disposed across the high voltage page buffer region PB_HV and the low voltage page buffer region PB_LV, and is controlled by a transistor disposed in the high voltage page buffer region PB_HV or the low voltage page buffer region PB_LV It can carry a signal or a bias voltage.

For example, the second conductive line short ML2 connects a predetermined voltage source (not shown) providing the cutoff control signal BLSLT and the gate of the high voltage transistor NM1 (refer to FIG. 6 ) disposed in the high voltage page buffer region PB_HV. It may be electrically connected, and the blocking control signal BLSLT provided from the voltage source may be transmitted to the gate of the high voltage transistor NM1 . Meanwhile, the second conductive line short ML2 may electrically connect a predetermined voltage source (not shown) providing a ground bias voltage and a transistor formed in the high voltage page buffer region PB_HV or the low voltage page buffer region PB_LV, The ground bias voltage provided from the voltage source may be transferred to the transistor formed in the high voltage page buffer region PB_HV or the low voltage page buffer region PB_LV.

And, in order to use the control signal or the bias voltage to be transmitted to the transistor of the high voltage page buffer region PB_HV or the low voltage page buffer region PB_LV, the main bit lines BL are connected to the high voltage page buffer region PB_HV or the low voltage page buffer region. The region PB_LV may be cut by a cutting process to have the cut portion CUT2 .

As the degree of integration of the flash memory device increases, the size and spacing of patterns constituting the memory device are decreasing. As a technique for reducing the size and spacing of the patterns, a spacer patterning technology (SPT) is used. The main bit lines BL, the dummy bit lines DBL, and the conductive line ML may also be formed based on the SPT method, and thus the main bit lines BL, the dummy bit lines DBL, and the conductive line ML. The line ML may have a fine size and spacing equal to or less than the limit resolution. However, as the gap is reduced, the breakdown voltage (BV) of the insulating film formed between adjacent lines is lowered, making it very vulnerable to current leakage.

In particular, a current leakage problem between the dummy bit lines DBL and between the dummy bit line DBL and the conductive line ML is becoming an issue due to a high erase bias voltage applied during an erase operation. will be described later with reference to

7 is a diagram illustrating an erase process of a flash memory device according to the present invention. For simplification of the drawing, only one main cell string ST and one dummy cell string DST connected to the common source line CSL are illustrated in FIG. 7 , but a plurality of main cell strings are connected to the common source line CSL. It should be understood that the (STs) and the plurality of dummy cell strings (DST) are connected.

In order to extract electrons injected into the charge storage layers of the memory cells C0 to Ck and Ck+1 to Cn of the main cell string ST during the erase operation, an erase bias voltage is applied to the common through the first conductive line short ML1. It is applied to the source line CSL. A high voltage of about 23.5V is used as the erase bias voltage.

Since the dummy bit line DBL is connected to the common source line CSL through the U-shaped channel of the dummy cell string DST, the erase bias voltage applied to the common source line CSL is applied to the dummy cell string DST. It will be transferred to the dummy bit line DBL through the U-shaped channel. Also, since the main bit line BL is also connected to the common source line CSL through the U-shaped channel of the main cell string ST, the erase bias voltage applied to the common source line CSL is the main cell string ST. ) will be transmitted to the main bit line BL through the U-shaped channel. At this time, in order to prevent the high erase bias voltage applied to the main bit line BL from being transferred to the transistor formed in the low-voltage page buffer region, a low level, for example, 0V cutoff control signal BLSLT (refer to FIG. 6 ) is applied to the second conductivity It may be provided to the gate of the high voltage transistor MN1 (refer to FIG. 6 ) formed in the high voltage page buffer region PB_HV through the line short ML2 .

That is, a voltage of 0V is applied to the second conductive line short circuit ML2 and a voltage of 23.5V is applied to the dummy bit line DBL, so that 23.5V is applied between the second conductive line short circuit ML2 and the dummy bit line DBL. A large potential difference is generated, which causes current leakage between the second conductive line short circuit ML2 and the dummy bit line DBL. When a current leakage occurs between the second conductive line short circuit ML2 and the dummy bit line DBL, an excessive current flows undesirably to the page buffer, which may cause a failure or malfunction of the page buffer. Therefore, it is necessary to prevent current leakage.

Referring back to FIG. 2 , the dummy bit lines DBL are cut at once in a straight line perpendicular to the bit lines BL and DBL by a wide cutting process in the high voltage page buffer region PB_HV to have a slit SLIT. . That is, the slit SLIT cuts the dummy bit lines DBL at once along a straight line perpendicular to the bit lines BL and DBL. Also, as the dummy bit lines DBL are divided by the slit SLIT, each of the dummy bit lines DBL has first and second dummy bit line short circuits DBL1 and DBL2.

The first dummy bit line short DBL1 is disposed over the memory cell area CELL and the high voltage page buffer area PB_HV, and is electrically connected to the dummy cell string formed in the memory cell area CELL. The first dummy bit line short DBL1 faces the first conductive line short ML1 in a direction perpendicular to the bit lines BL and DBL and faces the second conductive line short ML2 in a diagonal direction. can be placed. To this end, the slit SLIT may be disposed closer to the memory cell region CELL than the cut portion CUT1 provided in the conductive line ML. That is, the distance between the memory cell region CELL and the slit SLIT may be shorter than the distance between the memory cell region CELL and the cutting part CUT1 .

Since the first dummy bit line short DBL1 faces the second conductive line short ML2 in a diagonal direction, a sufficient distance between the first dummy bit line short DBL1 and the second conductive line short ML2 can be secured. Therefore, current leakage can be prevented even when a large potential difference is generated between the first dummy bit line short circuit DBL1 and the second conductive line short circuit ML2 .

Meanwhile, the second dummy bit line short DBL2 is disposed over the high voltage page buffer area PB_HV and the low voltage page buffer area PB_LV and may be electrically floating. The second dummy bit line short DBL2 may be disposed to face the second conductive line short ML2 in a direction perpendicular to the bit lines BL and DBL.

As the second dummy bit line short DBL2 and the second conductive line short ML2 are disposed to face each other in a direction perpendicular to the bit lines MBL and DBL, the second dummy bit line short DBL2 and the second conductivity The distance between the line shorts ML2 is shortened. However, the second dummy bit line short circuit DBL2 is in an electrically floating state, and the voltage applied to the second conductive line short circuit ML2 is a bias voltage or a control signal used for transistors formed in the page buffer regions PB_HV and PB_LV. Since it has a low voltage level, current leakage will not occur between the second dummy bit line short circuit DBL2 and the second conductive line short circuit ML2 .

In addition, since the dummy bit lines DBL are cut at once along a straight line perpendicular to the bit lines BL and DBL, the first dummy bit line short DBL1 and the second dummy bit line short DBL2 are connected to the bit line ( DBL2 ). BL and DBL do not face each other in a direction perpendicular to each other, and a distance between the first dummy bit line short DBL1 and the second dummy bit line short DBL2 is secured. Accordingly, current leakage due to the high erase bias voltage applied to the first dummy bit line short-circuit DBL1 will not occur during the erase operation.

As described above, according to the present exemplary embodiment, current leakage in the page buffer area can be prevented, thereby preventing current leakage and resulting page buffer failure, and furthermore, the reliability of the flash memory device can be improved.

In the detailed description of the present invention described above, although it has been described with reference to the embodiments of the present invention, those skilled in the art or those having ordinary knowledge in the technical field will It will be understood that various modifications and variations of the present invention can be made without departing from the technical scope.

BL: main bit line
DBL: dummy bit line
ML: Challenge Line
ML1, ML2: Shorting the first and second conductive lines
DBL1, DBL2: Shorting the first and second dummy bit lines
CSL: Common Source Line
SLIT: slit

Claims (15)

main bit lines crossing the memory cell area and the page buffer area;
dummy bit lines arranged in parallel with the main bit lines outside the main bit lines;
main cell strings connected between the main bit line and a common source line;
dummy cell strings connected between the dummy bit line and the common source line;
a conductive line disposed between the main bit lines and the dummy bit lines and including a first conductive line short electrically connected to the common source line and a second conductive line short circuit electrically connected to the page buffer region;
a slit for cutting the dummy bit lines along a straight line perpendicular to the main bit line in the page buffer area;
Each of the dummy bit lines includes a first dummy bit line short connected to the dummy cell string and a second dummy bit line short separated from the first dummy bit line short by the slit,
The conductive line includes a cutting part dividing the short circuit between the first conductive line and the second conductive line, and a distance between the memory cell region and the slit is shorter than a distance between the memory cell region and the cutting part. memory device. ◈Claim 2 was abandoned when paying the registration fee.◈ The flash memory device of claim 1 , wherein the main bit lines, the dummy bit lines, and the conductive line are disposed on the same layer. ◈Claim 3 was abandoned when paying the registration fee.◈ The flash memory device of claim 1 , wherein the common source line is disposed on a different layer than the conductive line, and the common source line is electrically connected to the first conductive line short through a contact. ◈Claim 4 was abandoned when paying the registration fee.◈ The flash memory device of claim 1 , wherein the first conductive line short is disposed over the memory cell area and the page buffer area, and the second conductive line short is disposed over the page buffer area. ◈Claim 5 was abandoned when paying the registration fee.◈ 5. The method of claim 4, wherein the page buffer region comprises a high voltage page buffer region in which a high voltage transistor is disposed and a low voltage page buffer region in which a low voltage transistor is disposed;
The first conductive line short is disposed over the memory cell area and the high voltage page buffer area, and the second conductive line short is disposed over the high voltage page buffer area and the low voltage page buffer area. ◈Claim 6 was abandoned when paying the registration fee.◈ The flash memory device of claim 1 , wherein the second conductive line short circuit is electrically connected to a voltage source that provides a bias voltage to the page buffer region. ◈Claim 7 was abandoned at the time of payment of the registration fee.◈ The flash memory device of claim 6 , wherein the second conductive line short circuit is electrically connected to a voltage source providing a ground bias voltage to the page buffer region. ◈Claim 8 was abandoned when paying the registration fee.◈ The flash memory device of claim 1 , wherein the second conductive line short circuit is electrically connected to a voltage source providing a control signal to the page buffer region. ◈Claim 9 was abandoned at the time of payment of the registration fee.◈ The method of claim 8 , wherein the page buffer region comprises a high voltage page buffer region in which a high voltage transistor is disposed and a low voltage page buffer region in which a low voltage transistor is disposed,
The second conductive line short circuit is electrically connected to a voltage source providing a cutoff control signal to a gate of a high voltage transistor connected between the main bit line and the low voltage page buffer region. ◈Claim 10 was abandoned when paying the registration fee.◈ The flash memory device of claim 1 , wherein the first dummy bit line short is disposed over the memory cell area and the page buffer area, and the second dummy bit line short is disposed over the page buffer area. ◈Claim 11 was abandoned when paying the registration fee.◈ The flash memory device of claim 1 , wherein the second dummy bit line short is electrically floated. ◈Claim 12 was abandoned when paying the registration fee.◈ The method of claim 1, wherein each of the main cell strings comprises a U-shaped channel layer and a plurality of memory cells connected along the U-shaped channel layer, and each of the dummy cell strings comprises a U-shaped channel layer and a U-shaped channel layer. Accordingly, a flash memory device including a plurality of connected dummy memory cells; ◈Claim 13 was abandoned when paying the registration fee.◈ The flash memory device of claim 1 , wherein the main bit lines, the dummy bit lines, the conductive line, and the common source line are disposed on the main cell string and the dummy cell string. delete delete

Images