KR102358352B1 - Modeling method and apparatus for memristor device - Google Patents

Abstract

The present invention relates to a method and apparatus for modeling a memristor element. In the modeling method of a memristor device according to an embodiment of the present invention, resistance switching of a resistance change occurs according to an applied voltage between a lower electrode provided on a substrate, and an upper electrode and a lower electrode, and is provided on the lower electrode and IGZO A modeling method for a memristor device comprising a switching material layer including a switching material layer, and an upper electrode provided on the switching material layer, respectively, in which resistance switching occurs according to a change in a Schottky barrier height (SBH), the SBH modeling the change as a stretched exponential function (SEF).

Description

Modeling method and apparatus for memristor device

The present invention relates to a modeling method and apparatus for a memristor element, and more particularly, to a modeling method and apparatus capable of implementing a model for a memristor element in an electronic circuit simulation such as SPICE.

The computing system developed so far consists of a von-Neumann architecture in which a memory, a processor, and a controller are separately present, and has been developed through arithmetic and logic devices using semiconductor materials and integration of the memory devices. For example, most digital and analog circuits of the memory and processing unit may be configured to include a complementary metal-oxide-semiconductor (CMOS) device. According to the performance improvement of computing and information technology, it is possible to effectively reduce power consumption while increasing the operating frequency based on the permanent scaling down of such CMOS devices.

However, compared to the system improvement request which requires continuous improvement of the integration density, it has almost reached a limit in increasing the integration degree of the device. That is, the degree of integration of the latest CMOS devices and the like does not follow Moore's Law, and its scaling down is also rapidly reaching its physical limit.

In addition, in a more complex information processing environment and an environment requiring high-density information storage, the conventional von Neumann system has a limitation in performance improvement due to delay in signal transmission between a logic element and a memory element, and a problem of high energy consumption. have. That is, the performance of the von Neumann system may be severely degraded due to the time and energy required to transfer data between the memory and the processor while power consumption and operating temperature increase due to an increase in operating frequency and device density. This phenomenon is particularly noticeable in data-driven applications such as real-time image recognition and natural language processing, and von Neumann systems in these applications cannot outperform the human brain.

Unlike the von Neumann system, the human brain has the characteristic of simultaneously performing computational and memory functions through synapses as well as parallel processing capabilities using high connectivity. In other words, there are about 10 ¹¹ neurons in the human brain, which act as a low-power computing element, and about 10 ⁴ synapses exist between each neuron and neurons, which act as an adaptive memory element. , it is possible to process massive amounts of information in parallel through a massively parallel structure in which they are connected. As a result, the von Neumann system performs better than the human brain in simple calculations, but the human brain performs better in complex environments such as unstructured data classification and pattern recognition.

Therefore, in a complex information processing environment, a neuromorphic computing system simulating a human brain may show better performance than a von Neumann system. Such a neuromorphic computing system may be implemented as a synaptic device and a neural circuit made of electronic devices. For example, a pneumatic computing system can mimic the massively parallel and extremely low-power operation found in the human brain through an ultra-dense crossbar array of memristor elements.

On the other hand, the memristor element operates as an electrical resistance switch (resistive switch) capable of maintaining the state of the internal resistance based on the history of the applied voltage and current. In other words, memristor devices can store and process information, and provide several performance characteristics that outperform conventional integrated circuit technologies. For example, a memristor element may consist of a stack of conductor-insulator-conductor, and for large-scale applications, it may be used in the form of a crossbar array. Such a memristor device has a large geometrical similarity to a biological synapse, so it can serve as a synaptic device of a crossbar array in a pneumomorphic computing system. That is, a change in signal conductivity in a biological synapse may be similarly implemented as a change in electrical conductivity in a synaptic device or a change in synaptic weight.

In order to obtain analog switching characteristics that provide multi-level definable weights in memristor devices, vigorous efforts have been made with special attention to the materials of the switching layer. In particular, in the case of a ternary or higher metal oxide material (hereinafter referred to as “the material of the back”) such as IGZO (indium-gallium-zinc-oxide), high carrier mobility, high uniformity of thin film manufacturing, transparency, and low heat budget process Due to integration and the like, it can be widely applied to flexible electronic products, wearable health care systems, biosensors and displays, and the like, as well as logic and memory devices with high cost-effectiveness.

A material such as IGZO may be applied as a switching layer in a memristor device for a neuromorphic computing system. In this case, for high-density array and system level verification, a compact model for applying a memristor device to which a material such as IGZO is applied as a switching layer to an electronic circuit simulation such as SPICE is absolutely necessary. . However, until now, a model for a memristor device to which such IGZO or the like is applied has not been developed. This is because modeling of a memristor device to which IGZO, etc. is applied can only be derived based on an understanding of the main mechanism that determines resistance switching characteristics and conduction behavior, but the mechanism is not known yet. to be.

KR 10-2013-0061743 A

An object of the present invention is to provide a modeling method and apparatus capable of implementing a model for a memristor element in an electronic circuit simulation such as SPICE.

However, the problems to be solved by the present invention are not limited to the problems mentioned above, and other problems not mentioned can be clearly understood by those of ordinary skill in the art to which the present invention belongs from the description below. There will be.

In the modeling method of a memristor device according to an embodiment of the present invention for solving the above problems, resistance switching of a resistance change occurs according to an applied voltage between a lower electrode provided on a substrate, and an upper electrode and a lower electrode, A memristor that is provided on the lower electrode and includes a switching material layer including IGZO and an upper electrode provided on the switching material layer, and in which resistance switching occurs according to a change in Schottky barrier height (SBH). A modeling method for a device, comprising: modeling an SBH change as a stretched exponential function (SEF).

In the memristor device, an SBH change may occur as electrons are trapped/detrapped in an oxygen vacancy formed at an interface between the lower electrode and the switching material layer.

The generation of the oxygen vacancies may be affected by Ar ion bombardment when the switching material layer is formed by sputtering on the lower electrode.

The expression according to the SEF may include an expression of a first SEF indicating a change in SBH that increases with time, and an expression of a second SEF indicating a change in SBH that decreases with time.

The equation of the first SEF may be expressed by the following equation (2), and the equation of the second SEF may be expressed as the following equation (3).

where ΔΦ _Bi is the time- and voltage-dependent SBH change, ΔΦ _B0i is the time- and voltage-dependent maximum SBH change, t is the time, and τ _si is the characteristic time constant in the SET operation for the voltage-dependent SBH change ( characteristic time constant), τ _ri is the characteristic time constant in the reset (RESET) operation for voltage-dependent SBH changes, β _si is the stretching exponent in the set operation for SBH changes, β _ri is the reset for SBH changes Each represents a stretching exponent in operation, where i is expressed as 1 or 2, but i=1 is an indication related to the change occurring at the interface between the upper electrode and the switching material layer when V<0, i= 2 is an indication related to the change occurring at the interface between the switching material layer and the lower electrode when V>0.

The modeling method of a memristor device according to an embodiment of the present invention further includes modeling the hot electron emission generated from a Schottky contact between a switching material layer and a main electrode as a mechanism in which conduction of the memristor device occurs. can do.

The main electrode may be an electrode having a larger work function among the lower electrode and the upper electrode.

The modeling method of a memristor device according to an embodiment of the present invention further includes modeling the relationship between the current and the SBH for the memristor device using thermistor emission generated from the Schottky contact between the switching material layer and the main electrode. can do.

The method for modeling a memristor device according to an embodiment of the present invention may further include determining a value of a parameter included in the SEF.

In the determining step, the value of the parameter may be determined by using a mechanism in which conduction of the memristor element is generated by the emission of hot electrons generated in the Schottky contact between the switching material layer and the main electrode, wherein the main electrode is It may be an electrode having a larger work function among the lower electrode and the upper electrode.

In the determining, the value of the parameter may be determined by deriving a change in SBH with time using an equation representing the thermionic emission.

The formula representing the hot electron emission may be the following formula (1).

Here, I _mem is the current flowing in the memristor element 100, A is the cross-sectional area of the contact area between the main electrode and the switching material layer, A* is the Richardson constant, T is the absolute temperature, kT is the heat Energy, q is electric charge, E is electric field, and Φ _B is SBH.

The modeling method of the memristor device according to an embodiment of the present invention uses the determined parameter value and the conduction characteristic of the memristor according to the hot electron emission for the memristor device, and the current change according to voltage or current according to time It may further include the step of performing a simulation of the change.

In the modeling apparatus of a memristor element according to an embodiment of the present invention, resistance switching of a resistance change occurs according to an applied voltage between a lower electrode provided on a substrate, and an upper electrode and a lower electrode, and is provided on the lower electrode and IGZO A modeling device for a memristor device including a switching material layer including a switching material layer, and an upper electrode provided on the switching material layer, respectively, in which resistance switching occurs according to a change in a Schottky barrier height (SBH), the SBH The change is modeled as a stretched exponential function (SEF).

The apparatus for modeling a memristor element according to an embodiment of the present invention may determine a value of a parameter included in an SEF, store a predetermined value of the parameter, or receive a predetermined value of the parameter from another device. have.

The Equation according to the SEF may include Equation (2), which represents a change in SBH that increases with time, and Equation (3) below, which represents a change in SBH that decreases with time.

where ΔΦ _Bi is the time- and voltage-dependent SBH change, ΔΦ _B0i is the time- and voltage-dependent maximum SBH change, t is the time, and τ _si is the characteristic time constant in the SET operation for the voltage-dependent SBH change ( characteristic time constant), τ _ri is the characteristic time constant in the reset (RESET) operation for voltage-dependent SBH changes, β _si is the stretching exponent in the set operation for SBH changes, β _ri is the reset for SBH changes Each represents a stretching exponent in operation, where i is expressed as 1 or 2, but i=1 is an indication related to the change occurring at the interface between the upper electrode and the switching material layer when V<0, i= 2 is an indication related to the change occurring at the interface between the switching material layer and the lower electrode when V>0.

The value of the parameter may be determined using a mechanism in which conduction of the memristor element is generated by hot electron emission generated in a Schottky contact between the switching material layer and the main electrode, wherein the main electrode is a lower electrode and an upper electrode It may be an electrode having a larger work function.

The value of the parameter can be determined by deriving the change in SBH with time using Equation (1), which represents thermionic emission.

Here, I _mem is the current flowing in the memristor element 100, A is the cross-sectional area of the contact area between the main electrode and the switching material layer, A* is the Richardson constant, T is the absolute temperature, kT is the heat Energy, q is electric charge, E is electric field, and Φ _B is SBH.

The apparatus for modeling a memristor element according to an embodiment of the present invention uses the determined parameter value and the conduction characteristic of the memristor according to the hot electron emission for the memristor element, the current change according to voltage or current according to time Change simulations can be performed.

The present invention configured as described above can accurately and simply implement a model for a memristor element in an electronic circuit simulation such as SPICE, and thus has an advantage that can be utilized for high-density arrays and system-level verification.

The effects obtainable in the present invention are not limited to the above-mentioned effects, and other effects not mentioned may be clearly understood by those of ordinary skill in the art to which the present invention belongs from the following description. will be.

1 shows the configuration of a memristor device 100 according to an embodiment of the present invention.
2 shows a process process of the actually fabricated memristor device 100 according to an embodiment of the present invention.
3 is a circuit diagram of the fabricated samples A and B, and the measured current-voltage (IV) characteristics are shown.
4 shows the mechanism of resistance switching.
5 shows the linear fitting results for the manufactured samples A and B.
6 shows a change in Schottky barrier height (SBH) with time.
7 shows the dependence of the parameters of the memristor device 100 on the voltage of the upper electrode TE.
8 shows a comparison between the measurement results for samples A and B and the SPICE simulation results through modeling for them.

The above object and means of the present invention and its effects will become more apparent through the following detailed description in relation to the accompanying drawings, and accordingly, those of ordinary skill in the art to which the present invention pertains can easily understand the technical idea of the present invention. will be able to carry out In addition, in describing the present invention, if it is determined that a detailed description of a known technology related to the present invention may unnecessarily obscure the gist of the present invention, the detailed description thereof will be omitted.

The terminology used herein is for the purpose of describing the embodiments, and is not intended to limit the present invention. In the present specification, the singular form also includes the plural form as the case may be, unless otherwise specified in the phrase. In this specification, terms such as “include”, “provide”, “provide” or “have” do not exclude the presence or addition of one or more other components other than the mentioned components.

In this specification, terms such as “or” and “at least one” may indicate one of the words listed together, or a combination of two or more. For example, “or B” and “at least one of B” may include only one of A or B, or both A and B.

In the present specification, descriptions according to “for example” and the like may not exactly match the information presented, such as recited properties, variables, or values, tolerances, measurement errors, limits of measurement accuracy, and other commonly known factors The embodiments of the present invention according to various embodiments of the present invention should not be limited by effects such as modifications including .

In this specification, when it is described that a certain element is 'connected' or 'connected' to another element, it may be directly connected or connected to the other element, but other elements may exist in between. It should be understood that there may be On the other hand, when it is mentioned that a certain element is 'directly connected' or 'directly connected' to another element, it should be understood that the other element does not exist in the middle.

In this specification, when it is described that a certain element is 'on' or 'in contact with' another element, it may be directly in contact with or connected to the other element, but another element may exist in the middle. It should be understood that On the other hand, when it is described that a certain element is 'directly on' or 'directly' of another element, it may be understood that another element does not exist in the middle. Other expressions describing the relationship between the elements, for example, 'between' and 'directly between', etc. may be interpreted similarly.

In this specification, terms such as 'first' and 'second' may be used to describe various components, but the components should not be limited by the above terms. In addition, the above terms should not be construed as limiting the order of each component, and may be used for the purpose of distinguishing one component from another. For example, a 'first component' may be referred to as a 'second component', and similarly, a 'second component' may also be referred to as a 'first component'.

Unless otherwise defined, all terms used herein may be used with meanings commonly understood by those of ordinary skill in the art to which the present invention pertains. In addition, terms defined in a commonly used dictionary are not to be interpreted ideally or excessively unless specifically defined explicitly.

Hereinafter, a preferred embodiment according to the present invention will be described in detail with reference to the accompanying drawings.

1 shows the configuration of a memristor device 100 according to an embodiment of the present invention.

The memristor device 100 according to an embodiment of the present invention is a device capable of resistive switching (RS), and as shown in FIG. 1 , a substrate 10 , a lower electrode 20 , and a switching material layer 30 and the second electrode 40 may be included, and they may have a structure in which they are sequentially stacked. The memristor device 100 may be a two-terminal device with a lower electrode 20 and an upper electrode 40 .

The substrate 10 is a base for supporting the remaining components, and may be made of Si. For example, it may be formed of a high concentration of P-type Si (p ⁺ Si). In this case, the substrate 10 may act as a conductive substrate.

The bottom electrode (BE) 20 includes a conductive material and is provided on the substrate 10 . A common voltage such as ground may be applied to the lower electrode 20 . For example, the lower electrode 20 includes at least one material selected from Cu, Ni, Ti, Hf, Zr, ZN, W, Co, V, Al, Ag, C, Pd, Pt, Mo, ITO, etc. function, but is not limited thereto.

The switching material layer 30 includes an oxide material and is provided on the lower electrode 20 . The switching material layer 30 may act as a switching layer, that is, a memristor layer. That is, the switching material layer 30 may have a resistance change according to the applied voltage between the first and second electrodes 20 and 40 , and may have a characteristic of storing the changed resistance value according to the applied voltage.

In addition, the switching material layer 30 may form a Schottky barrier (SB) at an interface with the lower electrode 20 and an interface with the upper electrode 40 , respectively. Such a Schottky barrier may act as a kind of tunnel barrier. At this time, the switching material layer 30 affects the effective SB height (Schottky Barrier height, SBH) (Φ _B ) according to the oxygen content so that various resistive switching (RS) is possible. material may be included.

For example, the switching material layer 30 may include a metal oxide material of three or more elements, such as IGZO, ITZO, IWZO, ZSO, IZO, and IGO, capable of integrating a transistor and a memory using a single material. However, the present invention is not limited thereto. In particular, the IGZO material can be fabricated on a flexible substrate, and can act as RS and active film in memristors and thin-film transistors, respectively. This suggests that it is possible to integrate synaptic arrays as well as peripheral circuits, including neurons, into monolithic integration using a single material.

However, when the switching material layer 30 is made of a metal oxide material of three or more elements, particularly IGZO, the mechanism for determining the resistance switching characteristics and conduction behavior of the memristor device 100 is still known. there wasn't Accordingly, in the present invention, based on an understanding of the mechanism of the memristor element 100 to be described later, it is intended to implement modeling of the corresponding memristor element 100 in an electronic circuit simulation such as SPICE.

A top electrode (TE) 40 includes a conductive material and is provided on the switching material layer 30 . A voltage having a potential difference of V _TE with respect to the lower electrode 20 may be supplied to the upper electrode 40 . That is, V _TE may also be referred to as a voltage supplied to the upper electrode 40 when the lower electrode 20 is connected to the ground. For example, the upper electrode 40 includes at least one material selected from Cu, Ni, Ti, Hf, Zr, ZN, W, Co, V, Al, Ag, C, Pd, Pt, Mo, ITO, etc. function, but is not limited thereto.

Meanwhile, a conductive protective layer (not shown) may be provided on the upper electrode 40 . That is, the conductive protective layer includes a conductive material and is provided on the upper electrode 40 to protect the upper electrode 40 . In this case, it may be preferable that the conductive protective layer be made of a high-conductivity metal material that has a low metal reactivity to prevent oxidation of the upper electrode 40 in air and facilitates charge flow according to an applied voltage. For example, the conductive protective layer 50 may include at least one material selected from Au, Pt, Ag, and the like, but is not limited thereto.

<Production of Memristor (100)>

2 shows a process process of the actually fabricated memristor device 100 according to an embodiment of the present invention.

For an experiment to understand the mechanism for determining the resistance switching characteristics and conduction behavior of the memristor element 100, the memristor element 100 was actually manufactured according to the process of FIG. 2 . At this time, FIGS. 2(a) to 2(d) shows a process in which the substrate 10, the lower electrode 20, the switching material layer 30, and the upper electrode 40 are sequentially formed, and FIG. 2(e) is shown in FIGS. 2(a) to 2 A memristor element 100a (hereinafter referred to as “Sample A”) formed according to (d) is shown, and FIG. 2(f) is a lower electrode 20 according to FIGS. 2(a) to 2(d) and A memristor element 100b (hereinafter, referred to as “Sample B”) formed in which the material of the upper electrode 40 is exchanged is shown.

Hereinafter, for convenience, in Samples A and B of the drawings and description, the substrate 10 may be omitted or denoted as Si, while the lower electrode 20 is made of BE or a corresponding material (ie, Mo or Pd), and the upper The electrode 40 can be denoted by TE or a corresponding material (ie, Pd or Mo), and the switching material layer 30 can be denoted by IGZO, respectively. Also, the memristor device 100 may be denoted as TE/IGZO/BE depending on its stack. That is, sample A may be represented by Pd(TE)/IGZO/Mo(BE), and sample B may be represented by Mo(TE)/IGZO/Pd(BE), respectively.

Specifically, samples A and B were prepared as follows. First, as shown in FIG. 2( a ), a Si substrate 10 was prepared and washed. At this time, a p ⁺ -Si substrate 10 having a doping concentration of 2x10 ¹⁹ cm ^-3 and a resistivity of 0.005 Ω·cm was prepared and initially cleaned for the next process. Then, as shown in FIG. 2( b ), BE of Mo having a thickness of about 100 nm was deposited on the Si substrate by performing E-beam evaporation. Of course, in sample B according to Fig. 2(f), BE of Pd was deposited. Then, as shown in Figure 2 (c), sputtering (sputtering) was performed to deposit a thickness of about 80nm IGZO. At this time, the gas mixture was Ar/O ² =3sccm/2sccm, and the RF power during the deposition process was 150W. Then, as shown in FIG. 2( d ), electron beam deposition using a shadow mask (M) was performed again to deposit about 100 nm thick TE of Pd on the IGZO. Of course, in sample B according to Fig. 2(f), BE of Mo was deposited.

To analyze the electrical properties of the fabricated samples A and B, a Keithley-4200 semiconductor characterization system (Tektronix) was used, and DC current-voltage (IV) properties were measured at room temperature and dark conditions. At this time, in all measurements, BE was connected to ground (0V), and V _TE in a voltage range of -9V to 9V was applied to TE, and the compliance current was set to 100nA to prevent failure. At this time, the voltage V _TE applied to the TE may be simply expressed as “V”, and the current flowing through the IGZO according to the V may be expressed as “I _mem ” or simply “I”.

<current characteristics and behavioral physics>

In order to implement a high-precision SPICE compact model for the memristor element 100 , an understanding of the mechanisms of resistance switching (RS) and conduction behavior of the memristor element 100 must be preceded.

3 is a circuit diagram for the fabricated samples A and B, and the measured current-voltage (I-V) characteristics are shown. That is, FIGS. 3(a) and 3(c) show the respective circuit diagrams of samples A and B, and FIGS. 3(b) and 3(d) are DC sweeps repeated 5 times for samples A and B. ), each IV characteristic measured according to However, in FIGS. 3(b) and 3(d) , each measurement result is displayed in a linear scale, but is displayed in a different color for different DC sweeps.

First, in order to understand the physical properties of conduction behavior, IV properties were obtained for the fabricated samples A and B, as shown in FIG. 3 . Samples A and B were found to perform SET and RESET operations at positive V _TE and negative V _TE , respectively.

It is highly likely that an interfacial oxide layer is respectively formed between the metal electrode and the oxide (switching layer) (ie, between TE/IGZO and between IGZO/BE). In this case, as the work function according to the type of metal of the electrode is lower, it tends to have a lower formation energy for oxidation thereof. This oxidation process may be accelerated or decelerated by an electric field according to an applied voltage during operation of the memristor element 100 . The interfacial layer of more abundant oxygen vacancy has a relatively low work function Mo (about 4.36 ~ 4.95 eV) than the interface of Pd/IGZO with a relatively high work function Pd (about 5.22 ~ 5.6 eV). ) can be more easily formed at the interface of Mo/IGZO with IGZO, which is a switching layer, can obtain a large number of electron capture/emission traps or ionized oxygen vacancies by an interfacial layer rich in oxygen vacancies (ie, an interfacial layer of Mo/IGZO). Accordingly, the Schottky barrier height (SBH) at the interface between Mo and IGZO is modulated (modulated) by electron trapping/de-trapping, or the number of ionized oxygen vacancies. can be modulated by a change in This process may lead to an analog synaptic operation while a set or reset is being performed.

When a positive bias is applied to the TE, electron detrapping occurs at the IGZO/BE interface, and negatively charged oxygen ions migrate from the IGZO/BE interface to the TE. A low-resistance state (LRS) may be established as TE and BE are connected by positively charged oxygen vacancies. On the other hand, when a negative bias is applied to the TE, the process occurs in the opposite direction to that described above, and a high-resistance state (HRS) may be established.

However, the mechanism of resistance switching does not occur solely due to the combination of these materials. That is, the more fundamental reason that the IGZO/BE interface and the TE/IGZO interface have different interface states lies in the processing technique. The IGZO/BE interface provided at the bottom is formed by IGZO sputtering performed on the BE. On the other hand, the TE/IGZO interface provided thereon is formed by electron beam deposition of TE performed on IGZO. In particular, while IGZO is deposited on the BE by sputtering, the effect of re-sputtered Ar ions from the source alternating the surface properties of the target, that is, the argon bombardment effect (Ar ion bombardment) occurs. Due to this, as shown in Figs. 3(b) and 3(d), only by changing the polarity of the DC sweep, the respective IV curves for samples A and B in which the metallic materials of BE and TE were exchanged appear identical to each other. does not

4 shows the mechanism of resistance switching. That is, Fig. 4(a) is a schematic diagram of ionic conduction, Fig. 4(b) is a schematic diagram of Schottky barrier height adjustment by oxygen vacancies, and Fig. 4(c) is a schematic diagram of Sample A at high compliance current. IV characteristic, Fig. 4(d) shows the IV characteristic of sample B at high compliance current, respectively.

The above-described resistance switching mechanism is schematically shown in Figs. 4(a) and 4(b). Of these two mechanisms, the more dominant one can be determined by the measurement results in a DC sweep with a high compliance current. That is, as the compliance current increases, electron trapping/de-trapping and oxygen ion migration at the IGZO/BE interface may be accelerated. As shown in Figs. 4(c) and 4(d), when the compliance current is high, in both samples A and B, only a set operation is observed in the positive TE voltage region. On the other hand, only in sample A, both set and reset operations are observed at this negative TE voltage. In the case of such complementary switching, there is an advantage in that a sneak current can be effectively suppressed in a cross array based on a device having two or more switching layers. In the resistive switching operation of prepared samples A and B, if oxygen ion migration was the only mechanism, complementary switching would not have been observed. Due to electron trapping and detrapping, resistive switching behavior occurred in both the IGZO/BE and TE/IGZO interfacial layers. That is, in Sample A, high SBH is formed at the Pd/IGZO (TE/IGZO) interface, and an ion bombardment effect occurs at the IGZO/Mo (IGZO/BE) interface. Therefore, the resistance switching characteristic can be strong at all interfaces (ie, TE/IGZO interface and IGZO/BE interface) in sample A. On the other hand, in sample B, a high SBH appears at the IGZO/Pd(IGZO/BE) interface, and an ion bombardment effect (also occurs, so that the SBH modulation can be further increased during the SET process. As a result, Only in sample A, high SBH and ion bombardment effects were applied to different interfaces (TE/IGZO interface and IGZO/BE interface), resulting in corresponding complementary switching characteristics.

5 shows the linear fitting results for the manufactured samples A and B. That is, FIG. 5(a) shows the corresponding result for the manufactured sample A, and FIG. 5(b) shows the corresponding result for the manufactured sample B, respectively.

In the prepared samples A and B, in order to understand the mechanism of conduction behavior, as shown in Figs. 5(a) and 5(b), linear fitting of semi-logarithmic scale This was done. Possible mechanisms involved in the conduction behavior of the memristor device 100 are thermionic emission, Poole-Frenkel (PF) emission, Ohmic conduction, and space charge-limited conduction (SCLC). Each can be classified. However, referring to FIGS. 5A and 5B , it is determined that the prepared samples A and B follow thermionic emission and PF emission more than the ohmic conduction and SCLC proportional to V and V ² , respectively. Since thermionic emission occurs with a large energy barrier, it is likely to be observed in trap-deficient regions, such as dielectrics. On the other hand, PF emission is analyzed as a trap site, that is, carrier hopping between conductive media. 5(a) and 5(b) show that the effective depletion width is smaller than the thickness of the IGZO deposited on the BE. According to the above-described measurement result and its physical characteristics, each of the following equations may be selected and specified to be applied to compact modeling.

<Compact modeling of the memristor device 100>

The main mechanism of conduction behavior derived from the above-described measurement results and physical properties is thermionic emission that occurs at the Schottky contact between IGZO and Pd (that is, an electrode with a higher work function metal). to be. The I-V characteristic of the memristor device 100 may be expressed by the following Equation (1) according to the Schottky barrier height (SBH) lowering effect.

Here, I _mem represents a current flowing through the memristor device 100 , and A represents a cross-sectional area of the memristor device 100 . In addition, A* is a Richardson constant, T is absolute temperature, kT is thermal energy, q is an electronic charge, E is an electric field, and Φ _B is SBH, respectively. For the SPICE compact model with high accuracy, the SBH change along with the mechanism of conduction and resistance switching of the memristor element 100 should be reflected in the corresponding model. In order to consider electron trapping/detrapping at trap defect sites, which is the mechanism of resistance switching, a stretched exponential function (SEF) is used in the following equations (2) and (3). did Equation (2) represents an increase in SBH with time, and Equation (3) represents a decrease in SBH over time.

Here, ΔΦ _Bi represents the time- and voltage-dependent SBH change, and ΔΦ _B0i represents the time- and voltage-dependent maximum SBH change. t denotes a present time spot, τ _si and τ _ri denote characteristic time constants in set and reset operations for voltage-dependent SBH changes, and β _si and β _ri denote SBH changes. Each of the stretching exponents in the set and reset operations for each is indicated. i=1 is related to the modulation (change) occurring at the TE/IGZO interface when V<0, and i=2 is related to the modulation (change) occurring at the IGZO/BE interface when V>0. Also, τ _si and β _si are parameters of a set operation, and τ _ri and β _ri are parameters of a reset operation. Equations (2) and (3) do not provide a real-time update of the non-quasi-static SBH, but if the measurement-dependent time-dependent SBH change is known, it can be used to obtain the value of the SBH at a specific instant can Therefore, the real-time update of the SBH can be obtained by changing the original equations (2) and (3) to (4) and (5), respectively.

Here, Δ denotes a time interval between times during which simulations are performed, and V denotes a voltage applied to TE. As a result, the real-time SBH change at t can be obtained by considering the time history up to t. In order to improve reliability by reflecting the physical operation of the memristor element 100 dependent on the process sequence in the SPICE compact model, model parameters must first be prepared. That is, material properties, device critical dimensions, temperature parameters and mathematically extracted effective depletion widths can be used to model the conduction behavior. In addition, to model the resistance switching operation, a time-dependent SBH modulation characteristic analyzed from a transient current analysis under a given applied voltage can be used. These model parameters can be extracted by equations (2) and (3) and their differential forms, equations (4) and (5).

6 shows a change in Schottky barrier height (SBH) with time. 6(a) shows the SBH change when each TE voltage of 5V, 3.9V, 4.2V, and 4.5V is applied to Sample A for 5 seconds, and FIG. 6(b) is -0.1V, - Shows the SBH change when each TE voltage of 0.2V, -0.3V, and -0.4V is applied for 0.4 seconds. 6(c) shows the SBH change when each TE voltage of 3.5V, 3.9V, 4.2V, and 4.5V is applied to sample B for 5 seconds, and FIG. 6(d) is -0.1 to sample B Shows the SBH change when each TE voltage of V, -0.2V, -0.3V, and -0.4V was applied for 60 ms.

That is, FIGS. 6(a) to 6(d) show a time-dependent SBH change converted using Equation (1) for a time-dependent current measured according to each applied voltage. ) (ΔΦ). Equation (6) used to derive this SBH change is as follows, and the corresponding Equation (6) is a converted expression from Equation (1).

Based on the results of Figs. 6(a) to 6(d), the voltage-dependent parameters of equations (2) and (3) can be extracted by a recursive fitting process .

It was found that SBH increased according to the TE voltage in the positive voltage region where the set operation occurred. On the other hand, in the negative voltage region, SBH hardly changes with the TE voltage. Therefore, the parameters in the positive TE voltage region expressed in equations (2) and (4) are extracted to have voltage dependence, whereas the parameters in the negative TE voltage region expressed in equations (3) and (5) are It was extracted to have no voltage dependence.

7 shows the dependence of the parameters of the memristor device 100 on the voltage of the upper electrode TE.

That is, FIG. 7(a) is the SBH relationship for the TE voltage of sample A, FIG. 7(b) is the relationship between the stretching exponent (β) for the TE voltage of the sample A, and FIG. 7(c) is the sample A characteristic time constant (τ) relationship to the TE voltage of A is shown, respectively. 7(d), 7(e), and (f) respectively show the relationship of each same parameter with respect to the TE voltage of the sample B. As shown in FIG.

That is, ln(SBH), β _i and ln(τ _i ) experimentally obtained from the measurement results of FIGS. 6(a) to 6(d) are as shown in FIGS. 7(a) to 7(f). Likewise, it can be expressed as a function of DC to TE voltage. In this case, it can be seen that ln(SBH) and ln(τ _i ) have a linear relationship with the TE voltage. On the other hand, it can be seen that β has a constant value with respect to the TE voltage. Accordingly, the linear relationship between ln(SBH) and ln(τ _i ) with respect to the TE voltage, V, can be modeled as the following equations (7) and (8).

Here, α _i is a coefficient related to the exponentially incremental speed of SBH, and ΔΦ _B00i is ΔΦ _B0i when the TE voltage is 0V (ie, the maximum SBH change dependent on time and voltage). Table 1 below summarizes the model parameters extracted according to the above-described equations and methods.

parameter Sample A (Pd/IGZO/Mo) Sample B (Mo/IGZO/Pd) Unit A 30,000 μm ² T 300 K A* 40.8 - qΦ _B01 (HRS/LRS, V<0) 0.94/0.78 0.84/0.78 eV/eV qΦ _B02 (HRS/LRS, V>0) 0.98/0.86 0.76/0.72 eV/eV ε _IGZO 0.354 pF/cm X _T1 /X _T2 25/10 13/10 Nm qΔΦ _B00s2 /τ _0s2 89/15 32.8/7.1 meV/s α _s2 /γ _s2 0.075/-0.508 0.243/-0.483 V ^-1 /V ^-1 qΔΦ _B00s1 /τ _0s1 49/15 12.8/7.1 meV/s α _s1 /γ _s1 0.075/-0.508 0.243/-0.483 V ^-1 /V ^-1 β _s 0.65 0.6 - τ _0r /β _r 0.15/0.7 0.008/0.5 s/-

In Table 1, “/” is a mark to distinguish each parameter on the left and right. The definition of each parameter is summarized as follows. A: A cross-sectional area of a memristor, as shown in FIG. 1, a cross-sectional area of a portion where the TE 40 and the switching material layer 30 come into contact

T: the absolute temperature of the sample

A*: Richardson constant of IGZO

q: electronic charge

Φ _B01 : Effective SBH between TE and IGZO when V<0

Φ _B02 : Effective SBH between BE and IGZO when V>0

ε _IGZO : Permeability of IGZO

X _T1 : effective depletion width in IGZO near the TE interface

X _T2 : effective depletion width in IGZO near the BE interface

ΔΦ _B0s1 : time- and voltage-dependent SBH change between TE and IGZO during set operation

ΔΦ _B0s2 : time- and voltage-dependent SBH change between BE and IGZO during set operation

τ _0s1 : characteristic time constant for SBH modulation between TE and IGZO during set operation

τ _0s2 : characteristic time constant for SBH between BE and IGZO during set operation

τ _0r : characteristic time constant for SBH during reset operation (τ _0r1 = τ _0r2 )

α _s1 : exponential coefficient for the relationship between voltage and ΔΦ _B01 during set operation

α _s2 : exponential coefficient for the relationship between voltage and ΔΦ _B02 during set operation

γ _s1 : exponential coefficient for the relationship between voltage and τ _0s1 during set operation

γ _s2 : exponential coefficient for the relationship between voltage and τ _0s2 during set operation

β _s : Stretching exponent of ΔΦ _Bi during set operation (β _s1 = β _s2 )

β _r : Stretching index of ΔΦ _Bi during reset operation (β _r1 = β _r2 )

The parameter values extracted from samples A and B with different deposition sequences for Mo and Pd were verified. The extracted SBH values ranged from 0.7 eV to 1.0 eV. The experimentally obtained work function of Pd and the electron affinity of IGZO are about 5.3 eV and about 4.3 eV, respectively, with a difference of about 1.0 eV. Therefore, it was confirmed that the extracted SBH, which controls thermionic emission, belongs to a physically reasonable value. Sample A's SBH at V>0 (qΦ _B02 ) is greater than Sample B's SBH at V>0 (qΦ _B02 ). This is because Ar ion bombardment has a greater effect on the IGZO/BE interface. Since the conduction properties are largely determined by the interface between Pd and IGZO, sample B with Mo/IGZO/Pd stack has a higher trap density at the IGZO/Pd interface, and consequently the 'TE applied voltage at the IGZO/BE interface. The change in SBH according to (DC voltage)', that is, 'α' becomes large.

At this time, the reason why α of sample A is smaller than α of sample B is as follows. That is, as described above, since complementary switching characteristics occur in Sample A, Sample A exhibits a decrease in SBH at the IGZO/BE interface at V>0V, and an increase in SBH at the TE/IGZO interface occurs. At this time, since the increase in SBH means that the voltage applied at the TE is relatively less applied to the IGZO/BE interface compared to when the SBH is small, the SBH change in IGZO/BE is less generated in Sample A.

For this reason, although the formation energy for the interface between the oxidized metal electrode and the IGZO switching layer affects the properties of the memristor device 100 first, Ar ion bombardment (i.e., the deposition process sequence) It can be concluded that ) (deposition processing sequence) has a more dominant influence on determining conduction and switching behavior.

Meanwhile, referring to Table 1, the SBH change at the IGZO/BE interface of Sample A (qΔΦ _B02 , qΔΦ _B00s2 ) is larger than the SBH change at the IGZO/BE interface of Sample B (qΔΦ _B02 , qΔΦ _B00s2 ), and Sample A The SBH change at the TE/IGZO interface of (qΔΦ _B01 , qΔΦ _B00s1 ) is larger than the SBH change at the TE/IGZO interface of sample B (qΔΦ _B01 , qΔΦ _B00s1 ). This is because, in Sample A, the SBH of Pd/IGZO (TE/IGZO) is larger than the SBH of IGZO/Mo (IGZO/BE), and there is no Ar ion bombardment effect in Pd/IGZO (TE/IGZO) with a large SBH. As a result, sample A has a lower trap concentration than sample B, and thus the SBH change is larger than sample B.

In Table 1, X _T1 and X _T2 are effective depletion widths in IGZO near the TE and BE interfaces, respectively, and can be expressed as Equation (9) below.

Table 2 below shows the Verilog-A model for the memristor device 100 .

// Verilog-A code of SPICE compact model.
// Schottky barrier modulation
// Voltage-dependent tau (Increasing in the SBH)
tau_s_TE = tau_s_TE0 × exp(γ1 × Vapp);
tau_s_BE = tau_s_BE0 × exp(γ2 × Vapp);
// Increasing in the SBH
Delta_SBH_TE = ((Delta_SBH_TE0 × exp(αs1 × Vapp))-SBH_TE) × pow(Δt/tau_s_TE, βs1);
Delta_SBH_BE = ((Delta_SBH_BE0 × exp(αs2 × Vapp))-SBH_BE) × pow(Δt/tau_s_BE, βs2);
// Decreasing in the SBH
Delta_SBH_TE = (SBH_TE) × pow(Δt/tau_r_BE, βr1);
Delta_SBH_BE = (SBH_BE) × pow(Δt/tau_r_BE, βr2);
// Update the SBH
SBH_TE = SBH_TE + Delta_SBH_TE;
SBH_BE = SBH_BE + Delta_SBH_BE;
// Thermionic emission
if(Vapp > 0) begin
Imem = A × A*×pow(T, 2) × exp((SBH_BE-sqrt(q × Vapp/(4πεXT)))/(kT/q)); end
else begin
Imem = A × A*×pow(T, 2) × exp((SBH_TE-sqrt(q × sqrt(Vapp)/(4πεXT)))/(kT/q)); end

In equation (9), ND is the doping concentration of _IGZO . As can be seen from Equation (9), X _T depends not only on the SBH between the metal electrode and the semiconductor (IGZO), but also on the doping concentration of the semiconductor (IGZO). From Equation (9), as SBH increases, X _T increases, and as doping concentration increases, X _T decreases. Oxygen vacancies ( _VO ) are filled at the IGZO/BE interface by Ar impact, and the doping concentration of IGZO increases locally. Consequently, samples A and B both have X _T2 less than X _T1 , but with X _T2 equal to or similar to each other. It was also confirmed that sample B had a smaller X _T1 than sample A. This is because sample B has a smaller initial SBH than sample A, so X _T of sample B is smaller than X _T of sample A according to equation (9). Equations (1) to (9) were considered to model the characteristics of a non-quasi-static current through the memristor device 100 in which time and voltage are continuously updated with the SBH change effect. . All equations can be coded in Verilog-A with the parameters summarized in Table 2 and supplied as a SPICE compact model.

8 shows a comparison between the measurement results for samples A and B and the SPICE simulation results through modeling for them. That is, FIG. 8(a) is a comparison of current-voltage characteristics according to DC voltage sweep of Sample A, FIG. 8(b) is a comparison of current-time characteristics according to DC voltage sweep of Sample A, and FIG. 8(c) is Sample B A comparison of current-voltage according to a DC voltage sweep of , FIG. 8( d ) shows a comparison of current-time characteristics according to a DC voltage sweep of sample B, respectively.

As shown in FIG. 8 , the measurement results for samples A and B and the SPICE simulation results through modeling were compared. At this time, the DC voltage sweep was set from -9V to 9V for the positive direction sweep and from 9V to -9V for the negative direction sweep again, and the respective sweep rates were 2V/s and -2V/s. has been set All parameters are continuously updated at 20ms time intervals. The current change for a total of 18 seconds is shown in FIGS. 8(b) and 8(d). The model developed according to the present invention succeeded in reconstructing the measurement results for samples A and B with high accuracy, as shown in FIGS. 8(a) to 8(d).

9 is a flowchart illustrating a modeling method of the memristor device 100 according to an embodiment of the present invention.

The modeling method of the memristor device 100 follows the process according to the above description, and the process is summarized as follows.

<Summary>

1) Identify each major mechanism of resistance switching and conduction

- Resistance switching mechanism: electronic trapping/detrapping and Ar ion bombardment

- Conduction mechanism: thermionic emission from the Schottky contact between IGZO and Pd (i.e., an electrode with a metal with a higher work function)

2) The thermionic emission between IGZO and Pd, which is a conduction mechanism, is expressed by Equation (1).

3) In order to reflect the SBH change according to the resistance switching mechanism (that is, to consider the electron trapping/detrapping at the trap defect site), the SBH change is calculated using the formula of the stretched exponential function (SEF) ( 2) and Expression (3)

4) In order to express the real-time update of SBH, equations (2) and (3) are transformed into equations (4) and (5), respectively.

5) For samples A and B, the current when each TE voltage of 5V, 3.9V, 4.2V and 4.5V was applied for 5 seconds, and the current of -0.1V, -0.2V, -0.3V and -0.4V Actual measurement of current when each TE voltage is applied for 0.4 seconds

6) Substitute the measured voltage/current of 5) into Equation (6), which is a modification of Equation (1), to derive the change in SBH with time

7) Substituting the derived SBH change with time in 6) into equations (2) and (3) to extract the parameter values of equations (2) and (3): that is, ΔΦ _B0i according to samples A and B, Extracting each value of τ _si , τ _ri , β _si , β _ri

8) That is, by substituting the SBH change into Equations (2) and (3), ΔΦ _B0 , τ according to each voltage is applied as a function of Equations (7) and (8) to Equations (4) and ( 5) substituting

9) Additionally, using Equation (9), we derive the effective depletion width in IGZO

That is, the modeling method of the memristor element 100 according to an embodiment of the present invention is a method for accurately and conveniently implementing a model for the memristor element 100 in an electronic circuit simulation such as SPICE. As shown in 9, it may include S100 to S300.

In S100, for the memristor device 100 in which resistance switching occurs according to a change in the Schottky barrier height (SBH), using the corresponding resistance switching mechanism, the SBH change is expressed as a stretched exponential function (stretched exponential) function, SEF).

At this time, in the memristor device 100 according to the resistance switching mechanism, electrons are trapped/detrapped in oxygen vacancy formed at the interface between the lower electrode 20 and the switching material layer 30 . SBH changes may occur. In particular, the generation of oxygen vacancies may be affected by Ar ion bombardment when the switching material layer 30 is formed by sputtering on the lower electrode 20 .

According to such a resistance switching mechanism, the expression of SEF may include an expression of a first SEF representing an SBH change that increases with time, and an expression of a second SEF representing a change of an SBH that decreases with time. That is, the equation of the first SEF may be expressed as Equation (2), and the equation of the second SEF may be expressed as Equation (3). In addition, equations (2) and (3) can be transformed into equations (4) and (5), respectively, to express real-time update of the SBH.

Also, in S100 , the main conduction mechanism of the memristor device 100 may be modeled as thermionic emission generated from the Schottky contact between the switching material layer 30 and the main electrode. That is, the relationship between the current and the SBH for the memristor device 100 can be expressed by Equation (1) representing the hot electron emission, and a modification thereof is Equation (6). In this case, the “main electrode” may refer to a metal electrode having a larger work function among the lower electrode 20 and the upper electrode 40 .

Meanwhile, in S200 , a value of a parameter included in the SEF may be determined. Specifically, the value of the corresponding parameter may be determined using the main conduction mechanism of the memristor element, that is, thermionic emission generated from the Schottky contact between the switching material layer 30 and the main electrode.

That is, it is possible to determine the value of the parameter by deriving the change in SBH with time using an equation representing the hot electron emission. As described above, the expression representing the hot electron emission is Equation (1), and a modification thereof is Equation (6).

At this time, for pre-measured samples (eg, samples A and B), currents according to various TE voltages are measured and substituted in Equation (1) or (6) to derive the change in SBH with time can do. By substituting the derived SBH change according to time into Equations (2) and (3), the parameter values of Equations (2) and (3) can be extracted. That is, by substituting the SBH change into Equations (2) and (3), ΔΦ _B0 , τ according to each voltage is applied as a function of Equations (7) and (8) to obtain Equations (4) and (5) can be substituted into In addition, the effective depletion width in IGZO can be derived using Equation (9).

In S300 , various simulations may be performed with respect to the memristor device 100 using the determined parameter value and the conduction characteristics of the memristor according to the hot electron emission. For example, with respect to the memristor element 100, as shown in FIG. 8, a simulation of a current change according to voltage or a current change according to time is performed using Equation (1), and the corresponding value or its value The graph may be displayed on the display unit 220 of the modeling device 200 or transmitted to another device. In addition, in S300 , the determined value of each parameter or a graph thereof may be displayed on the display unit 220 of the modeling apparatus 200 or transmitted to another apparatus.

10 is a schematic block diagram of a modeling apparatus 200 of a memristor device 100 according to an embodiment of the present invention.

Meanwhile, the modeling apparatus 200 of the memristor element 100 according to an embodiment of the present invention may be an electronic device, and may perform the above-described modeling method of the memristor element 100 . In this case, the electronic device is a device capable of computing, for example, a desktop personal computer (PC), a laptop personal computer (PC), a tablet personal computer (PC), a netbook computer (netbook computer), a smart phone (smart phone). phone), a smart pad, a personal digital assistant (PDA), a server, or the like, but is not limited thereto.

As shown in FIG. 10 , the modeling apparatus 200 of the memristor element 100 according to an embodiment of the present invention includes an input unit 210 , a display unit 220 , a storage unit 230 , and a communication unit 240 . , a control unit 250 and the like.

The input unit 210 is configured to receive various types of information. That is, the input unit 210 generates input data in response to a user's input. The input unit 210 may include at least one input means. For example, the input unit 210 may include a keyboard, a keypad, various switches, a touch panel, a touch key, a mouse, or a menu button ( menu button), but is not limited thereto. In particular, the input unit 210 may receive current/voltage measurement values, various parameter values, information related to modeling, and the like.

The display unit 220 is configured to display display data according to the operation of the modeling apparatus 200 . For example, the display unit 220 may include a liquid crystal display (LCD), a light emitting diode (LED) display, an organic light emitting diode (OLED) display, and a micro electromechanical system (MEMS). mechanical systems) may include a display, an electronic paper display, or the like, but is not limited thereto. Also, the display unit 220 may be combined with the input unit 210 to be implemented as a touch screen or the like.

The storage unit 230 is configured to store various types of information. That is, the storage unit 230 may store various types of information and software required for the operation of the measurement device 100 . In particular, the storage unit 230 may store information necessary for processing by the control unit 250 , information calculated by the control unit 250 , and the like. For example, the storage unit 230 may be a hard disk type, a magnetic media type, a compact disc read only memory (CD-ROM), or an optical media type depending on the type. type), a Sagneto-optical media type, a multimedia card micro type, a flash memory type, a read only memory type, or a RAM type ( random access memory type), but is not limited thereto. In addition, the storage unit 230 may be a cache, a buffer, a main memory, an auxiliary memory, or a separately provided storage system according to its purpose/location, but is not limited thereto.

The communication unit 240 is configured to communicate with other devices, servers, systems, and the like (hereinafter referred to as “other devices”). In this case, the communication unit 240 may include wired/wireless communication modules of various communication methods. For example, the communication unit 240 is 5th generation communication (5G), long term evolution-advanced (LTE-A), long term evolution (LTE), Bluetooth, bluetooth low energe (BLE), or near field communication (NFC). It is possible to perform wireless communication such as cable communication, etc., and may perform wired communication such as cable communication, but is not limited thereto.

The control unit 250 controls operations of the remaining components of the modeling apparatus 200 , and calculates various pieces of information required by the modeling apparatus 200 . In particular, the controller 250 may control the performance of the modeling method of the memristor device 100 described above, and may control the use or operation of Equations (1) to (9). For example, the control unit 250 may include a processor such as a CUP, or software (program) executed in the corresponding processor, but is not limited thereto.

That is, the control unit 250 uses a resistance switching mechanism to convert the SBH change to the stretch index for the memristor device 100 in which resistance switching occurs according to a change in the Schottky barrier height (SBH). It can be controlled to model as a stretched exponential function (SEF). That is, the control unit 250 may control the expression according to the SEF to model the SBH change that increases with time by Equation (2), and control the SBH change that decreases with time to model the Equation (3) by Equation (3). .

In addition, the control unit 250 may model the main conduction mechanism of the memristor device 100 as thermionic emission generated from the Schottky contact between the switching material layer 30 and the main electrode. That is, the control unit 250 may express the relationship between the current and the SBH for the memristor device 100 by Equation (1) representing the hot electron emission, and a modification thereof is Equation (6).

In addition, the control unit 250 controls to determine the value of the parameter included in the SEF, controls to store the predetermined parameter value in the storage unit 230, or transmits the predetermined parameter value from another device to the communication unit 240 It can be controlled to receive via .

In this case, when controlling to determine a value of a parameter included in the SEF, the controller 250 may use a conduction mechanism of the memristor element 100 . That is, the controller 250 may determine the parameter value by using the hot electron emission generated from the Schottky contact between the switching material layer 30 and the main electrode. In this case, the control unit 250 may use Equation (1) and a modification thereof Equation (6). Specifically, the controller 250 substitutes the measured current/voltage values for the pre-measured samples (eg, samples A and B) into Equation (1) or Equation (6), and the change in SBH with time can be derived. The control unit 250 may extract the parameter values of Equations (2) and (3) by substituting the SBH change according to the time derived in this way into Equations (2) and (3). That is, by substituting the SBH change into Equations (2) and (3), ΔΦ _B0 , τ according to each voltage is applied as a function of Equations (7) and (8) to obtain Equations (4) and (5) can be substituted into In addition, the control unit 250 may derive the effective depletion width in IGZO using Equation (9).

Meanwhile, the controller 250 may control the execution of various simulations with respect to the memristor device 100 by using the determined parameter value and the conduction characteristics of the memristor according to the hot electron emission. For example, with respect to the memristor element 100, as shown in FIG. 8, a simulation of a current change according to voltage or a current change according to time is performed using Equation (1), and the corresponding value or its value The graph may be controlled to be displayed on the display unit 220 of the modeling device 200 or transmitted to another device through the communication unit 240 . In addition, the control unit 250 may control to display the determined value of each parameter or a graph thereof on the display unit 220 of the modeling apparatus 200 or to transmit the determined value to another device through the communication unit 240 . The controller 250 may control the above-described simulation to be performed in an electronic circuit simulation program such as SPICE.

In the present invention, a model has been developed for a memristor device 100 having a Schottky barrier height that is non-quasi-statically updated (ie, changes with time). At this time, in order to achieve higher accuracy and compact modeling of the analog memristor, an understanding of the switching characteristic and conduction behavior should be preceded. It has been experimentally found that these switching characteristics and conduction behavior depend on the metal type of the electrode and the processing approach. The switching characteristic is more heavily determined by the interface between the switching material layer 30 and the lower electrode 20, and the state of the interface is controlled by ar bombardment. To identify the mechanism of conduction, a series of device simulations were performed, and the internal electric field distribution for the structure of the memristor element 100 according to samples A and B was scrutinized. It has been shown that the conduction behavior is mainly determined by thermionic emission occurring between an electrode having a higher work function (ie, Pd) and the switching material layer 30 .

In order to prepare the model parameters together with the experimental results, a transient measurement technique was established at the same time, so as to know the difference between the model parameter set obtained by the theory and the technique. That is, a new experimental parameter extraction method was developed while revealing the conduction and switching mechanisms, and the extracted parameters were found to have a strong dependence on process conditions.

As a result, a more accurate and realistic SPICE compact model of the memristor device 100 including the switching material layer 30 of IGZO was developed. In other words, through the understanding of the switching and conduction mechanisms and the extraction of parameters that enable simultaneous support of Verilog-A equation build-up for equations reflecting the non-quasi-statically updated Schottky barrier height , a very stable model for the memristor device 100 has been developed, and the simulation results for the model showed significant agreement with the measurement results.

Electrode materials having different work functions and the switching effect according to the deposition sequence, that is, the process sequence of the switching material layer 30 and the upper/lower electrodes 20 and 40 were reflected in the compact model. The underlying reason that the asymmetric switching characteristic is observed lies in the fact that Ar ion bombardment affects the state at the interface between IGZO and BE. The main conduction mechanism in a given structure was identified as thermionic emission. The model proposed by the present invention is a real-time updated time- and voltage-dependent memristor compact model, which has high practicality in high-level circuit and system design and analysis for high-density memory and hardware-based neuromorphic applications. .

In the detailed description of the present invention, although specific embodiments have been described, various modifications are possible without departing from the scope of the present invention. Therefore, the scope of the present invention is not limited to the described embodiments, and should be defined by the following claims and their equivalents.

10, Si: substrate 20, BE: lower electrode
30, IGZO: switching material layer 40, TE: second electrode

Claims (17)

A lower electrode provided on the substrate, resistance switching of resistance change occurs according to an applied voltage between the upper electrode and the lower electrode, and a switching material layer provided on the lower electrode and including IGZO, and an upper electrode provided on the switching material layer A modeling method for a memristor device in which resistance switching occurs according to a change in Schottky barrier height (SBH), each comprising:
A method for modeling a memristor device, comprising the step of modeling the SBH change as a stretched exponential function (SEF).
The method of claim 1,
The modeling method of the memristor device in which the SBH change occurs as electrons are trapped/detrapped in an oxygen vacancy formed at an interface between the lower electrode and the switching material layer in the memristor device.
3. The method of claim 2,
A modeling method of a memristor device in which the generation of the oxygen vacancies is affected by ar ion bombardment when the switching material layer is formed by sputtering on the lower electrode.
The method of claim 1,
The expression according to the SEF includes an expression of a first SEF indicating a change in SBH that increases with time, and an expression of a second SEF indicating a change in SBH that decreases with time.
5. The method of claim 4,
The first SEF formula is represented by the following formula (2), and the second SEF formula is represented by the following formula (3).

where ΔΦ _Bi is the time- and voltage-dependent SBH change, ΔΦ _B0i is the time- and voltage-dependent maximum SBH change, t is the time, and τ _si is the characteristic time constant in the SET operation for the voltage-dependent SBH change ( characteristic time constant), τ _ri is the characteristic time constant in the reset (RESET) operation for voltage-dependent SBH changes, β _si is the stretching exponent in the set operation for SBH changes, β _ri is the reset for SBH changes Each represents a stretching exponent in operation, where i is expressed as 1 or 2, but i=1 is an indication related to the change occurring at the interface between the upper electrode and the switching material layer when V<0, i= 2 is an indication related to the change occurring at the interface between the switching material layer and the lower electrode when V>0.
The method of claim 1,
The method further comprises the step of modeling the hot electron emission from the Schottky contact of the switching material layer and the main electrode as a mechanism by which conduction of the memristor element occurs,
The method of modeling a memristor device, wherein the main electrode is an electrode having a larger work function among the lower electrode and the upper electrode.
The method of claim 1,
Modeling the relationship between the current and the SBH for the memristor device using thermistor emission from the Schottky contact of the switching material layer and the main electrode,
The method of modeling a memristor device, wherein the main electrode is an electrode having a larger work function among the lower electrode and the upper electrode.
The method of claim 1,
The modeling method of the memristor device further comprising the step of determining the value of the parameter included in the SEF.
9. The method of claim 8,
In the determining step, the value of the parameter is determined by using a mechanism in which conduction of the memristor element occurs by the emission of hot electrons generated in the Schottky contact between the switching material layer and the main electrode,
The method of modeling a memristor device, wherein the main electrode is an electrode having a larger work function among the lower electrode and the upper electrode.
10. The method of claim 9,
The determining is a modeling method of a memristor device for determining a value of the parameter by deriving an SBH change with time using an equation representing the hot electron emission.
11. The method of claim 7 or 10,
The formula representing the hot electron emission is a modeling method of a memristor device of the following formula (1).

Here, I _mem is the current flowing in the memristor element 100, A is the cross-sectional area of the contact area between the main electrode and the switching material layer, A* is the Richardson constant, T is the absolute temperature, kT is the heat Energy, q is electric charge, E is electric field, and Φ _B is SBH.
11. The method according to any one of claims 6 to 10,
Using the determined parameter value and the conduction characteristics of the memristor according to the emission of hot electrons for the memristor element, further comprising the step of performing a simulation of a current change according to voltage or a current change according to time modeling method.
A lower electrode provided on the substrate, resistance switching of resistance change occurs according to an applied voltage between the upper electrode and the lower electrode, and a switching material layer provided on the lower electrode and including IGZO, and an upper electrode provided on the switching material layer A modeling device for a memristor device in which resistance switching occurs according to a change in Schottky barrier height (SBH), each comprising:
Model the SBH change as a stretched exponential function (SEF),
A modeling apparatus for a memristor element that determines a value of a parameter included in SEF, stores a predetermined value of the parameter, or receives a predetermined value of the parameter from another device.
14. The method of claim 13,
A modeling apparatus for a memristor device comprising the following equation (2) representing the SBH change that increases with time, and the following equation (3) showing the SBH change that decreases with time according to the SEF equation.

where ΔΦ _Bi is the time- and voltage-dependent SBH change, ΔΦ _B0i is the time- and voltage-dependent maximum SBH change, t is the time, and τ _si is the characteristic time constant in the SET operation for the voltage-dependent SBH change ( characteristic time constant), τ _ri is the characteristic time constant in the reset (RESET) operation for voltage-dependent SBH changes, β _si is the stretching exponent in the set operation for SBH changes, β _ri is the reset for SBH changes Each represents a stretching exponent in operation, where i is expressed as 1 or 2, but i=1 is an indication related to the change occurring at the interface between the upper electrode and the switching material layer when V<0, i= 2 is an indication related to the change occurring at the interface between the switching material layer and the lower electrode when V>0.
14. The method of claim 13,
The value of the parameter is determined using a mechanism in which conduction of the memristor element is generated by the emission of hot electrons generated in the Schottky contact between the switching material layer and the main electrode,
The main electrode is an electrode having a larger work function among the lower electrode and the upper electrode. A modeling device for a memristor element.
16. The method of claim 15,
The value of the parameter is determined by deriving the SBH change with time using the following equation (1) representing the hot electron emission.

Here, I _mem is the current flowing in the memristor element 100, A is the cross-sectional area of the contact area between the main electrode and the switching material layer, A* is the Richardson constant, T is the absolute temperature, kT is the heat Energy, q is electric charge, E is electric field, and Φ _B is SBH.
17. The method of claim 15 or 16,
A modeling apparatus for a memristor element that performs a simulation of a current change according to voltage or a current change according to time with respect to the memristor element by using the determined parameter value and the conduction characteristics of the memristor according to the emission of hot electrons.

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