KR102357099B1 - Memory controller changing the minimum time interval between commands provided to a memory device and memory thermal throttling method using the same - Google Patents

Abstract

According to the present invention, when it is determined that a temperature of a monitored memory device is higher than a normal temperature according to a first detection period, a first level of a throttling level is applied to the throttling level of a memory bank, and monitoring of the temperature of the memory device is started according to the second sensing period. After that, when it is determined that the temperature of the memory device is higher than a predetermined critical temperature that is higher than the normal temperature, disclosed is a memory controller which sets the throttling level of the memory bank to the throttling level of a second level and provides an interrupt for handover of a temperature control right to a processing unit. The memory controller controls an operation of the memory device according to the throttling level.

Description

{Memory controller changing the minimum time interval between commands provided to a memory device and memory thermal throttling method using the same}

The present invention relates to a memory controller, and more particularly, to a technology for managing a temperature of a memory.

1 shows an example of the structure of a memory controller and a memory module controlled by the memory controller.

DRAM consists of a set of cells made up of capacitors and access transistors. Each cell represents the bits of '1' and '0' as the amount of charge charged in the capacitor, and the cells are usually composed of tens of thousands of rows and hundreds of columns. Cells composed of these rows and columns are again composed of a bank, and several banks are gathered to form a single DRAM chip.

As shown in FIG. 1 , from the perspective of a DRAM system, a plurality of DRAM chips constitute one rank, and a plurality of ranks are gathered to form one DRAM module.

DRAM operations are basically divided into activation, precharge, read/write, and refresh. In DRAM, the corresponding row to be read/write must be opened before performing a read/write operation, and opening the corresponding row is called activation. Through activation, data of cells belonging to the selected row is loaded into a row buffer (sense amplifier), and only then read/write operations are performed through this row buffer. The precharge operation means closing the row buffer opened by the activation operation for access to another row. Activation takes a relatively long time compared to other DRAM operations and the power consumption is also large.

The main factors of DRAM energy consumption can be briefly divided into activation and background energy consumption. Since activation and refresh consume a relatively long time and power compared to other DRAM operations such as read/write, and background power is always consumed even when the DRAM is performing or not performing any operation, these two factors contribute to the overall It accounts for a significant portion of DRAM energy consumption. Energy consumption in DRAM is associated with an increase in DRAM temperature.

Recently proposed techniques are a method of dividing a rank into small sub-rank units, a method of reducing the size of an active row inside a DRAM chip, and a method of using only necessary DRAM chips in consideration of the characteristics of data to be written to the memory. It is designed to reduce the cost of activation that occurs when

Memory has an address in a matrix structure composed of rows and columns like a checkerboard to store information or read stored information. When a memory controller, or processor containing the memory controller, reads information from or writes information to memory, it first sends an enable command (ACT command) to a row and then a Column Address Strobe (CAS) signal (CAS command) or read to a column. Send the /write command to verify the address.

In order to give commands to the memory to read and write, the bank must be activated along with the row and column of the memory. After activating one bank, another bank may be activated after a predetermined time has elapsed.

As a prior patent dealing with a thermal throttling method for temperature management of a memory, there is US Patent Registration US8122265 (power management using adaptive thermal throttling). This prior patent discloses a scheduler that schedules a signal to be transmitted to a fully buffered dual inline memory module (FBD) system outside the chip, a transmitter that transmits a scheduled signal outside the chip, and a signal including temperature information related to the outside temperature of the chip. A receiver that receives a signal containing, and a control circuit that selectively limits the number of commands that can be scheduled within a series of small windows while checking temperature information near the conclusion of a large window consisting of several small windows. A chip that contains

Also, as a prior patent related to memory system management based on thermal information of the memory system, there is Korean Patent Registration No. KR 10-1786572. This prior patent relates to a device including a plurality of memory chips stacked on each other. Here, each of the plurality of memory chips includes at least two channel regions. The at least two channel regions include respective thermal sensors configured to sense temperatures of the respective channel regions to generate temperature data and a storage configured to store the temperature data read from the respective thermal sensors. . and the apparatus further comprises thermal control logic (TCL) configured to periodically read the temperature data from the respective thermal sensors and provide the temperature data, wherein time intervals between readings of the temperature data are It is adjusted based on the temperature data.

The above-mentioned contents are presented to help the understanding of the present invention, and the above-mentioned contents may include contents not disclosed by the inventors of the present invention at the time of filing the present patent application. Accordingly, all of the above should not be considered as prior art of course. In addition, the scope of the present invention should not be limited by the above content.

An object of the present invention is to provide an efficient technique for controlling the temperature of the memory by throttling heat generated in the memory.

In a memory device temperature management method provided according to an aspect of the present invention, a memory controller configured to obtain a temperature of the memory device sets a throttling level to a first level when the temperature of the memory device is lower than a first threshold temperature. setting the throttling level of and setting, by the memory controller, a throttling level to a second throttling level when the temperature of the memory device is higher than the first threshold temperature. In this case, at least one of a constraint on a time schedule in which a command prepared by the memory controller is provided to the memory device and the maximum number of banks that can be simultaneously activated among the banks in the memory device varies according to the throttling level.

In this case, when the temperature of the memory device is higher than the first threshold temperature and lower than a second threshold temperature that is higher than the first threshold temperature, the memory controller sets the throttling level to the throttling level of the second level may be made to do. In the memory device temperature management method, when the temperature of the memory device is higher than the second threshold temperature, the memory controller provides an interrupt for handover of the temperature control right of the memory device to the processing unit; may include

In this case, when the temperature of the memory device is lower than the first threshold temperature, the memory controller may be configured to acquire the temperature of the memory device according to a first temperature sensing period. In addition, when the temperature of the memory device is higher than the first threshold temperature, the memory controller may be configured to acquire the temperature of the memory device according to a second sensing period shorter than the first temperature sensing period.

In this case, the value of the second sensing period may be changed according to the value of the temperature of the memory device.

In this case, the number of commands provided to the memory device may include the number of CAS commands and the number of ACT commands provided by the memory controller to the memory device.

In this case, in the memory device temperature management method, the memory controller sets the throttling level to a throttling level of a third level when the temperature of the memory device is higher than a second threshold temperature that is higher than the first threshold temperature It may further include the step of

In this case, when the throttling level is set to the second level of the throttling level, the second maximum activation number, which is the maximum number of banks that can be simultaneously activated among the banks in the memory device, is the second maximum activation number, wherein the throttling level is the second level. It may be smaller than the first maximum activation number, which is the maximum number of banks that can be simultaneously activated among the banks in the memory device in a state where the throttling level is set to one level.

At this time, when the throttling level is set to the second level of throttling, when the number of activated banks among the banks included in the memory device reaches the same number as the second maximum activated number, a new bank is created A bank activation command for activation may not be transmitted to the memory device.

In this case, the memory controller may be configured to calculate an inactivity maintenance cycle, which is a value indicating a level of an inactive state of an inactive bank, which is a bank having an inactive state in the memory device. In addition, the memory controller inactivates any one of the banks having an active state in the memory device when the inactivity maintenance cycle exceeds a predetermined threshold value, and selects the inactive bank instead of the inactive one of the banks It may be configured to be activated.

In this case, the inactivity maintenance cycle includes a time period for which the inactive bank maintains an inactive state, the number of commands waiting in the memory controller as commands to be provided to the inactive bank, and while the inactive bank maintains an inactive state It may be calculated based on a combination of one or more of the number of commands provided to other activated banks in the memory device.

In this case, in a state where the throttling level is the first throttling level, the total number of commands that can be provided from the memory controller to the memory device during one predetermined unit period P is a first limited number It can be limited to (#N1). And in a state where the throttling level is the second level of throttling level, the total number of commands that can be provided from the memory controller to the memory device during one unit period P is the first limited number ( It may be limited to a second limited number (#N2) less than #N1).

In this case, the memory controller may be configured to obtain the value of the unit period P and the value of the first limited number #N1 during the unit period from the processing unit.

Also, the memory controller may be configured to acquire the value of the second limited number #N2.

In this case, in a state in which the throttling level is set to the second level of the throttling level, the memory controller sends the memory device to the memory device during a first time period from the start to the end of one unit period P Even after the second limited number (#N2) of commands are transmitted, if a priority command, which is a command having a priority higher than or equal to a predetermined level, is generated by the memory controller, the memory controller transmits the priority command to the first time period may be further configured to transmit to the memory device in the

In this case, the priority command may be generated when the memory controller receives a transaction having a priority higher than or equal to a predetermined level from the processing unit.

Alternatively, the memory controller may be configured to increase the priority of a transaction having a specific attribute by using a sideband signal. In this case, the memory controller may generate a priority command related to the increased transaction according to the sideband signal.

The memory controller may select one or some of the transactions to be processed to increase the processing priority of the selected transaction. To this end, the memory controller must select only some of the transactions in the memory controller.

The method according to an embodiment of selecting the partial transaction may use a sideband bus, which is a bus provided separately from the command bus connected to the memory controller. The sideband bus may exist between the processing unit and the memory control. The processing unit may send a signal for selecting a specific transaction to the memory controller through the sideband bus. For example, a plurality of processing units may be connected to the memory controller through a command bus, and information indicating which transaction is requested by which processing unit may be transmitted together through the command bus. In this case, the same number of signals as the number of processing units requesting an increase in the processing priority of a transaction may be applied between the processing unit and the memory controller. When it is desired to increase the processing priority of a specific transaction from the nth processing unit, the nth signal may be applied.

A method according to another embodiment of selecting the partial transaction may use a method of adding a command 'increase the processing priority of a specific transaction' to the command bus.

The sideband signal may refer to a signal provided to the memory controller to increase the processing priority of the specific transaction.

In this case, in the memory device temperature management method, the memory controller sets the throttling level to a throttling level of a third level when the temperature of the memory device is higher than a second threshold temperature that is higher than the first threshold temperature It may further include the step of In a state in which the throttling level is set to the second level of throttling, the total number of commands that can be provided from the memory controller to the memory device during one predetermined unit period P is a predetermined second It can be set to a limited number (#N2).

In a state in which the throttling level is set to the third level of throttling level, the total number of commands that can be provided from the memory controller to the memory device during the unit period P is the second limited number (#N2). ) may be set to a third limited number (N3) less than.

In this case, when the throttling level is set to the first level of the throttling level, the command provided to the memory device is controlled so that the time interval between commands adjacent to each other on the time axis is not smaller than the first minimum time interval. can In a state in which the throttling level is set to the second level of throttling level, a second minimum time interval between commands provided to the memory device, which is adjacent to each other on a time axis, is larger than the first minimum time interval. It can be controlled not to be smaller than the time interval.

In this case, when a priority command, which is a command having a priority higher than or equal to a predetermined level, is generated by the memory controller in a state in which the throttling level is set to the second level of throttling level, the memory controller performs the priority command and It may be configured to allow a time interval between previous commands to have a value smaller than the second minimum time interval. The immediately preceding command is a command provided from the memory controller to the memory device immediately before the priority command.

According to another aspect of the present invention, a memory device in which a memory controller including a throttling control logic (1), a temperature sensing logic (2), a memory controller (3), and an interrupt handler (4) manages the temperature of the memory device A temperature management method may be provided. In the memory device temperature management method, the temperature sensing logic transmits, to the memory controller, a first request to acquire the temperature of the memory device at a first time selected according to a first sensing cycle provided from the throttling control logic. to do; receiving, by the memory controller, a first temperature that is a temperature of the memory device from a temperature sensing device that senses a temperature of the memory device in response to the first request, and providing the first temperature to a throttling control logic; ; When it is determined by the throttling control logic that the first temperature is greater than a predetermined first threshold temperature, the throttling level is set to a second level of throttling level, and a second sensing cycle is provided to the temperature sensing logic. providing; transmitting, by the temperature sensing logic, a second request to acquire the temperature of the memory device to the memory controller at a second time selected according to the second sensing period; receiving, by the memory controller, a second temperature that is a temperature of the memory device from the memory device in response to the second request, and providing the second temperature to throttling control logic; and when the throttling control logic determines that the second temperature is higher than a predetermined second threshold temperature that is higher than the first threshold temperature, the throttling level is set to a throttling level of a third level, and the processing unit and turning on the interrupt handler to provide an interrupt for handover of temperature control to (20). In this case, the memory controller is configured to set the throttling level to a first level throttling level when the temperature of the memory device is lower than the first threshold temperature, and a command prepared by the memory controller is configured to set the throttling level of the memory device. At least one of a constraint on the time schedule provided to the memory device and the maximum number of banks that can be simultaneously activated among the banks in the memory device varies according to the throttling level.

According to the present invention, it is possible to provide an efficient technique for controlling the temperature of the memory by throttling the heat generated in the memory.

1 shows an example of the structure of a memory controller and a memory module controlled by the memory controller.
2 shows the structure of a computing device provided according to an embodiment of the present invention.
3 is a detailed view showing the configuration of the memory controller shown in FIG. 2 .
4 is a flowchart illustrating a method of controlling a throttling level of a memory by a memory controller provided according to an embodiment of the present invention.
5 is a diagram for describing a method in which a memory controller controls activation of a bank of a memory according to an embodiment of the present invention.
6 is a flowchart illustrating a memory device temperature management method provided according to an embodiment of the present invention.
7 is a diagram illustrating a method in which a memory controller provides instructions to a memory during a unit period at different throttling levels according to an embodiment of the present invention.
8 is a diagram illustrating a method in which a memory controller provides instructions to a memory during a unit period at different throttling levels according to another embodiment of the present invention.

Hereinafter, embodiments of the present invention will be described with reference to the accompanying drawings. However, the present invention is not limited to the embodiments described herein and may be implemented in various other forms. The terminology used herein is for the purpose of helping the understanding of the embodiments, and is not intended to limit the scope of the present invention. Also, singular forms used hereinafter include plural forms unless the phrases clearly indicate the opposite.

2 shows the structure of a computing device provided according to an embodiment of the present invention.

The computing device 100 provided according to an embodiment of the present invention may include a processing unit 20 , a memory controller 10 , and a memory 30 . The memory 30 may be, for example, DRAM.

The memory controller 10 may have a predetermined control right over the memory 30 . In addition, when a predetermined condition is reached, the memory controller 10 may generate an interrupt for returning the control right to the processing unit 20 .

The processing unit 20 retains the control right and may return the control right back to the memory controller 10 when another predetermined condition is satisfied (hand-back).

In this case, the predetermined control right for the memory 30 may be a control right for controlling the temperature of the memory 30 .

The memory controller 10 may transmit various commands to the memory 30 through a command bus, and may transmit data accompanying the commands to the memory 30 through a data bus.

The processing unit 20 may be a main processor or a sub-processor or an interconnect of the computing device 100 .

3 is a detailed view showing the configuration of the memory controller shown in FIG. 2 .

The memory controller 10 may include a throttling control logic 1 , a temperature sensing logic 2 , a scheduler 3 , and an interrupt handler 4 .

The throttling control logic 1 is the main functional logic of the memory controller 10 . The throttling control logic 1 may set a detection period based on the number of commands transmitted by the scheduler 3 to the memory 30 or the temperature of the memory 30 . The throttling control logic 1 may receive the temperature of the memory 30 obtained by the scheduler 3 from the scheduler 3 . The throttling control logic 1 may apply different throttling levels based on the current temperature of the memory 30 . The throttling control logic 1 may turn on the interrupt handler 4 when the current temperature of the memory 30 exceeds a predetermined level, for example, a predetermined second threshold temperature. .

The scheduler 3 may apply the throttling condition determined by the throttling control logic 1 . The scheduler 3 may provide the temperature of the memory 30 obtained by the scheduler 3 to the throttling control logic 1 . Also, the scheduler 3 may provide the throttling control logic 1 with information about the number of commands that the scheduler 3 should provide to the memory 30 .

The throttling control logic 1 may provide the throttling level value set by the throttling control logic 1 to the scheduler 3 . Also, the throttling control logic 1 may provide the scheduler 3 with the maximum number of banks in the memory 30 that are allowed to be simultaneously activated according to each of the throttling levels. In addition, the throttling control logic 1 has a predetermined unit period P and a limited number ( N) can be provided. The unit period P and/or the limited number N may have different values according to each throttling level.

The throttling control logic 1 may provide the temperature sensing logic 2 with a sensing period of the temperature of the memory 30 determined according to the respective throttling levels.

The temperature sensing logic 2 may transmit a temperature sensing request to the scheduler 3 to sense the temperature of the memory 30 at each time determined according to the currently applied sensing period. The scheduler 3 receiving the temperature sensing request may acquire the current temperature of the memory 30 from a separate temperature sensing device that detects the current temperature of the memory 30 . The temperature sensing device may be included in the memory 30 or the memory 30 may be provided separately.

When a predetermined condition is reached, the throttling control logic 1 gives the processing unit 20 a control right for throttling heat in order to control the temperature of the memory 30 that the throttling control logic 1 had. A request for generating an interrupt for handover may be sent to the interrupt handler 4 .

The interrupt handler 4 may generate an interrupt for handover of the control right to the temperature of the memory 30 in response to the interrupt generation request and provide it to the processing unit 20 .

In FIG. 3 , the throttling control logic 1 and the scheduler 3 are presented separately from each other, but this is for convenience of explanation, and the throttling control logic 1 and the scheduler 3 are the scheduler 3 ) can also be incorporated.

4 is a flowchart illustrating a method of controlling a throttling level of a memory by a memory controller provided according to an embodiment of the present invention.

Hereinafter, it will be described with reference to FIG. 4 .

In step S10 , the memory controller 10 may measure the temperature of the memory 30 according to a preset first detection period. That is, the temperature of the memory 30 may be measured at intervals of the first sensing cycle.

In step S11 , the memory controller 10 may determine whether the first temperature, which is the temperature of the memory 30 measured according to the first detection period, is less than a preset first limit temperature.

When the first temperature is smaller than the first limit temperature, the process may return to step S10 again. On the other hand, if the first temperature is not smaller than the first limit temperature, the process may proceed to step S12 to be described later.

In step S12 , the memory controller 10 may set the throttling level to the second throttling level.

In step S13 , the memory controller 10 may measure the temperature of the memory 30 according to a preset second detection period. That is, the temperature of the memory 30 may be measured at the second sensing cycle interval.

The second sensing period may be shorter than the first sensing period.

In step S14 , the memory controller 10 may determine whether a second temperature, which is a temperature of the memory 30 measured according to the second detection period, is less than the first limit temperature.

When the second temperature is smaller than the first limit temperature, the process may proceed to step S19 to be described later. On the other hand, if the second temperature is not smaller than the first limit temperature, the process may proceed to step S15 to be described later.

In step S15 , the memory controller 10 may determine whether the second temperature measured according to the second detection period is smaller than a preset second limit temperature.

The second limit temperature may be higher than the first limit temperature.

If the second temperature is less than the second limit temperature, the process may return to step S13. On the other hand, if the second temperature is not smaller than the second limit temperature, the process may proceed to step S16 to be described later.

In step S16 , the memory controller 10 may set the throttling level to the third throttling level.

In step S17 , the memory controller 10 generates an interrupt and transmits the interrupt to the processing unit 20 , so that the memory controller 10 has a temperature control right for the memory 30 . management) may be handed over to the processing unit 20 .

In step S18 , the memory controller 10 performs a transaction while maintaining the enhanced throttling level until the processing unit 20 hand-backs the temperature controllability back to the memory controller 10 . can also be processed.

The enhanced throttling level may be the third throttling level described above.

For example, the processing unit 20 measures the temperature of the memory 30 while controlling the operation of the memory 30 by itself, and when a predetermined condition is reached, the processing unit 20 hands the temperature control right of the memory 30 to the memory controller 10 again. - You can do a hundred.

In step S19 , the memory controller 10 may release a throttling level. That is, the memory controller 10 may apply a first throttling level, which is a throttling level applicable when the temperature of the memory is lower than the first threshold temperature. And it can go back to step (S10).

In the first throttling level, the memory controller 10 may use the memory thermal throttling algorithm provided by default by the processing unit 20 , and the memory temperature control algorithm of the memory controller 10 itself may not be applied. can The throttling level in this way may be referred to as the above-described first throttling level.

5 is a diagram for describing a method in which a memory controller controls activation of a bank of a memory according to an embodiment of the present invention.

The memory controller 10 and the memories 30 may be connected to each other by a command bus and a data bus.

Each of the memories 30 connected to the memory controller 10 may include a plurality of banks 300 . A peripheral device 320 used to connect the memory controller 10 and the bank 300 may be connected to each of the banks 300 .

The peripheral device 320 is a circuit part for input/output and control, such as address/command and data in/out.

Each of the banks 300 may be independently activated/deactivated. The ACT command, which is an activation command for each bank, may be provided by the memory controller 10 to the memory 30 .

The memory controller 10 is configured to limit the number of the banks 300 included in the first memory 31 or the second memory 32 that can be activated.

Alternatively, in an embodiment, the memory controller 10 may be configured to limit the number of the banks 300 included in all the memories 30 connected to the memory controller 10 to be activated.

It may be assumed that the memory controller 10 sets the maximum number of the banks 300 included in the first memory 31 to be activated as the first maximum activation number. At this time, if the banks corresponding to the first maximum activation number among the banks 300 included in the first memory 31 are activated, among the banks 300 included in the first memory 31 , The ACT command for further activating the new bank 300 is not transmitted from the memory controller 10 to the first memory 31 .

6 is a flowchart illustrating a memory device temperature management method provided according to an embodiment of the present invention.

In step S110 , the memory controller 10 configured to obtain the temperature of the memory device 30 sets a first throttling level when the temperature of the memory device 10 is lower than a first predetermined threshold temperature. It can be set to the throttling level of the level.

In operation S120 , when the temperature of the memory device 30 is higher than the first threshold temperature, the memory controller 10 may set the throttling level to the second level of the throttling level.

In this case, a constraint on a time schedule in which a command prepared by the memory controller 10 is provided to the memory device 30 and the maximum number of banks that can be simultaneously activated among the banks 300 in the memory device 30 . At least one of them varies according to the throttling level.

At this time, when the temperature of the memory device 30 is higher than the first threshold temperature and lower than a second threshold temperature higher than the first threshold temperature, the memory controller 10 sets the throttling level to the second threshold temperature. It may be configured to set the throttling level of the level.

In step S130 , when the temperature of the memory device 30 is higher than the second threshold temperature, the memory controller 10 hands over the right to control the temperature of the memory device 30 to the processing unit 20 . Interrupts can be provided.

At this time, when the temperature of the memory device 30 is lower than the first limit temperature, the memory controller 10 is configured to acquire the temperature of the memory device 30 according to a preset first temperature sensing period. can And when the temperature of the memory device 30 is higher than the first threshold temperature, the memory controller 10 adjusts the temperature of the memory device 30 according to a second sensing period shorter than the first temperature sensing period. may be intended to be obtained.

At this time, in a state in which the throttling level is set to the second throttling level, the second maximum activation number, which is the maximum number of banks 300 that can be simultaneously activated among the banks 300 in the memory device 30 . is the first maximum activation number that is the maximum number of banks 300 that can be simultaneously activated among the banks 300 in the memory device 30 when the throttling level is set to the first level throttling level may be smaller than

In this case, the memory controller 10 may be configured to calculate an inactivity maintenance cycle, which is a value indicating a level of an inactive state of an inactive bank that is the bank 300 having an inactive state in the memory device 30 .

And when the inactivity maintenance cycle exceeds a predetermined threshold value, the memory controller 10 inactivates any one of the banks 300 having an active state in the memory device 30, Instead of the inactive one of the banks 300, the inactive bank may be activated.

In this case, the inactivity maintenance cycle includes a time period for which the inactive bank continuously maintains an inactive state, the number of commands waiting in the memory controller 10 as commands to be provided to the inactive bank, and the inactive bank is inactive It may be calculated based on a combination of one or more of the number of commands provided to other activated banks in the memory device 30 while maintaining the state.

7 is a diagram illustrating a method in which a memory controller provides instructions to a memory during a unit period at different throttling levels according to an embodiment of the present invention.

The memory controller 10 provides from the memory controller 10 to the memory device 30 for one predetermined unit period P while the throttling level is the first level throttling level The total number of commands that can be made may be limited to the first limited number (#N1).

In this case, the memory controller 10 transfers from the memory controller 10 to the memory device 30 for one unit period P while the throttling level is the second level of the throttling level. The total number of commands that can be provided may be limited to a second limited number #N2 smaller than the first limited number #N1.

However, in a state in which the throttling level is set to the second level of the throttling level, during a first time period from the start to the end of one unit period P, the memory controller 10 Even after the second limited number of commands #N2 are transmitted to the device 30 , when the priority command CP, which is a command having a priority higher than or equal to a predetermined level, is generated by the memory controller 10 , the memory The controller 10 may be configured to further transmit the priority command CP to the memory device 30 within the first time period.

However, in a state in which the throttling level is set to the second level of the throttling level, during a first time period from the start to the end of the one unit period P, the memory controller 10 After the second limited number of commands #N2 are transmitted to the memory device 30 , the memory controller 10 generates a lower priority command CL, which is a command having a lower priority than the predetermined level. , the memory controller 10 may not transmit the lower priority command CL to the memory device 30 within the first time period.

The subordinate command CL that has not been transmitted may be stored in the memory controller 10 and transmitted to the memory 30 during a unit period after the first time period.

In this case, the priority command CP may be generated in the memory controller 10 when the memory controller 10 receives a transaction having a priority higher than or equal to a predetermined level from the processing unit 20 .

At least one of the unit period P and the first limited number #N1 may be generated by the processing unit 20 and provided to the memory controller 10 .

The second limited number #N2 may be a value determined by the processing unit and provided to the memory controller 10 .

7A shows a state in which the throttling level is set to the first level throttling level, and FIGS. 7B and 7C show that the throttling level is set to the second level Indicates the state set to the throttling level of .

In FIG. 7 , the horizontal axis is the time axis.

In FIG. 7 , reference numeral CP denotes the priority command, and reference numeral CL denotes a subordinate command having a lower priority than the priority command.

In FIG. 7, #N1 is illustrated as being 12, and #N2 is illustrated as being 8.

Referring to FIG. 7A , the memory controller 10 may transmit the priority command and/or the sub-priority command up to #N1 at most during the unit period P.

Referring to FIGS. 7B and 7C , the memory controller 10 may transmit the priority command and/or the sub-priority command up to #N1 at most during the unit period P.

As shown in (b) of FIG. 7 , in a state in which the throttling level is set to the second level of throttling level, after #N2 commands are transmitted after the unit period P starts, the unit No other commands can be additionally transmitted before the period P ends.

However, as shown in (c) of FIG. 7 , in a state in which the throttling level is set to the second level of throttling level, after the unit period P starts, after #N2 commands are transmitted, Even before the unit period P ends, when the memory controller 10 generates the priority command CP, the generated priority command CP can be transmitted to the memory 30 . have.

8 is a diagram for describing a method in which a memory controller provides instructions to a memory during a unit period at different throttling levels according to another embodiment of the present invention.

The memory controller 10 is a command provided to the memory device 30 in a state in which the throttling level is set to the first throttling level, and a time interval between commands adjacent to each other on a time axis is 1 It can be controlled so that it is not smaller than the minimum time interval t1.

In addition, the memory controller 10 is a command provided to the memory device 30 in a state in which the throttling level is set to the second level of the throttling level, and the time interval between commands adjacent to each other on the time axis is It may be controlled not to be smaller than the second minimum time interval t2 which is larger than the first minimum time interval t1.

However, in a state in which the throttling level is set to the second throttling level, the memory controller 10 may generate a priority command CP, which is a command having a priority higher than or equal to a predetermined level. In this case, the memory controller 10 may be configured to allow a time interval between the generated priority command and the immediately preceding command to have a value smaller than the second minimum time interval t2 . The immediately preceding command is a command provided to the memory device 30 from the memory controller 10 immediately before the priority command. For example, the time interval between the generated priority command and the immediately preceding command may be the same as the first minimum time interval t1.

8A shows a state in which the throttling level is set to the first level throttling level, and FIGS. 8B and 8C show that the throttling level is set to the second level Indicates the state set to the throttling level of .

In FIG. 8 , the horizontal axis is the time axis.

In FIG. 8, reference numeral CP denotes the priority command, and reference numeral CL denotes a subordinate command having a lower priority than the priority command.

Referring to (a) of FIG. 8 , the difference between the times when two adjacent commands are provided from the memory controller 10 to the memory 30 is maintained to be the same as the first minimum time interval t1, so that the difference The value is controlled not to be smaller than the first minimum time interval t1.

Referring to (b) of FIG. 8 , the difference between the times when two adjacent commands are provided from the memory controller 10 to the memory 30 is maintained to be the same as the second minimum time interval t2, so that the difference The value is controlled not to be smaller than the second minimum time interval t2.

Referring to (c) of FIG. 8 , the difference between the times when two adjacent commands are provided from the memory controller 10 to the memory 30 is basically maintained to be the same as the second minimum time interval t2 . Thus, it is controlled so that the difference value is not smaller than the second minimum time interval t2. However, when the second command generated later among the two adjacent commands is the priority command CP, the first command and the second command generated earlier among the two adjacent commands are transmitted from the memory controller 10 to the memory 30 . The time difference value provided to the user may be controlled to have a value smaller than the second minimum time interval t2. For example, as shown in (c) of FIG. 8 , the difference between the times when the first command and the second command are provided from the memory controller 10 to the memory 30 is the first minimum time interval t1 . may be the same as

7 and 8 , when the throttling level is changed from the first level of throttling to the second level of throttling, in order to reduce heat generation of the memory 30 , the memory controller Commands transmitted from (10) to the memory (30) are transmitted according to an enhanced time schedule.

That is, if commands transmitted from the memory controller 10 to the memory 30 are transmitted according to a time schedule according to the first rule in a state in which the first level of throttling level is set, the second level of throttling In the state set to the level, commands transmitted from the memory controller 10 to the memory 30 are transmitted according to a time schedule according to the second rule. In this case, the time schedule according to the second rule may be a more strengthened schedule to reduce heat generation of the memory 30 when compared with the time schedule according to the first rule.

However, in a state in which the second level of throttling level is set, if some of the commands are priority commands having priority over other commands, the reinforced time schedule may not be applied to the priority commands. . That is, the time schedule according to the first rule may not be applied to the priority command, but the time schedule according to the second rule may be applied.

By using the above-described embodiments of the present invention, those skilled in the art will be able to easily implement various changes and modifications within the scope without departing from the essential characteristics of the present invention. The content of each claim in the claims may be combined with other claims without reference within the scope that can be understood through this specification.

1: Throttling control logic
2: Temperature sensing logic
3: Scheduler
4: Interrupt handler
10: memory controller
20: processing unit
30: memory
31: first memory
32: second memory
300: bank

Claims (14)

setting, by the memory controller configured to acquire a temperature of the memory device, a throttling level to a first level when the temperature of the memory device is lower than a first threshold temperature; and
setting, by the memory controller, a throttling level to a second throttling level when the temperature of the memory device is higher than the first threshold temperature;
includes,
At least one of a constraint on a time schedule for providing a command prepared by the memory controller to the memory device and the maximum number of banks that can be simultaneously activated among the banks in the memory device varies according to the throttling level,
In a state in which the throttling level is set to the first level of throttling level, the command provided to the memory device is controlled so that a time interval between commands adjacent to each other on a time axis is not smaller than a first minimum time interval,
In a state in which the throttling level is set to the second level of throttling level, the command provided to the memory device, wherein a time interval between commands adjacent to each other on a time axis is a second minimum time greater than the first minimum time interval characterized in that it is controlled so as not to be smaller than the
Memory device temperature management method. According to claim 1,
the memory controller is configured to set a throttling level to the throttling level of the second level when the temperature of the memory device is higher than the first threshold temperature and lower than a second threshold temperature that is higher than the first threshold temperature there is,
After the step of setting the throttling level to the second throttling level, when the temperature of the memory device is higher than the second threshold temperature, the memory controller hands over the right to control the temperature of the memory device to the processing unit providing an overrun interrupt;
further comprising,
Memory device temperature management method. According to claim 1,
when the temperature of the memory device is lower than the first threshold temperature, the memory controller acquires the temperature of the memory device according to a first temperature sensing period;
when the temperature of the memory device is higher than the first threshold temperature, the memory controller acquires the temperature of the memory device according to a second sensing period shorter than the first temperature sensing period;
Memory device temperature management method. The method of claim 1 , wherein the second maximum activation number, which is the maximum number of banks that can be simultaneously activated among the banks in the memory device when the throttling level is set to the second throttling level, comprises: The method of claim 1, wherein the first maximum activation number is less than the maximum number of banks that can be simultaneously activated among the banks in the memory device when the level is set to the throttling level of the first level. delete According to claim 1,
The memory controller is configured to calculate an inactivity maintenance cycle that is a value indicating a level of an inactive state of an inactive bank, which is a bank having an inactive state in the memory device;
The memory controller inactivates any one of the banks having an active state in the memory device when the inactivity maintenance cycle exceeds a predetermined threshold, and activates the inactive bank instead of the inactive one of the banks is to be done,
The inactive maintenance cycle is
the time the inactive bank remains inactive;
the number of commands waiting in the memory controller as commands to be provided to the inactive bank, and
The number of commands provided to other active banks in the memory device while the inactive bank maintains an inactive state.
Characterized in that it is calculated based on a combination of one or more of
Memory device temperature management method. According to claim 1,
In a state where the throttling level is the first throttling level, the total number of commands that can be provided from the memory controller to the memory device during one predetermined unit period P is a first limited number (#). limited to N1),
In a state where the throttling level is the second throttling level, the total number of commands that can be provided from the memory controller to the memory device during one unit period P is the first limited number (#). Characterized in that it is limited to a second limited number (#N2) less than N1),
Memory device temperature management method. The method of claim 7 , wherein, in a state in which the throttling level is set to the second level of throttling level, during a first time period from beginning to end of one unit period (P), the memory controller Even after the second limited number of commands #N2 are transmitted to the memory device, if a priority command that is a command having a priority higher than or equal to a predetermined level is generated by the memory controller, the memory controller executes the priority command and further transmit to the memory device within a first time period. 9. The method of claim 8,
The memory controller is configured to increase the priority of a transaction having a specific attribute by using a sideband signal,
wherein the memory controller is configured to generate a priority command for the transaction having an elevated priority according to the sideband signal;
Memory device temperature management method. The method of claim 8 , wherein the priority command is generated when the memory controller receives a transaction having a priority higher than or equal to the predetermined level from the processing unit. According to claim 1,
In a state in which the throttling level is set to the second level of throttling, when a priority command that is a command having a priority higher than or equal to a predetermined level is generated by the memory controller, the memory controller performs the priority command and the previous command to allow the time interval between the intervals to have a value smaller than the second minimum time interval,
The immediately preceding command is a command provided from the memory controller to the memory device immediately before the priority command,
Memory device temperature management method. A memory controller comprising:
a scheduler configured to obtain a temperature of the memory device; and
When the temperature of the memory device is lower than the first threshold temperature, the throttling level is set to the first throttling level, and when the temperature of the memory device is higher than the first threshold temperature, the throttling level is set to a second throttling control logic configured to set to a throttling level of the level;
includes,
In the scheduler, one or more of a constraint on a time schedule for providing a command prepared by the memory controller to the memory device and a maximum number of banks that can be simultaneously activated among the banks in the memory device is determined according to the throttling level. is variable,
In a state in which the throttling level is set to the first level of throttling level, the command provided to the memory device is controlled so that a time interval between commands adjacent to each other on a time axis is not smaller than a first minimum time interval,
In a state in which the throttling level is set to the second level of throttling level, the command provided to the memory device, wherein a time interval between commands adjacent to each other on a time axis is a second minimum time greater than the first minimum time interval characterized in that it is controlled so as not to be smaller than the
memory controller. 13. The method of claim 12,
It further includes an interrupt handler,
The throttling control logic is configured to set a throttling level to the throttling level of the second level when the temperature of the memory device is higher than the first threshold temperature and lower than a second threshold temperature that is higher than the first threshold temperature has been made,
wherein the interrupt handler is configured to provide an interrupt for handover of a temperature control right of the memory device to a processing unit when the temperature of the memory device is higher than the second threshold temperature;
memory controller. A computing device comprising the memory controller of claim 12 or 13 , and the memory device.

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