KR102356701B1 - Integrated circuit device and method of manufacturing the same - Google Patents

Abstract

The integrated circuit device includes a first gate stack formed over a first high-k film and having a first workfunction controlling metal-containing structure, and a first gate stack formed over the second high-k film and having an oxygen content greater than an oxygen content in the first workfunction controlling metal-containing structure. and a second gate stack having a second work function control metal containing structure having an oxygen content.

Description

Integrated circuit device and method of manufacturing the same

TECHNICAL FIELD The present invention relates to an integrated circuit device and a method for manufacturing the same, and more particularly, to an integrated circuit device including a metal-oxide-semiconductor (MOS) transistor and a method for manufacturing the same.

Due to the development of electronic technology, down-scaling of semiconductor devices is rapidly progressing in recent years. Recently, since a semiconductor device requires not only a fast operation speed but also an operation accuracy, various studies for optimizing the structure of a transistor included in the semiconductor device are being conducted.

An object of the present invention is to provide an integrated circuit device having a gate structure having various work functions optimized for a plurality of transistors requiring different threshold voltages.

Another technical problem to be achieved by the technical idea of the present invention is to provide a method of manufacturing an integrated circuit device capable of forming a gate structure having various work functions optimized for a plurality of transistors requiring different threshold voltages, respectively will be.

In an integrated circuit device according to an aspect of the inventive concept, a first gate having a first high-k film formed on a first active region of a substrate and a structure containing a first work function control metal formed on the first high-k film a stack; a second high-k film formed over the second active region of the substrate; and a second gate stack having a metal containing structure.

In some embodiments, the first high-k layer and the second high-k layer may include a metal oxide, and the first high-k layer and the second high-k layer may have different oxygen vacancy densities. .

In some embodiments, the first high-k layer and the second high-k layer may include a metal oxide, and the second high-k layer may have a lower oxygen vacancy density than that of the first high-k layer.

In some embodiments, the first work function control metal-containing structure includes a first conductive layer that is in direct contact with the first high-k layer and includes a single layer having a first thickness, and the second work function control metal-containing structure includes: a second conductive layer formed on the same level as the first conductive layer and including a multilayer having the first thickness, wherein the second conductive layer includes a lower second conductive layer in direct contact with the second high-k layer; The upper second conductive layer may include an upper second conductive layer having an oxygen content greater than an oxygen content in the first conductive layer. In an example, the lower second conductive layer may have the same oxygen content as the oxygen content in the first conductive layer. In another example, the lower second conductive layer may be formed of a metal-containing layer that does not contain oxygen. The upper second conductive layer may have a second thickness that is 10 to 90% of the first thickness. A sum of the thickness of the lower second conductive layer and the thickness of the upper second conductive layer may be equal to the thickness of the first conductive layer.

In some embodiments, the first work function control metal-containing structure includes a first conductive layer in direct contact with the first high-k layer and includes a single layer having a first thickness, and the second work function control metal-containing structure includes a second conductive film made of a multi-layer having a second thickness greater than the first thickness, wherein the second conductive film is in direct contact with the second high-k film and has an oxygen content greater than an oxygen content in the first conductive film It may include a lower second conductive layer having a content, and an upper second conductive layer having the first thickness and having the same oxygen content as in the first conductive layer. In an example, the first conductive layer and the upper second conductive layer may not contain oxygen. In an example, the first conductive layer and the upper second conductive layer may be made of the same material.

In some embodiments, the first work function control metal-containing structure includes a first conductive layer that is in direct contact with the first high-k layer and includes a single layer having a first thickness, and the second work function control metal-containing structure includes: A second conductive layer directly in contact with the second high-k layer, the second conductive layer having the first thickness, and having an oxygen content greater than an oxygen content in the first conductive layer may be included. In an example, the first conductive layer and the second conductive layer may include the same metal. In an example, the first conductive layer may not contain oxygen.

In an integrated circuit device according to an aspect according to the inventive concept, the first work function control metal-containing structure includes a first conductive layer having a first oxygen content per unit volume, and contains the second work function control metal The structure may include a conductive layer having a second oxygen content greater than the first oxygen content by 5 to 30 atomic% per unit volume.

In an integrated circuit device according to an aspect according to the inventive concept, the first active region has a first channel region of a first conductivity type covered with the first high-k film, and the second active region includes the It may have a second channel region of the second conductivity type covered with a second high-k film. In some embodiments, the first channel region may be an N-type channel region, and the second channel region may be a P-type channel region.

In an integrated circuit device according to an aspect according to the inventive concept, the first active region has a first channel region of a first conductivity type covered with the first high-k film, and the second active region includes the The second channel region of the first conductivity type may be covered with a second high-k film. In one example, the first channel region and the second channel region may be an N-type channel region. In another example, the first channel region and the second channel region may be a P-type channel region.

An integrated circuit device according to another aspect of the inventive concept includes a first high-k film formed on a first active region of a substrate and having a first oxygen vacancy density, and formed on the first high-k film and a first gate structure having a first work function control metal-containing structure comprising a first conductive layer having a first oxygen content, and a first gate structure formed over a second active region of the substrate and having a lower first oxygen vacancy density than the first oxygen vacancy density. a second work function control metal-containing structure including a second high-k film having a density of 2 oxygen vacancy and a second conductive film formed on the second high-k film and having a second oxygen content greater than the first oxygen content; The branch includes a second gate structure.

In an integrated circuit device according to another aspect of the inventive concept, each of the first high-k film and the second high-k film includes a first metal, and the first conductive layer and the second conductive layer each include the It may include a second metal different from the first metal.

In some embodiments, the first conductive layer and the second conductive layer may have the same thickness.

In an integrated circuit device according to another aspect of the inventive concept, a thickness of the second work function control metal-containing structure may be greater than a thickness of the first work function control metal-containing structure.

An integrated circuit device according to another aspect of the inventive concept includes a third high-k film formed on a third active region of the substrate and having a third oxygen vacancy density lower than the second oxygen vacancy density; A third gate structure may further include a third gate structure having a third work function control metal-containing structure formed on the third high-k film and including a third conductive film having a third oxygen content greater than the second oxygen content. The first conductive layer, the second conductive layer, and the third conductive layer may include the same metal. In some embodiments, at least two active regions of the first active region, the second active region, and the third active region may have a channel region in which a channel of the same conductivity type is formed.

In a method of manufacturing an integrated circuit device according to an aspect of the inventive concept, a first dielectric layer is formed on a substrate in a first region, and a second dielectric layer is formed on the substrate in a second region. An oxygen content greater than an oxygen content in the first work function regulating metal-containing structure covering the first dielectric layer in the first region and the second work function regulating metal-containing structure covering the second dielectric layer in the second region To form a second work function control metal-containing structure having a.

The forming of the first work function control metal-containing structure and the second work function control metal-containing structure includes a work function control metal-containing structure covering the first dielectric layer and the second dielectric layer in the first region and the second region. The method may include forming a film and oxidizing at least a portion of the work function control metal-containing film in the second region.

The step of oxidizing at least a portion of the work function regulating metal-containing layer in the second region includes the work function regulating metal-containing layer in a state in which a portion of the work function regulating metal-containing layer in the first region is covered with a mask pattern. and exposing the portion in the second region to an oxidizing atmosphere.

The step of oxidizing at least a portion of the work function regulating metal-containing layer in the second region may include oxidizing only an upper portion of the work function regulating metal-containing layer without oxidizing a lower portion of the work function regulating metal-containing layer in the second region. The method may include oxidizing the work function control metal-containing layer.

The method of manufacturing an integrated circuit device according to an aspect according to the technical concept of the present invention includes lowering the oxygen vacancy density in the second dielectric layer while oxidizing at least a portion of the work function control metal-containing layer in the second region. It may include further steps.

In the method of manufacturing an integrated circuit device according to an aspect according to the inventive concept, the step of oxidizing at least a portion of the work function control metal-containing layer in the second region includes the work function control metal in the second region forming an oxygen-containing film on the film, and in the first region, heat-treating the resultant product on which the oxygen-containing film is formed while the work function control metal-containing film is exposed to remove oxygen atoms in the oxygen-containing film in the second region The method may include diffusing into the work function control metal-containing layer. In some embodiments, the method may further include lowering an oxygen vacancy density in the second dielectric layer in the second region while heat-treating a resultant product on which the oxygen-containing layer is formed.

In the method of manufacturing an integrated circuit device according to an aspect according to the inventive concept, the forming of the first work function regulating metal-containing structure and the second work function regulating metal-containing structure includes the first region and the second forming a first metal-containing film including oxygen atoms on the first dielectric film and the second dielectric film in two regions; selectively removing only a portion of the first metal-containing film in the first region; and forming a second metal-containing layer having a lower oxygen content than in the first metal-containing layer on the first dielectric layer and the first metal-containing layer in the first region and the second region. In some embodiments, the second metal-containing layer may be formed to contact the first dielectric layer in the first region and to contact the first metal-containing layer in the second region.

In the method of manufacturing an integrated circuit device according to an aspect according to the inventive concept, the forming of the first work function control metal-containing structure and the second work function control metal-containing structure includes the first region and the second forming a metal-containing film including oxygen atoms on the first dielectric film and the second dielectric film in two regions; and selectively removing oxygen atoms from the metal-containing film only in a portion of the metal-containing film in the first region may include steps. In some embodiments, removing the oxygen atom may include selectively reducing only a portion of the metal-containing layer in the first region. In some embodiments, the method may further include increasing an oxygen vacancy density in the first dielectric layer while selectively reducing only a portion of the metal-containing layer in the first region. In some embodiments, the removing of the oxygen atoms includes forming an oxygen trapping film covering the metal-containing film in the first region, and forming the oxygen trapping film in the second region while the metal-containing film is exposed. and heat-treating the resultant to move oxygen atoms in the metal-containing film to the oxygen trapping film in the first region. In some embodiments, the method may further include increasing the oxygen vacancy density in the first dielectric film in the first region while moving oxygen atoms in the metal-containing film to the oxygen trapping film.

An integrated circuit device according to the inventive concept includes a transistor including a work function control metal-containing structure having different oxygen contents in a plurality of regions requiring different threshold voltages. In the integrated circuit device according to the technical concept of the present invention, the work function of the transistor is adjusted differently for each of a plurality of regions requiring different threshold voltages, and the oxygen content in the metal-containing structure is differently adjusted to change the work function to have various threshold voltages. Transistors can be implemented. According to the method of manufacturing an integrated circuit device according to the technical idea of the present invention, it is possible to control (modulation) to have various threshold voltages over a wide range using a simple and easy process, and reproducibility is achieved by accurately controlling the oxygen content. An excellent threshold voltage control method can be secured.

1 is a cross-sectional view illustrating an integrated circuit device according to embodiments according to the inventive concept.
2 is a cross-sectional view illustrating an example of a structure containing a first work function regulating metal and a structure containing a second work function regulating metal of an integrated circuit device according to embodiments of the inventive concept;
3 is a cross-sectional view illustrating another example of a structure containing a first work function regulating metal and a structure containing a second work function regulating metal of an integrated circuit device according to embodiments of the inventive concept;
4 is a cross-sectional view illustrating an integrated circuit device according to other exemplary embodiments according to the inventive concept.
5 is a cross-sectional view illustrating still another example of a structure containing a first work function control metal and a structure containing a second work function control metal of an integrated circuit device according to embodiments of the inventive concept;
6 is a cross-sectional view illustrating an integrated circuit device according to still other embodiments according to the inventive concept.
7 is a cross-sectional view illustrating an integrated circuit device according to still other embodiments according to the inventive concept.
8A to 8D are cross-sectional views illustrating a process sequence in order to explain a method of manufacturing an integrated circuit device according to embodiments according to the inventive concept.
9A to 9E are cross-sectional views illustrating a process sequence in order to explain a method of manufacturing an integrated circuit device according to other embodiments according to the inventive concept.
10A to 10D are cross-sectional views illustrating a process sequence in order to explain a method of manufacturing an integrated circuit device according to still other embodiments according to the inventive concept.
11A to 11C are cross-sectional views illustrating a process sequence in order to explain a method of manufacturing an integrated circuit device according to still other embodiments according to the inventive concept.
12A to 12C are cross-sectional views illustrating a process sequence in order to explain a method of manufacturing an integrated circuit device according to still other embodiments according to the inventive concept.
13A to 13C are cross-sectional views illustrating a process sequence in order to explain a method of manufacturing an integrated circuit device according to still other embodiments according to the inventive concept.
14A to 14D are cross-sectional views illustrating a process sequence in order to explain a method of manufacturing an integrated circuit device according to still other embodiments according to the inventive concept.
15A to 15F are cross-sectional views illustrating a process sequence in order to explain a method of manufacturing an integrated circuit device according to still other embodiments according to the inventive concept.
16A to 16C are views for explaining an integrated circuit device according to embodiments according to the inventive concept, and FIG. 16A is a perspective view illustrating main components of an integrated circuit device including transistors having a FinFET structure. , FIG. 16B is a cross-sectional view taken along lines B1 - B1' and line B2 - B2' of FIG. 16A, and FIG. 16C is a cross-sectional view taken along line C1 - C1' and line C2 - C2' of FIG. 16A.
17A and 17B are diagrams for explaining an integrated circuit device according to embodiments according to the inventive concept, and FIG. 17A is a plan layout diagram of an integrated circuit device including transistors having a FinFET structure, and FIG. 17B is a cross-sectional view taken along lines B1 - B1' and B2 - B2' of FIG. 17A.
18A to 18E are cross-sectional views illustrating a process sequence to explain a method of manufacturing an integrated circuit device including transistors having a FinFET structure according to embodiments of the inventive concept.
19 is a block diagram of an integrated circuit device according to embodiments according to the inventive concept.
20 is a block diagram of an electronic system according to embodiments of the inventive concept.

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings. The same reference numerals are used for the same components in the drawings, and duplicate descriptions thereof are omitted.

The embodiments of the present invention are provided to more completely explain the present invention to those of ordinary skill in the art, and the following embodiments may be modified in various other forms, and the scope of the present invention It is not limited to the following examples. Rather, these examples are provided so that this disclosure will be more thorough and complete, and will fully convey the spirit of the invention to those skilled in the art.

Although the terms first, second, etc. are used herein to describe various members, regions, layers, regions, and/or components, these members, parts, regions, layers, regions, and/or components refer to these terms. It is self-evident that it should not be limited by These terms do not imply a specific order, upper and lower, or superiority, and are used only to distinguish one member, region, region, or component from another member, region, region, or component. Accordingly, a first member, region, region, or component described below may refer to a second member, region, region, or component without departing from the teachings of the present invention. For example, without departing from the scope of the present invention, a first component may be referred to as a second component, and similarly, the second component may also be referred to as a first component.

Unless defined otherwise, all terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which the inventive concept belongs, including technical and scientific terms. In addition, commonly used terms as defined in the dictionary should be construed as having a meaning consistent with their meaning in the context of the relevant technology, and unless explicitly defined herein, in an overly formal sense. It will be understood that they shall not be construed.

In cases where certain embodiments may be implemented otherwise, a specific process sequence may be performed different from the described sequence. For example, two processes described in succession may be performed substantially simultaneously, or may be performed in an order opposite to the described order.

In the accompanying drawings, variations of the illustrated shapes can be expected, for example depending on manufacturing technology and/or tolerances. Accordingly, the embodiments of the present invention should not be construed as limited to the specific shape of the region shown in the present specification, but should include, for example, changes in shape resulting from the manufacturing process. As used herein, all terms “and/or” include each and every combination of one or more of the recited elements. Also, as used herein, the term “substrate” may refer to a substrate itself or a laminate structure including a substrate and a predetermined layer or film formed on the surface thereof. Also, in this specification, the term "surface of a substrate" may mean an exposed surface of the substrate itself, or an outer surface of a predetermined layer or film formed on the substrate. In this specification, the term "high dielectric film" may mean a dielectric film made of a metal oxide having a higher dielectric constant than a _{silicon dioxide film (SiO 2 film).} As used herein, the term “oxygen content” may mean the number of oxygen atoms per unit volume, unless otherwise defined.

1 is a cross-sectional view illustrating an integrated circuit device according to embodiments according to the inventive concept.

Referring to FIG. 1 , the integrated circuit device 100 includes a substrate 110 having a first region I in which a first active region AC1 is formed and a second region II in which a second active region AC2 is formed. ) is included.

The first region I and the second region II refer to different regions of the substrate 110 , and may be regions performing different functions on the substrate 110 . The first region I and the second region II may be spaced apart from each other or may be connected to each other.

In some embodiments, the first transistor TR11 and the second transistor TR12 each requiring different threshold voltages may be formed in the first region I and the second region II.

The first transistor TR11 formed in the first region I includes the first interface layer 112 , the first high-k layer 122 , and the first gate stack GS11 sequentially formed on the first active region AC1 . include The first gate stack GS11 includes a first work function control metal-containing structure 132 formed on the first high-k film 122 , and a first upper gate covering the first work function control metal-containing structure 132 . membrane 142 .

The second transistor TR12 formed in the second region II connects the second interface layer 114 , the second high-k layer 124 , and the second gate stack GS12 sequentially formed on the second active region AC2 . include The second gate stack GS12 includes a second work function control metal-containing structure 134 formed on the second high-k film 124 , and a second upper gate covering the second work function control metal-containing structure 134 . membrane 144 .

In some embodiments, channels of different conductivity types may be formed in the first channel region CH1 of the first transistor TR11 and the second channel region CH2 of the second transistor TR12 . For example, the first region I may be an NMOS transistor region, and an N-type channel may be formed in the first channel region CH1 . The second region II is a PMOS transistor region, and a P-type channel may be formed in the second channel region CH2 . In this case, the first work function control metal-containing structure 132 constituting the first transistor TR11 has a work function of about 4.1 to 4.5 eV, and the second work function control structure constituting the second transistor TR12 is controlled. The metal-containing structure 134 may have a workfunction between about 4.8 and 5.2 eV.

In some other embodiments, the first channel region CH1 formed in the first active region AC1 and the second channel region CH2 formed in the second active region AC2 have a channel of the same conductivity type. can be formed.

In one example, each of the first region I and the second region II may be an NMOS transistor region. In this case, the first region (I) is a low-voltage NMOS transistor region requiring a lower threshold voltage than in the second region (II), and the second region (II) requires a higher threshold voltage than in the first region (I). It may be a high-voltage NMOS transistor region.

In another example, the first region I and the second region II may each be a PMOS transistor region. In this case, the first region (I) is a high voltage PMOS transistor region requiring a higher threshold voltage than in the second region (II), and the second region (II) requires a lower threshold voltage than in the first region (I). It may be a low-voltage PMOS transistor region.

In some other embodiments, the first region (I) is a region in which transistors having a lower threshold voltage and a faster switching speed than in the second region (II) are formed, and the second region (II) is the first region (I) ) may be a region in which a transistor with high threshold voltage and high reliability is formed even if the switching speed is not fast. For example, the first region I may be a cell array region in which unit memory cells are arranged in a matrix form. In some embodiments, the second region II may be a logic cell region or a memory cell region. Also, in the second region II, peripheral circuits performing a function of inputting external data into the internal circuit of the integrated circuit device 100 or outputting data from the internal circuit of the integrated circuit device 100 to the outside are formed It may be a peripheral circuit area. In some embodiments, the second region II may form a part of an input/output (I/O) circuit device. However, the above description is only an example, and the technical spirit of the present invention is not limited to the above illustration. For example, unlike the above example, the first region I may be a logic cell region or a memory cell region, and the second region II may be a peripheral circuit region.

The first interface layer 112 and the second interface layer 114 may be formed of a layer obtained by oxidizing the surfaces of the first active region AC1 and the second active region AC2, respectively. The first interface layer 112 may serve to heal an interface defect between the first active region AC1 and the first high-k layer 122 . The second interface layer 114 may serve to heal an interface defect between the first active region AC2 and the second high-k layer 124 .

In some embodiments, the first interface layer 112 and the second interface layer 114 may be formed of a low-k material layer having a dielectric constant of about 9 or less, for example, a silicon oxide layer, a silicon oxynitride layer, or a combination thereof. have. In some other embodiments, the first interface layer 112 and the second interface layer 114 may be formed of silicate, a combination of silicate and a silicon oxide layer, or a combination of silicate and a silicon oxynitride layer. In some embodiments, the first interface layer 112 and the second interface layer 114 may have a thickness of about 5 to 20 Å, but is not limited thereto. In some embodiments, the first interface layer 112 and the second interface layer 114 may be omitted.

Each of the first high-k layer 122 and the second high-k layer 124 may be formed of a metal oxide having a higher dielectric constant than that of a silicon oxide layer. For example, each of the first high-k layer 122 and the second high-k layer 124 may have a dielectric constant of about 10 to 25. The first high-k layer 122 and the second high-k layer 124 may include hafnium oxide, hafnium oxynitride, hafnium silicon oxide, lanthanum oxide, and lanthanum aluminum. lanthanum aluminum oxide, zirconium oxide, zirconium silicon oxide, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium Barium titanium oxide, strontium titanium oxide, yttrium oxide, aluminum oxide, lead scandium tantalum oxide, lead zinc niobate , and may be made of a material selected from combinations thereof, but is not limited thereto.

The first high-k layer 122 and the second high-k layer 124 may be formed by an atomic layer deposition (ALD), chemical vapor deposition (CVD), or physical vapor deposition (PVD) process. Each of the first high-k layer 122 and the second high-k layer 124 may have a thickness of about 10 to 40 Å, but is not limited thereto.

In some embodiments, the first high-k layer 122 and the second high-k layer 124 may be formed of metal oxide layers having different oxygen vacancy densities. In some embodiments, the second high-k layer 124 may have a lower oxygen vacancy density than that of the first high-k layer 122 . For example, the oxygen vacancy density in the first high-k film 122 is about 1 × 10 ¹² cm ^-3 or more, and the oxygen vacancy density in the second high-k film 124 is about 1 × 10 ^{It may be less than 12} cm ^-3 , but this is only an example, and the technical spirit of the present invention is not limited thereto.

In some other embodiments, the first high-k layer 122 and the second high-k layer 124 may be formed of metal oxide layers having different oxygen contents. Here, the term “oxygen content” refers to the number of oxygen atoms per unit volume of each of the first high-k film 122 and the second high-k film 124 . In some embodiments, the first high-k layer 122 is formed of a non-stoichiometric oxygen-deficient metal oxide layer that does not satisfy stoichiometry, and the second high-k layer 124 does not satisfy stoichiometry. It may be formed of a metal oxide film, or a non-stoichiometric oxygen-rich metal oxide film that does not satisfy stoichiometry. For example, when the first high-k layer 122 and the second high-k layer 124 are each made of hafnium oxide, the first high-k layer 122 is an HfO _{2 -x} (0.6 ≤ x ≤ 1) layer. and the second high-k film 124 _{may be formed of an HfO x} (x ≥ 2) film.

The first high-k layer 122 and the second high-k layer 124 may each exist in a crystalline phase or an amorphous phase. The density and/or oxygen content of oxygen vacancy in the first high-k film 122 and the second high-k film 124 may affect threshold voltages of the first and second transistors TR11 and TR12, respectively. have. For example, by forming the first high-k film 122 to have a relatively high oxygen vacancy density and the second high-k film 124 to have a relatively low oxygen vacancy density, the first transistor A desired threshold voltage may be obtained in the TR11 and the second transistor TR12, respectively. Alternatively, the first high-k layer 122 is formed to have an oxygen content lower than the stoichiometric oxygen content, and the second high-k layer 124 has an oxygen content higher than that of the first high-k layer 122 . By forming to have an oxygen content or to have an oxygen content satisfying a stoichiometry, desired threshold voltages may be obtained in each of the first transistor TR11 and the second transistor TR12 .

In the first region I, the first work function control metal-containing structure 132 may include a first conductive layer in contact with the first high-k layer 122 and having a first oxygen content. In the second region II, the second work function control metal-containing structure 134 includes a second conductive layer in contact with the second high-k layer 124 and having a second oxygen content greater than the first oxygen content. can do. Here, the term “oxygen content” refers to the number of oxygen atoms per unit volume of each of the first conductive layer and the second conductive layer. The first conductive layer formed in the first region I may be the first conductive layer 132A1 illustrated in FIG. 2 or the first conductive layer 132B1 illustrated in FIG. 3 . The second conductive layer formed in the second region II may be the second conductive layers 134A1 and 134A2 illustrated in FIG. 2 or the second conductive layer 134B1 illustrated in FIG. 3 . The first conductive layer 132A1 , the first conductive layer 132B1 , the second conductive layers 134A1 and 134A2 , and the second conductive layer 134B1 will be described later with reference to FIGS. 2 and 3 .

A first conductive layer constituting the first work function control metal-containing structure 132 in the first region (I), and a second layer constituting the second work function control metal-containing structure 134 in the second region (II) Each of the conductive layers may include a metal including Ti, Ta, Al, and a combination thereof. In some embodiments, the first conductive film is a Ti film, a TiN film, a TiON film, a TiO film, a Ta film, a TaN film, a TaON film, an oxygen-doped TiAlN (hereinafter referred to as “TiAlN(O)”) film; It may be formed of an oxygen-doped TaAlN (hereinafter, referred to as “TaAlN(O)”) film, or a combination thereof. The second conductive layer may be formed of a TiON layer, a TiO layer, a TaON layer, a TiAlN(O) layer, a TaAlN(O) layer, or a combination thereof.

In some embodiments, the first work function control metal-containing structure 132 is formed of a single layer having a first thickness TH11, and the second work function control metal-containing structure 134 has a second thickness ( TH11 ). TH12) may be formed of a single layer or multiple layers. The second thickness TH12 may be the same as or similar to the first thickness TH11.

The first upper gate layer 142 covering the first work function control metal-containing structure 132 and the second upper gate layer 144 covering the second work function control metal-containing structure 134 are formed of the same material. can be made with

In some embodiments, the first upper gate layer 142 and the second upper gate layer 144 are formed on the first work function control metal-containing structure 132 and the second work function control metal-containing structure 134 , respectively. It may include an upper work function control layer, a conductive barrier layer, a gap-fill metal layer, or a combination thereof sequentially stacked on the .

The upper work function control layer may be formed of TiAl, TiAlC, TiAlN, TiC, TaC, HfSi, or a combination thereof, but is not limited thereto.

The conductive barrier layer may be formed of a metal nitride, for example, TiN, TaN, or a combination thereof, but is not limited thereto.

The gap-fill metal layer may be formed to fill a gate space remaining on the conductive barrier layer. The gap-fill metal layer may be made of W.

The upper work function control layer, the conductive barrier layer, and the gap-fill metal layer may be respectively formed by an ALD, CVD, or PVD process. In some embodiments, at least one of the upper work function control layer, the conductive barrier layer, and the gap-fill metal layer may be omitted in the first region I and the second region II, respectively.

FIG. 2 is a cross-sectional view for explaining a more specific example of a partial configuration of the integrated circuit device 100 illustrated in FIG. 1 . In Fig. 2, the same reference numerals as in Fig. 1 denote the same members, and detailed descriptions thereof are omitted herein.

2 shows a first work function control metal-containing structure 132A and a second work function that can be employed as the first work function control metal-containing structure 132 and the second work function control metal-containing structure 134 illustrated in FIG. 1 . A conditioning metal containing structure 134A is illustrated.

Referring to FIG. 2 , the first work function control metal-containing structure 132A includes a first conductive layer 132A1 that is in direct contact with the first high-k layer 122 and is a single layer having a first thickness TH11. . The first conductive film 132A1 may be formed of a Ti film, a TiN film, a TiON film, a TiO film, a Ta film, a TaN film, a TaON film, a TiAlN(O) film, a TaAlN(O) film, or a combination thereof. .

The second work function control metal-containing structure 134A includes second conductive layers 134A1 and 134A2 formed on the same level as the first conductive layer 132A1 and formed of a multilayer having a second thickness TH12. do. The second thickness TH12 may be the same as or similar to the first thickness TH11.

The second conductive layers 134A1 and 134A2 include a lower second conductive layer 134A1 in direct contact with the second high-k layer 124 , and an upper second conductive layer 134A2 covering the lower second conductive layer 134A1 . includes The upper second conductive layer 134A2 has an oxygen content greater than that of the first conductive layer 132A1 formed in the first region I.

In some embodiments, the lower second conductive layer 134A1 may have an oxygen content that is the same as or similar to that of the first conductive layer 132A1 formed in the first region I. For example, the lower second conductive film 134A1 may be a Ti film, a TiN film, a TiON film, a TiO film, a Ta film, a TaN film, a TaON film, a TiAlN(O) film, a TaAlN(O) film, or a combination thereof. It can be done in combination.

In some embodiments, the lower second conductive layer 134A1 may be formed of a metal-containing layer that does not include oxygen. For example, the lower second conductive layer 134A1 may be formed of a Ti layer, a TiN layer, a Ta layer, a TaN layer, or a combination thereof.

In some embodiments, the upper second conductive layer 134A2 may be formed of a metal-containing layer including oxygen. For example, the upper second conductive layer 134A2 may be formed of a TiON layer, a TiO layer, a TaON layer, a TiAlN(O) layer, a TaAlN(O) layer, or a combination thereof.

In some embodiments, the first conductive layer 132A1 formed in the first region I and the lower second conductive layer 134A1 formed in the second region II may be made of the same material having the same composition. The first conductive layer 132A1 , the lower second conductive layer 134A1 , and the upper second conductive layer 134A2 may include the same metal. In an example, the first conductive layer 132A1 and the lower second conductive layer 134A1 may be formed of a TiN layer, and the upper second conductive layer 134A2 may be formed of a TiON layer. In another example, each of the first conductive layer 132A1 , the lower second conductive layer 134A1 , and the upper second conductive layer 134A2 is formed of a TiON layer, and is formed in the upper second conductive layer 134A2 . Oxygen content of the first conductive layer 132A1 and the lower second conductive layer 134A1 may be greater than the oxygen content of each. For example, the oxygen content in the upper second conductive layer 134A2 is greater than the oxygen content in each of the first conductive layer 132A1 and the lower second conductive layer 134A1 by about 5 to 30 atoms per unit volume. It can be as many as %.

A thickness THA2 of the upper second conductive layer 134A2 may be smaller than the first thickness TH11 and smaller than the second thickness TH12. In some embodiments, the thickness THA2 of the upper second conductive layer 134A2 may be about 10 to 90% of the first thickness TH11, or about 10 to 90% of the second thickness TH12. , the technical spirit of the present invention is not limited thereto. The sum of the thickness of the lower second conductive layer 134A1 and the thickness THA2 of the upper second conductive layer 134A2 is the first thickness TH11 of the first conductive layer 132A1 formed in the first region I ) can be the same as

FIG. 3 is a cross-sectional view for explaining another more specific example of a partial configuration of the integrated circuit device 100 illustrated in FIG. 1 . In Fig. 3, the same reference numerals as in Figs. 1 and 2 denote the same members, and detailed descriptions thereof are omitted herein.

3 shows a first work function control metal-containing structure 132B and a second work function employable as the first work function control metal-containing structure 132 and the second work function control metal-containing structure 134 illustrated in FIG. 1 . A conditioning metal containing structure 134B is illustrated.

Referring to FIG. 3 , the first work function control metal-containing structure 132B includes a first conductive layer 132B1 that is in direct contact with the first high-k layer 122 and is made of a single layer having a first thickness TH11. . A more detailed configuration of the first conductive layer 132B1 is substantially the same as that described for the first conductive layer 132A1 with reference to FIG. 2 .

The second work function control metal-containing structure 134B includes a second conductive layer 134B1 formed on the same level as the first conductive layer 132B1 and made of a single layer having a second thickness TH12.

The first thickness TH11 of the first conductive layer 132B1 and the second thickness TH12 of the second conductive layer 134B1 may be the same.

The second conductive layer 134B1 is in direct contact with the second high-k layer 124 , and has an oxygen content greater than an oxygen content in the first conductive layer 132B1 formed in the first region (I).

In some embodiments, the first conductive layer 132B1 and the second conductive layer 134B1 may include the same metal.

In some embodiments, the first conductive layer 132B1 may be formed of a metal-containing layer not containing oxygen, and the second conductive layer 134B1 may be formed of a metal-containing layer containing oxygen.

In some other embodiments, each of the first conductive layer 132B1 and the second conductive layer 134B1 is formed of a metal-containing layer including oxygen, and the oxygen content in the first conductive layer 132B1 is The oxygen content in the second conductive layer 134B1 may be less by about 5 to 30 atomic % per unit volume.

In some embodiments, the first conductive film 132B1 is a Ti film, a TiN film, a TiON film, a TiO film, a Ta film, a TaN film, a TaON film, a TiAlN(O) film, a TaAlN(O) film, or these films. can be made by a combination of In some embodiments, the second conductive layer 134B1 may be formed of a TiON layer, a TiO layer, a TaON layer, a TiAlN(O) layer, a TaAlN(O) layer, or a combination thereof. In one example, the first conductive layer 132B1 may be formed of a TiN layer, and the second conductive layer 134B1 may be formed of a TiON layer. In another example, each of the first conductive layer 132B1 and the second conductive layer 134B1 is formed of a TiON layer, and the oxygen content in the second conductive layer 134B1 is determined by the first conductive layer 132B1. It may be greater than the oxygen content within.

4 is a cross-sectional view illustrating an integrated circuit device according to other exemplary embodiments according to the inventive concept. In Fig. 4, the same reference numerals as in Fig. 1 denote the same members, and detailed descriptions thereof are omitted herein.

Referring to FIG. 4 , the integrated circuit device 200 includes a first transistor TR21 formed in a first region I of a substrate 110 and a second transistor TR22 formed in a second region II of a substrate 110 . do.

The first transistor TR21 includes a first interface layer 112 , a first high-k layer 122 , and a first gate stack GS21 sequentially formed on the first active region AC1 . The first gate stack GS21 includes a first work function control metal-containing structure 132 formed on the first high-k film 122 , and a first upper gate covering the first work function control metal-containing structure 132 . membrane 142 .

The second transistor TR22 includes a second interface layer 114 , a second high-k layer 224 , and a second gate stack GS22 sequentially formed on the second active region AC2 . The second high-k film 224 may have substantially the same configuration as that described for the second high-k film 124 with reference to FIG. 1 . The second gate stack GS22 includes a second work function control metal-containing structure 234 formed on the second high-k film 224 , and a second upper gate covering the second work function control metal-containing structure 234 . membrane 144 .

In some embodiments, the first high-k layer 122 and the second high-k layer 224 may be formed of metal oxide layers having different oxygen vacancy densities. In some embodiments, the second high-k film 224 may have a lower oxygen vacancy density than that of the first high-k film 122 .

In some other embodiments, the first high-k layer 122 and the second high-k layer 224 may be formed of metal oxide layers having different oxygen contents. In some embodiments, the first high-k film 122 is formed of an oxygen-deficient metal oxide film that does not satisfy stoichiometry, and the second high-k film 224 is a metal oxide film that does not satisfy stoichiometry, or has a stoichiometry. It may consist of an unsatisfactory oxygen-excessive metal oxide film. For example, the first high-k film 122 may be formed of an HfO _{2 -x} (0.6 ≤ x ≤ 1) film, and the second high-k film 224 _{may be formed of an HfO x} (x ≥ 2) film. .

The first work function control metal-containing structure 132 may include a first conductive layer in contact with the first high-k layer 122 and having a first oxygen content. The second work function control metal-containing structure 234 may include a second conductive layer in contact with the second high-k layer 224 and having a second oxygen content greater than the first oxygen content. In some embodiments, a more detailed configuration of the first conductive layer and the second conductive layer may be the same as described with reference to FIG. 1 . In some other embodiments, the first conductive layer may be the first conductive layer 132C1 illustrated in FIG. 5 . The second conductive layer may be the lower second conductive layer 234C1 illustrated in FIG. 5 . The first conductive layer 132C1 and the lower second conductive layer 234C1 will be described later with reference to FIG. 5 .

In some embodiments, the first work function control metal-containing structure 132 is formed of a single layer having a first thickness TH21, and the second work function control metal-containing structure 234 has a second thickness ( TH21 ). TH22) may be formed of a single layer or multiple layers. The second thickness TH22 may be greater than the first thickness TH21.

FIG. 5 is a cross-sectional view for explaining a more specific example of a partial configuration of the integrated circuit device 200 illustrated in FIG. 4 . In Fig. 5, the same reference numerals as in Figs. 1 to 4 denote the same members, and detailed descriptions thereof are omitted herein.

5 shows a first work function control metal-containing structure 132C and a second work function employable as the first work function control metal-containing structure 132 and the second work function control metal-containing structure 234 illustrated in FIG. 4 . A conditioning metal containing structure 234C is illustrated.

The first work function control metal-containing structure 132C formed in the first region I includes a first conductive layer 132C1 formed of a single layer having a first thickness TH21 in direct contact with the first high-k layer 122 . include The first conductive film 132C1 may be formed of a Ti film, a TiN film, a TiON film, a TiO film, a Ta film, a TaN film, a TaON film, a TiAlN(O) film, a TaAlN(O) film, or a combination thereof. .

The second work function control metal-containing structure 234C formed in the second region II includes second conductive layers 234C1 and 234C2 formed of a multilayer having a second thickness TH22. The second thickness TH22 is greater than the first thickness TH21.

The second conductive layers 234C1 and 234C2 include a lower second conductive layer 234C1 in direct contact with the second high-k layer 224 and an upper second conductive layer 234C2 covering the lower second conductive layer 234C1. includes The lower second conductive layer 234C1 may have an oxygen content greater than that of the first conductive layer 132C1 formed in the first region (I). The upper second conductive layer 234C2 may have an oxygen content less than that of the lower second conductive layer 234C1 . In some embodiments, the upper second conductive layer 234C2 may have the same oxygen content as that of the first conductive layer 132C1 formed in the first region I. For example, each of the first conductive layer 132C1 and the upper second conductive layer 234C2 has an oxygen content less than the oxygen content in the lower second conductive layer 234C1 by about 5 to 30 atomic% per unit volume. It may have an oxygen content, but is not limited thereto.

In some embodiments, the lower second conductive film 234C1 is a metal-containing film including oxygen, for example, a TiON film, a TiO film, a TaON film, a TiAlN(O) film, a TaAlN(O) film, or these films. can be made by a combination of

In some embodiments, the first conductive layer 132C1 and the upper second conductive layer 234C2 may be formed of a metal-containing layer that does not contain oxygen. For example, the first conductive layer 132C1 and the upper second conductive layer 234C2 may be formed of a Ti layer, a TiN layer, a Ta layer, a TaN layer, or a combination thereof.

In some other embodiments, the first conductive layer 132C1 and the upper second conductive layer 234C2 may be formed of a metal-containing layer including oxygen. In this case, the oxygen content in the first conductive layer 132C1 and the upper second conductive layer 234C2 may be less than the oxygen content in the lower second conductive layer 234C1 .

In some embodiments, the first conductive layer 132C1 formed in the first region I and the upper second conductive layer 234C2 formed in the second region II may be made of the same material having the same composition.

The first conductive layer 132C1 formed in the first region (I) and the lower second conductive layer 234C1 and the upper second conductive layer 234C2 formed in the second region (II) may include the same metal. can In one example, the first conductive layer 132C1 and the upper second conductive layer 234C2 may be formed of a TiN layer, and the lower second conductive layer 234C1 may be formed of a TiON layer. In another example, each of the first conductive layer 132C1 , the lower second conductive layer 234C1 , and the upper second conductive layer 234C2 is made of a TiON layer, and is formed in the lower second conductive layer 234C1 . Oxygen content of , may be greater than oxygen content in the first conductive layer 132C1 and the upper second conductive layer 234C2 .

In some embodiments, the thickness THC2 of the upper second conductive layer 234C2 may be the same as the first thickness TH21 of the first conductive layer 132C1 .

6 is a cross-sectional view illustrating an integrated circuit device according to still other embodiments according to the inventive concept. In Fig. 6, the same reference numerals as in Fig. 1 denote the same members, and detailed descriptions thereof are omitted herein.

Referring to FIG. 6 , the integrated circuit device 300 has substantially the same configuration as the integrated circuit device 100 illustrated in FIG. 1 . However, the integrated circuit device 300 further includes a third transistor TR13 formed in the third region III of the substrate 110 .

The third transistor TR13 has a third interface layer 116 , a third high-k dielectric layer 126 , and a third gate sequentially formed on the third active region AC3 in the third region III of the substrate 110 . and a stack GS13. The third gate stack GS13 includes a third work function control metal-containing structure 136 formed on the third high-k film 126 , and a third upper gate covering the third work function control metal-containing structure 136 . membrane 146 .

The third region (III) may be a region spaced apart from at least one of the first region (I) and the second region (II), and includes at least one of the first region (I) and the second region (II); They may be areas connected to each other.

In some embodiments, different threshold voltages may be required for the first transistor TR11 , the second transistor TR12 , and the third transistor TR13 .

In some embodiments, the third channel region CH13 of the third transistor TR13 includes the first channel region CH11 of the first transistor TR11 and the second channel region CH12 of the second transistor TR12 . A channel having the same conductivity type as that in at least one channel region may be formed. For example, an N-type channel or a P-type channel may be formed in the third channel region CH13 .

In some other embodiments, the third channel region CH13 of the third transistor TR13 includes the first channel region CH11 of the first transistor TR11 and the second channel region CH12 of the second transistor TR12 . ), a channel of the same conductivity type as that in any one channel region is formed, but a channel of a conductivity type opposite to that of the other channel region may be formed. In one example, two transistors selected from among the first to third transistors TR11, TR12, and TR13 may be NMOS transistors, and the other transistor may be a PMOS transistor. In another example, one transistor selected from among the first to third transistors TR11, TR12, and TR13 may be an NMOS transistor, and the other two transistors may be a PMOS transistor.

In some embodiments, the first channel region CH11 formed in the first active region AC1 , the second channel region CH12 formed in the second active region AC2 , and the third active region AC3 Channels of the same conductivity type may be formed in the third channel region CH13 formed in .

In one example, the first region I, the second region II, and the third region III are all NMOS transistor regions, and the first channel region CH11 , the second channel region CH12 , and the second region III An N-type channel may be formed in each of the three channel regions CH13. In this case, the first region (I) is a low-voltage NMOS transistor region requiring a lower threshold voltage than in the second region (II), and the third region (III) is a high-voltage NMOS transistor region higher than that in the first region (I). , and the second region II may be a medium voltage NMOS transistor region in which a threshold voltage higher than that of the first region I but lower than that of the third region II is required.

In another example, the first region I, the second region II, and the third region III are all PMOS transistor regions, and the first channel region CH11 , the second channel region CH12 , and the second region III A P-type channel may be formed in each of the three channel regions CH13. In this case, the first region (I) is a high-voltage PMOS transistor region requiring a higher threshold voltage than in the second region (II), and the third region (III) is a low-voltage PMOS transistor region lower than that in the first region (I). , and the second region II may be an intermediate voltage PMOS transistor region in which a threshold voltage lower than in the first region I and higher than in the third region II is required.

In some embodiments, the first region I, the second region II, and the third region III may each independently be a logic cell region, a memory cell region, or a peripheral circuit region.

In the integrated circuit device 300 illustrated in FIG. 6 , the third interface layer 116 may be formed of a layer obtained by oxidizing the surface of the third active region AC3 . The third interface layer 116 may serve to heal an interface defect between the third active region AC3 and the third high-k layer 126 . A more detailed configuration of the third interface layer 116 is substantially the same as that described for the first interface layer 112 and the second interface layer 114 with reference to FIG. 1 . In some embodiments, the third interface layer 116 may be omitted.

The third high-k film 126 may have substantially the same configuration as described for the first high-k film 122 and the second high-k film 124 with reference to FIG. 1 . However, the first high-k layer 122 , the second high-k layer 124 , and the third high-k layer 126 may have different oxygen vacancy densities. In some embodiments, the third high-k film 126 may have an oxygen vacancy density lower than the oxygen vacancy density of the first high-k film 122 and the second high-k film 124 .

The first high-k layer 122 , the second high-k layer 124 , and the third high-k layer 126 may have different oxygen contents. In some embodiments, the third high-k layer 126 may have an oxygen content higher than that of the first high-k layer 122 and the second high-k layer 124 .

For example, each of the first high-k layer 122 , the second high-k layer 124 , and the third high-k layer 126 may be formed of hafnium oxide. In this case, the first high-k film 122 and the second high-k film 124 are formed of an HfO _{2 -x} (0.6 ≤ x ≤ 1) film, and a second high-k film ( The oxygen content in 124 is higher, and the third high-k film 126 _{may be formed of an HfO x} (x ≥ 2) film. Alternatively, the first high-k film 122 is formed of an HfO _2-x (0.6 ≤ x ≤ 1) film, and the second high-k film 124 and the third high-k film 126 are formed of HfO _x (x ≥ 2). ) layer, but the oxygen content in the third high-k layer 126 may be higher than in the second high-k layer 124 .

The third work function control metal-containing structure 136 may be formed to be in contact with the third high-k film 126 . The third work function control metal-containing structure 136 has a third conductivity having a third oxygen content greater than a second oxygen content in the second work function control metal-containing structure 134 formed in the second region II. It may include a membrane. The third conductive layer may be formed of a metal-containing layer having a higher oxygen content than that of the second conductive layer constituting the second work function control metal-containing structure 134 . The third conductive layer may be formed of a single layer or multiple layers having a third thickness TH13. The third thickness TH13 may be the same as or similar to the first thickness TH11. In some embodiments, the third conductive layer may be formed of a TiON layer, a TiO layer, a TaON layer, a TiAlN(O) layer, a TaAlN(O) layer, or a combination thereof.

The third upper gate layer 146 covering the third work function control metal-containing structure 136 is formed on the first upper gate layer 142 formed in the first region (I) and/or in the second region (II). It may be made of the same material as that of the formed second upper gate layer 144 . In some embodiments, the third upper gate layer 146 is an upper work function control layer, a conductive barrier layer, and a gap-fill metal layer, similarly to the first upper gate layer 142 and the second upper gate layer 144 . , or a combination thereof. For a more detailed configuration of the upper work function control layer, the conductive barrier layer, and the gap-fill metal layer, refer to FIG. 1 , for adjusting the upper work function constituting the first upper gate layer 142 and the second upper gate layer 144 . Reference is made to the description of the film, the conductive barrier film, and the gap-fill metal film. In some embodiments, in the third transistor TR13 , at least one of an upper work function control layer, a conductive barrier layer, and a gap-fill metal layer constituting the third upper gate layer 146 may be omitted.

In some embodiments, the third work function control metal-containing structure 136 included in the third transistor TR13 has the same structure as the second work function control metal-containing structure 134A described with reference to FIG. 2 . However, it may have a higher oxygen content than in the second work function control metal-containing structure 134A.

In some other embodiments, the third work function control metal-containing structure 136 included in the third transistor TR13 has the same structure as the second work function control metal-containing structure 134B described with reference to FIG. 3 . However, it may have a higher oxygen content than in the second work function control metal-containing structure 134B.

7 is a cross-sectional view illustrating an integrated circuit device according to still other embodiments according to the inventive concept. In Fig. 7, the same reference numerals as in Figs. 1 to 6 denote the same members, and detailed descriptions thereof are omitted herein.

Referring to FIG. 7 , the integrated circuit device 400 has substantially the same configuration as the integrated circuit device 200 illustrated in FIG. 4 . However, the integrated circuit device 400 further includes a third transistor TR23 formed in the third region III of the substrate 110 .

The third transistor TR23 has a third interface layer 116 , a third high-k dielectric layer 226 , and a third gate sequentially formed on the third active region AC3 in the third region III of the substrate 110 . and a stack GS23. The third gate stack GS23 includes a third work function control metal-containing structure 236 formed on the third high-k film 226 , and a third upper gate covering the third work function control metal-containing structure 236 . membrane 146 .

In some embodiments, different threshold voltages may be required for the first transistor TR21 , the second transistor TR22 , and the third transistor TR23 .

In some embodiments, more details of the third transistor TR23 are substantially similar to those described with respect to the third transistor TR13 with reference to FIG. 6 . However, in the integrated circuit device 400 illustrated in FIG. 7 , the third work function control metal-containing structure 236 is substantially the same as the second work function control metal-containing structure 234 formed in the second region II. However, the third conductive layer may include a third conductive layer having a third oxygen content greater than a second oxygen content in the second work function control metal-containing structure 234 .

The third work function control metal-containing structure 236 may be formed of a multilayer having a third thickness TH23. The third thickness TH23 may be greater than the first thickness TH21 and may be the same as or similar to the second thickness TH22. In some embodiments, the third conductive layer constituting the third work function control metal-containing structure 236 is a TiON layer, a TiO layer, a TaON layer, a TiAlN(O) layer, a TaAlN(O) layer, or a combination thereof. can be made with

In some embodiments, the third work function control metal-containing structure 236 included in the third transistor TR23 has the same structure as the second work function control metal-containing structure 234C described with reference to FIG. 5 . However, it may have a higher oxygen content than in the second work function control metal-containing structure 234C.

Next, a method of manufacturing an integrated circuit device according to embodiments according to the technical spirit of the present invention will be described in detail.

8A to 8D are cross-sectional views illustrating a process sequence in order to explain a method of manufacturing an integrated circuit device according to embodiments according to the inventive concept. 8A to 8D, the same reference numerals as in FIGS. 1 to 7 denote the same members, and detailed description thereof will be omitted herein.

Referring to FIG. 8A , a substrate 110 having a first region (I) and a second region (II) is prepared.

The substrate 110 may include a semiconductor such as Si or Ge, or a compound semiconductor such as SiGe, SiC, GaAs, InAs, or InP. In some embodiments, the substrate 110 may be formed of at least one of a group III-V material and a group IV material. The group III-V material may be a binary, ternary, or quaternary compound including at least one group III element and at least one group V element. The group III-V material may be a compound including at least one of In, Ga, and Al as a group III element, and at least one of As, P, and Sb as a group V element. For example, the III-V material may be selected from InP, InzGa _1-z As (0 ≤ z ≤ 1), and Al _z Ga _1-z As (0 ≤ z ≤ 1). The binary compound may be, for example, any one of InP, GaAs, InAs, InSb, and GaSb. The ternary compound may be any one of InGaP, InGaAs, AlInAs, InGaSb, GaAsSb, and GaAsP. The group IV material may be Si or Ge. However, the group III-V material and the group IV material usable in the integrated circuit device according to the technical spirit of the present invention are not limited to those exemplified above. The group III-V material and the group IV material such as Ge may be used as a channel material for making a low-power, high-speed transistor. Using a semiconductor substrate made of a group III-V material, for example, GaAs, having high electron mobility compared to the Si substrate, and a semiconductor substrate made of a semiconductor material having high hole mobility compared to the Si substrate, for example, Ge. High-performance CMOS can be formed. In some embodiments, when forming the MMOS transistor on the substrate 110 , the substrate 110 may be formed of any one of the group III-V materials exemplified above. In some other embodiments, when the PMOS transistor is formed on the substrate 110 , at least a portion of the substrate 110 may be formed of Ge. In another example, the substrate 110 may have a silicon on insulator (SOI) structure. The substrate 110 may include a conductive region, for example, a well doped with an impurity or a structure doped with an impurity.

The first interface layer 112 is formed on the first active region AC1 of the first region I, and the second interface layer 114 is formed on the second active region AC2 of the second region II. do.

The first interface layer 112 and the second interface layer 114 may be simultaneously formed. The first interface layer 112 and the second interface layer 114 may be formed of a low-k material layer having a dielectric constant of about 9 or less, for example, a silicon oxide layer, a silicon oxynitride layer, or a combination thereof. In some embodiments, the first interface layer 112 and the second interface layer 114 may be obtained by oxidizing the surfaces of the first active region AC1 and the second active region AC2 , respectively. In some other embodiments, the first interface layer 112 and the second interface layer 114 may be formed of silicate, a combination of silicate and a silicon oxide layer, or a combination of silicate and a silicon oxynitride layer. In some embodiments, each of the first interface layer 112 and the second interface layer 114 may have a thickness of about 5 to 20 Å, but is not limited thereto.

A first high-k film 122 is formed on the first interface film 112 in the first region (I), and a second high-k film 124 is formed on the second interface film 114 in the second region (II). do.

In order to form the first high-k layer 122 and the second high-k layer 124 , after a preliminary high-k layer made of a metal oxide is formed, the preliminary high-k layer may be heat-treated. For a more detailed configuration of the preliminary high-k film, reference will be made to the description of the preliminary high-k film 120 with reference to FIG. 9A . The heat treatment may be performed in an oxygen atmosphere or an inert gas atmosphere, if necessary.

In some embodiments, in the heat treatment of the preliminary high-k film, a portion of the preliminary high-k film in the first region I is covered with a mask pattern (not shown) and a portion in the second region II is exposed. The heat treatment may be performed in an oxygen atmosphere in the In this case, the portion in the first region (I) of the preliminary high-k film remains as the first high-k film 122 without a change in composition, and the portion in the second region (I) is the first high-k film 122 . The second high-k film 124 may have a higher oxygen content than that of . As a result, the oxygen vacancy density in the first high-k film 122 may be higher than the oxygen vacancy density in the second high-k film 124 . The heat treatment may be performed at a temperature of about 400 to 1000 °C.

In some other embodiments, the heat treatment of the preliminary high-k film may be performed in an inert gas atmosphere, for example, a nitrogen atmosphere. In this case, there may be no substantial change in oxygen content in the preliminary high-k film in the first region I and the second region II. In this case, there may be no substantial difference in oxygen vacancy density in each of the first high-k film 122 and the second high-k film 124 .

A work function control metal-containing layer 130 is formed on the first high-k layer 122 and the second high-k layer 124 in the first region (I) and the second region (II).

In some embodiments, the work function control metal-containing film 130 is a Ti film, a TiN film, a TiON film, a TiO film, a Ta film, a TaN film, a TaON film, a TiAlN(O) film, a TaAlN(O) film, Or it may be made of a combination thereof, but is not limited to the above-described bar.

Referring to FIG. 8B , a mask pattern 160 that selectively covers only a portion of the work function control metal-containing layer 130 in the first region I is formed.

After the mask pattern 160 is formed, the work function control metal-containing layer 130 may be exposed in the second region II. The mask pattern 160 may be formed of, for example, a photoresist pattern or a hard mask pattern. The hard mask pattern may be formed of a silicon oxide film, a silicon nitride film, a polysilicon film, or a combination thereof, but is not limited thereto.

Referring to FIG. 8C , only a portion of the work function control metal-containing film 130 (refer to FIG. 8B ) of the second region II exposed through the mask pattern 160 is oxidized by a predetermined depth from the upper surface of the second region ( In II), an upper second conductive layer 134A2 is formed on an upper portion of the work function control metal-containing layer 130 . In the second region II, a portion of the work function control metal-containing layer 130 except for the upper second conductive layer 134A2 may remain as the lower second conductive layer 134A1 .

In the second region II, the oxidizing atmosphere 162 may be used to oxidize only a portion of the work function control metal-containing layer 130 to a predetermined depth from the top surface. In some embodiments, the oxidizing atmosphere 162 may include ozone water. For example, to form the upper second conductive film 134A2, the upper surface of the work function control metal-containing film 130 exposed in the second region II is brought into contact with ozone water for about 10 seconds to about 3 minutes. can To this end, ozone water may be sprayed onto the substrate 110 or the substrate 110 may be dipping into the ozone water. While the upper surface of the work function control metal-containing layer 130 exposed in the second region II is brought into contact with ozone water, the work function control metal containing metal is contained within a predetermined thickness range from the top surface of the work function control metal-containing layer 130 . A material constituting the film 130 may be oxidized. For example, when the work function control metal-containing layer 130 is made of a TiN layer, a portion of the work function control metal-containing layer 130 is oxidized to TiO by contact with the ozone water, and the lower second conductivity An upper second conductive layer 134A2 having a higher oxygen content than that of the layer 134A1 may be obtained.

The thickness THA2 of the upper second conductive layer 134A2 may be about 10 to 90% of the total thickness of the work function control metal-containing layer 130 , but is not limited to the above-described range.

While the upper second conductive layer 134A2 is formed in the second region II, the portion of the work function control metal-containing layer 130 in the first region I does not substantially change. 132A1) may remain.

Referring to FIG. 8D , after removing the mask pattern 160 (see FIG. 8C ) covering the first region I, the first upper gate layer is formed on the first conductive layer 132A1 in the first region I. 142 is formed, and a second upper gate layer 144 is formed on the upper second conductive layer 134A2 in the second region II.

In FIG. 8D , the first upper gate layer 142 has a stacked structure of a first conductive barrier layer 142A1 and a first gap-fill metal layer 142A2 , and the second upper gate layer 144 has a second conductive structure. A case in which the barrier layer 144A1 and the second gap-fill metal layer 144A2 are stacked is exemplified.

In some embodiments, each of the first conductive barrier layer 142A1 and the second conductive barrier layer 144A1 may be formed of TiN, TaN, or a combination thereof. In some embodiments, the first gap-fill metal layer 142A2 and the second gap-fill metal layer 144A2 may be formed of W.

In some embodiments, between the first conductive layer 132A1 and the first upper gate layer 142 , and/or between the upper second conductive layer 134A2 and the second upper gate layer 144 . An upper work function regulating layer may be further formed between the layers. The upper work function control layer may be formed of TiAlC, TiAlN, TiC, TaC, HfSi, or a combination thereof, but is not limited thereto.

According to the method of manufacturing the integrated circuit device described with reference to FIGS. 8A to 8D , the first transistor TR11 and the second transistor TR12 of the integrated circuit device 100 illustrated in FIG. 1 may be formed.

9A to 9E are cross-sectional views illustrating a process sequence in order to explain a method of manufacturing an integrated circuit device according to other embodiments according to the inventive concept. 9A to 9E, the same reference numerals as in FIGS. 1 to 8D denote the same members, and detailed description thereof will be omitted herein.

Referring to FIG. 9A , the first interface layer 112 is formed on the first active region AC1 in the first region I of the substrate 110 in the same manner as described with reference to FIG. 8A , and the second region In (II), the second interface layer 114 is formed on the second active region AC2.

Thereafter, a preliminary high-k dielectric layer 120 is formed on the first interface layer 112 and the second interface layer 114 in the first region (I) and the second region (II).

The preliminary high-k film 120 may include hafnium oxide, hafnium oxynitride, hafnium silicon oxide, lanthanum oxide, lanthanum aluminum oxide, zirconium oxide, zirconium silicon oxide, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide. It may be made of a material selected from oxide, yttrium oxide, aluminum oxide, lead scandium tantalum oxide, lead zinc niobate, and combinations thereof, but is not limited thereto.

A work function control metal-containing layer 230 is formed on the preliminary high-k layer 120 in the first region (I) and the second region (II).

The work function control metal-containing layer 230 may be formed of a metal-containing layer including oxygen. For example, the work function control metal-containing film 230 may be formed of a TiON film, a TiO film, a TaON film, a TiAlN(O) film, a TaAlN(O) film, or a combination thereof. it is not going to be

Referring to FIG. 9B , a mask pattern 260 that selectively covers only a portion of the work function control metal-containing layer 230 in the second region II is formed.

After the mask pattern 260 is formed, the work function control metal-containing layer 230 may be exposed in the first region I.

In some embodiments, the mask pattern 260 may be formed of a photoresist pattern. In some other embodiments, the mask pattern 260 may be formed of a hard mask pattern capable of providing an etch selectivity between the mask pattern 260 and the work function control metal-containing layer 230 . The hard mask pattern may be formed of a silicon oxide film, a silicon nitride film, a polysilicon film, or a combination thereof, but is not limited thereto.

Referring to FIG. 9C , the work function control metal-containing layer 230 (refer to FIG. 9B ) exposed in the first region (I) is removed to expose the preliminary high-k film 120 in the first region (I).

A portion of the work function control metal-containing layer 230 remaining in the second region II may become a lower second conductive layer 234C1 .

Referring to FIG. 9D , after the mask pattern 260 (see FIG. 9C ) covering the second region II is removed, conductive layers 132C1 and 234C2 are formed in the first region I and the second region II. to form

The conductive layers 132C1 and 234C2 are formed on the first conductive layer 132C1 formed on the preliminary high-k film 120 in the first region (I) and on the lower second conductive layer 234C1 in the second region (II). and an upper second conductive layer 234C2 to be formed. The conductive layers 132C1 and 234C2 may be simultaneously formed in the first region I and the second region II. The conductive layers 132C1 and 234C2 may have an oxygen content lower than that of the lower second conductive layer 234C1 formed in the second region II. In some embodiments, the conductive layers 132C1 and 234C2 may not include oxygen. In some other embodiments, the conductive layers 132C1 and 234C2 may have an oxygen content lower than that of the lower second conductive layer 234C1 by about 5 to 30 atomic % per unit volume. In some embodiments, the conductive films 132C1 and 234C2 are a Ti film, a TiN film, a TiON film, a TiO film, a Ta film, a TaN film, a TaON film, a TiAlN(O) film, a TaAlN(O) film, or these films. It may be made of a combination of, but is not limited to the above exemplified bar.

The conductive layers 132C1 and 234C2 may have a thickness less than or greater than a thickness of the lower second conductive layer 234C1 formed in the second region II. Alternatively, the conductive layers 132C1 and 234C2 may have the same thickness as that of the lower second conductive layer 234C1 formed in the second region II.

In some embodiments, between the preliminary high-k layer 120 and the first conductive layer 132C1 in the first region (I), and in the second region (II) between the lower second conductive layer 234C1 and the upper third conductive layer (II) An additional metal-containing layer (not shown) may be further included between the second conductive layer 234C2. For example, the additional metal-containing layer may be formed of TiN, TaN, or a combination thereof, but is not limited thereto.

A more detailed configuration of the first conductive layer 132C1 , the lower second conductive layer 234C1 , and the upper second conductive layer 234C2 has been described with reference to FIG. 5 .

A resultant product of forming the conductive layers 132C1 and 234C2 may be heat-treated. While the heat treatment is performed, oxygen atoms may diffuse from the first conductive layer 132C1 in the first region I to the preliminary high-k layer 120 (refer to FIG. 9C ). The heat treatment may be performed in an inert gas atmosphere, for example, a nitrogen atmosphere at a temperature of about 400 to 1000 °C. The heat treatment may be performed for about 1 second to about 10 seconds, but is not limited thereto.

When the first conductive layer 132C1 does not contain oxygen atoms, diffusion of oxygen atoms from the first conductive layer 132C1 to the preliminary high-k layer 120 may not be performed while the heat treatment is performed. . On the other hand, while the heat treatment is performed, oxygen atoms may diffuse from the lower second conductive layer 234C1 in the second region II to the preliminary high-k layer 120 . At this time, since the oxygen content of the lower second conductive layer 234C1 is greater than that of the first conductive layer 132C1 , after the heat treatment is performed, the first of the preliminary high-k film 120 . The portion in the region I may remain as the first high-k film 122 with a relatively low oxygen content, and the portion in the second region II may remain as the second high-k film 224 with a relatively high oxygen content. . The oxygen vacancy density of the first high-k film 122 may be higher than that of the second high-k film 224 . A more detailed configuration of the first high-k film 122 and the second high-k film 224 has been described with reference to FIGS. 1, 4, and 5 .

In some embodiments, the heat treatment may be omitted.

In some embodiments, while a deposition process for forming the conductive layers 132C1 and 234C2 is performed, oxygen atoms may be diffused into the preliminary high-k layer 120 by a deposition process temperature. As a result, the first high-k layer 122 and the second high-k layer 224 may be obtained from the preliminary high-k layer 120 .

Referring to FIG. 9E , a first upper gate layer 142 is formed on the first conductive layer 132C1 in the first region (I), and an upper second conductive layer 234C2 in the second region (II) is formed. A second upper gate layer 144 is formed thereon.

A detailed configuration of the first upper gate layer 142 and the second upper gate layer 144 is described with reference to FIG. 8D .

According to the method of manufacturing the integrated circuit device described with reference to FIGS. 9A to 9E , the first transistor TR21 and the second transistor TR22 of the integrated circuit device 200 illustrated in FIG. 4 may be formed.

10A to 10D are cross-sectional views illustrating a process sequence in order to explain a method of manufacturing an integrated circuit device according to still other embodiments according to the inventive concept. 10A to 10D, the same reference numerals as in FIGS. 1 to 9E denote the same members, and detailed descriptions thereof are omitted herein.

Referring to FIG. 10A , the first interface layer 112 is formed on the first active region AC1 in the first region I of the substrate 110 in the same manner as described with reference to FIG. 9A , and the second region In (II), the second interface layer 114 is formed on the second active region AC2. Thereafter, a preliminary high-k dielectric layer 120 is formed on the first interface layer 112 and the second interface layer 114 in the first region (I) and the second region (II).

Thereafter, a work function control metal-containing layer 130 is formed on the preliminary high-k layer 120 in the first region (I) and the second region (II). For details of the work function control metal-containing layer 130 , refer to the description with reference to FIG. 8A .

Referring to FIG. 10B , a mask pattern 270 that selectively covers only a portion of the work function control metal-containing layer 130 in the first region I is formed.

After the mask pattern 270 is formed, the work function control metal-containing layer 130 may be exposed in the second region II. The mask pattern 270 may be formed of a photoresist pattern or a hard mask pattern. The hard mask pattern may be formed of a silicon oxide film, a silicon nitride film, a polysilicon film, or a combination thereof, but is not limited thereto.

In a state in which the mask pattern 270 covers the first region (I), oxygen atoms are supplied into the work function control metal-containing layer 130 in the second region (II) to provide work in the second region (II). At least a portion of the function control metal-containing layer 130 is oxidized. To this end, the resultant product on which the mask pattern 270 is formed may be annealed in an oxygen-containing atmosphere 272 .

In some embodiments, the oxygen-containing atmosphere 272 may be O ₂ , O ₃ , H ₂ O, a combination thereof, or a plasma atmosphere thereof.

In some embodiments, in order to perform the annealing, a rapid thermal annealing (RTA) process may be performed on a resultant product on which the mask pattern 270 is formed. The RTA process may be performed at a temperature of about 400° C. to 1000° C. for several ms to several seconds, for example, about 1 to 10 seconds.

While the annealing is performed under the oxygen-containing atmosphere 272 , oxygen atoms are supplied into the work function control metal-containing film 130 exposed to the oxygen-containing atmosphere 272 in the second region II to supply the second conductive film ( 134B1) may be formed. In addition, some of the oxygen atoms supplied into the work function control metal-containing layer 130 diffuse to the inside of the preliminary high-k film 120 under the work function control metal-containing layer 130 , and thus the preliminary intrinsic property before annealing. A second high-k film 124 having an oxygen content greater than an oxygen content in the front film 120 may be formed.

On the other hand, in the first region I, since the work function control metal-containing layer 130 is covered by the mask pattern 270 , it may not be substantially affected by annealing in the oxygen-containing atmosphere 272 . As a result, in the first region I, the work function control metal-containing layer 130 remains as a first conductive layer 132B1 having a lower oxygen content than in the second conductive layer 134B1, and the first region In (I), the preliminary high-k layer 120 may also remain as the first high-k layer 122 having a lower oxygen content than that of the second high-k layer 124 . The oxygen vacancy density in the first high-k film 122 may be higher than that in the second high-k film 124 . A more detailed configuration of the first high-k film 122 and the second high-k film 124 has been described with reference to FIGS. 1 and 3 .

Referring to FIG. 10C , the mask pattern 270 (refer to FIG. 10B ) is removed to expose the first conductive layer 132B1 in the first region I.

Referring to FIG. 10D , the first upper gate layer 142 is formed on the first conductive layer 132B1 in the first region (I), and on the second conductive layer 134B1 in the second region (II). A second upper gate layer 144 is formed.

A detailed configuration of the first upper gate layer 142 and the second upper gate layer 144 is described with reference to FIG. 8D .

The first transistor TR11 and the second transistor TR12 of the integrated circuit device 100 illustrated in FIG. 1 may be formed according to the method of manufacturing the integrated circuit device described with reference to FIGS. 10A to 10D .

11A to 11C are cross-sectional views illustrating a process sequence in order to explain a method of manufacturing an integrated circuit device according to still other embodiments according to the inventive concept. 11A to 11C, the same reference numerals as in FIGS. 1 to 10D denote the same members, and detailed descriptions thereof are omitted herein.

Referring to FIG. 11A , in the same manner as described with reference to FIG. 9A , the first interface layer 112 is formed on the first active region AC1 in the first region I of the substrate 110 , and the second A second interface layer 114 is formed on the second active region AC2 in the region II. Thereafter, in the first region (I) and in the second region (II), the preliminary high-k film 120 and the work function control metal-containing film 230 are formed on the first interface film 112 and the second interface film 114 . ) are formed in turn. The work function control metal-containing layer 230 may be formed of a metal-containing layer including oxygen.

Referring to FIG. 11B , a mask pattern 280 selectively covering only a portion of the work function control metal-containing layer 230 in the second region II is formed.

The mask pattern 280 may have the same configuration as described for the mask pattern 260 with reference to FIG. 9B .

In the second region (II), a reducing gas is supplied into the work function control metal-containing layer 230 in the first region (I) while the mask pattern 280 covers the work function control metal-containing layer 230 . , at least a portion of the work function control metal-containing layer 230 in the first region I is reduced. To this end, the resultant on which the mask pattern 280 is formed may be annealed in a reducing gas atmosphere 282 .

In some embodiments, the reducing gas atmosphere 282 is NH ₃ , light hydrogen molecules (H ₂ ), deuterium molecules (D ₂ ), a combination thereof, or a plasma atmosphere thereof.

In some embodiments, in order to perform annealing in the reducing gas atmosphere 282, the resultant mask pattern 280 is formed at a temperature of about 400° C. to 700° C. for several ms to several minutes, for example, It can be heat-treated for about 1 to 60 seconds.

While the annealing in the reducing gas atmosphere 282 is performed, a reduction reaction is performed in at least a portion of the work function control metal-containing film 230 exposed to the reducing gas atmosphere 282 in the first region (I), A first conductive layer 132B1 having a lower oxygen content than in the work function control metal-containing layer 230 before annealing may be obtained. In addition, some of the reducing gas constituent elements supplied into the work function control metal-containing layer 230 are diffused to the inside of the preliminary high-k film 120 under the work function control metal-containing layer 230 , and the first A reduction reaction may also be performed in the preliminary high-k film 120 in the region (I). As a result, in the first region I, the first high-k film 122 having an oxygen content less than that of the preliminary high-k film 120 before annealing may be formed.

On the other hand, in the second region II, since the work function control metal-containing layer 230 is covered by the mask pattern 280 , it may not be substantially affected by annealing in the reducing gas atmosphere 282 . As a result, in the second region II, the work function control metal-containing layer 230 remains as a second conductive layer 134B1 having a greater oxygen content than in the first conductive layer 132B1, and the second region The preliminary high-k film 120 in (II) may also remain as the second high-k film 124 having a higher oxygen content than in the first high-k film 122 . The oxygen vacancy density in the first high-k film 122 may be higher than that in the second high-k film 124 . A more detailed configuration of the first high-k film 122 and the second high-k film 124 has been described with reference to FIGS. 1 and 3 .

Referring to FIG. 11C , after removing the mask pattern 280 (see FIG. 11B ), a first upper gate layer 142 is formed on the first conductive layer 132B1 in the first region I, and a second A second upper gate layer 144 is formed on the second conductive layer 134B1 in the region II.

A detailed configuration of the first upper gate layer 142 and the second upper gate layer 144 is described with reference to FIG. 8D .

According to the method of manufacturing the integrated circuit device described with reference to FIGS. 11A to 11C , the first transistor TR11 and the second transistor TR12 of the integrated circuit device 100 illustrated in FIG. 1 may be formed.

12A to 12C are cross-sectional views illustrating a process sequence in order to explain a method of manufacturing an integrated circuit device according to still other embodiments according to the inventive concept. In FIGS. 12A to 12C , the same reference numerals as in FIGS. 1 to 11C denote the same members, and detailed descriptions thereof are omitted herein.

Referring to FIG. 12A , in the same manner as described with reference to FIG. 10A , the first interface layer 112 is formed on the first active region AC1 in the first region I of the substrate 110 , and the second A second interface layer 114 is formed on the second active region AC2 in the region II. Thereafter, in the first region (I) and the second region (II), the preliminary high-k film 120 and the work function control metal-containing film 130 are formed on the first interface film 112 and the second interface film 114 in the second region (II). ) are formed in turn. The work function control metal-containing layer 130 may be formed of a metal-containing layer that does not contain oxygen or a metal-containing layer that includes oxygen.

Referring to FIG. 12B , an oxygen-containing layer 292 selectively covering only a portion of the work function control metal-containing layer 130 in the second region II is formed.

The oxygen-containing film 292 is a film capable of supplying oxygen to the surroundings during heat treatment, and may be formed of, for example, a hafnium oxide film, a zirconium oxide film, or a silicon oxide film, but is not limited thereto.

The oxygen-containing layer 292 covering the second region II is subjected to heat treatment under an inert atmosphere 294, for example, a nitrogen atmosphere or an argon atmosphere, and the oxygen-containing layer 292 is formed in the second region II. ) diffuses into the work function control metal-containing layer 130 to oxidize at least a portion of the work function control metal-containing layer 130 in the second region (II). In some embodiments, the heat treatment may be performed at a temperature of about 400 to 1000° C. for several ms to several seconds, for example, about 1 to 10 seconds.

While the oxygen-containing film 292 covering the second region II is heat-treated under the inert atmosphere 294 , oxygen atoms in the oxygen-containing film 292 in the second region II adjust the work function. By diffusion into the metal-containing layer 130 , the second conductive layer 134B1 having a greater oxygen content than in the work function control metal-containing layer 130 before heat treatment may be formed. In addition, some of the oxygen atoms that have diffused into the work function control metal-containing layer 130 are diffused to the inside of the preliminary high-k film 120 under the work function control metal-containing layer 130, A second high-k film 124 having an oxygen content greater than an oxygen content in the high-k film 120 may be formed.

On the other hand, the first region I may not be substantially affected by the oxygen-containing layer 292 . As a result, in the first region I, the work function control metal-containing layer 130 remains as a first conductive layer 132B1 having a lower oxygen content than in the second conductive layer 134B1, and the first region In (I), the preliminary high-k layer 120 may also remain as the first high-k layer 122 having a lower oxygen content than that of the second high-k layer 124 . The oxygen vacancy density in the first high-k film 122 may be higher than that in the second high-k film 124 .

Referring to FIG. 12C , after removing the oxygen-containing layer 292 (see FIG. 12B ), a first upper gate layer 142 is formed on the first conductive layer 132B1 in the first region I, and the second upper gate layer 142 is formed. A first transistor TR11 and a second transistor TR12 may be formed by forming the second upper gate layer 144 on the second conductive layer 134B1 in the second region II.

13A to 13C are cross-sectional views illustrating a process sequence in order to explain a method of manufacturing an integrated circuit device according to still other embodiments according to the inventive concept. 13A to 13C, the same reference numerals as in FIGS. 1 to 12C denote the same members, and detailed description thereof will be omitted herein.

Referring to FIG. 13A , in the same manner as described with reference to FIG. 9A , the first interface layer 112 is formed on the first active region AC1 in the first region I of the substrate 110 , and the second A second interface layer 114 is formed on the second active region AC2 in the region II. Thereafter, in the first region (I) and in the second region (II), the preliminary high-k film 120 and the work function control metal-containing film 230 are formed on the first interface film 112 and the second interface film 114 . ) are formed in turn. The work function control metal-containing layer 230 may be formed of a metal-containing layer including oxygen.

Referring to FIG. 13B , an oxygen gettering film 296 selectively covering only a portion in the first region (I) of the work function control metal-containing film 230 is formed and in an inert atmosphere 298 . A heat treatment process is performed.

The oxygen trapping layer 296 serves to attract and trap oxygen atoms from the surrounding oxygen-containing layer, and is made of a material having a chemical bond energy with oxygen lower than that of the work function control metal-containing layer 230 . can Accordingly, in the first region (I), oxygen atoms in the work function control metal-containing film 230 are diffused in the direction of the arrow A by the heat treatment process in the inert atmosphere 298 to form the oxygen trapping film 296 . can move in

In some embodiments, the oxygen trapping layer 296 may be formed of a metal, for example, Al, Ti, Mg, Zn, La, Ta, Zr, Cu, or a combination thereof. In some other embodiments, the oxygen trapping film 296 may be formed of a partially oxidized metal oxide film. For example, the oxygen trapping film 296 may be formed of TiO, TaO, AlO, or a combination thereof. In some embodiments, the oxygen trapping layer 296 may be formed to a thickness of about 1 to 100 nm.

The heat treatment process in the inert atmosphere 298 may be performed in a nitrogen atmosphere or an argon atmosphere at a temperature of about 400 to 1000° C. for several ms to several seconds, for example, about 1 to 10 seconds.

During the heat treatment under the inert atmosphere 298 in a state where the oxygen trapping layer 296 covers the first region I, oxygen atoms in the work function control metal-containing layer 230 are converted to the oxygen trapping layer 296 . ), in the first region I, the first conductive layer 132B1 having a smaller oxygen content than in the work function control metal-containing layer 230 before the heat treatment process may be formed. In addition, during the heat treatment under the inert atmosphere 298 , oxygen atoms in the preliminary high-k film 120 under the work function control metal-containing film 230 in the first region (I) also move in the direction of the arrow (A). , the first high-k film 122 having a smaller oxygen content than the oxygen content in the preliminary high-k film 120 before heat treatment may be formed.

On the other hand, while the heat treatment process is performed under the inert atmosphere 298 , the work function control metal-containing film 230 and the preliminary high-k film 120 in the second region II may not be substantially affected. As a result, in the second region II, the work function control metal-containing layer 230 remains as a second conductive layer 134B1 having a greater oxygen content than in the first conductive layer 132B1, and the second region The preliminary high-k film 120 in (II) may also remain as the second high-k film 124 having a higher oxygen content than in the first high-k film 122 .

Referring to FIG. 13C , after the oxygen trapping film 296 (see FIG. 13B ) is removed, a first upper gate film 142 is formed on the first conductive film 132B1 in the first region I, and the second upper gate film 142 is formed. A first transistor TR11 and a second transistor TR12 may be formed by forming the second upper gate layer 144 on the second conductive layer 134B1 in the second region II.

14A to 14D are cross-sectional views illustrating a process sequence in order to explain a method of manufacturing an integrated circuit device according to still other embodiments according to the inventive concept. 14A to 14D, the same reference numerals as in FIGS. 1 to 13C denote the same members, and detailed description thereof will be omitted herein.

Referring to FIG. 14A , a substrate 110 including a first region (I), a second region (II), and a third region (III) is prepared. Thereafter, in a method similar to that described with reference to FIGS. 10A to 10C , the first interface layer 112 , the first high-k dielectric layer 122 , and the first high-k dielectric layer 122 on the first active region AC1 in the first region I A structure in which first conductive layers 132B1 are sequentially stacked is formed, and in the second region II, the second interface layer 114 , the second high-k layer 124 , and the second conductive layer are on the second active region AC2 . The films 134B1 are sequentially stacked to form a structure. At this time, the same process as in the second region (II) is simultaneously performed in the third region (III), and the third interface layer 116 , the first high-k layer 124 , and the A structure in which second conductive layers 134B1 are sequentially stacked is formed.

Referring to FIG. 14B , in a manner similar to that described with reference to FIG. 8B , covering the first conductive layer 132B1 in the first region I and the second conductive layer 134B1 in the second region II is applied. A mask pattern 160 is formed. The mask pattern 160 is not formed in the third region III. Accordingly, the second conductive layer 134B1 in the third region III may be exposed to the outside. In this state, only a portion of the second conductive layer 134B1 exposed in the third region III is partially oxidized by a predetermined depth from the top surface of the third region III using the oxidizing atmosphere 162 in a similar manner to that described with reference to FIG. 8C , and the upper second A conductive film 134B2 is formed. The upper second conductive layer 134B2 may form a third work function control metal-containing structure 136 together with the second conductive layer 134B1 remaining in the third region III.

In the third work function control metal-containing structure 136 , the upper second conductive layer 134B2 may have a greater oxygen content than the second conductive layer 134B1 remaining thereunder.

After forming the upper second conductive layer 134B2 using the oxidizing atmosphere 162 , an additional heat treatment is performed to remove the third work function control metal-containing structure 136 in the third region III. 2 Oxygen atoms may be diffused into the high-k film 124 . As a result, the lower portion of the third work function control metal-containing structure 136 in the third region III has an oxygen content greater than the oxygen content in the second high-k film 124 in the second region II. A third high-k film 126 may be obtained.

Referring to FIG. 14C , the first conductive layer 132B1 in the first region I is removed by removing the mask pattern 160 (see FIG. 14B ) covering the first region I and the second region II. and the second conductive layer 134B1 in the second region II is exposed.

Referring to FIG. 14D , the first upper gate layer 142 is formed on the first conductive layer 132B1 in the first region (I), and on the second conductive layer 134B1 in the second region (II). A second upper gate film 144 is formed, and a third upper gate film 146 is formed on the third work function control metal-containing structure 136 in the third region III to form the first transistor TR11 . , a second transistor TR12 , and a third transistor TR13 may be formed.

15A to 15F are cross-sectional views illustrating a process sequence in order to explain a method of manufacturing an integrated circuit device according to still other embodiments according to the inventive concept. 15A to 15F, the same reference numerals as in FIGS. 1 to 14D denote the same members, and detailed descriptions thereof are omitted herein.

Referring to FIG. 15A , a substrate 110 including a first region (I), a second region (II), and a third region (III) is prepared. Thereafter, in a method similar to that described with reference to FIGS. 9A to 9C , a first interface layer 112 and a preliminary high-k dielectric layer 120 are sequentially stacked on the first active region AC1 in the first region I. A structure is formed, and in the second region II, the second interface layer 114 , the preliminary high-k layer 120 , the lower second conductive layer 234C1 , and the mask pattern 260 are on the second active region AC2 . This in turn forms a stacked structure. At this time, the same process as in the second region (II) is simultaneously performed in the third region (III), and the third interface layer 116, the preliminary high-k layer 120, and the lower third layer are formed on the third active region AC3. A structure in which the second conductive layer 234C1 and the mask pattern 260 are sequentially stacked is formed.

Referring to FIG. 15B , the mask pattern 260 (refer to FIG. 15A ) is removed from the second region II and the third region III to expose the lower second conductive layer 234C1 .

Referring to FIG. 15C , the preliminary high-k film 120 in the first region I and the lower second conductive layer 234C1 in the second region II are formed in a manner similar to that described with reference to FIG. 14B . A covering mask pattern 160 is formed. The mask pattern 160 is not formed in the third region III. In this state, only a portion of the lower second conductive layer 234C1 exposed in the third region III is partially oxidized by a predetermined depth from the upper surface of the lower second conductive layer 234C1 by using the oxidizing atmosphere 162 in a method similar to that described with reference to FIG. 8C . As a result, an upper portion of the lower second conductive layer 234C1 in the third region III is oxidized to form an upper second conductive layer 134B2 . In the third region III, the upper second conductive layer 134B2 and the remaining portion of the lower second conductive layer 234C1 may form a third work function control metal-containing structure 236 . In the third work function control metal-containing structure 236 , the upper second conductive layer 134B2 may have a higher oxygen content than the second conductive layer 234C1 remaining thereunder.

Referring to FIG. 15D , the resultant obtained after removing the mask pattern 160 (see FIG. 15C ) is heat treated to remove oxygen atoms from the lower second conductive layer 234C1 in the second region II. diffusion into the preliminary high-k film 120 in can spread. As a result, from the preliminary high-k film 120 , the first high-k film 122 in the first region (I), the second high-k film 124 in the second region (II), and the third region (III) A third high-k film 126 in .

Referring to FIG. 15E , in a method similar to that described for the method of forming the conductive films 132C1 and 234C2 with reference to FIG. 9D , the upper portion of the first high-k film 122 in the first region I, the second Conductive films 132C1 and 234C2 are formed on the lower second conductive film 234C1 in the region II and on the third work function control metal-containing structure 236 in the third region III .

Referring to FIG. 15F , in a manner similar to that described with reference to FIG. 9E , a first layer is formed on the conductive layers 132C1 and 234C2 in the first region (I), the second region (II), and the third region (III), respectively. The first upper gate layer 142 , the second upper gate layer 144 , and the third upper gate layer 146 are formed to form the first transistor TR21 , the second transistor TR22 , and the third transistor TR23 . ) can be formed.

Although exemplary manufacturing methods of integrated circuit devices according to the technical spirit of the present invention have been described with reference to FIGS. 8A to 15F , the manufacturing method of the integrated circuit device according to the technical spirit of the present invention is limited only to the above-described methods. it is not Integrated circuit devices having various structures can be manufactured from the above-described methods by applying various modifications and variations from the above-described methods.

16A to 16C are views for explaining an integrated circuit device according to embodiments according to the inventive concept, and FIG. 16A includes a first transistor TR51 and a second transistor TR52 having a FinFET structure. It is a perspective view showing main components of the integrated circuit device 500 to C2' is a cross-sectional view. 16A to 16C, the same reference numerals as in FIG. 1 denote the same members, and detailed descriptions thereof are omitted herein.

The integrated circuit device 500 includes a first fin-type active region (Z direction) protruding from the first region (I) and the second region (II) of the substrate 110 in a direction (Z direction) perpendicular to the main surface of the substrate 110, respectively F1) and a second fin-type active region F2.

The first fin-type active region F1 and the second fin-type active region F2 may extend in one direction (the Y-direction in FIGS. 16A to 16C ). On the substrate 110 in the first region (I) and the second region (II), a first device isolation layer 512 covering lower sidewalls of the first fin-type active region F1 and the second fin-type active region F2; A second device isolation layer 514 is formed. The first fin-type active region F1 protrudes over the first device isolation layer 512 in a fin shape, and the second fin-type active region F2 protrudes over the second device isolation layer 512 in a fin shape.

The first fin-type active region F1 and the second fin-type active region F2 may have a first channel region CH1 and a second channel region CH2 thereon, respectively.

In some embodiments, the first fin-type active region F1 and the second fin-type active region F2 may be formed of a single material. For example, all regions of the first fin-type active region F1 and the second fin-type active region F2 including the first channel region CH1 and the second channel region CH2 may be made of Si. In some other embodiments, the first fin-type active region F1 and the second fin-type active region F2 may include a region made of Ge and a region made of Si, respectively.

Each of the first and second device isolation layers 512 and 514 may be formed of a silicon-containing insulating layer such as a silicon oxide layer, a silicon nitride layer, a silicon oxynitride layer, or a silicon carbon nitride layer, polysilicon, or a combination thereof.

In the first region I, the first interface layer 112 , the first high-k layer 122 , the first work function control metal-containing structure 132 , and the first upper gate are disposed on the first fin-type active region F1 . A first gate structure FG51 in which layers 142 are sequentially stacked extends in a direction crossing the extending direction of the first fin-type active region F1 (X direction in FIGS. 16A to 16C ). The first transistor TR51 is formed in a portion where the first fin-type active region F1 and the first gate structure FG51 cross each other.

In the second region II, the second interface layer 114 , the second high-k layer 124 , the second work function control metal-containing structure 134 , and the second upper gate are disposed on the second fin-type active region F2 . A second gate structure FG52 in which layers 144 are sequentially stacked extend in a direction (X direction in FIGS. 16A to 16C ) crossing the extending direction of the second fin-type active region F2 . The second transistor TR52 is formed in a portion where the second fin-type active region F2 and the second gate structure FG52 intersect.

A pair of first source/drain regions 562 may be formed on both sides of the first gate structure FG51 in the first fin-type active region F1 . A pair of second source/drain regions 564 may be formed on both sides of the second gate structure FG52 of the second fin-type active region F2 .

The first and second source/drain regions 562 and 564 may include semiconductor layers epitaxially grown from the first and second fin-type active regions F1 and F2, respectively. The first and second source/drain regions 562 and 564 may be formed of an embedded SiGe structure including a plurality of epitaxially grown SiGe layers, an epitaxially grown Si layer, or an epitaxially grown SiC layer.

16A and 16C , the case where the first and second source/drain regions 562 and 564 have a specific shape is exemplified, but the cross-sectional shape of the first and second source/drain regions 562 and 564 It is not limited to the bar illustrated in FIGS. 16A and 16C and may have various shapes.

The first and second transistors TR51 and TR52 include MOS transistors having a three-dimensional structure in which channels are formed on top and both sides of the first and second fin-type active regions F1 and F2, respectively. The MOS transistor may constitute an NMOS transistor or a PMOS transistor.

In the first region I and the second region II, insulating spacers 572 may be formed on both sides of the first and second gate structures FG51 and FG52. As illustrated in FIG. 16C , an insulating layer 578 covering the insulating spacer 572 may be formed on opposite sides of the first and second gate structures FG51 and FG52 with respect to the insulating spacer 572 .

The insulating spacer 572 may be formed of a single layer or a multilayer. In some embodiments, the insulating spacer 572 may be formed of a silicon nitride film, a silicon oxynitride film, a silicon oxynitride film containing carbon, a SiOCN film, or a composite film thereof. The insulating spacer 572 may have a multilayer structure including an I-shaped insulating layer, an L-shaped insulating layer, or a combination thereof. In some other embodiments, the insulating spacer 572 may include an air gap therein.

The insulating layer 578 may be formed of a silicon oxide layer, but the technical spirit of the present invention is not limited thereto.

In the integrated circuit device 500 , the first gate structure FG51 of the first transistor TR51 includes the first interface layer 112 and the first gate structure FG51 as in the first transistor TR11 illustrated in FIG. 1 . It has a stacked structure including a high-k layer 122 and a first gate stack GS11 , wherein the first gate stack GS11 includes a first work function control metal-containing structure 132 and a first upper gate layer 142 . ) is included. In addition, as in the second transistor TR12 illustrated in FIG. 1 , the second gate structure FG52 of the second transistor TR52 includes a second interface layer 114 , a second high-k layer 124 , and A second gate stack GS12 is included, and the second gate stack GS12 includes a second work function control metal-containing structure 134 and a second upper gate layer 144 . However, the technical spirit of the present invention is not limited to the bars illustrated in FIGS. 16A to 16C . For example, the first gate structure FG51 and the second gate structure FG52 of the integrated circuit device 500 may have the same stacked structures as the various gate structures described with reference to FIGS. 1 to 15F , and a view from them. It may have a structure selected from among various modified and changed laminate structures within the scope of the technical spirit of the present invention.

17A and 17B are views for explaining an integrated circuit device according to embodiments according to the inventive concept, and FIG. 17A includes a first transistor TR61 and a second transistor TR62 having a FinFET structure. is a plan layout diagram of the integrated circuit device 600, and FIG. 17B is a cross-sectional view taken along lines B1 - B1' and lines B2 - B2' of FIG. 17A. In FIGS. 17A and 17B , the same reference numerals as in FIGS. 1 to 16C denote the same members, and detailed descriptions thereof are omitted herein.

17A and 17B , the integrated circuit device 600 includes a first transistor TR61 and a second transistor each having a FinFET structure in the first region I and the second region II of the substrate 110 . (TR62).

The first region I and the second region II of the integrated circuit device 600 may be regions performing different functions. In some embodiments, in the integrated circuit device 600 , the first region I is a region in which devices operating in a high power mode are formed, and the second region II is a region in which devices operating in a low power mode are formed. can For example, in the integrated circuit device 600 , the first region I may be a region in which a peripheral circuit such as an input/output circuit device is formed, and the second region II may be a region in which a memory device or a logic circuit is formed. .

In the first region I, a first gate line 640A extends over the first fin-type active region F1 to intersect the first fin-type active region F1. A first transistor TR61 may be formed at a point where the first fin-type active region F1 and the first gate line 640A intersect. In the second region II, the second gate line 640B extends to cross the second fin-type active region F2. A second transistor TR62 may be formed at a point where the second fin-type active region F2 and the second gate line 640B intersect. The first width W1 of the first gate line 640A in the longitudinal direction (Y direction) of the first fin-type active region F1 is a second width W1 in the longitudinal direction (Y direction) of the second fin-type active region F2. It is larger than the second width W2 of the second gate line 640B.

The first and second transistors TR61 and TR62 may constitute an NMOS transistor or a PMOS transistor, respectively.

17A illustrates one first and second fin-type active regions F1 and F2 and one first and second gate lines 640A and 640B in the first region I and the second region II, respectively. However, the number of each is not particularly limited, and a plurality of fin-type active regions and a plurality of gate lines may be formed to cross each other in the first region (I) and the second region (II).

In the integrated circuit device 600 , the first transistor TR61 formed in the first region I includes a first fin-type active region F1 protruding from the substrate 110 and the first fin-type active region F1 . A first gate structure FG61 including a first interface layer 612 , a first high-k layer 622 , and a first gate stack GS61 sequentially covering the top surface and both sidewalls of the first channel region CH1 of have The second transistor TR62 formed in the second region II includes a second fin-type active region F2 protruding from the substrate 110 and a second channel region CH2 of the second fin-type active region F2. A second gate structure FG62 including a second interface layer 614 , a second high-k layer 624 , and a second gate stack GS62 that sequentially covers the top surface and both sidewalls is provided.

In the integrated circuit device 600 described with reference to FIGS. 17A and 17B , the first gate structure FG61 of the first transistor TR61 and the second gate structure FG62 of the second transistor TR62 are respectively illustrated in FIG. 1 . It is possible to have the same stacked structure selected from the various gate structures described with reference to FIGS. 15F , or various stacked structures modified and changed within the scope of the inventive concept therefrom.

18A to 18E are cross-sectional views illustrating a process sequence in order to explain a method of manufacturing an integrated circuit device according to embodiments according to the inventive concept. An exemplary method of manufacturing the integrated circuit device 500 illustrated in FIGS. 16A to 16C will be described with reference to FIGS. 18A to 18E . 18A to 18E, the same reference numerals as in FIGS. 1 to 17C denote the same members, and detailed descriptions thereof are omitted herein.

Referring to FIG. 18A , a substrate 110 including a first region I and a second region II is prepared. A plurality of pad oxide layer patterns 712 and a plurality of mask patterns 714 are formed on the first region I and the second region II of the substrate 110 .

The plurality of pad oxide layer patterns 712 and the plurality of mask patterns 714 may extend parallel to each other along one direction (Y direction) on the substrate 110 . In some embodiments, the plurality of pad oxide layer patterns 712 may be formed of an oxide layer obtained by thermally oxidizing the surface of the substrate 110 . The plurality of mask patterns 714 may be formed of a silicon nitride film, a silicon oxynitride film, a spin on glass (SOG) film, a spin on hardmask (SOH) film, a photoresist film, or a combination thereof. it is not going to be

Referring to FIG. 18B , a partial region of the substrate 110 is etched using a plurality of mask patterns 714 as an etch mask, and a plurality of first trenches T1 are formed in the first region I of the substrate 110 . ) and forming a plurality of second trenches T2 in the second region II of the substrate 110 . As the plurality of first and second trenches T1 and T2 are formed, they protrude upward from the substrate 110 in a direction (Z direction) perpendicular to the main surface of the substrate 110 and in one direction (Y direction). direction), a plurality of first and second preliminary fin-type active regions P1 and P2 may be obtained.

Referring to FIG. 18C , a plurality of first and second trenches to cover the exposed surfaces of the plurality of first and second preliminary fin-type active regions P1 and P2 in the first region I and the second region II. A first device isolation layer 512 and a second device isolation layer 514 filling (T1, T2) are formed.

To form the first device isolation layer 512 and the second device isolation layer 514 , plasma enhanced chemical vapor deposition (PECVD), high density plasma CVD (HDP CVD), inductively coupled plasma CVD (ICP CVD), and CCP CVD (capacitor coupled plasma CVD), flowable chemical vapor deposition (FCVD), and/or spin coating (spin coating) process may be used, but is not limited to the above-described methods.

After the first device isolation layer 512 and the second device isolation layer 514 are formed, the top surface may be planarized to expose the plurality of mask patterns 714 . In this case, a portion of the plurality of mask patterns 714 may be consumed and the height thereof may be reduced.

Referring to FIG. 18D , a plurality of mask patterns 714 and a plurality of pad oxide layer patterns ( 712) (refer to FIG. 18C) is removed, and a recess process for removing portions of the first device isolation layer 512 and the second device isolation layer 514 is performed.

As a result, the height of the top surfaces of the first device isolation layer 512 and the second device isolation layer 514 in the first region (I) and the second region (II) is lowered, and the first and second preliminary fin-type active regions ( Upper portions of P1 and P2 may be exposed while protruding above the first device isolation layer 512 and the second device isolation layer 514 .

In order to perform the recess process, dry etching, wet etching, or a combination of dry etching and wet etching may be used.

When the plurality of mask patterns 714 are formed of a silicon nitride layer, a wet etching process using _{, for example, H 3} PO _{4 may be performed to remove the plurality of mask patterns 714 .} In order to remove the plurality of pad oxide layer patterns 712 , for example, a wet etching process using diluted HF (DHF) may be performed.

For the recess process of the first device isolation layer 512 and the second device isolation layer 514 _{, wet etching using HF, NH 4} OH, TMAH (tetramethyl ammonium hydroxide), KOH (potassium hydroxide) solution, etc. as an etchant A dry etching process such as inductively coupled plasma (ICP), transformer coupled plasma (TCP), electron cyclotron resonance (ECR), reactive ion etch (RIE), or the like may be used. When the recess process of the first device isolation layer 512 and the second device isolation layer 514 is performed by dry etching, a fluorine-containing gas such as _{CF 4 , a chlorine-containing gas such as Cl 2} , HBr, etc. may be used. However, it is not limited to the bar illustrated above.

During the recess process, upper portions of each of the first and second preliminary fin-type active regions P1 and P2 exposed in the first region I and the second region II are exposed to an etching atmosphere such as plasma. A portion of the first and second preliminary fin-type active regions P1 and P2 is consumed by an etching atmosphere for the recess process or a subsequent cleaning atmosphere, so that the first device isolation layer 512 and the second device First and second fin-type active regions F1 and F2 having an upper region having a smaller width than a lower region covered by the separation layer 514 may be obtained.

In some embodiments, an impurity ion implantation process for adjusting a threshold voltage may be performed on each of the first and second fin-type active regions F1 and F2 in the first region I and the second region II. During the impurity ion implantation process for controlling the threshold voltage, boron (B) ions as impurities are implanted into the region where the NMOS transistor is formed among the first region (I) and the second region (II), and into the region where the PMOS transistor is formed. As an impurity, phosphorus (P) or arsenic (As) may be ion-implanted.

Referring to FIG. 18E , the first gate structure FG51 and the second gate structure covering the upper portions of the first and second fin-type active regions F1 and F2 in the first region I and the second region II, respectively. FG52 is formed to form a first transistor TR51 and a second transistor TR52.

In order to form the first gate structure FG51 and the second gate structure FG52, gate structures having various structures may be formed using various processes described with reference to FIGS. 1 to 15F .

Although an exemplary method of manufacturing the integrated circuit device 500 illustrated in FIGS. 17A to 17C has been described with reference to FIGS. 18A to 18E , various methods modified and changed therefrom are used within the scope of the technical spirit of the present invention. Accordingly, integrated circuit devices having various structures exemplified herein, for example, the integrated circuit device 600 illustrated in FIGS. 17A and 17B can be easily implemented.

In addition, although a method of manufacturing an integrated circuit device including a FinFET having a three-dimensional channel has been described with reference to FIGS. 18A to 18E , the technical spirit of the present invention is not limited thereto. For example, through various modifications and changes within the scope of the technical spirit of the present invention, it is possible to provide integrated circuit devices including planar MOSFETs having features according to the technical spirit of the present invention and methods for manufacturing the same. Those of ordinary skill in the art will know well.

19 is a block diagram of an integrated circuit device according to embodiments of the inventive concept.

Referring to FIG. 19 , the integrated circuit device 700 includes a first area AR1 , a second area AR2 , and a third area AR3 .

The first area AR1 , the second area AR2 , and the third area AR3 of the substrate 110 refer to different areas of the substrate 110 .

In some embodiments, the first area AR1 , the second area AR2 , and the third area AR3 may be areas requiring different threshold voltages. In one example, the first region AR1 may be an NMOS transistor region, and the second region AR2 and the third region AR3 may be a PMOS transistor region. In another example, the first region AR1 and the second region AR2 may be an NMOS transistor region, and the third region AR3 may be a PMOS transistor region.

In some other embodiments, the first area AR1 , the second area AR2 , and the third area AR3 may be areas that perform different functions. The first area AR1 , the second area AR2 , and the third area AR3 may be spaced apart from each other or may be connected to each other.

In some embodiments, each of the first region AR1 , the second region AR2 , and the third region AR3 may be an NMOS transistor region. In this case, the first region AR1 is a low-voltage NMOS transistor region that requires a lower threshold voltage than that of the second region AR2 , and the third region AR3 is a high-voltage NMOS transistor region that is higher than that of the first region AR1 . , and the second region AR2 may be an intermediate voltage NMOS transistor region requiring a threshold voltage higher than that of the first region AR1 but lower than that of the third region AR3 .

In some other embodiments, each of the first region AR1 , the second region AR2 , and the third region AR3 may be a PMOS transistor region. In this case, the first region AR1 is a high-voltage PMOS transistor region requiring a higher threshold voltage than that of the second region AR2 , and the third region AR3 is a low-voltage PMOS transistor region lower than that of the first region AR1 . , and the second region AR2 may be an intermediate voltage PMOS transistor region in which a threshold voltage lower than that of the first region AR1 and higher than that of the third region AR3 is required.

In the present specification, a high voltage transistor may mean a transistor having a threshold voltage of 1 V or more, and a low voltage transistor may mean a transistor having a threshold voltage of less than 1 V, but is not limited thereto.

In some embodiments, the first area AR1 , the second area AR2 , and the third area AR3 may each independently be a logic cell area, a memory cell area, or a peripheral circuit area.

In some embodiments, at least one of the first region AR1 , the second region AR2 , and the third region AR3 has a relatively high threshold voltage and a region in which a reliable transistor is formed even if the switching speed is not fast. can be In some embodiments, at least one of the first area AR1 , the second area AR2 , and the third area AR3 inputs external data to the internal circuit of the integrated circuit device 500 , or the integrated circuit It may be a peripheral circuit region in which peripheral circuits performing a function of outputting data from an internal circuit of the device 500 to the outside are formed. In some embodiments, at least one of the first area AR1 , the second area AR2 , and the third area AR3 may form a part of an input/output (I/O) circuit device.

In some other embodiments, at least one of the first region AR1 , the second region AR2 , and the third region AR3 may be a region in which a transistor having a relatively low threshold voltage and a high switching speed is formed. In some embodiments, at least one of the first area AR1 , the second area AR2 , and the third area AR3 may be a cell array area in which unit memory cells are arranged in a matrix form. In some embodiments, at least one of the first area AR1 , the second area AR2 , and the third area AR3 may be a logic cell area or a memory cell area. The logic cell region is a standard cell that performs a desired logical function such as a counter and a buffer, and includes various types of circuit elements such as transistors and resistors. It may contain logic cells. The logic cell is, for example, AND, NAND, OR, NOR, XOR (exclusive OR), XNOR (exclusive NOR), INV (inverter), ADD (adder), BUF (buffer), DLY (delay), FILL ( filter), multiplexers (MXT/MXIT). OAI (OR/AND/INVERTER), AO (AND/OR), AOI (AND/OR/INVERTER), D flip-flop, reset flip-flop, master-slaver flip-flop, latch ) can be configured. However, the cells are merely examples, and the logic cells constituting the integrated circuit device according to the inventive concept are not limited to the cells exemplified above. The memory cell region may be at least one of SRAM, DRAM, MRAM, RRAM, and PRAM.

The integrated circuit devices 100, 200, 300, 400, 500, and 600 according to the technical idea of the present invention described with reference to FIGS. 1 to 17B and having a structure modified and changed within the scope of the technical idea of the present invention therefrom Each of the integrated circuit devices may be formed in at least one of the first area AR1 , the second area AR2 , and the third area AR3 illustrated in FIG. 19 . For example, the first region I and the second region II of the integrated circuit devices 100 , 200 , 500 , and 600 illustrated in FIGS. 1 , 4 , 16A to 16C , 17A and 17B . may be included in the same one of the first area AR1 , the second area AR2 , and the third area AR3 illustrated in FIG. 19 , or may be included in different areas. Similarly, the first region (I), the second region (II), and the third region (III) of the integrated circuit devices 300 and 400 illustrated in FIGS. 6 and 7 are the first regions illustrated in FIG. 19 . It may be included in the same one of the area AR1 , the second area AR2 , and the third area AR3 , or may be included in different areas.

20 is a block diagram of an electronic system 2000 according to embodiments according to the inventive concept.

The electronic system 2000 includes a controller 2010 , an input/output device (I/O) 2020 , a memory 2030 , and an interface 2040 , each of which is interconnected through a bus 2050 .

The controller 2010 may include at least one of a microprocessor, a digital signal processor, or a processing device similar thereto. The input/output device 2020 may include at least one of a keypad, a keyboard, and a display. The memory 2030 may be used to store commands executed by the controller 2010 . For example, the memory 2030 may be used to store user data.

The electronic system 2000 may constitute a wireless communication device or a device capable of transmitting and/or receiving information in a wireless environment. In order to transmit/receive data through a wireless communication network in the electronic system 2000, the interface 2040 may be configured as a wireless interface. The interface 2040 may include an antenna and/or a wireless transceiver. In some embodiments, the electronic system 2000 is a third generation communication system, for example, code division multiple access (CDMA), global system for mobile communications (GSM), north American digital cellular (NADC), E-TDMA (extended-time division multiple access), and/or may be used for a communication interface protocol of a third generation communication system such as wide band code division multiple access (WCDMA). The electronic system 2000 includes integrated circuit devices 100, 200, 300, 400, 500, and 600 according to the embodiments of the inventive concept described with reference to FIGS. It includes at least one of integrated circuit devices having a modified and changed structure within the scope of the technical idea.

Above, the present invention has been described in detail with reference to preferred embodiments, but the present invention is not limited to the above embodiments, and various modifications and changes by those skilled in the art within the technical spirit and scope of the present invention This is possible.

110: substrate, 112: first interface film, 114: second interface film, 122: first high-k film, 124: second high-k film, 132: first work function control metal-containing structure, 134: second work function control Metal-containing structure, 142: first upper gate film, 144: second upper gate film, GS11: first gate stack, GS12: second gate stack.

Claims (20)

a first high-k film formed over the first active region of the substrate;
a first gate stack formed on the first high-k film and having a first work function control metal-containing structure;
a second high-k film formed on the second active region of the substrate;
a second gate stack formed over the second high-k film and having a second work function control metal-containing structure having an oxygen content greater than an oxygen content in the first work function control metal-containing structure;
the first high-k film and the second high-k film are made of a metal oxide;
and the first high-k film and the second high-k film have different oxygen vacancy densities. delete The method of claim 1,
and the second high-k film has a lower oxygen vacancy density than that of the first high-k film. According to claim 1,
The first work function control metal-containing structure includes a first conductive layer that is in direct contact with the first high-k layer and includes a single layer having a first thickness;
The second work function control metal-containing structure includes a second conductive layer formed on the same level as the first conductive layer and formed of a multilayer having the first thickness,
The second conductive film is
a lower second conductive film in direct contact with the second high-k film;
and an upper second conductive layer having an oxygen content greater than an oxygen content in the first conductive layer. 5. The method of claim 4,
and the lower second conductive layer has an oxygen content equal to that of the first conductive layer. 5. The method of claim 4,
and the lower second conductive layer is formed of a metal-containing layer that does not contain oxygen. 5. The method of claim 4,
The upper second conductive layer has a second thickness that is 10 to 90% of the first thickness. 5. The method of claim 4,
The integrated circuit device of claim 1, wherein the sum of the thickness of the lower second conductive layer and the thickness of the upper second conductive layer is equal to the thickness of the first conductive layer. The method of claim 1,
The first work function control metal-containing structure includes a first conductive layer in direct contact with the first high-k layer and formed of a single layer having a first thickness,
The second work function control metal-containing structure includes a second conductive layer formed of a multilayer having a second thickness greater than the first thickness,
The second conductive film is
a lower second conductive film directly in contact with the second high-k film and having an oxygen content greater than an oxygen content in the first conductive film;
and an upper second conductive layer having the first thickness and the same oxygen content as in the first conductive layer. According to claim 1,
The first work function control metal-containing structure includes a first conductive layer that is in direct contact with the first high-k layer and includes a single layer having a first thickness;
wherein the second work function control metal-containing structure includes a second conductive layer directly in contact with the second high-k layer, the second conductive layer having the first thickness, and having an oxygen content greater than an oxygen content in the first conductive layer integrated circuit device. The method of claim 1,
The first work function control metal-containing structure includes a first conductive layer having a first oxygen content per unit volume,
and the second work function control metal-containing structure includes a conductive layer having a second oxygen content greater than the first oxygen content by 5 to 30 atomic% per unit volume. A first first high-k film formed on the first active region of the substrate and having a first oxygen vacancy density, and a first conductive film formed on the first high-k film and having a first oxygen content. a first gate structure having a work function control metal containing structure;
a second high-k film formed over the second active region of the substrate and having a second oxygen vacancy density lower than the first oxygen vacancy density; An integrated circuit device comprising a second gate structure having a second work function control metal-containing structure including a second conductive layer having a second oxygen content. 13. The method of claim 12,
each of the first high-k film and the second high-k film includes a first metal;
The first conductive layer and the second conductive layer each include a second metal different from the first metal. 13. The method of claim 12,
a third high-k film formed over a third active region of the substrate and having a third oxygen vacancy density lower than the second oxygen vacancy density; a third gate structure having a third work function control metal-containing structure including a third conductive film having a third oxygen content;
The first conductive layer, the second conductive layer, and the third conductive layer include the same metal. delete forming a first dielectric film on the substrate in a first region and forming a second dielectric film on the substrate in a second region;
An oxygen content greater than an oxygen content in the first work function regulating metal-containing structure covering the first dielectric layer in the first region and the second work function regulating metal-containing structure covering the second dielectric layer in the second region Comprising the step of forming a second work function control metal-containing structure having a,
Forming the first work function control metal-containing structure and the second work function control metal-containing structure comprises:
forming a work function control metal-containing film covering the first dielectric film and the second dielectric film in the first region and the second region;
and oxidizing at least a portion of the work function control metal-containing layer in the second region. forming a first dielectric film on the substrate in a first region and forming a second dielectric film on the substrate in a second region;
An oxygen content greater than an oxygen content in the first work function regulating metal-containing structure covering the first dielectric layer in the first region and the second work function regulating metal-containing structure covering the second dielectric layer in the second region Comprising the step of forming a second work function control metal-containing structure having a,
Forming the first work function control metal-containing structure and the second work function control metal-containing structure comprises:
forming a first metal-containing film including oxygen atoms on the first dielectric film and the second dielectric film in the first region and the second region;
selectively removing only a portion of the first metal-containing film in the first region;
and forming a second metal-containing film having a lower oxygen content than in the first metal-containing film on the first dielectric film and the first metal-containing film in the first region and the second region A method of manufacturing an integrated circuit device. forming a first dielectric film on the substrate in a first region and forming a second dielectric film on the substrate in a second region;
An oxygen content greater than an oxygen content in the first work function regulating metal-containing structure covering the first dielectric layer in the first region and the second work function regulating metal-containing structure covering the second dielectric layer in the second region Comprising the step of forming a second work function control metal-containing structure having a,
Forming the first work function control metal-containing structure and the second work function control metal-containing structure comprises:
forming a metal-containing film including oxygen atoms on the first dielectric film and the second dielectric film in the first region and the second region;
and selectively removing oxygen atoms from the metal-containing layer only from a portion of the metal-containing layer in the first region. 19. The method of claim 18,
The method of claim 1 , wherein removing the oxygen atom includes selectively reducing only a portion of the metal-containing layer in the first region. 19. The method of claim 18,
The step of removing the oxygen atom is
forming an oxygen trapping film covering the metal-containing film in the first region;
and heat-treating a resultant formed with the oxygen trapping film in a state in which the metal-containing film is exposed in the second region to move oxygen atoms in the metal-containing film to the oxygen trapping film in the first region. A method of manufacturing an integrated circuit device comprising:

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