KR102344954B1 - Reduced Calibration Time - Google Patents

Abstract

The memory system includes an external calibration device having a predetermined impedance and a first memory device having a first pad for selective connection to the external calibration device. The first memory device also includes an internal calibration device having a programmable impedance and a second pad coupled to the internal calibration device. The system further includes a second memory device having a third pad for selective coupling to a second pad of the first memory device. The processing device is operatively coupled to the first memory device and the second memory device. The processing device programs the impedance of the internal calibration device of the first memory device based on the external calibration device and programs the impedance of the terminating component of the second memory device based on the impedance of the internal calibration device of the first memory device.

Description

Reduced Calibration Time

The present disclosure relates to a system and method for ZQ calibration in a memory system, and more particularly to reducing ZQ calibration time using parallel measurement processing.

Semiconductor systems, such as semiconductor memories and processors, transmit data over data communication lines configured to have carefully matched impedance values. Changes in certain operating parameters, such as temperature, can lead to impedance mismatches that can negatively affect data transmission speed and quality. To mitigate this negative scenario, semiconductor systems may include termination components with programmable impedances, which may be adjusted based on a calibration process as operating conditions change. In some implementations, the impedance of the terminating component is programmed based on a voltage measurement made at a connection pad attached to an external connection (also referred to herein as an “external pin” or “pin”) of the semiconductor memory package. An external pin can connect to an external reference calibration device such as a resistor. However, the number of external pins available in a typical semiconductor memory package is limited, and typically only one external reference calibration device is provided per memory package. When the semiconductor system is a memory such as SRAM or DRAM, the memory system may include a memory package having a plurality of semiconductor components (eg, semiconductor dies) each including one or more memory devices including memory cells and termination components. can In such a memory system, each memory device must share an external reference calibration device via an external pin when programming each termination component based on the results of the calibration process. However, as the number of memory devices sharing an external reference calibration device increases, the calibration time of the memory system may become very long.

1 is a block diagram of an embodiment of a memory system according to the present disclosure;
2 is a block diagram of an embodiment of a termination component in accordance with the present disclosure;
3A is a schematic diagram of an embodiment of a pull-up unit according to the present disclosure;
3B is a schematic diagram of an embodiment of a pull-down unit according to the present disclosure;
4A is a schematic diagram of an embodiment of a calibration circuit for a primary memory device according to the present disclosure;
4B is a schematic diagram of another embodiment of a calibration circuit for a primary memory device in accordance with the present disclosure.
5 is a schematic diagram of an embodiment of a calibration circuit for a secondary memory device according to the present disclosure;
6 and 7 illustrate an embodiment of a memory device grouping and ZQ calibration sequence in accordance with the present disclosure.
8 is a flowchart for an embodiment of a calibration procedure according to the present disclosure.

The present disclosure relates to a memory system including a plurality of memory devices. The memory system may also include a connection pad (referred to herein as a “ZQ pad”) commonly coupled to multiple memory devices. The ZQ pad may be connected to an external reference calibration device having a predetermined fixed impedance. The plurality of memory devices may include a first memory device that uses the external reference calibration device to calibrate the connection terminal and the internal reference calibration device at the respective first memory device. The plurality of memory devices may also include a second memory device that uses a respective internal reference calibration device of the first memory device to calibrate the connection terminal of the corresponding second memory device.

1 is a block diagram of a memory system according to the present technology. 1 , the memory system of the present disclosure will be described with reference to the memory system 100 by way of example and not limitation. The memory system 100 may be a volatile memory such as SRAM or DRAM or a non-volatile memory such as a FLASH memory or a ferroelectric memory. In one embodiment, the memory system 100 may be a Double Data Rate (DDR) memory, such as Low Power Double Data Rate 4 (LPDDR4) or LPDDR5 or Low Power Double Rate 5 (LP5) memory. Memory system 100 may be arranged as a component of a computing device such as a laptop computer, desktop computer, cellular or other mobile device, table computer, personal digital terminal, and the like. The memory system 100 may be mounted in an appropriate memory slot or otherwise interconnected with a computing device such that communication may occur via pins on a package 108 (ie, a memory module) of the memory system 100 . A computing device including memory system 100 may generally include one or more processors (not shown in FIG. 1 ). A processor may be single-core or multi-core in various implementations. Typically, memory system 100 functions as a passive device that receives and executes instructions received from a processor or processor core in a larger system. Here, the computing device may include a bus interface 124 through which the memory system 100 and the processor or processor core may communicate. As shown in FIG. 1 , the bus interface 124 may include an address bus 128 , a data bus 132 , and a command bus 136 . Figure 1 shows these various buses as separate components by way of example and not limitation. In some cases, bus interface 124 may multiplex two or more of these separate buses. For example, in some implementations, address bus 128 and command bus 136 may be time division multiplexed such that these buses use the same physical line in different time slices.

The memory system 100 may be associated with one or more memory controllers 140 configured to provide data communication to and from the memory system 100 . The memory controller 140 may include a front end 144 that communicates via a bus interface 124 . Similarly, memory controller 140 can include a back end 148 in communication with memory system 100 . Each memory controller 140 may communicate via a separate memory bus 152 that couples the back end 148 of the memory controller 140 to one or more memory devices 104 associated with the memory system 100 . . Each memory bus 152 associated with a given controller 140 may include address, data, and control lines commonly coupled between the various memory devices 104 with which the controller 140 communicates. Each memory bus 152 has a separate chip select line 156 that can be selectively asserted such that one of the memory devices 104 can send or receive data over a common address, data, and control line. may further include. Through a combination of individual chip select lines 156 and common address, data and control lines, a memory bus 152 associated with a given controller 140 is connected between the controller and each of the various memory devices 104 with which the controller 140 communicates. to provide a separate communication pathway.

According to various embodiments, the memory system 100 may include a number of memory devices 104 that may be arranged on one or more semiconductor components, such as, for example, semiconductor dies. In some embodiments, each memory device 104 may correspond to a semiconductor component, such as, for example, a semiconductor die. However, in other embodiments, multiple memory devices 104 may be installed on a semiconductor component. The package 108 of the memory system 100 may include and interconnect semiconductor components that include the memory device 104 . The package 108 may provide a number of external pins that couple to contact pads arranged on the interior of the package 108 . The pins and pads may provide electrical coupling, such as between the memory device 104 and the larger system to which the memory system 100 is coupled, as described above. Pins and pads can also provide electrical connections to other components. For example, the ZQ pad and corresponding pins may connect to an external reference calibration device such as a resistor.

In operation, the processor or processor core sends commands to the memory system 100 by first sending commands over the bus interface 124 . Memory controller 140 receives commands via bus interface 124 and routes the commands to appropriate memory devices 104 on memory system 100 . Here, the memory controller 140 asserts the appropriate chip select line 156 and issues commands over the common address, data and control lines of the memory bus 152 . Appropriate memory device 104 receives commands from memory controller 140 and initially processes the commands through operation of command decoder 160 . The command decoder 160 may be configured to recognize a plurality of commands corresponding to various operations that may be executed by the memory device 104 . In the following discussion, calibration instructions are set forth to more particularly describe certain embodiments of the present invention. However, it should be understood that the command decoder 160 is generally configured to recognize and decode a number of commands not specifically discussed herein, such as, for example, read/write commands sent to the memory array 164 . Examples of specific components associated with these commands and descriptions of various commands in the drawings have been omitted for clarity and brevity.

In some embodiments, the calibration command may instruct the controller 190 of the memory device 104 to calibrate the impedance of each termination of the termination component 188 . In some embodiments, the termination component may be an On-Die Termination (ODT) circuit. As is known, the ODT circuit can be tuned to provide a matched impedance for the data bus to which it is connected. In FIG. 1 , the termination component 188 is shown independent of the output buffer 176 . However, it is also possible for the output buffer to include the termination component 188 as part of the output buffer. In this case, the ODT operation is performed by at least a portion of the output buffer. For clarity, an exemplary embodiment of the present disclosure will be discussed with respect to the termination component 188 . However, one of ordinary skill in the art will recognize that the description may also apply where the termination component 188 is part of the output buffer 176 .

Upon receipt, the command decoder 160 routes a calibration command to the controller 190 that may be configured to adjust the impedance of the termination at the termination component 188 based on the calibration procedure initiated by the calibration command. Calibration of the impedance of the termination of the termination component 188 may be required because the impedance of the termination may change due to changes in operating conditions such as, for example, temperature changes that occur during operation of the memory system 100 . In some embodiments, each termination of termination component 188 is a pull-up and pull-down transistor controlled (eg, enabled (ON) or disabled (OFF)) by the controller 190 . may contain a group of The controller 190 enables/disables the pull-up and pull-down transistors based on the pull-up code signal and the pull-down code signal, respectively, to match the impedance of the terminating component 188 and thus the impedance of the data bus to which the output buffer 176 is connected. do. In this way, signal reflection due to impedance mismatch can be prevented.

Termination component 188 may include one or more pairs of pull-up units and pull-down units for each data input/output terminal. For example, in the illustrated embodiment of FIG. 2 , the termination component 188 includes 7 pull-up units (PU0 to PU6) and 7 pull-down units (PD0) for one data input/output terminal (or data bit) DQ. to PD6). Each of the pull-up units PU0 to PU6 has the same circuit configuration including a group of pull-up transistors known in the art. Similarly, each of the pull-down units PD0 to PD6 has the same circuit configuration comprising a group of pull-down transistors as is known in the art. Output nodes of the pull-up units PU0 to PU6 and the pull-down units PD0 to PD6 may be commonly connected to the corresponding data input/output terminal DQ through the resistor R.

3A and 3B show exemplary embodiments of pull-up and pull-down unit circuits, respectively. Turning to Fig. 3a, the pull-up unit (PU) includes seven N-channel MOS transistors (TNU0 to TNU6) (connected in parallel) and resistors (RW and RAL). Alternatively, the pull-up unit PU may include a P-channel MOS transistor. Drains of the transistors TNU0 to TNU6 may be commonly connected to a power supply line VL that supplies a power supply potential VDDQ. Sources of the transistors TNU0 to TNU6 may be connected to the data input/output terminal DQ through resistors RW and RAL. The resistor RW may be made of a tungsten wire or the like, and may be, for example, about 120 ohms. The resistor RAL may be made of an aluminum wire or the like, and may be, for example, a small resistor of 1 ohm or less.

Bits DCODEPU0 to DCODEPU6 of the code control signal DCODEPU are respectively supplied to the gate electrodes of the transistors TNU0 to TNU6. Accordingly, the seven transistors TNU0 to TNU6 may be controlled to be selectively turned on or off based on the value of the code control signal DCODEPU. As shown in Fig. 3A, the code control signal DCODEPU is generated by logically combining each bit of the code signal CODEPU and the internal data bit (data DATA) using an AND gate circuit. When the internal data bit (data DATA) is at a low level, all bits DCODEPU0 to DCODEPU6 of the code control signal DCODEPU are at the low level regardless of the value of the code signal CODEPU. As a result, all the transistors TNU0 to TNU6 are set to OFF. When the internal data bit (data DATA) is at a high level, the value of the code control signal DCODEPU is equal to the value of the code signal CODEPU. As a result, the transistors TNU0 to TNU6 are selectively turned on or off based on individual bit values of the code control signal DCODEPU. The impedance of the pull-up unit PU and thus the data input/output terminal DQ may be adjusted according to the value of the code signal CODEPU.

As shown in Fig. 3B, the pull-down unit PD includes seven N-channel MOS transistors TND0 to TND6 (connected in parallel) and resistors RW and RAL. Sources of the transistors TND0 to TND6 may be commonly connected to a power supply line SL that supplies a ground potential VSSQ. The drains of the transistors TND0 to TND6 may be connected to the data input/output terminal DQ through resistors RW and RAL.

The bits DCODEPD0 to DCODEPD6 of the code control signal DCODEPD are supplied to the gate electrodes of the transistors TND0 to TND6, respectively. Accordingly, the seven transistors TND0 to TND6 may be controlled in such a way that they are selectively turned on or off according to the value of the code control signal DCODEPD. As shown in FIG. 3B , the code control signal DCODEPD is generated by logically combining each bit of the code signal CODEPD and inverted internal data bits (data DATA) using an AND gate circuit. When the internal data bit (data DATA) is at the high level, all bits DCODEPD0 to DCODEPD6 of the code control signal DCODEPD are at the low level regardless of the value of the code signal CODEPD. As a result, all the transistors TND0 to TND6 are set to off. When the internal data bit (data DATA) is at the low level, the value of the code control signal DCODEPD is equal to the value of the code signal CODEPD. As a result, the transistors TND0 to TND6 are selectively turned on or off based on individual bit values of the code control signal DCODEPD. Similar to the pull-up unit, the impedance of the pull-down unit PD and thus the data input/output terminal DQ can be adjusted according to the value of the code signal CODEPD. As those skilled in the art understand the paired construction and operation of the pull-up and pull-down unit at the termination component 188, for the sake of brevity, the construction and operation of the pull-up and pull-down unit will not be discussed further.

Turning to FIG. 1 , in some embodiments, the calibration circuit 192 sets (or calibrates) the impedance value of each termination of the termination component 188 based on an impedance measurement of a reference calibration device having a known impedance. For example, as shown in FIG. 1 , the package 108 of the memory system 100 has an external pin 116 (also referred to herein as the ZQ pin 116 ) connected to a reference calibration device having a known impedance. may include In the illustrated exemplary embodiment, the reference calibration device may be a resistor 120 (also referred to herein as a ZQ resistor 120 ) having a known impedance value (RZQ) (eg, resistance). In some embodiments, the value of RZQ may be, for example, 240 ohms ± 1%. The code signals CODEPU and CODEPD may be generated by the calibration circuit 192 based on the impedance measurement of the ZQ resistor 120 . Because the ZQ resistor 120 is located outside the package 108 , the impedance of the ZQ resistor 120 is generally stable regardless of operating conditions, such as, for example, the temperature of the memory device 104 . ZQ resistor 120 is coupled to one or more memory devices 104 through ZQ pads 112 in each memory device 104 .

In an embodiment of the present technology, the impedance target value corresponding to the code signal CODEPU for the pull-up units PU0 to PU6 is twice the value of the ZQ resistor 120 , and may be, for example, 2RZQ. The impedance target value corresponding to the code signal CODEPD for the pull-down units PD0 to PD6 is the value of the ZQ resistor 120, and may be, for example, RZQ. Of course, 2RZQ and RZQ for the pull-up and pull-down units Each of the target impedance values is not limited and other embodiments may have different target impedances for one or both of the pull-up and pull-down units. In some embodiments, one or more of the memory devices 104 may use the ZQ resistor 120 in an impedance calibration process, which is described in more detail below.

In some embodiments, as part of a calibration command for calibrating the impedance of terminating component 188 , a known current generated by calibration circuit 192 passes through ZQ resistor 120 through ZQ pin 116 and ZQ A voltage corresponding to the impedance of resistor 120 is measured at ZQ pad 112 . The impedance of the ZQ resistor 120 represents the impedance seen by the data bus to which each termination of the termination component 188 is coupled. Calibration circuit 192 takes the measured voltage at ZQ pad 112 and compares that voltage to an internal reference voltage corresponding to the desired impedance for each termination of termination component 188 . The comparison result can be used to adjust the calibration circuit to step up or step down the voltage at the ZQ pad 112 to bring the ZQ pin 116 voltage closer to the reference voltage. To adjust the impedance to match the impedance of the connected data bus, the comparison process generates code signals (CODEPU and CODEPD) that can be used to enable/disable the various pull-up and pull-down transistors associated with the termination component 188 ( described in the application as programming the termination component).

4A shows an exemplary embodiment of a calibration circuit 192 that can generate code signals (CODEPU and CODEPD) used to program the termination at the termination component 188 of the respective memory device 104 . As shown in FIG. 4A , the output node of the pull-down unit PDR1 is connected to a comparator circuit COMPD and to an external ZQ resistor 120 through a ZQ pad 112 . The comparator circuit COMPD compares the potential of the ZQ pad 112 with the reference potential VREFDQ in response to activation of the calibration command signal CAL, and based on the result, the up-down signal UDD ) is created. The value of the reference potential (VREFDQ) is set to a value that provides the desired impedance to the pull-down unit. In this case, a reference potential (VREFDQ) of 1/2 VDDQ is used to obtain the desired impedance of RZQ to the pull-down units (PD0-PD6) at the termination component (188). The up-down signal UDD is supplied to the counter circuit CNTD, and the code signal CODEPD (multi-bit count value of the counter circuit CNTD) is boosted or reduced based on the up-down signal UDD. Step-up or pressure-down of the counter circuit CNTD is performed in synchronization with the update signal UPDATED. The update signal UPDATED is generated by the timing generation circuit TMD in synchronization with the internal clock signal ICLK when the calibration signal CAL is activated. The comparator circuit COMPD operates until the potential of the ZQ pad 112 and the potential of the reference potential VREFDQ are within a predetermined value and/or the counter circuit CNTD performs a dither condition (eg, up and down). A comparison is made between the potential of the ZQ pad 112 and the reference potential VREFDQ until entering the oscillation between up and down for the signal UDD. When the comparison result is within the predetermined value and/or the dithering condition is reached, the counter circuit CNTD may generate a signal ENDPD to indicate that the code signal CODEPD is at the calibrated value (the present application) Also known as "calibrated code signal (CODEPD)"). That is, the code signal CODEPD is at a value that will program the pull-down unit of the termination component 188 with an impedance that matches the data bus to which it is connected. The counter circuit (CNTD) maintains the calibrated code signal (CODEPD) value until the next calibration cycle.

To calibrate the code signal CODEPU, an exemplary embodiment of the present technology may use a pull-down unit programmed with the calibrated code signal CODEPD. 4A, after programming the pull-down unit PDR1, the calibrated code signal CODEPD is copied to the pull-down unit PDR0. Of course, the counter circuit CNTD may also update the pull-down unit PDR0 with an intermediate code signal CODEPD during the calibration process while the update is sent to the pull-down unit PDR1. Based on the calibrated code signal CODEPD, it turns on/off (programming) the appropriate transistor of the pull-down unit (PDR0) and sets (or calibrates) the impedance, which in this case is RZQ. The calibrated code signal (CODEPU) can then be determined using a pull-down unit (PDR0) programmed with the desired impedance.

As shown in Fig. 4a, the pull-up unit PUR0 and the pull-down unit PDR0 are connected at a common connection point A through respective resistors. Connection point A is connected to a comparator circuit COMPU which, in response to activation of a calibration signal CAL, compares the potential of connection point A with a reference potential VOH and generates an up-down signal UDU according to the result. The up-down signal UDU is supplied to the counter circuit CNTU, and the code signal CODEPU, which is a count value of the counter circuit CNTU, is boosted or reduced based on the up-down signal UDU. Step-up or pressure-down of the counter circuit CNTU is performed in synchronization with the update signal UPDATEU. The update signal UPDATEU is generated by the timing generation circuit TMU in synchronization with the internal clock signal ICLK when the calibration signal CAL and the end signal ENDPD are activated. The comparator circuit COMPU indicates that the potential of the point A and the potential of the reference potential VOH are within a predetermined value and/or the counter circuit CNTU enters a dithering condition (eg, oscillation between the up-down to the up-down signal UDU). Perform a comparison between the potential at point A and the reference potential VOH until In the exemplary embodiment of FIG. 4A , the reference potential VOH may be 1/2 VDDQ. If the comparison result is within a predetermined value or a dithering condition is reached, the counter circuit (CNTU) maintains the last code signal (CODEPU) as the calibrated code signal (CODEPU) and uses the calibrated code signal (CODEPU) to use the terminating component 188 ) and program the associated pull-up transistor. In this case, the impedance values of pull-up transistors associated with pull-up unit PUR0 and termination component 188 are set (or calibrated) to match the values of ZQ resistor 120 (eg, RZQ).

The calibration procedure described above determines the calibrated code signals (CODEPU and CODEPD) in the memory device 104 . However, as noted above, more than one memory device 104 may share the ZQ pin 116 . Because multiple memory devices 104 may share a single ZQ pin 116 , a contention issue may arise when multiple memory devices 104 simultaneously perform ZQ calibration operations. For example, in the configuration of FIG. 1 , when memory device 104 is in communication with a respective memory controller 140 , both memory controllers 140 each memory device 104 to simultaneously perform their respective calibration operations. It may be possible to issue a calibration command to To prevent a contention problem from occurring on the ZQ pin 116 , each controller 190 may include an arbiter circuit 196 to resolve contention. For example, arbitration circuitry 196 from multiple memory devices 104 shares a data bus (not shown) and uses a token ring when arbitration circuitry 196 of memory device 104 has a token. until the memory device 104 accesses the ZQ pin 116 . Another way to avoid the contention problem is to measure the potential on ZQ pin 116 to see if another memory device 104 is accessing ZQ pin 116, and if so, before attempting to connect to ZQ pin 116 beforehand. Waiting for a decided time. As those skilled in the art will understand arbitration circuits, for the sake of brevity, arbitration circuits are not discussed further except as necessary to describe exemplary embodiments of the present technology and/or to describe non-conventional arbitration circuits and methods. won't

As noted above, each package 108 may have more than one semiconductor component, such as, for example, a die. For example, in some embodiments, package 108 may have 16 semiconductor components (eg, dies), each of which may have a memory device 104 . The ZQ pads 112 of the 16 memory devices 104 may be connected to a common ZQ pin 116 on the package 108 , and the arbitration circuit 196 allows multiple memory devices 104 to operate as discussed above. It can be ensured that ZQ calibrations are not performed at the same time. However, since there are 16 memory devices 104, it may take a very long time to perform all 16 ZQ calibrations sequentially. Accordingly, in exemplary embodiments of the present technology, the memory devices 104 are configured such that at least a portion of the ZQ calibration process between the multiple memory devices 104 can be performed in parallel.

For example, the calibration circuit 192 of FIG. 4A includes a second pull-up unit PUR1 that may act as a reference calibration device for another memory device 104 , such that the calibration is performed in parallel. shows When the pull-up unit calibration process is completed, the calibrated code signal CODEPU is copied from the pull-up unit PUR0 to the pull-up unit PUR1. Of course, the pull-up unit PUR1 is connected to the counter circuit CNTU so that both pull-up units PUR0 and PUR1 can be simultaneously updated with the intermediate code signal CODEPU during the calibration process. When programmed with a calibrated code signal (CODEPU), the impedance of the pull-up unit (PUR1) corresponds to RZQ. Since the impedance of the pull-up unit PUR1 is known, the pull-up unit PUR1 can function as a reference calibration device for the purpose of calibrating the pull-down unit in another memory device 104 .

For example, as shown in FIG. 4A , the pull-up unit PUR1 may be connected to the inner pad 114 through a resistor. Internal pads 114 (also referred to herein as ZQI pads 114 ) may allow interconnects (eg, die-to-die connections) between memory devices 104 . For example, in some embodiments, the ZQ pads of one or more memory devices (referred to herein as “secondary” memory devices and identified as SEC in FIG. 1 ) are the ZQI pads 114 of the primary memory device. ) to the internal reference calibration device (e.g., pull-up unit PUR1) of another memory device (referred to herein as “primary” memory device and identified as PRI in FIG. 1 ) via . For example, as shown in FIG. 1 , a ZQ pad 112 of a secondary memory device 104( 2 ) may be coupled to a ZQI pad 114 of a primary memory device 104( 1 ), ZQ pad 112 of primary memory device 104( 1 ) may be coupled to ZQ resistor 120 . Similarly, ZQ pad 112 of secondary memory device 104(n) may be coupled to ZQI pad 114 of primary memory device 104(n-1), and primary memory device 104( The ZQ pad 112 of n-1)) may be connected to the ZQ resistor 120 . 1 , memory devices 104 ( 1 ) and 104 ( n - 1 ) are primary memory devices because they are coupled to an external reference calibration device (eg, ZQ resistor 120 ), and the memory devices 104(2) and 104(n) are secondary memory devices because they are connected to an internal reference calibration device located in the primary memory device (eg, pull-up unit PUR1). Because calibration circuit 192 is coupled to ZQ resistor 120 , calibration circuit 192 is an example of a calibration circuit that may be used in a primary memory device, such as memory device 104 ( 2 ). In some embodiments, multiple secondary memory devices may be coupled to the ZQI pad to connect to an internal reference calibration device of the primary memory device. In some embodiments, one or more primary memory devices may be coupled to the secondary memory device, while one or more other primary memory devices of the memory system may not be coupled to the secondary device.

When two or more primary memory devices are connected to an external reference calibration device (eg, ZQ resistor 120 ) through their respective ZQ pads, the primary memory device uses an arbitration circuit to connect a pin to the external reference calibration device. can avoid contention problems. Similarly, when the ZQ pads of two or more secondary memory devices are connected to the internal reference calibration device of the primary memory device via the ZQI pads of the primary memory device, the secondary memory devices contend at the ZQI pads using an arbitration circuit. problems can be avoided. The arbitration circuitry of the primary and/or secondary memory device may be configured to ensure that one or more memory devices do not access an appropriate external reference calibration device or an internal reference calibration device using token ring and/or pad voltage type arbitration methods. can Also, in some embodiments of the present technology, the controller 190, controller 140, and/or other controllers are configured such that the one or more memory devices do not have access to an appropriate external reference calibration device and/or an internal reference calibration device. It can be programmed into a calibration sequence for the primary and/or secondary memory devices to prevent

As discussed above, FIG. 4A shows a calibration circuit for a primary memory device. In contrast, FIG. 5 illustrates an embodiment of a calibration circuit that may be used in a secondary memory device, such as, for example, memory device 104( 2 ). Other than the calibration process, the operation of the primary and secondary memory devices may be identical. 4A and 5 , in the calibration circuit 192a of the secondary memory device, instead of the ZQ pad 112 connected to the ZQ resistor 120 , the ZQ pad 112 is the ZQI pad of the primary memory device. It is connected via 114 to the programmable pull-up unit PUR1 (internal reference calibration device) of the primary memory device. The ZQI pad 114 connection of the primary memory device is connected to the calibration circuit 192a of the secondary memory device when performing a calibration process to determine the calibrated code signal (CODEPD) of the secondary memory device. Allows the pull-up unit (PUR1) to be used as a reference calibration device. As discussed above, the pull-up unit (PUR1) of the primary memory device has a known impedance value as it has been programmed with the calibrated code signal (CODEPU) of the primary memory device. That is, the previously programmed pull-up unit PUR1 of the primary memory device replaces the external ZQ resistor 120 as the reference calibration device when programming the secondary memory device. For example, in the illustrated embodiment of FIG. 4A , the impedance of the pull-up unit PUR1 programmed with the calibrated code signal is RZQ and the reference potential VREFDQ of the circuit 192a is the pull-up unit of the primary memory device ( Since the impedance of PUR1) is RZQ, it is 1/2 VDDQ. Of course, the impedance value of the pre-calibrated pull-up unit PUR1 in the primary memory device may be different from that of the ZQ resistor 120 . In this case, when the calibration circuit 192a performs a calibration process to determine the code signal CODEPD for the secondary memory device, an appropriate adjustment to the reference potential VREFDQ in the calibration circuit 192a may be necessary. have.

As shown in FIG. 5 , the output node of the pull-down unit PDR1 of the calibration circuit 192a is connected to the comparator circuit COMPD and the ZQ pad 112 . The ZQ pad 112 of the calibration circuit 192a is connected to the ZQI pad 114 of the primary memory device. The comparator circuit COMPD compares the potential of the ZQI pad 114 (via the ZQ pad 112) with the reference potential VREFDQ in response to activation of the calibration command signal CAL, and an up-down signal based on the result. (UDD) is created. The value of the reference option (VREFDQ) is set to a value that provides the desired impedance for the pull-down unit. In this case, the impedance of PUR1 in the primary memory device is RZQ, so a VREFDQ of 1/2 VDDQ is used to obtain the desired RZQ impedance for the pull-down units (PD0-PD6). Once the calibrated code signal CODEPD is generated for the secondary memory device, the calibrated code signal CODEPU for the secondary memory device is generated in a manner similar to that described above for the calibration circuit 192 .

In the embodiment of Figure 4a, a separate pull-up unit PUR1 has been added to the calibration circuit 192 to act as a reference calibration device. However, the pull-up unit PUR0, which is part of the calibration circuit that generates the calibrated code signal CODEPU, also has an impedance of RZQ at the end of the calibration process. Accordingly, in some embodiments, the pull-up unit PUR1 is not included in the calibration circuit of the primary memory device. Instead, the post-calibration pull-up unit PUR0 performs the function of the reference calibration device used by the secondary memory device. For example, FIG. 4B illustrates an embodiment of the calibration circuit 192b in which the pull-up unit PUR0 is used as the internal reference calibration device and the pull-up unit PUR1 is eliminated. In this embodiment, Node A may include a ZQI pad 114 (or may be coupled to the ZQI pad 114 ). However, before another secondary memory device is connected to the pull-up unit PUR0 through the ZQI pad 114 , PDR0 must be disabled to prevent interference. For example, PDR0 can be turned off or disconnected so that there is a high impedance between node A and the output of PDR0. Because there is one less copy operation for the code signal CODEPU (eg, copy to the pull-up unit PUR1) in this embodiment, a random error is reduced compared to the calibration circuit 192 of FIG. 4A , the code signal CODEPU ) is less likely to be inserted into

In any configuration of calibration circuitry for the primary device (eg, calibration circuitry 192 or calibration 192b ), the one or more secondary memory devices include one or more secondary memory devices that perform calibration of respective code signals (CODEPD and CODEPU). Calibration of the individual code signals (CODEPD and CODEPU) can be performed in parallel with the primary memory device. Accordingly, as will be discussed in greater detail below, exemplary embodiments of the present technology reduce the calibration time of a memory system having multiple memory devices, for example, by about one-third as compared to a memory system that does not perform parallel calibration. It can be reduced from 3 to 1/2 (depending on the arrangement of the primary and secondary memory devices and the number of memory devices). This is because, in a conventional memory component, all memory devices of the memory system share the same external reference calibration device (eg, ZQ resistor 120 ) and the ZQ calibration must be performed sequentially.

6 shows an exemplary embodiment that can reduce the calibration time by approximately one-half for a memory system having 16 memory devices 104 . As shown in FIG. 6 , memory devices 104 are assembled into groups A-D having one or more memory devices 104 . At least one memory device 104 of each group is configured as a primary memory device such that a ZQ pad 112 is coupled to a ZQ pin 116 of the package 108 . The other memory devices 104 of each group are configured as secondary memory devices such that each ZQ pad 112 is coupled to the ZQI pad 114 of the primary memory device. In the embodiment of FIG. 6 , package 108 includes 16 memory devices 104( 1 ) - 104 ( 16 ) evenly arranged such that each of the four groups A-D has four memory devices 104 . For clarity, the internal circuitry for each memory device 104 is not shown, and only connections to the ZQ pad and ZQI pad (for the primary memory device) are shown for each memory device. The primary memory devices for each group (eg, memory device 104(1) of group A, 104(5) of group B, 104(9) of group C, 104(13) of group D) are each It is connected in parallel to the ZQ resistor 120 through the ZQ pad. The secondary memory devices of each group are connected in parallel to the ZQI pads of the primary memory devices through respective ZQ pads. For example, as shown in FIG. 6 , the ZQ pads of the secondary memory devices 104( 2 ) - 104( 4 ) are connected to the ZQI pads of the primary memory device 104( 1 ), and the secondary The ZQ pads of the memory devices 104 ( 6 ) - 104 ( 8 ) are coupled to the ZQI pads of the primary memory device 104 ( 5 ), and the ZQ pads of the secondary memory devices 104 ( 10 ) - 104 ( 12 ). is connected to the ZQI pad of the primary memory device 104(9), and the ZQ pads of the secondary memory devices 104(14)-104(16) are the ZQI pads of the primary memory device 104(13). is connected to

As discussed above, ZQ calibration of a memory device uses a ZQ resistor to program a pull-down unit to determine a calibrated code signal (CODEPD) and calibrates using a pull-down unit programmed with a calibrated code signal (CODEPD). It involves a two-step process involving programming of a pull-up unit to determine the coded code signal (CODEPU). Assuming each step of the two-step calibration process is a calibration step, for example, in a conventional memory system with 16 memory devices in a package, a minimum of 17 calibration steps is required to calibrate all memory devices sequentially (CODEPU Assume that if calibration starts on one memory device, then CODEPD calibration starts on the next memory device). However, in the exemplary embodiment of FIG. 6 , the total number of calibration steps may be reduced to nine steps. In Fig. 6, two numbers are shown above each memory device to indicate a calibration step corresponding to the two steps for each memory device. The step number above the ZQ terminal corresponds to the first calibration step for each memory device and the number above the ZQI terminal (primary memory device) or empty box (secondary memory device) is the second calibration step for each memory device. corresponding to the steps.

Table 1 summarizes the steps of the ZQ calibration process for calibrating the code signals (CODEPD and CODEPU) for each of the 16 memory devices 104 . 6 and Table 1, in the first step of the ZQ calibration process for package 108, memory device 104(1) connects ZQ resistor 120 through ZQ pad 112 as described above. to calibrate the code signal (CODEPD). In the second step of the ZQ calibration process, the memory device 104(1) calibrates the code signal CODEPU and the memory device 104(5) uses the ZQ resistor 120 via the ZQ pad 112 to Simultaneously calibrate the code signal (CODEPD). In the third step of the ZQ calibration process, memory device 104(5) calibrates code signal CODEPU and memory device 104(9) uses ZQ resistor 120 via ZQ pad 112 to Simultaneously calibrate the code signal (CODEPD). Also, unlike the existing system, during the third stage of the ZQ calibration process, the memory device 104(2) performs the calibration of the code signal CODEPD in the memory device 104(9) in parallel with the ZQ pad 112 and Calibration of the code signal CODEPD is performed using the currently programmed pull-up unit of the memory device 104( 1 ) via the connection between the ZQI pads 114 of the memory device 104 ( 1 ). Thus, unlike conventional systems, the memory device 104(2) has its ZQ resistance No need to wait for release. In step 4, memory devices 104(2) and 104(9) perform CODEPU calibration, and memory device 104(13) uses ZQ resistor 120 via ZQ pad 112 to signal a code signal. (CODEPD), and memory devices 104(3) and 104(6) with ZQ pads 112 of memory devices 104(1) and 104(5), respectively, as shown in FIG. Through the connection between the ZQI pads 114 , the respective code signal CODEPD is calibrated using the currently programmed pull-up units of the memory devices 104 ( 1 ) and 104 ( 5 ). In step 5, memory devices 104(3), 104(6), and 104(13) perform CODEPU calibration, and memory devices 104(4), 104(7), and 104(10) are memory devices, respectively. Memory devices 104(1), 104(5) and 104(9) via a connection between ZQ pad 112 and ZQI pad 114 of devices 104(1), 104(5) and 104(9). ))), calibrate each code signal (CODEPD) using the currently programmed pull-up unit. Since this embodiment has only four primary memory devices, the ZQ resistor 120 is not accessed by the memory device 104 starting in step 5 . 6 and Table 1, steps 6 to 9 are not discussed for the sake of brevity, as those skilled in the art can understand the calibration sequence for the remaining steps. Of course, the sequence in which the primary device accesses the external reference calibration device is not limited to that shown in Table 1 and other suitable sequences may be used. Similarly, the sequence in which the secondary memory device accesses each internal reference calibration device is not limited to that shown in Table 1 and other suitable sequences may be used.

Table 1

In the exemplary embodiment of FIG. 6 , groups A-D have the same number of memory devices 104 . By equalizing the groupings, the manufacturing process for the interconnections between ZQ pads and ZQI pads is simpler than if each grouping had a different number of memory devices. However, as can be seen in Table 1, there is no memory device accessing ZQ resistor 120 for CODEPD calibration in steps 5-9. Accordingly, when it is not necessary to make the number of memory devices in each group the same, the ZQ calibration time can be further reduced.

7 shows another exemplary embodiment of the present invention. As shown in Figure 7, the memory devices of the package 108 are arranged in six groups A-F. There are 5 memory devices in group A, 4 memory devices in group B, 3 memory devices in group C, 2 memory devices in group D, and only one memory device in groups E and F have. In Fig. 7, which is similar to the embodiment of Fig. 6, two numbers representing calibration steps corresponding to the two steps for each memory device are displayed above each memory device. The step number above the ZQ terminal corresponds to the first calibration step for each memory device and the number above the ZQI terminal (primary memory device) or empty box (secondary memory device) corresponds to the second calibration step for each memory device. corresponds to the stage.

By arranging the memory devices in groups A-F as shown in Fig. 7, the number of ZQ calibration steps can be reduced to seven. For the sake of brevity, the ZQ calibration steps are not discussed because the calibration sequence is understandable to those skilled in the art based on the above description with respect to FIG. 6 , the embodiment shown in FIG. 7 and a summary of the calibration steps in Table 2. Of course, the sequence in which the primary device accesses the external reference calibration device is not limited to the sequence shown in Table 2, and other suitable sequences may be used. Similarly, the sequence order in which the secondary memory device accesses each internal reference calibration device is not limited to the sequence shown in Table 2 and other suitable sequences may be used.

Table 2

The exemplary ZQ calibration sequences of FIGS. 6 and 7 are for a memory system with 16 memory devices. However, those skilled in the art will understand that the techniques used in the exemplary embodiment of FIGS. 6 and 7 may be applied to memory systems having two or more memory devices, including memory systems having more than 16 memory devices. By arranging the memory devices 104 into groups in which one or more memory devices perform parallel calibration using the internal calibration device of another memory device as a reference, a reduction in ZQ calibration time can be achieved.

8 is a flow diagram illustrating an example method 800 for managing ZQ calibration in a memory device. Method 800 may include hardware (eg, processing device, circuitry, dedicated logic, programmable logic, microcode, hardware of the device, integrated circuit, etc.), software (eg, instructions performed or executed on the processing device). , or a combination thereof. In some embodiments, method 800 is performed by controller 190 , controller 140 , and/or other controllers. Although indicated in a specific sequence or order, the order of the processes may be modified unless otherwise specified. Accordingly, the illustrated embodiments are to be understood as examples only, and the illustrated processes may be performed in a different order, and some processes may be performed in parallel. Additionally, one or more processes may be omitted in various embodiments. Accordingly, not all processes are necessary in all embodiments. Other process flows are possible.

At block 810 , a processing device (eg, controller 190 , controller 140 , and/or other controller) couples the first memory device to an external calibration device coupled to a pin of the package. For example, as discussed above and shown in FIGS. 1 , 4A and 4B , the ZQ pad 112 of the primary memory device may be connected to the ZQ resistor 120 via pin 116 of the package 108 . can

At block 820 , the processing device (eg, controller 190 , controller 140 , and/or other controller) programs a first impedance of an internal calibration device of the first memory device based on the external calibration device. . For example, as discussed above and shown in FIGS. 4A and 4B , after determining the calibrated code signal CODEPU, an internal calibration device (eg, pull-up unit PUR1 (FIG. 4A) or (PUR0) (FIG. 4B)) is calibrated by the calibration circuit of the primary memory device.

At block 830 , the processing device (eg, controller 190 , controller 140 , and/or other controller) programs a second impedance of the terminating component in the second memory device based on the first impedance. For example, as discussed above and shown in FIGS. 1 and 5 , the calibration circuit 192a of the secondary memory device determines a calibrated code signal CODEPD based on an internal calibration device of the primary memory device. do. Calibration circuitry 192a may also determine a calibrated code signal (CODEPU) for the secondary memory device, and then the calibrated code signals (CODEPD and CODEPU) may be used to program the termination at termination component 188 .

In the above-described embodiments, the calibrated code signal CODEPD of the memory device is first determined, and then the calibrated code signal CODEPU of the memory device is determined based on the calibrated code signal CODEPD. However, a person skilled in the art understands that the calibrated code signal CODEPU can be determined first and then the calibrated code signal CODEPD can be determined based on the calibrated code signal CODEPU. Also, in the above-described embodiment, the internal reference calibration device is a pull-up unit. However, a person skilled in the art understands that the internal reference calibration device may be a pull-down unit.

In the above exemplary embodiment, for clarity, the primary memory device and the secondary memory device have been described as having different structures for each calibration circuit, and the secondary memory device is shown without a ZQI pad. However, one of ordinary skill in the art understands that all memory devices may have the same structure and/or structures in which the calibration function corresponding to the primary and secondary memory devices at least partially overlaps. For example, every memory device can be configured to have a ZQ pad that can connect to an external reference calibration device or an internal reference calibration device of another memory device through a pin on the package, and/or all memory devices can It can be configured to have a ZQI pad that can access an internal reference calibration device. During the calibration operation, the execution of other functions between the primary memory device and the secondary memory device may be accomplished by suitable circuitry such as, for example, a switching circuit. For example, with respect to the function of selecting an external or internal calibration device, the ZQ pad 112 is connected via pin 116 to the ZQ resistor 120 (eg, to perform the function of the calibration circuit 192 ). ) or a ZQI pad 114 of the primary memory device (eg, to perform the function of the calibration circuit 192a). have. Accordingly, in some embodiments, the structure of the memory device 104 may be the same, and the functions of the primary memory device and the secondary memory device may suitably program the controller 190 , the controller 140 , and/or other controllers. can be achieved by

The above detailed description of embodiments of the technology is not intended to be exhaustive or to limit the technology to the precise form disclosed above. Although specific embodiments and examples of the technology have been described above for purposes of explanation, various equivalent modifications are possible within the scope of the technology as those skilled in the relevant art will recognize. For example, while steps are presented in a given order, alternative embodiments may perform the steps in a different order. The various embodiments described herein may also be combined to provide further embodiments.

As described above, specific embodiments of the technology have been described in this application for purposes of illustration, but well-known structures and functions have not been shown or described in detail to avoid unnecessarily obscuring the description of the embodiments of the technology. will be able to know Where the context permits, singular or plural terms may include each plural or singular term. Moreover, unless the word “or” in relation to a list of two or more items is expressly limited to mean only a single item exclusive of any other item, the use of “or” in such a list is (a) a single item of the list. items, (b) all items on the list, or (c) any combination of items on the list. Additionally, the terms “comprising,” “comprising,” “having,” and “with” are used in their entirety to at least not exclude any larger number of the same features and/or other features of additional types, such that at least the referred features are not excluded. is meant to include (s).

A processing device (eg, controller 190 , controller 140 , and/or other controllers) represents one or more general-purpose processing devices, such as microprocessors, central processing units, and the like. More specifically, the processing device comprises a complex instruction set computing (CISC) microprocessor, reduced instruction set computing (RISC) microprocessor, very long instruction word (VLIW) microprocessor, or a processor or combination of instruction sets implementing another instruction set. It may be a processor that implements it. A processing device (eg, controller 190 , controller 140 and/or other controllers) may be one or more special purpose such as an application specific integrated circuit (ASIC), a field programmable gate array (FPGA), a digital signal processor (DSP), a network processor, and the like. It may be a processing device. A processing device (eg, controller 190 , controller 140 , and/or other controllers) is configured to execute instructions for performing the operations and steps discussed herein.

A machine-readable storage medium (also referred to as a computer-readable medium) has stored therein one or more sets of instructions or software implementing any one or more of the methodologies or functions described in this application. The machine-readable storage medium may be, for example, the memory system 100 or other memory device. The term "machine-readable storage medium" should be considered to include a single medium or multiple media having one or more sets of instructions stored thereon. The term "machine-readable storage medium" is also intended to include any medium capable of storing or encoding a set of instructions for execution by a machine and causing a machine to perform any one or more of the methodologies of this disclosure. . Accordingly, the term "machine-readable storage medium" should be considered to include, but is not limited to, solid state memory, optical media, and magnetic media.

Portions of the foregoing detailed description have been presented in terms of algorithms and symbolic representations of operations on bits of data within a computer memory. These algorithmic descriptions and representations are methods used by those skilled in the data processing arts to most effectively convey the substance of their work to those skilled in the art. An algorithm is here generally regarded as a coherent sequence of actions leading to a desired result. Actions are those that require physical manipulation of physical quantities. Typically, but not necessarily, these quantities take the form of electrical or magnetic signals capable of being stored, combined, compared, and otherwise manipulated. It has proven convenient to refer to these signals as bits, values, elements, symbols, characters, terms, numbers, etc., principally for reasons of common usage.

It should be borne in mind, however, that these and similar terms should all be associated with the appropriate physical quantities and are merely convenient labels applied to these quantities. The present disclosure provides a computer system for manipulating and converting data expressed in physical (electronic) quantities within registers and memories of the computer system into other data similarly expressed in physical quantities within computer system memory or registers or other such information storage systems. or to the operations and processes of similar electronic computing devices.

The present disclosure also relates to an apparatus for performing the operations in the present application. This apparatus may be specially constructed for its intended purpose or it may comprise a general purpose computer selectively activated or reconfigured by a computer program stored in the computer. These computer programs may include floppy disks, optical disks, CD-ROMs and magneto-optical disks, read-only memory (ROM), random access memory (RAM), EPROMs, EEPROMs, magnetic or optical cards, each coupled to a computer system bus; may be stored in a computer-readable storage medium such as a disk of any type including any tangible medium suitable for storing electronic instructions.

The algorithms and displays presented in this application are not inherently related to any particular computer or other device. A variety of general purpose systems may be used with programs in accordance with the teachings of this application, or it may prove convenient to construct more specialized apparatus to perform the methods. The architecture of these various systems is presented as described in the description below. In addition, the present disclosure is not described with reference to any particular programming language. It will be understood that a variety of programming languages may be used to implement the teachings of the disclosure described in this application.

The present disclosure may be provided as a computer program product or software, which may include a machine-readable medium having stored thereon instructions that can be used to program a computer system (or other electronic device) to perform a process according to the present disclosure. Machine-readable media includes any mechanism for storing information in a form readable by a machine (eg, a computer). In some embodiments, a machine-readable (eg, computer-readable) medium is a machine (eg, computer)-readable storage medium such as read-only memory (“ROM”), random access memory (“RAM”) , magnetic disk storage media, optical storage media, flash memory devices, and the like.

In addition, it will be appreciated that various modifications are possible without departing from the present disclosure. For example, those skilled in the art will understand that the various components of the technology may be further divided into sub-components or that the various components and functions of the technology may be combined and integrated. In addition, certain aspects of a technology that are described in the context of certain embodiments may also be combined or eliminated in other embodiments. Moreover, although advantages associated with particular embodiments of the new technology have been described in the context of these embodiments, other embodiments may exhibit such advantages, and not all embodiments necessarily exhibit such advantages to be within the scope of the technology. Accordingly, the disclosure and related technology may include other embodiments not explicitly shown or described.

Claims (24)

In the device,
a package having pins configured to connect to an external calibration device;
A first memory device disposed in the package, comprising:
a first pad for selective connection to the external calibration device via the pin;
a first internal calibration device having a first programmable reference impedance, and
a second pad coupled to the first internal calibration device;
A second memory device disposed in the package, comprising:
a second internal calibration device having a second programmable reference impedance, and
the second memory device comprising a third pad for selective coupling to a second pad of the first memory device; and
a processing device operatively coupled to the first memory device and the second memory device;
programming the first reference impedance based on the external calibration device; and
determine a calibration code signal based on programming the second reference impedance using the first reference impedance of the first internal calibration device;
and the processing device for programming a termination impedance of a termination component in the second memory device based on the calibration code signal. The method of claim 1,
a third memory device disposed in the package, the third memory device comprising a fourth pad for selective connection to the external calibration device via the pin;
the processing device is further configured to determine a second calibration code signal for programming a second terminating impedance of a second terminating component of the third memory device;
and determining the second calibration code signal and determining the calibration code signal for the terminating component of the second memory device are performed in parallel. The method of claim 1 , wherein the programming of the first reference impedance comprises:
determining a second calibration code signal for a second terminating component of the first memory device using the external calibration device;
determining a third calibration code signal for the second terminating component using the second calibration code signal; and
and programming the first reference impedance using the third calibration code signal. 2. The method of claim 1, wherein the second memory device is one of a plurality of second memory devices disposed in the package, and
and each respective third pad of the plurality of second memory devices is configured for selective coupling to a second pad of the first memory device. In the device,
a package having pins configured to connect to an external calibration device;
A first memory device disposed in the package, comprising:
a first pad for selective connection to the external calibration device via the pin;
an internal calibration device having a programmable first impedance, and
a second pad coupled to the internal calibration device;
a second memory device disposed in the package, the second memory device comprising a third pad for selective coupling to a second pad of the first memory device; and
a processing device operatively coupled to the first memory device and the second memory device;
programming the first impedance based on the external calibration device; and
the processing device for programming a second impedance of a termination component in the second memory device based on the first impedance;
the first memory device is one of a plurality of first memory devices disposed in the package, the second memory device is one of a plurality of second memory devices disposed in the package;
For each first memory device of the plurality of first memory devices, a portion of the plurality of second memory devices passes through the third pad of each second memory device to a second memory device of each of the first memory devices. A device configured to selectively connect to a pad. 6. The method of claim 5, wherein each of the first memory devices comprises a first arbiter circuit to ensure that only one first memory device is coupled to the external calibration device, and wherein the second memory devices each comprising a second arbitration circuit to ensure that only one second memory device is coupled to the internal calibration device of the respective first memory device. 6. The apparatus of claim 5, wherein the number of first memory devices ranges from 1 to 6, and for each portion of the second memory devices, the number of second memory devices is at most four. 6. The apparatus of claim 5, wherein the number of first memory devices is four and the number of second memory devices in each portion of the second memory device is three. In the method,
coupling the first memory device to an external calibration device coupled to a pin of the package;
programming a first reference impedance of a first internal calibration device of a first memory device based on the external calibration device;
coupling the first internal calibration device to a second memory device;
determining a calibration code signal based on programming a second reference impedance of a second internal calibration device of the second memory device using the first reference impedance of the first internal calibration device; and
and programming a terminating impedance of a terminating component in the second memory device based on the calibration code signal. 10. The method of claim 9,
connecting a third memory device to the external calibration device via the pin;
determining a second calibration code signal for programming a second terminating impedance of a second terminating component of the third memory device;
and determining the second calibration code signal and determining the calibration code signal for the terminating component of the second memory device are performed in parallel. 10. The method of claim 9, wherein the programming of the first reference impedance comprises:
determining a second calibration code signal for a second terminating component of the first memory device using the external calibration device;
determining a third calibration code signal for the second terminating component using the second calibration code signal; and
and programming the first reference impedance using the third calibration code signal. 10. The method of claim 9, wherein the second memory device is one of a plurality of second memory devices selectively coupled to the first memory device. In the method,
coupling the first memory device to an external calibration device coupled to a pin of the package;
programming a first impedance of an internal calibration device of a first memory device based on the external calibration device; and
programming a second impedance of a terminating component in a second memory device based on the first impedance;
the first memory device is one of a plurality of first memory devices disposed in the package, the second memory device is one of a plurality of second memory devices disposed in the package;
and for each first memory device of the plurality of first memory devices, some of the plurality of second memory devices are configured to selectively couple to the respective first memory device. 14. The method of claim 13,
controlling each of the first memory devices' access to the external calibration device to ensure that only one first memory device is connected to the external calibration device; and
controlling each access of the second memory device to each of the first memory devices to ensure that only one second memory device is connected to the internal calibration device of each of the first memory devices. Including method. 14. The method of claim 13, wherein the number of first memory devices ranges from 1 to 6, and for each portion of the second memory devices, the number of second memory devices is at most four. 14. The method of claim 13, wherein the number of first memory devices is four and the number of second memory devices in each portion of the second memory device is three. A non-transitory computer-readable storage medium comprising instructions, wherein the instructions, when executed by a processing device, cause the processing device to:
operatively connect the first memory device to an external calibration device coupled to a pin of the package;
programming a first reference impedance of a first internal calibration device of the first memory device based on the external calibration device;
operatively connect the first internal calibration device to a second memory device;
determine a calibration code signal based on programming a second reference impedance of a second internal calibration device of the second memory device using the first reference impedance of the first internal calibration device;
and program a terminating impedance of a terminating component in the second memory device based on the calibration code signal. 18. The method of claim 17, wherein when executed by the processing device causes the processing device to:
operatively connect a third memory device to the external calibration device via the pin;
instructions for determining a second calibration code signal for programming a second terminating impedance of a second terminating component of the third memory device;
and determining the second calibration code signal and determining the calibration code signal for the terminating component of the second memory device are performed in parallel. 18. The method of claim 17, wherein the programming of the first reference impedance comprises:
determining a second calibration code signal for a second terminating component of the first memory device using the external calibration device;
determining a third calibration code signal for the second terminating component using the second calibration code signal; and
and programming the first reference impedance using the third calibration code signal. 18. The non-transitory computer-readable storage medium of claim 17, wherein the second memory device is one of a plurality of second memory devices selectively coupled to the first memory device. A non-transitory computer-readable storage medium comprising instructions, wherein the instructions, when executed by a processing device, cause the processing device to:
operatively connect the first memory device to an external calibration device coupled to a pin of the package;
programming a first impedance of an internal calibration device of the first memory device based on the external calibration device;
program a second impedance of a terminating component to a second memory device based on the first impedance;
the first memory device is one of a plurality of first memory devices disposed in the package, the second memory device is one of a plurality of second memory devices disposed in the package;
and for each first memory device of the plurality of first memory devices, some of the plurality of second memory devices are configured to selectively couple to the respective first memory device. 18. The method of claim 17, wherein when executed by the processing device causes the processing device to:
control access of each first memory device to the external calibration device to ensure that only one first memory device is connected to the external calibration device; and
control access of each said second memory device to each first memory device to ensure that only one second memory device is connected to the internal calibration device of each said first memory device further comprising a non-transitory computer-readable storage medium. 23. The computer readable non-transitory computer of claim 22, wherein the number of first memory devices ranges from 1 to 6, and for each portion of the second memory devices, the number of second memory devices is at most four. Available storage media. 23. The non-transitory computer-readable storage medium of claim 22, wherein the number of first memory devices is four and the number of second memory devices in each portion of the second memory device is three.

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