KR102340212B1 - Semiconductor device - Google Patents

Abstract

The present invention relates to a semiconductor device, and is a technology for reducing power consumption during a refresh operation. According to the present invention, a first word line driver for driving a first word line in response to an enable signal, an enable bar signal, and a first word line enable signal, an enable signal, an enable bar signal, and a second word line enable A second word line driver for driving the second word line in response to the enable signal and a connection controller for connecting the first word line and the second word line to each other in response to the enable signal and the enable bar signal in the word line charge sharing section and, in the refresh mode, the first word line and the second word line are sequentially driven.

Description

semiconductor device

The present invention relates to a semiconductor device, and is a technology for reducing power consumption during a refresh operation.

Among semiconductor memory devices, a dynamic random access memory (DRAM) is a representative volatile memory. A memory cell of a DRAM is composed of a cell transistor and a cell capacitor. Here, the cell transistor serves to control access to the cell capacitor, and the cell capacitor stores charge corresponding to data. That is, high-level data or low-level data is classified according to the amount of charge stored in the cell capacitor.

In such a memory cell of a DRAM, electric charge flows into or out of the cell capacitor due to a leakage component, and thus corresponding data must be periodically stored again. As described above, an operation periodically performed to accurately maintain data is referred to as a refresh operation.

In an active mode, a memory cell of a DRAM is activated. In addition, the bit line sense/amplifier circuit senses and amplifies data transmitted from the activated memory cell, and transmits it back to the memory cell.

Also, in the precharge mode, the memory cell is inactivated and retains data. That is, the refresh operation may be described as repeatedly performing the active operation and the precharge operation at a constant cycle.

When enabling multiple word lines during a refresh operation, the word lines selected by the row address decoder are sequentially enabled one by one. That is, the active and precharge operations of the first word line are performed, and the active and precharge operations of the next word line are performed after a predetermined time (tRP: Row Precharge Time).

However, during the active operation of the word line, the word line is charged to the high voltage (VPP) level, and during the precharge operation, the word line is discharged to the low voltage (VSS or VBBW) level. When the charging and discharging operations of the word line are repeatedly performed in this way, current consumption increases.

As semiconductor devices become large-capacity and high-density, the tech shrinks and the refresh capability decreases. In this case, more active operations are required, which increases power consumption.

The present invention has a feature of reducing current consumption through charge-sharing of word lines that are sequentially enabled during a refresh operation.

A semiconductor device according to an embodiment of the present invention includes: a first word line driver configured to drive a first word line in response to an enable signal, an enable bar signal, and a first word line enable signal; a second word line driver for driving a second word line in response to the enable signal, the enable bar signal, and the second word line enable signal; and a connection control unit connecting the first word line and the second word line to each other in response to the enable signal and the enable bar signal in the word line charge-sharing section, wherein in the refresh mode, the first word line and the second word line are It is characterized in that it is driven sequentially.

A semiconductor device according to another embodiment of the present invention includes: a plurality of word line drivers selectively driving a plurality of word lines in response to a plurality of enable signals, a plurality of enable bar signals, and a plurality of word line enable signals; and a plurality of connection controllers for selectively connecting two word lines among a plurality of word lines in response to a plurality of enable signals and a plurality of enable bar signals in a word line charge-sharing section, and in a refresh mode, the plurality of word lines are sequentially driven.

The present invention provides an effect of reducing current consumption through charge-sharing of word lines that are sequentially enabled during a refresh operation.

In addition, the embodiment of the present invention is for illustration, and those skilled in the art will be able to make various modifications, changes, substitutions and additions through the technical spirit and scope of the appended claims, and such modifications and changes fall within the scope of the following claims. should be seen as

1 is a block diagram of a semiconductor device according to an embodiment of the present invention;
FIG. 2 is a detailed circuit diagram of the control signal generator of FIG. 1;
FIG. 3 is an operation waveform diagram of the semiconductor device according to the embodiment of FIG. 1 ;
4 is a block diagram of a semiconductor device according to another embodiment of the present invention;
5 is a detailed circuit diagram of the control signal generator of FIG. 4;
6 is an operation waveform diagram of the semiconductor device according to the embodiment of FIG. 4 ;

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.

1 is a block diagram of a semiconductor device according to an embodiment of the present invention.

A semiconductor device according to an embodiment of the present invention includes a plurality of word line drivers 100 to 130 , a plurality of connection controllers 200 and 210 , and a control signal generator 300 .

The plurality of word line drivers 100 to 130 control whether the word line is activated during the refresh operation period. The word line driver 100 controls whether the word line WL0 is activated in response to the enable signal CSEN, the enable bar signal CSENB, and the word line enable signal WLOEN. The word line driver 110 controls whether the word line WL1 is activated in response to the enable signal CSEN, the enable bar signal CSENB, and the word line enable signal WL1EN. In addition, the word line driver 120 controls whether the word line WL2 is activated in response to the enable signal CSEN, the enable bar signal CSENB, and the word line enable signal WL2EN. The word line driver 130 controls whether the word line WL3 is activated in response to the enable signal CSEN, the enable bar signal CSENB, and the word line enable signal WL3EN.

Here, the enable bar signal CSENB is a signal whose phase is opposite to that of the enable signal CSEN. Further, in the embodiment of the present invention, the number of word lines WL0 to WL3 and the word line driver 100 to 130 has been described as an example of four, but this is only an example. The word lines WL0 to WL3 and the word line driver 100 The number of ~130) is not limited.

In addition, the plurality of connection controllers 200 and 210 connect two word lines during a 'word line charge-sharing period' so that charges can be shared between the two word lines. Here, the 'word line charge-sharing period' refers to a period from which two adjacent word lines are connected to each other until the first word line is precharged and the second word line is activated.

For example, when the enable signal CSEN is activated during the first 'word line charge-sharing period', the connection controller 200 connects two adjacent word lines WL0 and WL1 to each other. In addition, when the enable signal CSEN is activated during the second 'word line charge-sharing period', the connection control unit 200 connects two adjacent word lines WL2 and WL3 to each other.

In a precharge operation after the word line WLO is activated, the voltage of the word line WLO is discharged from a high voltage (eg, VPP) to a low voltage (eg, VSS or VBBW). In an operation in which the word line WL1 is precharged and then activated, the voltage of the word line WL1 is charged from a low voltage to a high voltage. However, a large amount of current may be consumed when more active-precharge operations are performed in order to improve the performance value of the refresh operation.

Accordingly, in the embodiment of the present invention, the current of the high level word line (eg, word line WL0) is transferred to the low level word line (eg, word line WL1) during the word line charge sharing period. do. In this case, even when the number of active-precharge operations increases in the refresh mode, current consumption can be reduced.

In addition, the control signal generator 300 controls whether the enable signal CSEN and the enable bar signal CSENB are activated during the word line charge-sharing period during the refresh operation. The control signal generator 300 controls whether the enable signal CSEN and the enable bar signal CSENB are activated in response to the refresh signal REF and the bank active signal BACT. When the refresh signal REF is activated and the bank active signal BACT is deactivated, the control signal generator 300 activates the enable signal CSEN and deactivates the enable bar signal CSENB, and outputs it.

A detailed circuit configuration of the plurality of word line drivers 100 to 130 and the plurality of connection controllers 200 and 210 described above will be described as follows.

The word line driving unit 100 includes a driving control unit 101 and a driving unit 102 . Here, the driving control unit 101 includes a NAND gate ND1 and a NOR gate NOR1. The NAND gate ND1 performs a NAND operation on the enable bar signal CSENB and the word line enable signal WLOEN. Then, the NOR gate NOR1 performs NOR operations on the word line enable signal WLOEN and the enable signal CSEN. In addition, the driving unit 102 includes a PMOS transistor P1 and an NMOS transistor N1 connected in series between a power supply voltage terminal and a ground voltage terminal. The output of the NAND gate ND1 is applied through the gate terminal of the PMOS transistor P1, and the output of the NOR gate NOR1 is applied through the gate terminal of the NMOS transistor N1. In addition, a common drain terminal of the PMOS transistor P1 and the NMOS transistor N1 is connected to the word line WL0.

In addition, the word line driving unit 110 includes a driving control unit 111 and a driving unit 112 . Here, the driving control unit 111 includes a NAND gate ND2 and a NOR gate NOR2. The NAND gate ND2 performs a NAND operation on the enable bar signal CSENB and the word line enable signal WL1EN. Then, the NOR gate NOR2 performs a NOR operation on the word line enable signal WL1EN and the enable signal CSEN. In addition, the driver 112 includes a PMOS transistor P2 and an NMOS transistor N2 connected in series between a power supply voltage terminal and a ground voltage terminal. The output of the NAND gate ND2 is applied to the PMOS transistor P2 through the gate terminal, and the output of the NOR gate NOR2 is applied to the NMOS transistor N2 through the gate terminal. In addition, a common drain terminal of the PMOS transistor P2 and the NMOS transistor N2 is connected to the word line WL1.

In addition, the word line driving unit 120 includes a driving control unit 121 and a driving unit 122 . Here, the driving control unit 121 includes a NAND gate ND3 and a NOR gate NOR3. The NAND gate ND3 performs a NAND operation on the enable bar signal CSENB and the word line enable signal WL2EN. Then, the NOR gate NOR3 performs a NOR operation on the word line enable signal WL2EN and the enable signal CSEN. Also, the driving unit 122 includes a PMOS transistor P3 and an NMOS transistor N3 connected in series between a power voltage terminal and a ground voltage terminal. The output of the NAND gate ND3 is applied through the gate terminal of the PMOS transistor P3, and the output of the NOR gate NOR3 is applied through the gate terminal of the NMOS transistor N3. In addition, a common drain terminal of the PMOS transistor P3 and the NMOS transistor N3 is connected to the word line WL2.

The word line driving unit 130 includes a driving control unit 131 and a driving unit 132 . Here, the driving control unit 131 includes a NAND gate ND4 and a NOR gate NOR4 . The NAND gate ND4 performs a NAND operation on the enable bar signal CSENB and the word line enable signal WL3EN. Then, the NOR gate NOR4 performs a NOR operation on the word line enable signal WL3EN and the enable signal CSEN. Also, the driving unit 132 includes a PMOS transistor P4 and an NMOS transistor N4 connected in series between a power voltage terminal and a ground voltage terminal. The output of the NAND gate ND4 is applied to the PMOS transistor P4 through the gate terminal, and the output of the NOR gate NOR4 is applied to the NMOS transistor N4 through the gate terminal. In addition, a common drain terminal of the PMOS transistor P4 and the NMOS transistor N4 is connected to the word line WL3.

And, the connection control unit 200 includes a transmission gate T1. The transfer gate T1 selectively controls the connection of two word lines WL0 and WL1 in response to the enable signal CSEN and the enable bar signal CSENB. For example, when the enable signal CSEN is at a high level and the enable bar signal CSENB is at a low level, the transfer gate T1 is turned on to connect the two word lines WL0 and WL1 to each other. On the other hand, when the enable signal CSEN is at a low level and the enable bar signal CSENB is at a high level, the transfer gate T1 is turned off to cut off the connection between the two word lines WL0 and WL1.

In addition, the connection control unit 210 includes a transmission gate T2. The transfer gate T2 selectively controls the connection of the two word lines WL2 and WL3 in response to the enable signal CSEN and the enable bar signal CSENB. For example, when the enable signal CSEN is at a high level and the enable bar signal CSENB is at a low level, the transfer gate T2 is turned on to connect the two word lines WL2 and WL3 to each other. On the other hand, when the enable signal CSEN is at a low level and the enable bar signal CSENB is at a high level, the transfer gate T2 is turned off to cut off the connection between the two word lines WL2 and WL3.

FIG. 2 is a detailed circuit diagram of the control signal generator 300 of FIG. 1 .

The control signal generator 300 includes a plurality of inverters IV1 and IV2 and a NAND gate ND5. Here, the NAND gate ND5 performs a NAND operation on the refresh signal REF and the bank active signal BACT inverted by the inverter IV1 to output the enable bar signal CSENB. Then, the inverter IV2 inverts the enable bar signal CSENB to output the enable signal CSEN.

When the refresh signal REF is activated to a high level and the bank active signal BACT is deactivated to a low level during a refresh operation, the control signal generator 300 outputs the enable bar signal CSENB to a low level and sets the enable signal CSEN to a high level. print out When the enable signal CSEN is activated to a high level, the word line charge-sharing period is entered and the connection controllers 200 and 210 are turned on. Then, two adjacent word lines WL0 and WL1 and two adjacent word lines WL2 and WL3 are connected to each other so that a charge is shared between the word lines.

FIG. 3 is an operation waveform diagram of the semiconductor device according to the embodiment of FIG. 1 .

When the refresh mode is entered, the refresh signal REF is activated at a high level. Then, when the bank active signal BACT is activated to a high level, a plurality of word lines WL0 to WL3 are sequentially enabled.

When the bank active signal BACT is at the high level, the enable signal CSEN is inactivated at the low level. Then, the connection controllers 200 and 210 are turned off, and each of the word line drivers 100 to 130 operates in the normal mode. That is, the word lines WL0 to WL3 are selected one by one by the respective word line drivers 100 to 130 and are sequentially enabled with a predetermined interval.

In the timing diagram of FIG. 3 , the operation of the word line drivers 100 and 110 for controlling the two word lines WL0 and WL1 will be described as an example. Also, in the timing diagram of FIG. 3 , a case in which two active operations are performed to enable two adjacent word lines WL0 and WL1 during a refresh operation will be described as an example.

In a section in which the bank active signal BACT is first activated, the enable bar signal CSENB becomes high level and the enable signal CSEN becomes low level. Then, the transfer gates T1 and T2 are both turned off, and the word lines WL0 and WL1 are disconnected from each other.

And, when the word line enable signal WL0EN is at a high level, the output of the NAND gate ND1 is at a low level. Then, the PMOS transistor P1 is turned on, and the word line WL0 is enabled to a high level. In addition, when the word line enable signal WL0EN is at a high level, the output of the NOR gate NOR1 is at a low level, and the NMOS transistor N1 is turned off.

In addition, when the word line enable signal WL1EN is at a low level, the output of the NAND gate ND2 becomes a high level, and the PMOS transistor P2 is turned off. And, when the word line enable signal WL1EN is at the low level, the output of the NOR gate NOR1 becomes the high level. Then, the NMOS transistor N1 is turned on to disable the word line WL1 to a low level.

Thereafter, when the bank active signal BACT is disabled at the low level, the word line charge-sharing period A is entered. That is, the active and precharge operations of the first word line WL0 are performed, and the active and precharge operations of the next word line WL1 are performed after a predetermined time (tRP: Row Precharge Time). The word line charge-sharing period (A) represents this pre-charge period (tRP), and during the word line charge-sharing period (A), the charges of the two word lines WL0 and WL1 are shared, so that the charge of the word line WL0 is discharged and the word line The charge of WL1 is occupied.

In the word line charge-sharing section A in which the word lines WL0 and WL1 are precharged, the enable bar signal CSENB goes to a low level and the enable signal CSEN transitions to a high level. Then, the transfer gates T1 and T2 are both turned on, and the adjacent word lines WL0 and WL1 are connected to each other.

Then, when the enable bar signal CSENB becomes a low level and the enable signal CSEN becomes a high level, both the word line drivers 100 and 110 are in a floating state. That is, the outputs of the NAND gates ND1 and ND2 become high levels, and the outputs of the NOR gates NOR1 and NOR2 become low levels.

Then, regardless of the logic levels of the word line enable signals WL0EN and WL1EN, the drivers 102 and 112 are turned off so that the charge of the word lines WL0 and WL1 is shared. In the word line charge-sharing period A, the potential of the word line WL0 is transferred to the word line WL1. The potential of the word line WL0 gradually decreases and the potential of the word line WL1 gradually increases.

Subsequently, in a section in which the bank active signal BACT is activated for the second time, the enable bar signal CSENB becomes high level again and the enable signal CSEN becomes low level again. Then, the transfer gates T1 and T2 are both turned off, so that the word lines WL0 and WL1 are disconnected from each other, and the word line drivers 100 and 110 operate independently.

Meanwhile, FIG. 4 is a configuration diagram of a semiconductor device according to another embodiment of the present invention.

A semiconductor device according to another embodiment of the present invention includes a plurality of word line drivers 400 to 430 , a plurality of connection controllers 500 to 520 , and a control signal generator 600 .

The plurality of word line drivers 400 to 430 control whether the word line is activated during the refresh operation period. The word line driver 400 controls whether the word line WL0 is activated in response to the enable signal CSEN0, the enable bar signal CSENB0, and the word line enable signal WLOEN. The word line driver 410 controls whether the word line WL1 is activated in response to the enable signals CSEN0 and CSEN1, the enable bar signals CSENB0 and CSENB1, and the word line enable signal WL1EN. In addition, the word line driver 420 controls whether the word line WL2 is activated in response to the enable signals CSEN1 and CSEN2, the enable bar signals CSENB1 and CSENB2, and the word line enable signal WL2EN. The word line driver 430 controls whether the word line WL3 is activated in response to the enable signal CSEN2, the enable bar signal CSENB2, and the word line enable signal WL3EN.

Here, the enable bar signals CSEN0 to CSENB2 are signals opposite in phase to the enable signals CSEN0 to CSEN2. Also, in the embodiment of the present invention, the number of word lines WL0 to WL3 and the word line driver 400 to 430 has been described as an example, but this is only an example. ~430) is not limited in number.

In addition, the plurality of connection control units 500 to 520 connect two adjacent word lines during the 'word line charge-sharing period' so that charges can be shared between the two word lines. Here, the 'word line charge-sharing period' refers to a period from which two adjacent word lines are connected to each other until the first word line is precharged and the second word line is activated.

For example, when the enable signal CSEN0 is activated during the first 'word line charge-sharing period', the connection controller 500 connects two adjacent word lines WL0 and WL1 to each other. In addition, when the enable signal CSEN1 is activated during the second 'word line charge-sharing period', the connection control unit 510 connects two adjacent word lines WL1 and WL2 to each other. Also, when the enable signal CSEN2 is activated during the third 'word line charge-sharing period', the connection controller 520 connects two adjacent word lines WL2 and WL3 to each other.

In addition, the control signal generator 600 controls whether the enable signals CSEN0 to CSEN2 and the enable bar signals CSENB0 to CSENB2 are activated during the word line charge sharing period during the refresh operation. The control signal generator 600 controls whether the enable signals CSEN0 to CSEN2 and the enable bar signals CSENB0 to CSENB2 are activated in response to the refresh signal REF and the bank active signal BACT. When the refresh signal REF is activated and the bank active signal BACT is deactivated, the control signal generator 600 sequentially activates and outputs the enable signals CSEN0 to CSEN2.

A detailed circuit configuration of the plurality of word line drivers 400 to 430 and the plurality of connection controllers 500 to 520 described above will be described below.

The word line driving unit 400 includes a driving control unit 401 and a driving unit 402 . Here, the driving control unit 401 includes a NAND gate ND6 and a NOR gate NOR5 . The NAND gate ND6 performs a NAND operation on the enable bar signal CSENB0 and the word line enable signal WL0EN. Then, the NOR gate NOR5 performs a NOR operation on the word line enable signal WLOEN and the enable signal CSEN0. In addition, the driver 402 includes a PMOS transistor P5 and an NMOS transistor N5 connected in series between a power supply voltage terminal and a ground voltage terminal. The output of the NAND gate ND6 is applied through the gate terminal of the PMOS transistor P5, and the output of the NOR gate NOR5 is applied through the gate terminal of the NMOS transistor N5. In addition, a common drain terminal of the PMOS transistor P5 and the NMOS transistor N5 is connected to the word line WL0.

In addition, the word line driver 410 includes a driving controller 411 and a driver 412 . Here, the driving control unit 411 includes a NAND gate ND7 and a NOR gate NOR6 . The NAND gate ND7 performs a NAND operation on the enable bar signals CSENB0 and CSENB1 and the word line enable signal WL1EN. The NOR gate NOR6 performs NOR operations on the word line enable signal WL1EN and the enable signals CSEN0 and CSEN1. In addition, the driving unit 412 includes a PMOS transistor P6 and an NMOS transistor N6 connected in series between the power voltage terminal and the ground voltage terminal. The output of the NAND gate ND7 is applied through the gate terminal of the PMOS transistor P6, and the output of the NOR gate NOR6 is applied through the gate terminal of the NMOS transistor N6. In addition, a common drain terminal of the PMOS transistor P6 and the NMOS transistor N6 is connected to the word line WL1.

In addition, the word line driving unit 420 includes a driving control unit 421 and a driving unit 422 . Here, the driving control unit 421 includes a NAND gate ND8 and a NOR gate NOR7. The NAND gate ND8 performs a NAND operation on the enable bar signals CSENB1 and CSENB2 and the word line enable signal WL2EN. The NOR gate NOR7 performs NOR operations on the word line enable signal WL2EN and the enable signals CSEN1 and CSEN2. In addition, the driving unit 422 includes a PMOS transistor P7 and an NMOS transistor N7 connected in series between the power voltage terminal and the ground voltage terminal. The output of the NAND gate ND8 is applied through the gate terminal of the PMOS transistor P7, and the output of the NOR gate NOR7 is applied through the gate terminal of the NMOS transistor N7. In addition, a common drain terminal of the PMOS transistor P7 and the NMOS transistor N7 is connected to the word line WL2.

The word line driving unit 430 includes a driving control unit 431 and a driving unit 432 . Here, the driving control unit 431 includes a NAND gate ND9 and a NOR gate NOR8. The NAND gate ND9 performs a NAND operation on the enable bar signal CSENB2 and the word line enable signal WL3EN. And, the NOR gate NOR8 performs NOR operations on the word line enable signal WL3EN and the enable signal CSEN2. Also, the driving unit 432 includes a PMOS transistor P8 and an NMOS transistor N8 connected in series between a power voltage terminal and a ground voltage terminal. The output of the NAND gate ND9 is applied through the gate terminal of the PMOS transistor P8, and the output of the NOR gate NOR8 is applied through the gate terminal of the NMOS transistor N8. In addition, a common drain terminal of the PMOS transistor P8 and the NMOS transistor N8 is connected to the word line WL3.

And, the connection control unit 500 includes a transmission gate T3. The transfer gate T3 selectively controls the connection of two word lines WL0 and WL1 in response to the enable signal CSEN0 and the enable bar signal CSENB0. For example, when the enable signal CSEN0 is at a high level and the enable bar signal CSENB0 is at a low level, the transfer gate T3 is turned on to connect the two word lines WL0 and WL1 to each other. On the other hand, when the enable signal CSEN0 is at a low level and the enable bar signal CSENB0 is at a high level, the transfer gate T3 is turned off to cut off the connection between the two word lines WL0 and WL1.

In addition, the connection control unit 510 includes a transmission gate T4. The transfer gate T4 selectively controls the connection of the two word lines WL1 and WL2 in response to the enable signal CSEN1 and the enable bar signal CSENB1. For example, when the enable signal CSEN1 is at a high level and the enable bar signal CSENB1 is at a low level, the transfer gate T4 is turned on to connect the two word lines WL1 and WL2 to each other. On the other hand, when the enable signal CSEN1 is at a low level and the enable bar signal CSENB1 is at a high level, the transfer gate T4 is turned off to cut off the connection between the two word lines WL1 and WL2.

In addition, the connection control unit 520 includes a transmission gate T5. The transfer gate T5 selectively controls the connection of two word lines WL2 and WL3 in response to the enable signal CSEN2 and the enable bar signal CSENB2. For example, when the enable signal CSEN2 is at a high level and the enable bar signal CSENB2 is at a low level, the transfer gate T5 is turned on to connect the two word lines WL2 and WL3 to each other. On the other hand, when the enable signal CSEN2 is at a low level and the enable bar signal CSENB2 is at a high level, the transfer gate T5 is turned off to cut off the connection between the two word lines WL2 and WL3.

FIG. 5 is a detailed circuit diagram of the control signal generator 600 of FIG. 4 .

The control signal generation unit 600 includes a combination unit 610 , a counting unit 620 , and an enable signal control unit 630 .

Here, the combination unit 610 selectively activates the enable bar signal CSENB in response to the refresh signal REF and the bank active signal BACT. The combination unit 610 includes a plurality of inverters IV3 and IV4 and a NAND gate ND10.

Here, the NAND gate ND10 performs a NAND operation on the refresh signal REF and the bank active signal BACT inverted by the inverter IV3. Then, the inverter IV4 inverts the output of the NAND gate ND10 to output the enable signal CSEN. The combination unit 610 outputs the enable signal CSEN to a high level when the refresh signal REF is activated to a high level and the bank active signal BACT is deactivated to a low level during a refresh operation.

Then, the counting unit 620 counts the enable signal CSEN to sequentially activate the counting signals CNT<0> and CNT<1>. Here, the counting unit 620 may sequentially output the counting signals CNT<0> and CNT<1> by increasing the 2-bit signals to “00”, “01”, “10”, and “11”.

The counting unit 620 includes a plurality of counters CNT1 and CNT2 and an inverter IV5. The counter CNT1 counts the inverted signal of the enable signal CSEN and outputs a counting signal CNT<0>. Then, the counter CNT2 counts the counting signal CNT<0> and outputs the counting signal CNT<1>. Also, the counters CNT1 and CNT2 are reset by the refresh signal REF. For example, when the refresh signal REF becomes low level, the reset signal RESET is activated to initialize counters CNT1 and CNT2.

In addition, the enable signal control unit 630 selectively activates the enable signals CSEN0 to CSEN2 and the enable bar signals CSENB0 to CSENB2 in response to the enable signal CSEN and the counting signals CNT<0> and CNT<1>. The enable signal control unit 630 includes a plurality of NOR gates NOR9 to NOR11, a plurality of AND gates AND1 to AND3, and a plurality of inverters IV6 to IV8.

Here, the enable signal control unit 630 changes the counting signals CNT<0> and CNT<1> input to the plurality of NOR gates NOR9 to NOR11 into “00”, “01”, “10”, and “11”. They may be input sequentially. The enable signal control unit 630 sequentially activates the enable signals CSEN0 to CSEN2 according to changes in the counting signals CNT<0> and CNT<1>.

The NOR gate NOR9 performs NOR operations on the counting signals CNT<0> and CNT<1>. The AND gate AND1 outputs an enable signal CSEN0 by performing an AND operation on the outputs of the enable signal CSEN and the NOR gate NOR9. The inverter IV6 inverts the enable signal CSEN0 to output the enable bar signal CSENB0.

The NOR gate NOR10 performs NOR operation on the inverted signal of the counting signal CNT<0> and the counting signal CNT<1>. The AND gate AND2 outputs an enable signal CSEN1 by performing an AND operation on the outputs of the enable signal CSEN and the NOR gate NOR10. The inverter IV7 inverts the enable signal CSEN1 to output the enable bar signal CSENB1.

The NOR gate NOR11 performs NOR operation on the inverted signal of the counting signal CNT<0> and the counting signal CNT<1>. Then, the AND gate AND3 performs an AND operation on the output of the enable signal CSEN and the NOR gate NOR11 to output the enable signal CSEN2. The inverter IV8 inverts the enable signal CSEN2 to output the enable bar signal CSENB2.

6 is an operation waveform diagram of the semiconductor device according to the embodiment of FIG. 4 .

When the refresh mode is entered, the refresh signal REF is activated at a high level. Then, when the bank active signal BACT is activated to a high level, a plurality of word lines WL0 to WL3 are sequentially enabled.

When the bank active signal BACT is at the high level, the enable signal CSEN is inactivated at the low level. Then, the enable signal control unit 630 outputs the enable signal CSEN and the enable signals CSEN0 to CSEN2 at a low level, and outputs the enable bar signals CSENB0 to CSENB2 at a high level.

Accordingly, the connection controllers 500 to 520 are turned off, and each word line driver 400 to 430 operates in the normal mode. That is, the word lines WL0 to WL3 are selected one by one by the respective word line drivers 400 to 430 and are sequentially enabled with a predetermined interval.

In the timing diagram of FIG. 6 , the operation of the word line drivers 400 to 430 controlling the four word lines WL0 to WL3 will be described as an example. Also, in the timing diagram of FIG. 6 , a case in which four active operations are performed to enable two adjacent word lines during a refresh operation will be described as an example.

In a section in which the bank active signal BACT is first activated, the enable signal CSEN is at a low level. When the enable signal CSEN is at a low level, the counting signal CNT<1:0> of the counting unit 620 becomes a 2-bit signal “00 (expressed in decimal 1)”. Then, the enable signal control unit 630 outputs the enable bar signals CSENB0 to CSENB2 at a high level and outputs the enable signals CSEN0 to CSEN2 at a low level. Then, the transfer gates T3 to T5 are all turned off, and the connection between the word lines WL0 to WL3 is cut off from each other.

And, when the word line enable signal WL0EN is at a high level, the output of the NAND gate ND6 is at a low level. Then, the PMOS transistor P5 is turned on to enable the word line WL0 to a high level. In addition, when the word line enable signal WL0EN is at a high level, the output of the NOR gate NOR5 is at a low level, and the NMOS transistor N5 is turned off.

In addition, when the word line enable signals WL1EN to WL3EN are at a low level, the output of the remaining word line drivers 410 to 430 becomes a low level, so that the remaining word lines WL1 to WL3 are disabled to a low level.

Thereafter, when the bank active signal BACT is disabled to the low level, the first "word line charge sharing period B1" is entered. During the first "word line charge-sharing period B1", the charges of the two word lines WL0 and WL1 are shared, so that the charge of the word line WL0 is discharged and the charge of the word line WL1 is charged.

In the word line charge-sharing period B1 in which the word lines WL0 and WL1 are precharged, the enable signal CSEN is at a high level. Then, the enable bar signal CSEN0 goes to the low level and the enable signal CSEN0 transitions to the high level. Then, the transfer gate T3 is turned on and adjacent word lines WL0 and WL1 are connected to each other.

When the enable bar signal CSEN0 becomes a low level and the enable signal CSEN0 becomes a high level, both the word line drivers 400 and 410 are in a floating state. Then, the driving units 402 and 412 are turned off regardless of the logic levels of the word line enable signals WL0EN and WL1EN, so that the charge of the word lines WL0 and WL1 is shared. In the word line charge-sharing period B1, the potential of the word line WL0 is transferred to the word line WL1. The potential of the word line WL0 gradually decreases and the potential of the word line WL1 gradually increases.

In the word line charge-sharing period B1, the connection controllers 510 and 520 are turned off. In addition, since the word line enable signals WL2EN and WL3EN are at a low level, the word lines WL2 and WL3 are maintained in a disabled state.

Thereafter, in a section in which the bank active signal BACT is activated for the second time, the enable signal CSEN becomes the low level again. When the enable signal CSEN is at a low level, the counting signal CNT<1:0> of the counting unit 620 becomes a 2-bit signal “01 (expressed as decimal 1)”. Then, the enable bar signal CSEN0 becomes the high level again, and the enable signal CSEN0 becomes the low level again. Then, the transfer gate T3 is turned off, the word lines WL0 and WL1 are disconnected from each other, and the word line drivers 400 and 410 operate independently.

Similarly, when the bank active signal BACT is disabled for the second time, the second "word line charge sharing period B2" is entered. Then, the enable bar signal CSENB1 becomes low level and the enable signal CSEN1 becomes high level. During the second "word line charge-sharing period B2", the charges of the two word lines WL1 and WL2 are shared, so that the charge of the word line WL1 is discharged and the charge of the word line WL2 is charged.

Thereafter, in a section in which the bank active signal BACT is activated for the third time, the enable signal CSEN becomes the low level again. When the enable signal CSEN is at a low level, the counting signal CNT<1:0> of the counting unit 620 becomes a 2-bit signal "10 (expressed as a decimal number 2)". Then, the enable bar signal CSENB1 becomes high level again, and the enable signal CSEN1 becomes low level again. Then, the transfer gate T4 is turned off, the word lines WL1 and WL2 are disconnected from each other, and the word line drivers 410 and 420 operate independently.

Next, when the bank active signal BACT is disabled for the third time, the third "word line charge sharing period B3" is entered. During the third "word line charge-sharing period B3", the charges of the two word lines WL2 and WL3 are shared, so that the charge of the word line WL2 is discharged and the charge of the word line WL3 is charged.

Thereafter, in a section in which the bank active signal BACT is activated for the fourth time, the enable signal CSEN becomes the low level again. When the enable signal CSEN is at a low level, the counting signal CNT<1:0> of the counting unit 620 becomes a 2-bit signal “11 (expressed as a decimal number 3)”. Then, the enable bar signal CSENB2 becomes the high level again, and the enable signal CSEN2 becomes the low level again. Then, the transfer gate T5 is turned off, the word lines WL2 and WL3 are disconnected from each other, and the word line drivers 420 and 430 operate independently.

Subsequently, when both the refresh signal REF and the bank active signal BACT transition to the low level, the enable signal CSEN becomes the low level. Then, when the refresh signal REF reaches a low level, the counting unit 620 is reset and the counting signal CNT<1:0> becomes “00 (expressed as decimal 0)” again.

As described above, in the embodiment of the present invention, when the word lines WL0 to WL3 are sequentially enabled in the refresh mode, the charge-sharing operation between the two word lines is sequentially performed for each inactivation period of the bank active signal BACT. That is, in the section B1 in which the charge sharing operation between the word lines WL0 and WL1 is performed, the word line drivers 400 and 410 are floated. In addition, in the section B2 in which the charge sharing operation between the word lines WL1 and WL2 is performed, the word line drivers 410 and 420 are floated. In addition, the word line drivers 420 and 430 are floated in the section B3 in which the charge sharing operation between the word lines WL2 and WL3 is performed.

Those skilled in the art to which the present invention pertains should understand that the present invention can be embodied in other specific forms without changing the technical spirit or essential characteristics thereof, so the embodiments described above are illustrative in all respects and not restrictive. only do The scope of the present invention is indicated by the following claims rather than the detailed description, and all changes or modifications derived from the meaning and scope of the claims and their equivalent concepts should be construed as being included in the scope of the present invention. .

Claims (20)

a first word line driver for driving a first word line in response to an enable signal, an enable bar signal, and a first word line enable signal;
a second word line driver for driving a second word line in response to the enable signal, the enable bar signal, and a second word line enable signal; and
a connection control unit configured to connect the first word line and the second word line to each other in response to the enable signal and the enable bar signal in a word line charge sharing section;
The semiconductor device of claim 1 , wherein the first word line and the second word line are sequentially driven in the refresh mode. ◈Claim 2 was abandoned when paying the registration fee.◈ The method of claim 1, wherein the word line charge-sharing period is
The semiconductor device according to claim 1, wherein the period is from when the first word line is precharged to before the second word line is activated. ◈Claim 3 was abandoned when paying the registration fee.◈ The method of claim 1, wherein the first word line driver
a first driving control unit for combining the enable signal, the enable bar signal, and the first word line enable signal; and
and a first driver configured to drive the first word line in response to an output of the first driving controller. ◈Claim 4 was abandoned when paying the registration fee.◈ The method of claim 3, wherein the first driving control unit
a first logic gate performing a NAND operation on the enable bar signal and the first word line enable signal; and
and a second logic gate performing NOR operation on the enable signal and the first word line enable signal. ◈Claim 5 was abandoned when paying the registration fee.◈ 4. The method of claim 3, wherein the first driving unit
and a first PMOS transistor and a first NMOS transistor connected in series between a power supply voltage terminal and a ground voltage terminal, driven by an output of the first driving control unit, and having a common drain terminal connected to the first word line. ◈Claim 6 was abandoned when paying the registration fee.◈ The method of claim 1, wherein the second word line driver
a second driving control unit combining the enable signal, the enable bar signal, and the second word line enable signal;
and a second driving unit configured to drive the second word line in response to an output of the second driving control unit. ◈Claim 7 was abandoned at the time of payment of the registration fee.◈ The method of claim 6, wherein the second driving control unit
a third logic gate performing a NAND operation on the enable bar signal and the second word line enable signal; and
and a fourth logic gate performing NOR operation on the enable signal and the second word line enable signal. ◈Claim 8 was abandoned when paying the registration fee.◈ 7. The method of claim 6, wherein the second driving unit
and a second PMOS transistor and a second NMOS transistor connected in series between a power supply voltage terminal and a ground voltage terminal, driven by the output of the second driving control unit, and having a common drain terminal connected to the second word line. ◈Claim 9 was abandoned at the time of payment of the registration fee.◈ According to claim 1, wherein the connection control unit
and a transfer gate connecting the first word line and the second word line to each other when the enable signal is activated to a high level and the enable bar signal is activated to a low level. ◈Claim 10 was abandoned when paying the registration fee.◈ The method of claim 1,
and a control signal generator configured to control whether the enable signal and the enable bar signal are activated during the word line charge sharing period in response to a refresh signal and a bank active signal. ◈Claim 11 was abandoned when paying the registration fee.◈ 11. The method of claim 10, wherein the control signal generator
and when the refresh signal is activated and the bank active signal is deactivated, the enable signal is activated and the enable bar signal is deactivated. ◈Claim 12 was abandoned when paying the registration fee.◈ 12. The method of claim 11, wherein in the word line charge sharing section
and when the refresh signal is activated and the bank active signal is deactivated, the enable signal is activated to discharge the first word line and occupy the second word line. a plurality of word line drivers selectively driving a plurality of word lines in response to a plurality of enable signals, a plurality of enable bar signals, and a plurality of word line enable signals;
a plurality of connection controllers for selectively connecting two word lines among the plurality of word lines in response to the plurality of enable signals and the plurality of enable bar signals in a word line charge-sharing period;
In the refresh mode, the plurality of word lines are sequentially driven. ◈Claim 14 was abandoned at the time of payment of the registration fee.◈ 14. The method of claim 13, wherein the plurality of word line drivers
a first word line driver for driving a first word line in response to a first enable signal, a first enable bar signal, and a first word line enable signal;
A second word line driver for driving a second word line in response to the first enable signal, the second enable signal, the first enable bar signal, the second enable bar signal, and the second word line enable signal ;
A third word line driver driving a third word line in response to the second enable signal, the third enable signal, the second enable bar signal, the third enable bar signal, and the third word line enable signal ; and
and a fourth word line driver configured to drive a fourth word line in response to the third enable signal, the third enable bar signal, and the fourth word line enable signal. ◈Claim 15 was abandoned when paying the registration fee.◈ 15. The method of claim 14,
When the first enable signal is activated, a first connection control unit among the plurality of connection control units is turned on to connect the first word line and the second word line, and the first word line driver and the second word line A semiconductor device, characterized in that the driving unit is floating. ◈Claim 16 was abandoned when paying the registration fee.◈ 15. The method of claim 14,
When the second enable signal is activated, a second connection control unit among the plurality of connection control units is turned on to connect the second word line and the third word line, and the second word line driver and the third word line A semiconductor device, characterized in that the driving unit is floating. ◈Claim 17 was abandoned when paying the registration fee.◈ 14. The method of claim 13,
and a control signal generator configured to sequentially activate the plurality of enable signals during the word line charge sharing period in response to a refresh signal and a bank active signal. ◈Claim 18 was abandoned when paying the registration fee.◈ 18. The method of claim 17, wherein the control signal generator
a combination unit outputting an enable signal by combining the refresh signal and the bank active signal;
a counting unit for counting the enable signal and outputting a plurality of counting signals; and
and an enable signal controller configured to sequentially activate the plurality of enable signals in response to the enable signal and the plurality of counting signals. ◈Claim 19 was abandoned at the time of payment of the registration fee.◈ 19. The method of claim 18, wherein the counting unit
and a plurality of counters for counting the enable signals to increase the values of the plurality of counting signals;
The plurality of counters are reset when the refresh signal is deactivated. ◈Claim 20 was abandoned when paying the registration fee.◈ The method of claim 18, wherein the enable signal control unit
When the plurality of counting signals are increased to 2-bit signals and the plurality of enable signals are sequentially activated, two word lines among the plurality of word lines are sequentially connected in the activation period of the plurality of enable signals. semiconductor device with

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