KR102335638B1 - Read out circuit and image sensor including the same - Google Patents

Abstract

The present invention provides an analog amplifier for integrating a sensing signal of a TDI cycle; a comparator for comparing the analog integral signal level integrated in the analog amplifier with a comparison level; an ADC for converting the analog integral signal into a digital code when the analog integral signal level exceeds the comparison level; a memory for storing the digital code; and a DAC block for reducing the level of the analog integral signal integrated in the analog amplifier by the level of the digital code stored in the memory.

Description

Read out circuit and image sensor including the same

The present invention relates to a readout circuit and an image sensor including the same.

In the method of implementing the image sensor, in terms of power efficiency and integration due to the compatibility of pixels and readout circuits, a lot of conversion from CCD image sensors to CMOS image sensors has recently been made. However, the CMOS image sensor has a disadvantage in that it is structurally difficult to integrate many signals and thus has a lower signal to noise ratio (SNR) characteristic compared to the CCD image sensor. In order to overcome this drawback, the CMOS image sensor can increase the SNR by overlappingly integrating signals having the same position information using the TDI (Time Delayed Integration) method.

A representative method for implementing TDI is an analog method that continuously stacks up analog signals using an analog amplifier to increase the SNR of the final signal, and converts the stacked analog signal into a digital code and synthesizes the converted digital code several times. There are digital methods that increase the SNR of the final signal.

A basic example of the analog TDI scheme is shown in FIG. 1( a ). In the case of the analog method, the analog signal is continuously integrated with the analog amplifier, and the finally integrated TDI analog signal is transferred to the ADC (Analog to Digital Converter) to convert it into a digital code. The operation of repeatedly integrating the signal does not need to convert the domain of the signal into another form (eg, analog to digital), and is determined only by the characteristics of the analog system, so it is faster than other systems that require additional blocks. integration is possible However, at this time, the maximum stackable analog signal is limited by the swing range of the amplifier. In order to increase the SNR, either increase the power level supplied to the analog stage to physically increase the swing range of the analog amplifier or increase the noise level. You have to design the level very low. However, in this case, power consumption is greatly increased, and a low noise and high speed analog system design level of a fairly high degree of difficulty is required. can

A basic example of a digital TDI scheme is shown in FIG. 1(b). In the case of the digital method, first, the analog signal is sampled and held by the analog amplifier, and the held signal is transferred to the ADC to convert it into a digital code. By repeating this operation, digital codes for the same position are calculated several times, and finally, all digital codes are summed into one to form one data. If TDI is performed in this way, the SNR value of the signal for the same location can be increased, so that a high-quality image that is relatively less affected by noise can be obtained. In addition, the operation of integrating in this way has the advantage that the SNR value can be very high because the total integration amount of the signal is not particularly restricted compared to the analog TDI system using an analog amplifier. However, since the corresponding system additionally requires an ADC conversion process that converts the signal domain from analog to digital during the integration process, the integration time is inevitably limited due to the ADC conversion time compared to the analog TDI system. Therefore, when the digital TDI method is used to configure a system requiring fast operation, a high-performance ADC design capability having a very high speed is inevitably required. In addition, since a high operating clock is also required to implement a very fast ADC, the advantage in terms of power efficiency is reduced.

It is an object of the present invention to combine the analog TDI operation method and the digital TDI operation method to obtain the advantage of the analog TDI method having a faster integration speed compared to the digital TDI method, and the digital TDI method in which the integration amount is not significantly restricted compared to the analog TDI method It is to provide a method capable of fast operation while obtaining a high SNR by utilizing the advantages of the TDI method.

The present invention provides an analog amplifier for integrating a sensing signal of a TDI cycle; a comparator for comparing the analog integral signal level integrated in the analog amplifier with a comparison level; an ADC for converting the analog integral signal into a digital code when the analog integral signal level exceeds the comparison level; a memory for storing the digital code; and a DAC block for reducing the level of the analog integral signal integrated in the analog amplifier by the level of the digital code stored in the memory.

The ADC may output a digital signal obtained by summing the analog integral signal of the analog amplifier and the digital code of the memory at the end of the TDI cycle.

The readout circuit includes a signal integration region including the analog lamp and a DAC region including the ADC, wherein the signal integration region includes: an injection capacitor connected to an input terminal of the analog amplifier and to which the sensing signal is applied; a storage capacitor connected between an input terminal and an output terminal of the analog amplifier; a first switch connected between an input terminal and an output terminal of the analog amplifier; a second switch connected between one electrode of the storage capacitor and an output terminal of the analog amplifier; A third switch connected to one electrode of the storage capacitor and to which a reset reference voltage is applied may be included.

In another aspect, the present invention, a sensor panel including a pixel; Provided is an image sensor including a readout circuit for receiving the sensing signal from the pixel.

The readout circuit of the present invention uses a hybrid TDI operation method in which an analog method and a digital method coexist, which maintains the fast operation speed of the analog TDI method and at the same time can take the advantage of the digital TDI method in which the amount of integration is not limited, A CMOS TDI structure having a high operating speed and a high dynamic range, which is difficult to obtain in a conventional circuit system, can be implemented.

As a measure to increase the SNR in the analog TDI circuit system, the size of the power rail can be configured to be small in order to widen the swing range of the analog amplifier, so it has the advantage of reducing power consumption and the analog to extremely reduce noise The design difficulty of the amplifier can be greatly reduced. Furthermore, since some digital codes are calculated in advance in the amplifier stage and transferred to the ADC, the amount of digital codes to be calculated by the actual ADC is reduced in the same resolution environment compared to the conventional system, thereby eliminating the need for a high-resolution ADC. There are design advantages.

Since a high-speed CMOS TDI system having a high SNR can be implemented, high-performance product development and market selection of high-performance devices are possible. In addition, since the design difficulty of the analog amplifier and the design difficulty of the ADC can also be reduced compared to the conventional system, a significant reduction in development cost that occurs when developing a new high-performance IP can be expected.

1 is a diagram of a conventional analog TDI scheme and a digital TDI scheme.
2 is a view for explaining a basic operation concept of a readout circuit of an image sensor according to an embodiment of the present invention;
3 is a block diagram schematically showing the configurations of a readout circuit according to an embodiment of the present invention.
4 is a flowchart illustrating an operation flow in a readout circuit according to an embodiment of the present invention;
5 is a timing diagram of signals driving a readout circuit according to an embodiment of the present invention;
6 is a diagram illustrating the configuration and operation of a general cyclic ADC including a 1-bit DAC according to an embodiment of the present invention.
7 is a diagram comparing two cyclic ADCs using a 1-bit DAC and a 1.5-bit DAC according to an embodiment of the present invention.
8 is a diagram illustrating an example of operation of a readout circuit in which a digital TDI method and an analog TDI method are integrated and a cyclic ADC using a 1.5-bit DAC is included according to an embodiment of the present invention.
9 is a diagram showing an example of the structure of a readout circuit according to an embodiment of the present invention.
Fig. 10 is a diagram showing an example of a circuit structure of an analog amplifier used in the amplifier stage and the cyclic ADC stage of Fig. 9;
11 is a diagram illustrating a simulation operation waveform for an operation of an amplifier stage according to an embodiment of the present invention.

Hereinafter, embodiments of the present invention will be described in detail.

2 is a diagram for explaining a basic operating concept of a readout circuit of an image sensor according to an embodiment of the present invention.

Referring to FIG. 2 , an image sensor according to an embodiment of the present invention includes a sensor panel in which a plurality of pixels are arranged in a matrix form, and a readout for reading out an analog signal (or a sensing signal) sensed by the pixels. circuit may be included.

In an embodiment of the present invention, the integration method of the readout circuit is an analog method, and integration may be performed through an analog amplifier. As the TDI cycle progresses while maintaining the analog integral method, the integral value by the analog method gradually increases.

With respect to the integral signal, which is gradually increased as the TDI operation increases, it may be detected whether a comparison level has been exceeded by a comparator before reaching the limit of the swing range of the analog amplifier AMP. When it is detected that the comparison level is exceeded, it can be replaced with a digital code (or extra digital code), and the analog signal is reduced as much as the digital code is replaced, and the analog amplifier (AMP) is integrated again in the analog TDI method. It is possible to secure an extra swing range that can be used.

In the case of performing the above operation, whenever it is detected that the signal accumulated in the analog amplifier (AMP) exceeds the comparison level of the comparator, the analog signal is replaced with a digital code and the analog signal is reduced by the numerical value of the replaced digital code, The digital code may be stored in the memory. After that, when the TDI cycle is all finished, the last analog signal contained in the last analog amplifier (AMP) is transferred to the ADC and can be converted into a digital code. In addition, the digital code converted through the ADC is combined with the digital code converted in the previous TDI operation to create a final output digital TDI signal.

As described above, the TDI operation is performed by the analog amplifier AMP, and when the integral signal exceeds the comparison level of the comparator, the analog signal may be converted into a digital code. In addition, due to the reduced analog signal converted to the digital code, there is a margin in the swing range of the analog amplifier AMP for integrating the signal, so that an environment for continuous integration may be provided. Therefore, the problem that the final signal integration amount is limited due to the limitation of the swing range of the analog amplifier, which is a problem of the conventional analog TDI method, can be solved.

On the other hand, the digital code that is detected and converted by the comparison level of the comparator may be premised on not being a high-resolution digital code of a resolution level that the readout circuit system can actually implement. full) There is an advantage that it takes a shorter time compared to the system resolution conversion time. In addition, there is a design advantage in that the performance of the ADC does not have to be at the resolution level required by the system because the digital code is already calculated before the signal integrated through the analog amplifier (AMP) is transferred to the ADC. In this method, one TDI operation speed is analog TDI operation speed + digital code output speed, and this speed corresponds to a very small time compared to the ADC conversion time to obtain full resolution digital data of the system. The problem that the operating speed of the system is limited by the ADC conversion time, which is the problem of , can be solved.

A block diagram of a readout circuit showing more specific circuit configurations for implementing the method of the present embodiment as described above is shown in FIG. 3 .

Referring to FIG. 3 , when the circuit configurations of the readout circuit are largely divided into two regions, a signal integration region (or signal integrator) for performing an analog TDI operation, and a digital code calculation There may be a DAC operation area (or DAC operation unit) for

Regarding the signal integration region, a charge coupled switched capacitor structure may be applied, and when a signal is input from a pixel, depending on the capacity ratio of the injection capacitor CIN and the storage capacitor CS A TDI integral signal may be output to an output terminal of the analog amplifier AMP. Here, the starting point of the TDI integration signal may be determined through the reset reference voltage V_RESET_REFERENCE.

The injection capacitor CIN may be configured such that one electrode is connected to an input terminal (eg, an inverting (-) input terminal) of the analog amplifier AMP, and the other electrode receives a pixel signal. In addition, the storage capacitor CS may be configured to be connected in parallel to the analog amplifier AMP. One electrode has an output terminal of the analog amplifier AMP and an electrical connection is switched on/off, and the other electrode is the analog amplifier AMP. It may be connected to an input terminal (eg, an inverted (-) input terminal).

Furthermore, a plurality of switches for controlling operations of the storage capacitor CS and the analog amplifier AMP may be provided. In this regard, for example, the first switch SW_RESET connected between the input terminal and the output terminal of the analog amplifier AMP and the storage capacitor CS and the analog amplifier AMP are connected in series to one electrode of the storage capacitor CS. .

Meanwhile, an amplifier reference voltage V_AMP_REFERENCE may be applied to, for example, a non-inverting (-) input terminal as an input terminal of the analog amplifier AMP.

Regarding the DAC operating region, a comparator CMP may be connected to an output terminal of the analog amplifier AMP to detect that the integrated signal output of the analog amplifier AMP exceeds its swing range. The comparator CMP may have a parallel connection relationship with the ADC. A comparator reference voltage V_CMP_REFERENCE may be applied to the comparator CMP.

A memory MEM for storing the digital code generated by the comparator CMP may be connected to a rear end of the comparator CMP. In addition, a DAC block may be connected to the rear end of the comparator CMP. Regarding the DAC block, the DAC block (BLOCK) is provided in order to reduce the converted digital code so that the TDI signal to be integrated and accumulated later on the output signal of the analog amplifier (AMP) does not exceed the swing range of the analog amplifier (AMP). may be, and it may be connected to an input terminal (eg, an inverting (-) input terminal) of the analog amplifier AMP. In contrast, the DAC block receives a digital code from the comparator (CMP) and outputs an analog signal that can reduce the output signal of the analog amplifier (AMP) by a corresponding level to the input terminal of the analog amplifier (AMP). have. A DAC reference voltage (V_DAC_REFERENCE) may be applied to the DAC block.

In the signal integration region to which the charge-coupled switch capacitor structure is applied, the TDI integration signal may be output to the output terminal of the analog amplifier AMP according to the ratio of the injection capacitor CIN to the storage capacitor CS. Here, in order to increase the signal level, the size (or capacity) of the injection capacitor CIN may be greater than the size (or capacity) of the storage capacitor CS. That is, the size of the storage capacitor CS may be smaller than the size of the injection capacitor CIN. On the other hand, the relative ratio of the two capacitors (CIN, CS) may be desirably designed to be quite sophisticated in order to integrate the TDI signal. In general, as the size of the capacitors increases, they become less sensitive to the reset noise of the analog amplifier and the rate of change in characteristics of the semiconductor process.

It is desirable that the analog amplifier (AMP) in the signal integration region to which the charge-coupled switch capacitor structure is applied has a sufficiently wide bandwidth for fast system operation and a sufficiently high DC gain for high accuracy. . In terms of fast operation speed, it is desirable for the analog amplifier (AMP) to have a wide bandwidth, but the noise formed inside the analog amplifier (AMP) and the noise applied from the outside are affected by the wider bandwidth of the analog amplifier (AMP). AMP), so it can provide an effect of reducing the SNR characteristic of the system. In addition, in a system requiring high accuracy, a very high DC gain is required, and in this case, it can be designed to obtain a gain of two or more stages in general. In this case, due to the wide bandwidth designed for high operating speed, the non-dominant pole of the high frequency stage can enter into the UGF (Unity Gain Feedback) of the analog amplifier (AMP), and the stability of the system is reduced. Therefore, in order to satisfy both high operating speed and high DC gain, it may be necessary to consider additional means to compensate for the stability problem.

For the comparator CMP and the comparator CMP used in the DAC operation region composed of the DAC block and the memory MEM, a latched type comparator may be used for a fast comparison operation. In addition, the digital code output according to the configuration method of the comparator CMP may be a value of 1 bit or more.

The comparison reference voltage (V_CMP_REFERENCE) applied to the comparator (CMP) is the reference point (or reference value) at which the analog signal accumulated in the analog amplifier (AMP) changes to a digital value, and the corresponding value is different depending on the comparator (CMP) configuration. It can consist of multiple values.

In the case of the DAC block used in the DAC operation area, it can receive the signal from the comparator (CMP) and reduce the analog signal integrated in the analog amplifier (AMP) by the level corresponding to the digital code. The DAC block may have a structure similar to that of the charge-coupled switch capacitor structure including the input capacitor CIN and the storage capacitor CS in the signal integration region. When the DAC operation is similar to the charge-coupled switch capacitor operation, the speed of the operation is determined by the operation speed of the analog amplifier (AMP), so it can be seen as almost the same as the analog TDI operation speed.

For the memory (MEM) used in the DAC operation area, it may serve to store the digital code generated by the comparator (CMP). The digital codes continuously generated according to the TDI operation are summed up and continuously updated in the memory (MEM), and when the TDI operation is finished, the final digital code stored in the memory (MEM) is summed with the final digital code generated after the ADC operation. to generate a final output digital code.

A flowchart showing an operation flow in the readout circuit according to an embodiment of the present invention is shown in FIG. 4 .

Referring to FIG. 4 , it is possible to check the flow during the signal integration operation and the operation flow during the DAC operation. This is explained below.

First, when the TDI operation is started, an analog signal may be input from the pixel through the injection capacitor CIN.

When a signal is input and an output of the analog amplifier AMP is generated, the comparator CMP can determine the level of the analog signal contained in the analog amplifier AMP.

Here, if the signal value of the output terminal of the analog amplifier AMP exceeds the comparison level of the comparator CMP (ie, greater than the comparison level), a digital code is generated and an analog signal corresponding to the digital code value is simultaneously generated. It is possible to reduce the output of the analog amplifier (AMP) by the level, and accordingly, it is possible to sufficiently secure the swing range of the analog amplifier (AMP) for the next incoming analog signal. The generated digital code may be stored in the memory MEM.

If the analog signal contained in the analog amplifier (AMP) does not exceed the comparison level of the comparator (CMP) (ie, it is below the comparison level), similarly to the general analog TDI operation, the TDI operation cycle is completed until the end of the TDI operation cycle. can be done repeatedly.

If the TDI cycle is finished, the sum of the final analog signal of the analog amplifier (AMP) and the digital codes stored in the memory (MEM) may be transferred to the ADC at once and converted into a final digital signal together.

A timing diagram for implementing the above operation flow and some operation waveforms according to the timing operation are shown in FIG. 5 .

Each code in FIG. 5 will be described as follows. 'Analog Amp Out' is an output signal of the output terminal of the analog amplifier AMP of FIG. 3 . 'SIG_OUTPUT' is an output signal of the output terminal of the pixel of FIG. 3 . Here, a case in which the pixel is configured with a 3T pixel structure is taken as an example, and an operation injected from the pixel means a rising operation that means resetting the pixel. 'SW_RESET', 'SW_CON', and 'SW_RESET_CAP' are switching signals for switches (first to third switches) of the same name of FIG. 3 , respectively. 'CLK_CMP_LATCH' is a clock applied to the latch type comparator (CMP) to operate the DAC, and 'SW_SIG_TO_ADC' is a clock to transfer the accumulated TDI data to the ADC after the TDI cycle is finished. The three reference voltages in FIG. 4 correspond to reference voltages of the same name shown in FIG. 3 . Numbers 1 to 6 provided in FIG. 4 indicate sections for each situation.

First, the operation of FIG. 5 for each situation will be described as follows.

(1) Section 1 is a step in which the analog amplifier AMP and the storage capacitor CS are reset. In this case, the analog amplifier AMP may be reset to the V_AMP_REFERENCE level, and the storage capacitor CS may be reset to the V_RESET_REFERENCE level. Here, it can be seen that the analog Amp Out is UGF (Unity Gain Feedback) by the reset operation, so the output is also V_AMP_REFERENCE.

(2) In section 2, an operation in which the analog amplifier AMP releases the reset operation, is fed back to the storage capacitor CS, and then a signal is injected is performed. First, the output potential of the analog amplifier (AMP), which was output at the V_AMP_REFERENCE level, moves to the V_RESET_REFERENCE level formed in the storage capacitor (CS) as the feedback is changed to the storage capacitor (CS). Immediately after that, as a signal is injected from the pixel, the potential of the Analog Amp Output may decrease by the input amount (in the case of an inverted output structure).

(3) Section 3 is a step in which the DAC operation is performed by comparing the signal of the output terminal of the analog amplifier (AMP) with V_CMP_REFERENCE applied to the latch type comparator (CMP). At the present stage, since the amount of signal of the analog amplifier (AMP) is formed at a level smaller than V_CMP_REFERENCE applied to the comparator (CMP), no digital code is generated, and the amount of analog signal of the analog amplifier (AMP) does not change. , it can be seen that the output signal is maintained without any special change.

(4) Section 4 is a step representing a situation in which feedback is formed back to the storage capacitor CS when the first TDI cycle passes and the second TDI cycle proceeds. Analog Amp Output, whose potential was formed as V_AMP_REFERENCE, is changed to the last potential stored in the storage capacitor (CS) in the previous cycle (ie, the potential at the end of the first TDI cycle). After that, the signal is injected again from the pixel, and as a result, the analog amp output decreases by the amount of the signal applied from the pixel stacked twice. Here, it can be seen that the signal has crossed the V_CMP_REFERENCE level.

(5) Section 5 shows a situation in which Analog Amp Output rises again due to DAC operation when CLK_CMP_LATCH is applied while Analog Amp Output exceeds V_CMP_REFERENCE. In this step, the analog signal accumulated in the Analog Amp Output node is increased by the value of the digital code output from the comparator (CMP), so that the analog signal value already replaced with the digital code value does not remain.

(6) Section 6 is a step in which the last TDI cycle ends and finally the analog signal accumulated in the analog amplifier (AMP) is transferred to the ADC. At this time, while digital codes generated in previous TDI cycles are also transferred to the ADC, analog signals and digital codes generated during TDI cycles are transferred to the ADC. Thereafter, the ADC receives the corresponding signals and performs ADC conversion.

6 is a diagram illustrating the configuration and operation of a general cyclic ADC including a 1-bit DAC. 6(a) shows a circuit block for configuring a cyclic ADC, and FIGS. 6(b) and 6(c) illustrate a process of converting an analog signal into a digital code while the cyclic ADC operates. .

First, for the circuit block shown in Fig. 6(a), an analog amplifier, a latch-type comparator, and a DAC block operated using the outputs of the latch-type comparator are used. In addition, if you look at the process of the cyclic ADC converting an analog signal into a digital signal, you can see that the sampled signal is compared through the comparison level of the comparator and the operation is changed bit by bit with a digital code, and this operation is a cyclic It can be seen that the operation is repeated until the cycle of ADC is completed.

Comparing with the similarity of the circuit configuration and operation shown in FIG. 6 , it can be seen that this ADC has significant similarity to the configuration and operation of the system of the embodiment of the present invention shown in FIG. 3 . Therefore, when considering the reusability and compatibility of the circuit, by applying the cyclic ADC to the ADC of FIG. 3 , it is possible to obtain an advantage in that the complexity to be considered in the design part is significantly reduced.

7 is a diagram comparing two cyclic ADCs using a 1-bit DAC and a 1.5-bit DAC with each other.

Referring to FIG. 7 , looking at the circuit configuration of the two cyclic ADCs shown in the diagram on the left, most of the circuit configurations are similar, but the DAC is changed from 1 bit to 1.5 bits, and the comparator used in the circuit configuration is 1 to 2 The difference is that it has grown into a dog. Unlike a cyclic ADC using a 1-bit DAC, a cyclic ADC using a 1.5-bit DAC increases the complexity of circuit configuration, but the comparison error due to the influence of the input offset of the comparator is significantly mitigated. It can be seen from the figure on the right of Fig. 7.

First, in the case of a cyclic ADC using a 1-bit DAC, it can be seen that only an offset of 1 LSB or less of the resolution that the comparator offset error is trying to obtain from the ADC is allowed. If the comparator input offset of 1LSB or more occurs, it may lead to signal loss while the cyclic ADC operates.

Next, note that in the case of a cyclic ADC using a 1.5-bit DAC, no signal loss occurs even if the comparator offset error allows an input offset error of the level of the offset of 1/4 x ADC range that the ADC is trying to achieve. Able to know. Since this allows an error level of 128LSB based on a 10-bit ADC, it can be seen that the design burden of the comparator is significantly reduced compared to a cyclic ADC using a 1-bit DAC.

Therefore, as the ADC shown in Fig. 3, a cyclic ADC using a 1.5-bit DAC can be used, and the structure is equally applied to the comparator and DAC shown in Fig. 3, so that the offset error of the comparator affects the system of this embodiment. The advantage of being able to eliminate the problem and at the same time alleviating the difficulty of designing a comparator can be used.

An integrated readout circuit system for all of the above-described operating techniques is schematically illustrated in FIG. 8 . 8 shows an operation example of a readout circuit in which a digital TDI method and an analog TDI method are integrated and a cyclic ADC using a 1.5-bit DAC is included.

By using a 1.5-bit DAC, 1.5-bit level data can be output whenever a digital code (extra digital code) is extracted. FIG. 8 also shows an example of code synthesis for how a digital code generated in an analog TDI method in which a digital method is integrated is combined with a digital code generated in a cyclic ADC. Looking at the operation, since a part of the final digital code to be finally obtained can be extracted and synthesized in advance, the actual resolution covered by the cyclic ADC can be smaller than the overall resolution of the readout circuit system, It can be seen that the more digital codes to extract, the more the ADC design difficulty can be further reduced. Also, since the proposed system adopts the digital TDI method over the analog TDI method, the value of the analog signals that can be accumulated is greatly increased, so it is possible to obtain an effect as if the swing range of the analog amplifier performing the analog TDI operation was increased. The increased swing range of the amplifier is not a physically increased swing range, so it can be expressed as a virtual swing range. Assuming that there is a virtual swing range, the noise level of the system remains the same, while the integrable signal increases significantly by the virtual swing range, so there is an advantage of finally obtaining a high SNR.

In implementing the circuit method presented in the embodiment, an example of a more specific circuit configuration including a switch and the like is shown in FIG. 9 . Referring to FIG. 9 , an analog amplifier, a DAC block, a latch-type comparator, and the like, which are key to various switch structures and operations for operation, may be provided in both the amplifier stage and the cyclic ADC stage.

Here, in the case of the cyclic ADC stage, the cyclic ADC structure using the existing 1.5-bit DAC may be configured substantially the same. On the other hand, the difference from the existing structure is that the circuit block required to construct a cyclic ADC using a 1.5-bit DAC is also used in the amplifier stage to perform analog TDI, thereby integrating the characteristics of digital TDI operation into the analog TDI operation circuit. (merge) to enable a hybrid configuration, and by borrowing the 1.5-bit DAC structure used in the cyclic ADC as it is, it is also possible to obtain the advantage of reducing the influence of the input offset of the latch-type comparator.

The difference between the amplifier stage and the cyclic ADC stage is that the amplifier stage may first have a capacitor array consisting of multiple TDI capacitors to distinguish also the positional data present at each TDI location. This is illustrated in FIG. 9 , and a capacitor array including a plurality of storage capacitors Cap1 to CapN arranged in parallel may be connected to the analog amplifier of the amplifier stage. The storage capacitors Cap1 to CapN may increase by the TDI stage to be configured.

An example of the circuit structure of the analog amplifier used in the amplifier stage and the cyclic ADC stage in the presented structure is shown in FIG. 10 .

In order to satisfy the performance of the current readout circuit system, DC gain of about 120dB or more may be required, and UGF performance of 5Mhz or more may be required. In order to satisfy this performance, an analog amplifier having a simple structure having a two-stage structure as shown in FIG. 10 may be used. In this regard, the first stage (Stage 1) may be configured in a folded cascode amplifier (folded cascode amp) structure having a general NMOS input, and the second stage (Stage2) is a general common source amplifier (common source amp) can be structured.

The characteristic of the amplifier is that an additional device that can greatly increase the UGF of the amplifier may be added depending on the value of the setup switch called 'SW_Boost'. The reason that this part is included is that in the case of gain boost or column binning, the loop UGF in consideration of capacitor feedback may not come out to the 5 MHz required by the system due to the rapidly increased injection capacitor. Therefore, in such a situation, there is a need to significantly increase the UGF, and thus corresponding switches may be provided as a device for compensating for such a situation. When the gain boost is disabled, the magnitude of the input tail current of the first stage Stage1 is halved, thereby reducing the input transconductance. And, since the Miller capacitor is greatly increased, as a result, the UGF of the system, which is determined by the input transconductance and the size of the Miller capacitor, is in a reduced state.

Conversely, when the gain boost is enabled, the input transconductance of the first stage Stage1 increases and the Miller capacitor decreases, so a higher UGF is formed, and the loop UGF is reduced due to the capacitor feedback. can alleviate

In order to verify the operation of the system presented above, a simulation operation waveform for the operation of the amplifier stage is shown in FIG. 11 . In FIG. 11 , simulation operation for a case where a small signal is received while operating only in the analog TDI method (upper drawing), and when a sufficiently large signal is received while the operation of the digital TDI method is performed during the analog TDI method (lower drawing) The waveform is shown.

In case of operating only in the analog TDI method, since the DAC does not operate separately, every time a signal is received, it is accumulated in the analog amplifier.

Conversely, when operating in the analog TDI method and the digital TDI method, when a large signal is received, the swing range of the analog amplifier is replaced with a digital code before being saturated with the applied analog signal, so the applied signals are It can be seen that it is continuously stacked without being limited by the swing range of Through this, it can be seen that the readout circuit presented in this embodiment operates at a high speed, but the integral amount of the signal is not limited by the swing range of the analog amplifier.

As described above, the readout circuit of the present embodiment maintains the fast operation speed of the analog TDI method and at the same time can take the advantage of the digital TDI method in which the amount of integration is not limited. A hybrid TDI operation in which the analog method and the digital method coexist. By using the method, a CMOS TDI structure having a high operating speed and a high dynamic range, which is difficult to obtain in a conventional circuit system, can be implemented.

As a measure to increase the SNR in the analog TDI circuit system, the size of the power rail can be configured to be small in order to widen the swing range of the analog amplifier, so it has the advantage of reducing power consumption and the analog to extremely reduce noise The design difficulty of the amplifier can be greatly reduced. Furthermore, since some digital codes are calculated in advance in the amplifier stage and transferred to the ADC, the amount of digital codes to be calculated by the actual ADC is reduced in the same resolution environment compared to the conventional system, thereby eliminating the need for a high-resolution ADC. There are design advantages.

Since a high-speed CMOS TDI system having a high SNR can be implemented, high-performance product development and market selection of high-performance devices are possible. In addition, since the design difficulty of the analog amplifier and the design difficulty of the ADC can also be reduced compared to the conventional system, a significant reduction in development cost that occurs when developing a new high-performance IP can be expected.

The above-described embodiment of the present invention is an example of the present invention, and free modifications are possible within the scope included in the spirit of the present invention. Accordingly, the present invention is intended to cover the modifications of the present invention provided they come within the scope of the appended claims and their equivalents.

Claims (5)

an analog amplifier for integrating the sensing signal of the TDI cycle;
a comparator for comparing the analog integral signal level integrated in the analog amplifier with a comparison level;
an ADC for converting the analog integral signal into a digital code when the analog integral signal level exceeds the comparison level;
a memory for storing the digital code;
a DAC block for reducing the level of the analog integral signal integrated in the analog amplifier by the level of the digital code stored in the memory;
an injection capacitor connected to the input terminal of the analog amplifier and to which the sensing signal is applied;
a storage capacitor connected between an input terminal and an output terminal of the analog amplifier;
a first switch connected between an input terminal and an output terminal of the analog amplifier;
a second switch connected between one electrode of the storage capacitor and an output terminal of the analog amplifier
A readout circuit comprising a.
According to claim 1,
The ADC outputs a digital signal obtained by summing the analog integral signal of the analog amplifier and the digital code of the memory at the end of the TDI cycle.
According to claim 1,
A third switch connected to one electrode of the storage capacitor and to which a reset reference voltage is applied
A readout circuit further comprising a.
a sensor panel including pixels;
The readout circuit of any one of claims 1 to 3 for receiving the sensing signal from the pixel
An image sensor comprising a. a pixel array for generating an analog signal by sensing incident light;
a first stage of simultaneously generating a digital code while performing a TDI operation for continuously integrating the analog signal, and performing a DAC corresponding to the digital code to simultaneously generate analog data and digital data at the end of the TDI operation;
A second stage comprising an analog-to-digital converter that simultaneously receives the analog data and the digital data output from the first stage and converts them into a final digital code
An image sensor comprising a.

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