KR102333845B1 - Method, apparatus, device and storage medium for generating chip-based computing functions - Google Patents

Abstract

According to an embodiment of the present invention, a method, an apparatus, a device, and a storage medium for generating a chip-based computing function are provided. The method for generating a computing function based on a chip includes: obtaining an input parameter value related to a computing function supported by the chip; determining at least one candidate computing function template corresponding to the computing function based on the input parameter value, wherein the candidate computing function template has a configurable parameter related to execution performance of the candidate computing function template, wherein the configurable parameter includes at least one with candidate values - ; and determining the target computing function template and target values of the configurable parameters of the target computing function template according to the input parameter values and the candidate values of the configurable parameters of the candidate computing function templates to implement the chip-based computing function. do. The above method greatly simplifies the difficulty of manually implementing the computing function template, since the design of the chip is dynamically adaptable to different application scenarios/computation scale, and can implement dynamic configuration of configurable parameters, and chip design, especially chip software development improve efficiency;

Description

METHODS, APPARATUS, DEVICE AND STORAGE MEDIUM FOR GENERATING CHIP-BASED COMPUTING FUNCTIONS

Embodiments of the present invention mainly relate to the field of chips, and more particularly, to a method, apparatus, apparatus, and computer-readable storage medium for generating a chip-based computing function.

Recently, artificial intelligence (AI), including deep learning technology, has already been widely used in various fields (eg, speech processing, image processing, natural language processing, video processing, automatic control, etc.), and people's lifestyles With the advancement of artificial intelligence technology, people's expectations for the level of artificial intelligence are increasing. The level of artificial intelligence mainly depends on the development of deep learning, and deep learning technology has very high demands on computing functions, but existing processors are difficult to satisfy the needs of deep learning due to limitations in performance, cost and power, etc. Therefore, to meet the needs of deep learning technology, the design of high-performance AI chips in which software and hardware are tightly coupled, such as graphics processing units (GPUs) and application specific integrated circuits (ASICs), for example, is a major issue to be solved at present. It is a task.

According to an exemplary embodiment of the present invention, a chip-based computing function generation solution is provided.

A first aspect of the present invention provides a method comprising: obtaining an input parameter value related to a computing function supported by a chip; determining at least one candidate computing function template corresponding to the computing function based on the input parameter value, wherein the candidate computing function template has a configurable parameter related to execution performance of the candidate computing function template, wherein the configurable parameter includes at least one with candidate values - ; and determining the target computing function template and target values of the configurable parameters of the target computing function template according to the input parameter values and the candidate values of the configurable parameters of the candidate computing function templates to implement the chip-based computing function. A method for generating a chip-based computing function is provided.

A first aspect of the present invention provides an input parameter value obtaining module for obtaining an input parameter value related to a computing function supported by a chip; A candidate computing function template determining module configured to determine at least one candidate computing function template corresponding to the computing function based on the input parameter value, wherein the candidate computing function template has configurable parameters related to execution performance of the candidate computing function template and is configurable The parameter has at least one candidate value - ; and a target computing function to determine a target computing function template and a target value of the configurable parameter of the target computing function template according to the input parameter value and the candidate value of the configurable parameter of the candidate computing function template to implement the chip-based computing function Provided is an apparatus for generating a chip-based computing function including a template determination module.

A third aspect of the present invention includes: one or a plurality of processors; and a storage device in which one or a plurality of programs are stored, wherein when the one or a plurality of programs are executed by one or a plurality of processors, the one or plurality of processors generates a chip-based computing function according to the first aspect of the present invention An electronic device for implementing a method is provided.

A fourth aspect of the present invention provides a computer-readable storage medium having a computer program stored thereon, wherein the computer program, when executed by a processor, implements the method for generating a chip-based computing function according to the first aspect of the present invention.

It should be understood that the content described in the content section of the present invention does not limit the key or important features of the embodiments of the present invention and the scope of the present invention. Other features of the present invention will be more readily understood from the following description.

The foregoing description and other features, advantages and aspects of various embodiments of the present invention will become more apparent with reference to the following detailed description in conjunction with the accompanying drawings. In the drawings, the same or similar drawing designations refer to the same or similar elements.
1 shows a schematic diagram of an exemplary environment of a chip-based computing function generation solution according to various embodiments of the present invention.
2 shows a flowchart of a method for generating a chip-based computing function according to some exemplary embodiments of the present invention.
3 shows an exemplary block diagram of an apparatus for generating a chip-based computing function according to an embodiment of the present invention.
4 illustrates a block diagram of a computing device that may implement various embodiments of the present invention.

An embodiment of the present invention will be described in more detail with reference to the accompanying drawings below. Although some embodiments of the present invention are shown in the drawings, it should be understood that the present invention may be embodied in various forms, and should not be construed as being limited to the embodiments described herein. and provided for complete understanding. It should be understood that the drawings and embodiments of the present invention serve as examples only, and are not intended to limit the protection scope of the present invention.

In the course of describing the embodiments of the present invention, the term "comprises" and similar terms should be understood as open-ended inclusions such as "including but not limited to". The term “based” is to be understood as “at least partially based”. The terms “one embodiment” or “the embodiment” should be understood as “at least one embodiment.” The terms “first”, “second”, etc. may refer to different or the same object. It may further include explicit and implicit definitions.

As used herein, the term "chip" refers to a carrier capable of implementing a predetermined function through software or hardware technology to be developed in the past or in the future. In some application scenarios, this includes, but is not limited to, “wafer blocks”, “wafers”, “bare chips”, “integrated circuits”, “monolithic devices”, “semiconductor devices”, “microelectronic devices”, etc. does not

As used herein, the term “operator” refers to a unit in a chip that implements a basic arithmetic algorithm or function that may be implemented by existing or to be developed software or hardware technology. Various basic operations on the chip such as convolution, various value operations, various vector operations, various matrix operations, and various character operations can be implemented through operators.

As used herein, the term “computing function” as used herein refers to a logical unit that implements any computation/operation/algorithm in a chip, which may be implemented by an individual operator or a plurality of operators. and a plurality of operators may be combined through a preset or dynamically designated logical relationship.

As mentioned above, providing a high-performance chip for deep learning technology is currently a definitive problem to be solved. Existing deep learning users mainly use deep learning frames such as tensorflow, caffe, mxnet, pytorch, paddlepaddle, etc., but to apply AI chips to the deep learning field, they must be integrated into the frame. It implements the operator and implements the basic operations on the chip through operators such as convolution, various value operations, various vector operations, various matrix operations, various character operations, etc. Implementation of one or more computing functions. The execution performance of various computing functions of the chip directly determines the performance of the AI chip.

Major AI chip manufacturers have developed corresponding AI chips, such as nvidia GPUs, google TPUs, BAI du Kunlun chips, etc., based on their respective frames. These AI chips have their own instruction sets, have their own programming frames, such as CUDA, OPENCL, for example, and can be programmed in a programming language (eg, C / C ++, C #, Python, etc.).

Each operator of the AI chip or the above computing function of the present invention can be implemented through a programming method, but the bottom layer chip frame is, for example, a block division method, various storage spaces (eg, registers, buffers, memory, shared memory, etc.) It has many configurable parameters including efficient use of , program scheduling (eg, thread scheduling, processor scheduling, etc.) In order to reasonably configure a large number of parameters, the developer must be very familiar with the bottom-layer chip architecture, but even if they are familiar, the development cycle required to construct a high-performance AI chip is very long, and the AI chip software development efficiency is particularly low. In addition, since the application scenario/computation scale is rich, it is difficult for a chip designed for a specific application scenario/computation scale to achieve optimal performance at different computational scales.

The inventors have noted that a possible solution to creating a chip-based computing function is to manually implement some general-purpose operator library and implement the configuration of the chip bottom layer parameters in the operator. As analyzed above, the difficulty of generating a chip-based computing function through these solutions is very high, and the efficiency is low, and it cannot be flexibly applied to various application scenarios/computation scales. Another possible chip design solution is to create primitives in a high-level language while at the same time encoding them in a manual way to implement some optimized operator templates. The solution for generating such semi-automated chip-based computing functions improves the efficiency of the chip design process, especially the chip software development, but this solution blocks the hardware at the bottom layer of the chip frame, so that the performance of the chip is pre-encoded by the optimized operator. Because it relies on templates, it is difficult to implement high-performance operators. In addition, the inventor has also noted that chip-based computing functions can be created through a fully automated solution. In other words, polyhedral compilation technology is mainly used to generate the code completely by the compiler. In this solution, the user only describes the algorithm and the compiler automatically generates the code. This solution realizes high efficiency of chip software development, but completely blocks the hardware of the bottom layer of the chip frame, thereby reducing the possibility of implementing high-performance code.

According to an embodiment of the present invention, a chip-based computing function generation solution is proposed. In the above solution, the computing function supported by each chip corresponds to at least one candidate computing function template, the candidate computing function template having a configurable parameter related to the execution performance of the candidate computing function template, the configurable parameter has at least one candidate value. After obtaining the input parameter value of the computing function, at least one candidate computing function template is determined according to the input parameter value, and according to the input parameter value and the candidate value of the configurable parameter of the candidate computing function template, the target computing function template and the target A target value of a configurable parameter of the computing function template may be determined, and a chip-based computing function may be generated. In this way, the computing function template provides the configurable parameters inside the chip to the upper caller, and the upper caller dynamically configures the values of the configurable parameters according to the input parameter values. Dynamically adaptable to application scenarios/computation scale.

Further, in order to better implement the high-performance operator or the computing function of the present invention, according to an embodiment of the present invention, a target according to an input parameter value and a candidate value of a configurable parameter of a candidate computing function template using a machine learning method Determine target values of configurable parameters of the computing function template and the target computing function template. In this way, the dynamic configuration of configurable parameters is realized, while the difficulty of implementing the computing function template in a manual way and configuring the chip bottom layer parameters is greatly reduced. In addition, the machine learning method can efficiently complete the chip design even when the search range is very wide.

In addition, in order to better estimate the execution performance of the candidate computing function template, just-in-time (JIT) compilation is applied and tested to obtain execution performance. In this way, since code is generated at execution time rather than compilation time, the efficiency of the chip design process, especially chip software development, is improved, while the high-performance chip-based computing function generation is ensured.

Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. It is to be understood that the present invention is for illustrative purposes only and is not intended to limit the present invention in any way. Some exemplary embodiments of the present invention exemplify a computing function including a single basic function (ie, the function of one operator), while the computing function of the present invention includes a plurality of operator combinations for implementing the multiple operator functions. You have to understand that you can.

1 depicts a schematic diagram of an exemplary environment 100 in which various embodiments of the present invention may be implemented. In the example environment 100 , the computing device 130 may receive one or more input parameter values 110 - 1 , 110 - 2 to 110 -N related to a computing function. For convenience of description, the plurality of input parameter values 110 - 1 , 110 - 2 to 110 -N may be collectively referred to as an input parameter value 110 . In some demonstrative embodiments, the input parameter value 110 may be of any type related to a computing function. For example, for a computing function for vector multiplication, the input parameter value 110 may be the length value of two vectors describing the vector multiplication implementation, such as "100" and "100". In some demonstrative embodiments, the input parameter value 110 may be transmitted to the computing device 130 through wired communication or wireless communication. In some demonstrative embodiments, computing device 130 may also be input by a user through an input device coupled to computing device 130 (including but not limited to a mouse, keyboard, touch pen, touch screen, etc.) may receive the input parameter value 110 .

As shown in FIG. 1 , the computing device 130 may also obtain one or a plurality of candidate computing function templates 120 - 1 , 120 - 2 to 120 -M for the computing function. For convenience of description, the plurality of candidate computing function templates 120 - 1 , 120 - 2 to 120 -M may be collectively referred to as candidate computing function templates 120 .

In some demonstrative embodiments, computing device 130 is a candidate computing function of a computing function from a candidate computing function template database/memory located within computing device 130 or candidate computing function template database/memory located external to computing device 130 . A template 120 may be obtained. For example, in the case of a computing function for vector multiplication, the candidate computing function template 120 - 1 shown in FIG. 1 may be a computing function template implementing vector multiplication, and its configurable parameters are segments when executing vector multiplication. size, the candidate value of the segment size may be [3, 4, 5], and the other candidate computing function template 120-2 may be another computing function template implementing vector multiplication, and its configurable The parameter may be the number of processors called when executing vector multiplication, and a candidate value of the number of callable processors may be [1, 2, 4].

Computing device 130, based on the received input parameter value 110 and the obtained candidate computing function template 120, the target computing function template 140 for the input parameter value 110 and the target computing function template ( 140) may determine the target value of the configurable parameter. For example, in the example of FIG. 1 , computing device 130 uses a solution generating chip-based computing function of the present invention to input parameter values 110 "100, in the case of a computing function for vector multiplication, Based on this specified application scenario/computation scale of 100", the target computing function template 140 and target values of configurable parameters corresponding to the target computing function template 140 are determined. For example, it is determined that the candidate computing function template 120 - 1 is the target computing function template 140 , and at the same time that the segment size is “4” when vector multiplication is performed. These illustrated input parameter values, candidate computing function templates, configurable parameters, and candidate values of configurable parameters are provided as examples only, and the values of input parameter values, candidate computing function templates, configurable parameters, and configurable parameters are It should be understood that this may vary from case to case. The scope of the present invention is not limited thereto.

Hereinafter, a process of generating a chip-based computing function according to the present invention will be described in more detail with reference to FIG. 2 . 2 is a flowchart of a chip-based computing function generation process 200 according to some exemplary embodiments of the present invention, and the process 200 may be implemented by the computing device 130 of FIG. 1 . For ease of discussion, the process 200 will be described with reference to FIG. 1 .

At block 210 , the computing device 130 obtains an input parameter value 110 associated with a computing function supported by the chip. Specifically, a chip can support many computing functions. In a non-limiting exemplary embodiment of the present invention, the computing functions are the basic computing functions of basic operations (eg, convolution, various value operations, various character operations, various matrix operations, various vector operations, encryption, decoding, etc.). to implement According to different computing functions, the input parameter values 110 may be one or plural. In addition, the input parameter value 110 may be obtained in any manner including, but not limited to, a user input method or a method of reading a script/profile/command file.

In some exemplary embodiments of the present invention, the input parameter value 110 may be associated with an application scenario/computation scale. Specifically, the input parameter value 110 is, for example, when implementing a matrix operation, the input parameter value 110 identifies the size of the matrix, and when implementing the encryption operation, the input parameter value 110 is the value of the encryption algorithm. When the encryption length is identified, and a vector operation is implemented, the input parameter value 110 may identify the vector length, etc., and may identify the operation scale to be implemented by the computing function. It should be understood that the input parameter value 110 is provided by way of example only and that the value and type of the input parameter value 110 may vary in some other implementations. Accordingly, the type and/or value of the input parameter value 110 should not be limited to the above illustrated scope of the present invention and the input parameter value 110 may be of any suitable type and/or related to the application scenario/computation scale of the computing function. or a value.

In some exemplary embodiments of the present invention, the input parameter value 110 related to the application scenario/computation scale of the computing function is obtained by the computing device 130 , so that the chip-based computing function generating method can be used in various application scenarios/operations. It can be smoothly applied to scale and the generated computing function can be more suitably applied than the specified application scenario/computation scale.

In block 220 , the computing device 130 determines the candidate computing function template 120 corresponding to the computing function based on the input parameter value 110 obtained in block 210 . The computing device 130 may use the determined candidate computing function template 120 as a search space for performing a search for the target computing function template 140 , and there may be one or a plurality of candidate computing function templates 120 .

In some demonstrative embodiments of the present invention, each computing function may correspond to at least one candidate computing function template 120 , and each candidate computing function template 120 is execution of the candidate computing function template 120 . It may have at least one configurable parameter related to performance, for example, partition block size, segment size, number of threads, number of processors, register information, memory information, processor information, and the like. Each configurable parameter may have at least one candidate value, and in different application scenarios/computation scales, different candidate values of the configuration parameters may cause a designed chip to implement different execution performance. These configurable parameters are generally used as internal parameters of the computing function in the process of creating a chip-based computing function.

In some exemplary embodiments of the present invention, at least one candidate computing function template 120 for different computing function designs is implemented in a passive encoding manner, and candidate computing function templates 120 are implemented in a passive encoding manner to perform candidate computing. By making the execution logic of the function template 120 more precise, it is possible to some degree to ensure that the candidate computing function template 120 is retracted and better coupled with the chip bottom layer frame. However, it should be understood that the implementation of the candidate computing function template 120 is not limited to the manual encoding scheme shown in the present invention, and in some other exemplary embodiments, the candidate computing function template 120 may be implemented in an automatic or semi-automatic manner. do. In the solution for implementing the candidate computing function template 120 in such an automatic or semi-automatic manner, the existing optimized computing function template or the target computing function template 140/historical data/record of the configurable parameters, etc. may be referenced or combined. have.

In some exemplary embodiments of the present invention, the candidate computing function template 120 is implemented by applying a low-level programming language, such as a machine-oriented programming language. Additionally or alternatively, in some exemplary embodiments of the present invention, the process 200 performed by the computing device 130 is implemented by applying a low-level programming language, such as a machine-oriented programming language.

Compared to high-level programming languages, low-level programming languages are advantageous in better interacting with bottom-layer hardware, so as to better utilize the performance of hardware and ensure the implementation of high-performance chip computing functions.

In some demonstrative embodiments of the present invention, the plurality of candidate templates 120 are associated with different application scenarios/computation scales. For example, for the computing function of matrix multiplication, the candidate computing function template 120-1 implements good execution performance in the application scenario 1 (eg, the multiplied matrix scale is less than 50 * 50), and , the candidate computing function template 120 - 2 may implement good execution performance in the application scenario 2 (eg, the multiplied matrix scale is greater than 100 * 100). For computing functions with different functions, candidate computing function templates 120 for different application scenarios/computation scales may be designed and implemented, and may be designed and implemented to implement customization for different application scenarios/computation scales.

In some exemplary embodiments of the present invention, the number and value of the configurable parameters of the plurality of candidate computing function templates 120 may be arbitrary and may each have internal processing logic. Each candidate computing function template 120 provides complex, configurable parameters inside the chip according to a respective internal design to an upper caller (eg, computing device 130 ), so that the upper caller (eg, computing device 130) at least partially configurable parameters Based on , search, configuration, and testing can be performed on the candidate template 120 . In this way, while improving the flexibility of creating chip-based computing functions, configuring the internal parameters of the chip in a manual way reduces the difficulty of the chip design process, especially the chip software development, while at the same time, the rationality and accuracy of configuring the chip configurable parameters to improve

In some exemplary embodiments of the present invention, the candidate computing function template 120 also has a constraint, which constrains the scope of application of the candidate computing function template 120 . In some exemplary embodiments of the present invention, a constraint may be associated with an input parameter value 110 . For example, when performing a matrix operation, the constraint may be that the matrix size is smaller than 50 * 50.

Additionally or alternatively, in some demonstrative embodiments of the invention, the constraint may also define candidate values of the configurable parameters of the candidate computing function template 120 . For example, when a matrix operation is performed and a configurable parameter is a partition block size, the constraint may be that the value of the partition block size is [2, 4, 6].

Additionally or alternatively, in some exemplary embodiments of the present invention, a constraint may be associated with an input parameter value 110 and a configurable parameter at the same time. For example, the constraint may be a constraint such that a result of an operation in which the input parameter value 110 and configurable parameter values are input satisfies a preset condition.

The example of the constraint described in the present invention is merely exemplary and is not a limitation on the constraint, and that the constraint may be in any form or any value according to specific implementations of different candidate computing function templates 120 . have to understand

Additionally or alternatively, the computing device 130 determines at least one candidate computing function template 120 corresponding to the computing function based on the input parameter value 110 and the constraint condition. Since both the input parameter value 110 and/or the constraint may reflect a specified application scenario/computation scale to some extent, based on the input parameter value 110 and the constraint, at least one candidate computing corresponding to the computing function When the function template 120 is determined, the range of candidate computing function templates 120 to be searched is effectively reduced, thereby improving the efficiency of the chip design process, in particular, the chip software development.

With continued reference to FIG. 2 , in block 230 , the computing device 130 provides input parameter values 110 and candidate computing function templates 120 (block 220 ) to implement the chip-based computing function. The target computing function template 140 and target values of the configurable parameters of the target computing function template 140 are determined according to different candidate values of the configurable parameters of the determined candidate template 120).

In some exemplary embodiments of the present invention, the computing device 130 uses a machine learning method to perform target computing according to the input parameter value 110 and a plurality of different candidate values of the configurable parameters of the candidate computing function template 120 . The function template 140 and the target computing function template 140 determine target values of configurable parameters.

In some exemplary embodiments of the present invention, the computing device 130 estimates the execution performance of the candidate computing function template 120 at different candidate values of the configurable parameters of the candidate computing function template 120 , and the estimated Determine the target computing function template 140 and target values of configurable parameters of the target computing function template 140 based on the execution performance.

As a non-limiting illustrative example, computing device 130 generates one initial measurement set, wherein the initial measurement set includes input parameter values 110 and/or at least one candidate computing function template determined in block 220 . (120) configurable parameter values. For example, taking the case of multiplying two vectors as an example, the input parameter value 110 may be an identifier for a vector length, for example (50, 50), and specifying the multiplication of two vectors of length 50 Identify and calculate application scenarios. A configurable parameter of the candidate computing function template 120-1 is a vector segment length, a segment length candidate value is [2, 3, 4], and constraint that the operation vector length is less than 100; The configurable parameters of the candidate computing function template 120-2 are a vector segment length and a number of processors, wherein the candidate values of the segment length are [3, 4, 5], the candidate values of the number of processors are [3, 4], and , given that the operation vector length is less than 80 as a constraint, the initial value may be [50, 50, 3, 3], identifying and calculating the specified application scenario of multiplication of two vectors of length 50, the operation The segment length parameter applied at the time is 3, and the number of processors used is 3.

It should be understood that the selection of the initial measurement set value is merely exemplary and the number of parameters configurable in the initial measurement set value may be adjusted as necessary. In some demonstrative embodiments, this may include full configurable parameters related to all candidate computing function templates 120 determined at block 220 , and in some other demonstrative embodiments, determined at block 220 . It may include only some of the overall configurable parameters associated with all candidate computing function templates 120 . Similarly, the value of the initial measurement set may be reasonably set according to the candidate computing function template 120, and the present invention is not limited thereto. For example, as another example of the candidate computing function template 120 , for an application scenario where the vector lengths are each (1000, 1000), that is, each vector contains 1000 values, the candidate computing function template 120 is The configurable parameters are the number of computing cores activated (where the candidate value is m, where m is a positive integer), and the number of values produced by each computing core (the candidate value is n, where n is a positive integer). ), and the constraint may be m * n ≤ 1000.

The computing device 130 estimates the execution performance of the at least one candidate computing function template 120 in the initial measurement set according to the initial measurement set. Specifically, with continuing reference to the example of vector multiplication, the computing device 130 estimates the performance of each of the templates 120-1 and 120-2 in the initial measurement set [50, 50, 3, 3]. do.

The computing device 130 generates the next set of measurement parameters by a machine learning method. In some exemplary embodiments of the present invention, selection of a next measurement parameter set may be based on a measurement result of a previous measurement parameter set. In addition, the selection of the configurable number of parameters and values of the next set of measurement parameters is consistent with the initial set of measurement parameters and therefore is not repeated here further for the sake of brevity. It should be understood that this manipulation includes any existing or future development of machine learning techniques. By generating the next set of measurement parameters in a machine learning manner, more rational selection of the next set of measurement parameters eliminates the need to traverse the search space corresponding to all candidate values of configurable parameters, thereby increasing the efficiency of the method of generating chip-based computing functions. improve

Before the search is terminated, the steps of generating the next measurement parameter set and measuring the execution performance of the candidate computing function template 120 with respect to the generated measurement parameter set are repeatedly performed. Based on the measured execution performance, the target computing function template 140 and values of configurable parameters corresponding to the target computing function template 140 are determined. For example, if the measurement result indicates that the result with the best execution performance corresponds to the case where the candidate computing function template 120 - 1 has a segment length of 3 , the computing device 130 sets the candidate computing function template 120 - 1 ) is determined as the target template, and the candidate value 3 of the configurable parameter (ie, vector segment length) of the candidate computing function template 120 - 1 is determined as the target value.

In some exemplary embodiments of the present invention, the computing device 130 also determines the target computing function template 140 and target values of the configurable parameters of the target computing function template 140 at the same time as constraint conditions of the candidate computing function template Specifically, it can be expressed as follows. When the initial measurement parameter set and the next measurement parameter set are determined, and the initial measurement parameter set and the next measurement parameter set are applied to the candidate computing function template 120 , the constraint conditions of the candidate computing function template 120 are considered. In this way, the target computing function template 140 and the target values of the configurable parameters of the target computing function template 140 can be determined more efficiently and accurately.

Through the above method, the configurable parameters inside the chip are provided to the upper caller, which can be dynamically configured according to the test result of the execution performance during the chip software development process, thereby reducing the difficulty of configuring the configurable parameters inside the chip, It ensures the design of high-performance chips.

Additionally, in some exemplary embodiments of the present invention, the computing device 130 may perform a test by applying JIT compilation to obtain the execution performance of the candidate computing function template 120 . Specifically, the computing device 130 applies the generated measurement parameter to the candidate computing function template 120 to generate a final code in a JIT method and tests the performance of the candidate computing function template 120 . In this way, since code is generated at execution time rather than compilation time, the efficiency of the chip design process, especially chip software development, is improved, while the high-performance chip-based computing function generation is ensured.

In some exemplary embodiments of the present invention, the computing device 130 sets the target computing function template 140 and target values of configurable parameters of the target computing function template 140 to implement the chip-based computing function. confirm Specifically, the computing device 130 outputs the target computing function template 140 and codes corresponding to target values of the configurable parameters of the target computing function template 140 .

In addition, in order to further improve the efficiency of the chip software development process, the chip software development process may be controlled in various ways. In some exemplary embodiments of the present invention, the process of generating a chip-based computing function may be controlled by setting an execution performance threshold. Specifically, in the process of determining the target computing function template 140 and its target value, when the estimated execution performance is greater than the execution performance threshold, the candidate computing function template 120 and the candidate computing corresponding to the execution performance The candidate values of the configurable parameters of the function template 120 are determined as the target computing function template 140 and the target values of the configurable parameters of the target computing function template 140 .

The configuration of the execution performance threshold may be implemented in various ways, and in some exemplary embodiments of the present invention, the execution performance threshold may be input by a user. In some other demonstrative embodiments, the execution performance threshold may be a preconfigured default value and may also be stored in the computing device 130 in advance.

Additionally or alternatively, in some exemplary embodiments of the present invention, it is also possible to limit the process of generating a chip-based computing function within a preset time period. Specifically, the target computing function template 140 and target values of configurable parameters of the target computing function template 140 are determined within a preset time period.

The preset time zone may be configured in various ways. For example, it may be configured in a user input method, specifically, a method in which a user transmits a time zone related to a design time of a chip to the computing device 130 .

Additionally or alternatively, the preset time period may be determined by the input parameter value 110 . For example, the computing device 130 may set different preset time zones for different application scenarios/computation scales. Additionally or alternatively, the preset time zone may be configured by default in the computing device 130 .

Through the above method, it is possible to implement flexible control of the process of generating a chip-based computing function and to achieve a better balance between performance and efficiency.

Additionally, in some exemplary embodiments of the present invention, the computing device 130 determines the target computing function template 140 and the target value, and then sets the input parameter value 110 and the determined input parameter value 110 . and a corresponding relationship between a target computing function template 140 corresponding to , and a target value of a configurable parameter corresponding to the target computing function template 140 .

Additionally, in some demonstrative embodiments of the present invention, computing device 130 receives input parameter value 110 (as shown in block 210 ), and then searches for the input parameter value in an already stored correspondence. It is determined whether a corresponding relationship corresponding to 110 already exists, and when it is determined that a corresponding relationship corresponding to the input parameter value 110 exists, it corresponds to the input parameter value 110 based on the corresponding relationship The chip-based computing function is implemented by directly determining the target computing function template 140 and target values of configurable parameters corresponding to the target computing function template 140 .

Through the above method, the generated chip-based computing function can be dynamically applied to various application scenarios/computation scales, and the configurable parameters configured therein are determined according to the estimated execution performance, making it more reliable and machine learning method. It is used to select and measure parameter sets, and to determine target operator templates and target values, thereby reducing the difficulty of manually configuring parameters, enabling efficient generation of chip-based computing functions.

3 is a block diagram of an apparatus 300 for generating a chip-based computing function according to an embodiment of the present invention. Device 300 may be included in or implemented as computing device 130 of FIG. 1 . As shown in FIG. 3 , the device 300 includes an input parameter value obtaining module 310 that obtains an input parameter value 110 related to a computing function supported by the chip. The device 300 further includes a candidate computing function template determining module 320 configured to determine at least one candidate computing function template 120 corresponding to the computing function based on the input parameter value 110 , wherein the candidate computing function template 120 has a configurable parameter related to the execution performance of the candidate computing function template 120 , and the configurable parameter may have at least one candidate value. Furthermore, the device 300 is configured to implement the chip-based computing function, the target computing function template 140 and The method further includes a target computing function template determining module 330 configured to determine a target value of a configurable parameter of the target computing function template 140 .

In some exemplary embodiments of the present invention, the target computing function template determining module 330 uses a machine learning method to configure the input parameter values 110 and a plurality of different candidate values of the configurable parameters of the candidate computing function templates 120 . according to the target computing function template 140 and the machine learning module for determining the target values of the configurable parameters of the target computing function template 140 .

In some exemplary embodiments of the present invention, the target computing function template determining module 330 is configured to determine the execution performance of the estimated candidate computing function template 120 at different candidate values of configurable parameters of the candidate computing function template 120 . a performance estimation module for estimating; and a second target computing function template determining module configured to determine the target computing function template 140 and target values of the configurable parameters of the target computing function template 140 based on the estimated execution performance.

In some exemplary embodiments of the present invention, the second target computing function template determining module includes: a threshold value determining module, configured to determine whether the estimated execution performance is superior to an execution performance threshold; and in response to the estimated execution performance being superior to the execution performance threshold, the candidate computing function template 120 corresponding to the estimated execution performance and candidate values of the configurable parameters of the candidate computing function template 120 to the target computing function template (140) and a third target computing function template determining module for determining the target value of the configurable parameter of the target computing function template (140).

In some exemplary embodiments of the present invention, the execution performance threshold is entered by the user or preconfigured in the computing device 130 .

In some demonstrative embodiments of the present invention, the performance estimation module is configured to apply a parameter application that applies the input parameter value 110 and at least one candidate value of the at least one configurable parameter to the at least one candidate computing function template 120 . module; and a compilation module that generates the code of the at least one candidate computing function template 120 through a just-in-time compilation method and estimates execution performance of the at least one candidate computing function template 120 .

In some exemplary embodiments of the present invention, the candidate computing function template 120 further includes constraints related to input parameter values 110 and/or configurable parameters related to the execution performance of the candidate computing function template 120 , ; The candidate computing function template determination module 320 includes a first candidate computing function template determination module configured to determine at least one candidate computing function template 120 corresponding to the computing function based on the input parameter value 110 and the constraint condition. include

In some exemplary embodiments of the present invention, the device 300 includes an input parameter value 110 , a target computing function template 140 corresponding to the determined, input parameter value 110 , and a target computing function template 140 . and a storage module for storing a correspondence relationship between target values of configurable parameters corresponding to .

In some exemplary embodiments of the present invention, before determining the at least one candidate computing function template 120 corresponding to the computing function based on the input parameter value 110 , the device 300 may be configured to a correspondence determination module for determining whether a correspondence corresponding to the input parameter value 110 exists; and in response to determining that a corresponding relationship corresponding to the input parameter value 110 exists, the target computing function template 140 and the target computing function template 140 corresponding to the input parameter value 110 based on the correspondence relationship ), further comprising a fourth target computing function template determining module configured to determine a target value of a configurable parameter corresponding to .

In some exemplary embodiments of the present invention, the target computing function template determining module 330 is configured to determine the target computing function template 140 and target values of configurable parameters of the target computing function template 140 within a preset time period. and a fifth target computing function template determining module.

In some exemplary embodiments of the present invention, the preset time zone includes: a time zone input by a user, related to the design time of the chip; input parameter value 110; And it is determined based on at least one of the time zone related to the design time of the chip, which is previously configured in the computing device 130 .

In some demonstrative embodiments of the present invention, the at least one candidate computing function template 120 is implemented via a machine-oriented programming language.

In some exemplary embodiments of the present invention, each computing function corresponds to a plurality of candidate computing function templates 120 , and the plurality of candidate computing function templates 120 correspond to different application scenarios.

In some exemplary embodiments of the present invention, the input parameter value 110 is associated with an application scenario.

4 depicts an exemplary block diagram of an exemplary device 400 capable of implementing embodiments of the present invention. The device 400 may implement the computing device 130 of FIG. 1 . As shown in the figure, the device 400 responds to computer program instructions stored in a read-only memory (ROM) 402 or computer program instructions loaded from a storage unit 408 into a random access memory (RAM) 403 . , a computing unit 401 capable of performing various suitable operations and processing. The RAM 403 may further store various programs and data necessary for the operation of the device 400 . The computing unit 401 , the ROM 402 and the RAM 403 are connected to each other via a bus 404 . An input/output (I/O) interface 405 is also coupled to the bus 404 .

an input unit 406 including, for example, a keyboard, mouse, and the like; an output unit 407 including, for example, various types of displays, speakers, and the like; a storage unit 408 including, for example, a magnetic disk, an optical disk, or the like; and a communication unit 409 including, for example, a LAN card, a modem, a wireless communication transceiver, and the like. The communication unit 409 allows the device 400 to exchange information/data with other devices by means of a computer network such as the Internet and/or various telecommunication networks.

The computing unit 401 may be a variety of general-purpose and/or dedicated processing components having processing and computing capabilities. Some examples of computing unit 401 include a central processing unit (CPU), a graphics processing unit (GPU), various dedicated artificial intelligence (AI) computing chips, various computing units executing machine learning model algorithms, and a digital signal processor (DSP). ) and any suitable processor, controller, microcontroller, and the like. Computing unit 401 performs the various methods and processes described above, such as process 200 . For example, in some demonstrative embodiments, process 200 may be implemented as a computer software program tangibly embodied in a machine-readable medium, such as storage unit 408 . In some demonstrative embodiments, some or all of the computer program may be loaded and/or installed in the device 400 via the ROM 402 and/or the communication unit 409 . When the computer program is loaded into the RAM 403 and executed by the computing unit 401 , one or more steps of the process 200 described above may be performed. Alternatively, in other embodiments, computing unit 401 may be configured to perform process 200 by any other suitable means (eg, by firmware).

At least some of the functions described above in the text may be executed by one or a plurality of hardware logic members. For example, but not limited to, demonstration types of hardware logic elements that may be used include field programmable gate arrays (FPGAs), dedicated integrated circuits (ASICs), dedicated standard products (ASSPs), systems on a chip (SOC), complex programmable logic devices (CPLDs); and the like.

The program code implementing the method of the present invention may be edited in any combination of one or more programming languages. Such program code may be provided on the processor or controller of a general purpose computer, dedicated computer, or other programmable data processing device, and the program code, when executed by the processor or controller, implements the functions/operations specified in the flowcharts and/or block diagrams. can make it happen The program code may run entirely on the machine, partially run on the machine, or run on the machine as a standalone software package, some of which may run on a remote machine or run entirely on a remote machine or server.

In the context of the present invention, a machine-readable medium may be a tangible medium that can contain or store a program for use by or in combination with an instruction execution system, apparatus or apparatus. The machine-readable medium may be a machine-readable signal medium or a machine-readable storage medium. Machine-readable media may include, but are not limited to, electronic, magnetic, optical, electromagnetic, infrared or semiconductor systems, devices or appliances, or any suitable combination of the foregoing. More specific examples of machine-readable storage media include one or more wire-based electrical connections, portable computer disks, hard disks, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM). or flash memory), optical fiber, CD-ROM, optical storage device, magnetic storage device, or any suitable combination of the foregoing.

Additionally, although each operation has been described in a specific order, it should be understood that such operations may be required to be performed in the specific order or sequential order shown, or that all illustrated operations should be performed to achieve the desired results. In certain circumstances, handling multiple missions and mergers can be advantageous. Likewise, although several specific implementation details are included in the foregoing description, they should not be construed as limiting the scope of the invention. Certain features that are described in the context of independent embodiments may be implemented in combination into a single implementation. Conversely, various features that are described in the context of a single implementation may also be implemented in multiple implementations independently or in any suitable subcombination.

Although this subheading has been described in language specific to structural features and/or methodological acts, it is to be understood that the subject matter defined in the appended claims is not necessarily limited to the specific features or acts described above. To the contrary, the specific features and acts described above are for the purpose of implementing example forms of the claims only.

Claims (26)

A method for generating a chip-based computing function performed by a computing device, the method comprising:
obtaining input parameter values related to computing functions supported by the chip;
determining, based on the input parameter value, at least one candidate computing function template corresponding to the computing function, wherein the candidate computing function template has a configurable parameter related to execution performance of the candidate computing function template, wherein the configuration A possible parameter has at least one candidate value; and
To implement the chip-based computing function, according to the input parameter value and the candidate value of the configurable parameter of the candidate computing function template, a target computing function template and a target value of the configurable parameter of the target computing function template A method of generating a chip-based computing function comprising determining According to claim 1,
determining, according to the input parameter value and the candidate value of the configurable parameter of the candidate computing function template, a target computing function template and a target value of the configurable parameter of the target computing function template,
Using a machine learning method, according to the input parameter value and a plurality of different the candidate values of the configurable parameter of the candidate computing function template, the target computing function template and the configurable parameter of the target computing function template A method of generating a chip-based computing function, comprising determining a target value. According to claim 1,
determining, according to the input parameter value and the candidate value of the configurable parameter of the candidate computing function template, a target computing function template and a target value of the configurable parameter of the target computing function template,
estimating execution performance of the candidate computing function template at different candidate values of the configurable parameter of the candidate computing function template; and
and determining the target computing function template and the target value of the configurable parameter of the target computing function template based on the estimated execution performance. 4. The method of claim 3,
determining, based on the estimated execution performance, the target value of the target computing function template and the configurable parameter of the target computing function template,
determining whether the estimated execution performance is better than an execution performance threshold; and
In response to the estimated execution performance being superior to an execution performance threshold, the candidate computing function template corresponding to the estimated execution performance and the candidate value of the configurable parameter of the candidate computing function template are computed by the target computing function. and determining as the target value of the configurable parameter of a function template and the target computing function template. 5. The method of claim 4,
wherein the execution performance threshold is input by a user or preconfigured in a chip design device. 4. The method of claim 3,
estimating the execution performance of the candidate computing function template at different candidate values of the configurable parameter of the candidate computing function template;
applying the input parameter value and at least one said candidate value of at least one said configurable parameter to said at least one candidate computing function template; and
and generating the code of the at least one candidate computing function template through a just-in-time compilation method and estimating the execution performance of the at least one candidate computing function template. According to claim 1,
the candidate computing function template further comprises a constraint related to the input parameter value and/or a configurable parameter related to the execution performance of the candidate computing function template;
Determining at least one computing function template corresponding to the computing function includes:
and determining the at least one candidate computing function template corresponding to the computing function based on the input parameter value and the constraint condition. According to claim 1,
determining a correspondence relationship between the input parameter value and the determined target computing function template corresponding to the input parameter value and the target value of the configurable parameter corresponding to the target computing function template A method for generating chip-based computing capabilities. 9. The method of claim 8,
Before determining the at least one candidate computing function template corresponding to the computing function based on the input parameter value, determining whether a correspondence corresponding to the input parameter value exists in the stored correspondence relationship further comprising the steps of
Determining a target computing function template and target values of configurable parameters of the target computing function template include:
In response to determining that the correspondence corresponding to the input parameter value exists, based on the correspondence, a target computing function template corresponding to the input parameter value and the configurable parameter corresponding to the target computing function template and determining the target value of According to claim 1,
Determining a target computing function template and target values of configurable parameters of the target computing function template include:
and determining the target computing function template and the target value of the configurable parameter of the target computing function template within a preset time period. 11. The method of claim 10,
The preset time period is,
a time zone input by the user, associated with the design time of the chip;
the input parameter value; and
A method for generating a chip-based computing function, which is determined based on at least one of a time zone related to a design time of the chip, which is preconfigured in a chip design device. According to claim 1,
each of the computing functions corresponds to a plurality of the candidate computing function templates, the plurality of candidate computing function templates correspond to different application scenarios, and wherein the input parameter values are associated with the application scenarios. A device for designing a chip, comprising:
an input parameter value obtaining module for obtaining an input parameter value related to a computing function supported by the chip;
a candidate computing function template determining module configured to determine, based on the input parameter value, at least one candidate computing function template corresponding to the computing function, wherein the candidate computing function template is a configurable parameter related to execution performance of the candidate computing function template , wherein the configurable parameter has at least one candidate value; and
To implement the chip-based computing function, according to the input parameter value and the candidate value of the configurable parameter of the candidate computing function template, a target computing function template and a target value of the configurable parameter of the target computing function template An apparatus for designing a chip, comprising a target computing function template determining module for determining 14. The method of claim 13,
The target computing function template determination module,
Using a machine learning method, according to the input parameter value and a plurality of different the candidate values of the configurable parameter of the candidate computing function template, the target computing function template and the configurable parameter of the target computing function template Apparatus for designing a chip comprising a machine learning module for determining a target value. 14. The method of claim 13,
The target computing function template determination module,
a performance estimation module for estimating execution performance of the candidate computing function template at different candidate values of the configurable parameter of the candidate computing function template; and
and a second target computing function template determining module configured to determine the target computing function template and the target value of the configurable parameter of the target computing function template based on the estimated execution performance. 16. The method of claim 15,
The second target computing function template determination module,
a threshold value determination module for determining whether the estimated execution performance is superior to an execution performance threshold; and
In response to the estimated execution performance being better than an execution performance threshold, the candidate computing function template corresponding to the estimated execution performance and the candidate value of the configurable parameter of the candidate computing function template are computed by the target computing function. and a function template and a third target computing function template determining module configured to determine the target value of the configurable parameter of the target computing function template. 17. The method of claim 16,
and the execution performance threshold is inputted by a user or preconfigured in a chip design device. 16. The method of claim 15,
The performance estimation module,
a parameter application module for applying the input parameter value and at least one said candidate value of at least one said configurable parameter to said at least one candidate computing function template; and
and a compilation module for generating the code of the at least one candidate computing function template through a just-in-time compilation method and estimating the execution performance of the at least one candidate computing function template. 14. The method of claim 13,
the candidate computing function template further comprises a constraint related to the input parameter value and/or a configurable parameter related to the execution performance of the candidate computing function template;
The candidate computing function template determining module comprises:
and a first candidate computing function template determining module configured to determine the at least one candidate computing function template corresponding to the computing function, based on the input parameter value and the constraint condition. 14. The method of claim 13,
a storage module for storing a correspondence relationship between the input parameter value and the determined target computing function template corresponding to the input parameter value and the target value of the configurable parameter corresponding to the target computing function template device for chip design. 21. The method of claim 20,
Before determining the at least one candidate computing function template corresponding to the computing function, based on the input parameter value, a correspondence for determining whether a correspondence corresponding to the input parameter value exists in the previously stored correspondence relationship relationship determination module; and
In response to determining that the correspondence corresponding to the input parameter value exists, based on the correspondence, a target computing function template corresponding to the input parameter value and the configurable parameter corresponding to the target computing function template The apparatus for designing a chip further comprising a fourth target computing function template determining module configured to determine the target value of . 14. The method of claim 13,
The target computing function template determination module,
and a fifth target computing function template determining module configured to determine the target computing function template and the target value of the configurable parameter of the target computing function template within a preset time period. 23. The method of claim 22,
The preset time period is,
a time zone input by the user, associated with the design time of the chip;
the input parameter value; and
An apparatus for designing a chip, which is determined based on at least one of a time period related to a design time of the chip, which is preconfigured in the apparatus for designing a chip. 14. The method of claim 13,
each of the computing functions corresponds to a plurality of the candidate computing function templates, the plurality of candidate computing function templates correspond to different application scenarios, and wherein the input parameter values are associated with an application scenario. one or more processors; and
An electronic device comprising a memory for storing one or a plurality of programs,
An electronic device that enables the electronic device to implement the method for generating a chip-based computing function according to any one of claims 1 to 12 when the one or more programs are executed by the one or the plurality of processors. In a computer-readable storage medium storing a computer program,
A computer-readable storage medium for implementing the method for generating a chip-based computing function according to any one of claims 1 to 12 when the program is executed by a processor.

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