KR102333142B1 - Pixel and organic light emitting display device having the same - Google Patents

Abstract

A pixel of the organic light emitting diode display receives a constant first voltage irrespective of frame periods and a second voltage having different levels during frame periods. Before the pixel emits light, the anode of the organic light emitting diode is discharged to a voltage having a constant potential difference from the second voltage. Thereafter, the organic light emitting diode emits light in response to the data signal. The organic light emitting diode may display luminance corresponding to the grayscale value of the data signal. The organic light emitting diode may display black having a constant luminance regardless of the second voltage.

Description

A pixel and an organic light emitting display device including the pixel {PIXEL AND ORGANIC LIGHT EMITTING DISPLAY DEVICE HAVING THE SAME}

The present invention relates to a pixel and an organic light emitting display including the same, and more particularly, to a pixel and an organic light emitting display having improved display quality.

The organic light emitting display device includes a plurality of pixels. Each of the plurality of pixels includes an organic light emitting diode and a circuit unit controlling the organic light emitting diode. The circuit unit includes at least a switching transistor, a driving transistor, and a storage capacitor.

The organic light emitting diode includes an anode, a cathode, and an organic light emitting layer disposed between the anode and the cathode. The organic light emitting diode emits light when a voltage equal to or greater than the threshold voltage of the organic light emitting layer is applied between the anode and the cathode.

Accordingly, it is an object of the present invention to provide a pixel displaying uniform black luminance and an organic light emitting diode display including the same.

The pixel according to an embodiment of the present invention emits light in response to data signals received during the first frame period and the second frame period. Each of the first frame period and the second frame period includes an emission period and a first discharge period before the emission period. The pixel includes an organic light emitting diode and a circuit unit controlling light emission of the organic light emitting diode.

The organic light emitting diode includes an anode receiving a first voltage during the light emission period and a cathode receiving a second voltage having a lower level than the first voltage. The second voltage has different levels during the first frame period and the second frame period. During the first discharging period, the anode of the organic light emitting diode is discharged by a third voltage having a constant potential difference from the second voltage.

The circuit unit may include a driving transistor including an input electrode to which the first voltage is applied, an output electrode, and a control electrode connected to a first node during the light emission period, an input electrode to which the data signals are applied, and an input of the driving transistor A switching transistor including an output electrode connected to the electrode and a control electrode to which a scan signal activated during a scan period before the first discharge period is applied, between the first node and a second node to which the first voltage is applied A first control transistor including a storage capacitor connected thereto, an input electrode connected to an output electrode of the driving transistor, an output electrode connected to the first node, and a control electrode to which the scan signal is applied, an output electrode of the driving transistor a second control transistor including an input electrode connected to , an output electrode connected to the anode of the organic light emitting diode, and a control electrode for receiving a light emission control signal activated in the light emission section, and an input for receiving the third voltage an electrode, an output electrode connected to the anode of the organic light emitting diode, and a control electrode for receiving a first discharge control signal activated in the first discharge period, wherein the anode of the organic light emitting diode is connected to the anode during the first discharge period and a first discharge transistor providing a third voltage.

The circuit unit includes an input electrode receiving a fourth voltage of a lower level than the data signals, an output electrode connected to the first node, and a second discharge control signal activated during a second discharge period before the scan period. A second discharge transistor including a control electrode to be applied may be further included. The second discharge transistor provides the fourth voltage to the first node during the second discharge period.

The circuit unit may further include a third control transistor including an input electrode connected to the second node, an output electrode connected to the input electrode of the driving transistor, and a control electrode for receiving the emission control signal.

The potential difference between the second voltage and the third voltage is less than the emission threshold voltage of the organic light emitting diode.

An organic light emitting diode display according to an embodiment of the present invention includes a scan driver, a data driver, pixels, and a discharge voltage generator. Each of the pixels may be the same as the aforementioned pixel. The scan driver outputs scan signals and emission control signals during the first frame period and the second frame period. The data driver outputs data signals during the first frame period and the second frame period. The discharge voltage generator provides a third voltage having a constant potential difference from the second voltage to the pixels during the first frame period and the second frame period.

Of the pixels, an i-th scan line among the scan lines, a light emitting line corresponding to the i-th scan line, and a pixel connected to a j-th data line among the data lines (hereinafter, pixel (i,j)) The anode of the organic light emitting diode is discharged by the third voltage during a first discharge period before the emission period between the first frame period and the second frame period.

The first discharge control signal may be a scan signal applied to a scan line disposed after the i-th scan line. The second discharge control signal may be a scan signal applied to a scan line disposed before the i-th scan line.

The discharge voltage generator includes a first discharge voltage generator that generates the third voltage. The first discharge voltage generator outputs an inverting input terminal for receiving a reference voltage, a non-inverting input terminal for receiving the selected second voltage, and a differential voltage between the reference voltage and the selected second voltage as the third voltage It may include a differential amplifier including an output terminal.

The discharge voltage generator may further include a second discharge voltage generator configured to generate the fourth voltage. The second discharge voltage generator includes a plurality of resistors connected in series between the first voltage and the second voltage, and a voltage divider circuit configured to output the fourth voltage divided from the plurality of resistors connected in series. may include more.

Among the pixels, one pixel different from the pixel (i,j) may include an organic light emitting diode emitting a color different from that of the organic light emitting diode of the pixel (i, j). During the first frame period, the cathode of the organic light emitting diode of the other pixel may receive the second voltage having a different level than that of the cathode of the organic light emitting diode of the pixel (i, j).

During the first frame period, the anode of the organic light emitting diode of the other pixel may be discharged by the third voltage having a different level than the anode of the organic light emitting diode of the pixel (i, j).

As described above, the cathode of the organic light emitting diode receives second voltages of different levels during different frame periods. The second voltage may be differently selected according to a pixel or may be differently selected according to an operation mode of the organic light emitting display device.

Before the organic light emitting diode emits light, the anode of the organic light emitting diode is discharged to a voltage having a constant potential difference from the second voltage. Thereafter, the organic light emitting diode emits light in response to the data signal. The organic light emitting diode may display luminance corresponding to the grayscale value of the data signal. For example, the organic light emitting diode may display black with a constant luminance. The organic light emitting diode may display low grayscales having a luminance difference between the black and the black.

Anodes of the organic light emitting diodes displaying different colors may receive second voltages of different levels. The anodes of the organic light emitting diodes are respectively discharged by a corresponding second voltage and a voltage having a constant potential difference. Therefore, it is possible to display black with a constant luminance regardless of the type of the organic light emitting diodes.

1 is a block diagram of an organic light emitting display device according to an embodiment of the present invention.
2 is a circuit diagram of a first discharge voltage generator according to an embodiment of the present invention.
3A is a circuit diagram of a second discharge voltage generator according to an embodiment of the present invention.
3B is a waveform diagram illustrating voltages generated according to an embodiment of the present invention.
3B is a waveform diagram illustrating voltages generated according to an embodiment of the present invention.
4 is an equivalent circuit diagram of a pixel according to an embodiment of the present invention.
FIG. 5 is a waveform diagram illustrating driving signals for driving the pixel illustrated in FIG. 4 .
6A and 6B illustrate the operation of the pixel and waveforms of driving signals during the first period.
7A and 7B illustrate the operation of the pixel and waveforms of driving signals during the second period.
8A and 8B illustrate the operation of the pixel and waveforms of driving signals during the third period.
9A and 9B illustrate the operation of the pixel and waveforms of driving signals during the fourth period.

Hereinafter, an organic light emitting display device according to an embodiment of the present invention will be described with reference to the drawings. In the drawings, the scales of some components are exaggerated or reduced in order to clearly express various layers and regions. Like reference numerals refer to like elements throughout.

1 is a block diagram of an organic light emitting display device according to an embodiment of the present invention. 2 is a circuit diagram of a first discharge voltage generator according to an embodiment of the present invention. 3A is a circuit diagram of a second discharge voltage generator according to an embodiment of the present invention. 3B is a waveform diagram illustrating voltages generated according to an embodiment of the present invention. 3B is a waveform diagram illustrating voltages generated according to an embodiment of the present invention.

As shown in FIG. 1 , the organic light emitting display device includes a timing controller 100 , a scan driver 200 , a data driver 300 , a driving voltage generator 400 , a discharge voltage generator 500 , and a display panel. Includes part (DP).

The timing controller 100 receives input image signals (not shown), converts the data format of the input image signals to meet the interface specification with the data driver 300 to generate image data RGB. . The timing controller 100 outputs the image data RGB and various control signals DCS, SCS, and VCS.

The scan driver 200 receives a scan control signal SCS from the timing controller 100 . The scan control signal SCS may include a vertical start signal for starting the operation of the scan driver 200 and a clock signal for determining output timing of the signals. The scan driver 200 generates a plurality of scan signals and sequentially outputs the plurality of scan signals to a plurality of scan lines SL1 to SLn to be described later. In addition, the scan driver 200 generates a plurality of light emission control signals in response to the scan control signal SCS, and outputs the plurality of light emission control signals to a plurality of light emission lines EL1 to ELn, which will be described later. .

1 illustrates that the plurality of scan signals and the plurality of emission control signals are output from one scan driver 200, the present invention is not limited thereto. In an embodiment of the present invention, a plurality of scan drivers may divide and output the plurality of scan signals, and divide and output the plurality of light emission control signals. Also, in one embodiment of the present invention, the driving circuit generating and outputting the plurality of scan signals and the driving circuit generating and outputting the plurality of light emission control signals may be separately distinguished.

The data driver 300 receives the data control signal DCS and the image data RGB from the timing controller 100 . The data driver 300 converts the image data RGB into data signals, and outputs the data signals to a plurality of data lines DL1 to DLm to be described later. The data signals are analog voltages corresponding to grayscale values of the image data RGB.

The driving voltage generator 400 receives a power supply voltage Vin from a power supply unit (not shown). The driving voltage generator 400 converts the power supply voltage Vin to generate a first voltage ELVDD and a second voltage ELVSS having a lower level than the first voltage ELVDD.

The driving voltage generator 400 may include a DC-DC converter. The driving voltage generator 400 may include a boosting converter that boosts the power supply voltage Vin to generate the first voltage ELVDD. In addition, the driving voltage generator 400 may include a buck converter for generating the second voltage ELVSS by stepping down the power supply voltage Vin.

The driving voltage generator 400 receives the driving voltage control signal VCS from the timing controller 100 . The driving voltage generator 400 may generate the first voltage ELVDD having a predetermined constant level in response to the driving voltage control signal VCS.

The driving voltage generator 400 may generate the second voltage ELVSS within a predetermined voltage range in response to the driving voltage control signal VCS. The second voltage ELVSS may have a negative polarity voltage, for example, in a range of about -4V to about -2V. In response to the driving voltage control signal VCS, the driving voltage generator 400 is configured to have a second voltage ELVSS of -4V, a second voltage ELVSS of -3V, or a second voltage ELVSS of -2V. can optionally be created.

As will be described later with reference to FIGS. 3B and 3C , the driving voltage generator 400 may generate a second voltage ELVSS having different levels corresponding to frame sections. Also, the driving voltage generator 400 may generate a plurality of second voltages ELVSS having different levels within the predetermined voltage range. For example, the driving voltage generator 400 may generate a second voltage ELVSS of -4V, a second voltage ELVSS of -3V, and a second voltage of -2V in response to the driving voltage control signal VCS. ELVSS), at least two second voltages may be generated. In this case, the driving voltage generator 400 may include a plurality of buck converters.

In addition, the driving voltage generator 400 may generate other reference voltages necessary for driving the display device. For example, the driving voltage generator 400 may generate a reference voltage necessary for the operation of the display panel unit DP or a reference voltage necessary for the operation of the discharge voltage generator 500 .

The discharge voltage generator 500 receives the first voltage ELVDD and the second voltage ELVSS from the driving voltage generator 400 . The discharge voltage generator 500 generates a third voltage Vi1 and a fourth voltage Vi2 by using the first voltage ELVDD and the second voltage ELVSS. Each of the third voltage Vi1 and the fourth voltage Vi2 may be defined as a different discharge voltage. The discharge voltage generator 500 may generate a plurality of third voltages Vi1 and a plurality of fourth voltages Vi2 by using the first voltage ELVDD and the second voltage ELVSS.

The third voltage Vi1 has a level lower than that of the data signal. For example, it may have a lower level than the data signal of the highest grayscale. The fourth voltage Vi2 has a constant potential difference from the second voltage ELVSS. For example, when the second voltage ELVSS has a range of about -4V to about -2V, the fourth voltage Vi2 may have a range of about -3V to about -1V.

As shown in FIG. 2 , the discharge voltage generator 500 may include a first discharge voltage generator 500 - 1 that generates the third voltage Vi1 . The first discharge voltage generator 500 - 1 receives the first voltage ELVDD and the second voltage ELVSS, and is divided from the first voltage ELVDD and the second voltage ELVSS. and a voltage divider circuit generating the third voltage Vi1. The first discharge voltage generator 500 - 1 may include a plurality of voltage divider circuits each generating the third voltage Vi1 .

The voltage divider circuit includes a plurality of resistors connected in series between the first voltage ELVDD and the second voltage ELVSS. As shown in FIG. 2 , the voltage divider circuit may include a first resistor R1 and a second resistor R2 connected in series. The first resistor R1 is connected to the first voltage ELVDD, and the second resistor R2 is connected to the second voltage ELVSS. The third voltage Vi1 is output at a node NV between the first resistor R1 and the second resistor R2. The level of the third voltage Vi1 may be determined according to a resistance ratio between the first resistor R1 and the second resistor R2 .

In an embodiment of the present invention, the first discharge voltage generating unit 500 - 1 may be omitted. In this case, the third voltage Vi1 may be generated by the driving voltage generator 400 . The third voltage Vi1 may be generated from a buck converter of the driving voltage generator 400 .

As shown in FIG. 3A , the discharge voltage generator 500 may include a second discharge voltage generator 500 - 2 that generates the fourth voltage Vi2 . The second discharge voltage generator 500 - 2 outputs the differential voltage between the reference voltage Vref received from the driving voltage generator 400 and the second voltage ELVSS as the fourth voltage Vi2 . It includes a differential amplifier that

3A , the differential amplifier outputs an inverting input terminal receiving the reference voltage Vref, a non-inverting input terminal receiving the second voltage ELVSS, and the fourth voltage Vi2. output terminal is included. The reference voltage Vref is input to the inverting input terminal via a first resistor R10. A second resistor R20 is connected between the inverting input terminal and the output terminal. The second voltage ELVSS is input to the non-inverting input terminal via a third resistor R30. A fourth resistor R40 is connected between the inverting input terminal and the ground.

The differential amplifier may output a voltage proportional to a differential voltage between the reference voltage Vref and the second voltage ELVSS and a resistance ratio between the first resistor R10 and the second resistor R20. That is, the level of the fourth voltage Vi2 may be controlled by changing the resistance ratio between the first resistor R10 and the second resistor R20 .

Although not shown separately, the second discharge voltage generator 500 - 2 may further include a voltage follower that provides the reference voltage Vref to the differential amplifier. The voltage follower may provide a stable reference voltage Vref. The differential amplifier may receive the reference voltage Vref directly from the driving voltage generator 400 as well as receive the reference voltage Vref buffered through the voltage follower.

The differential amplifier may generate the fourth voltage Vi2 having different levels corresponding to frame sections. The differential amplifier is configured to generate a fourth voltage Vi2 having a constant potential difference from the second voltage ELVSS irrespective of frame sections based on the second voltage ELVSS changed to correspond to frame sections. can

As shown in FIG. 3B , the second discharge voltage generator 500 - 2 generates the fourth voltage Vi2 based on the second voltage ELVSS received in the k-th frame period Fk. generated, and based on the second voltage ELVSS of the k+1-th frame period Fk+1 that is lower than the second voltage ELVSS of the k-th frame period Fk, the k-th frame period Fk ), the fourth voltage Vi2 of the k+1th frame period Fk+1 may be generated at a level lower than the fourth voltage Vi2 of the . Although two consecutive frame sections Fk and Fk+1 have been exemplarily described in FIG. 3B , the differential amplifier generates the fourth voltage Vi2 having different levels corresponding to the discontinuous frame sections. You may.

The second discharge voltage generator 500 - 2 may generate a plurality of fourth voltages Vi2 having different levels. The second discharge voltage generator 500 - 2 may include a plurality of differential amplifiers that generate a plurality of fourth voltages Vi2 having different levels.

As shown in FIG. 3C , during the k-th frame period Fk, the second discharge voltage generator 500 - 2 generates a corresponding second voltage based on three second voltages ELVSS having different levels. It is possible to generate three fourth voltages Vi2 having a constant potential difference with the . When the levels of the three second voltages ELVSS are changed according to frame periods, the levels of the three fourth voltages Vi2 may also be changed correspondingly.

Referring back to FIG. 1 , the display panel unit DP includes a plurality of scan lines SL1 to SLn, a plurality of light emitting lines EL1 to ELn, a plurality of data lines DL1 to DLm, and a plurality of It includes pixels PX. The plurality of scan lines SL1 to SLn extend in a first direction DR1 and are arranged in a second direction DR2 orthogonal to the second direction. Each of the plurality of light emitting lines EL1 to ELn may be arranged in parallel with a corresponding one of the plurality of scan lines SL1 to SLn. The plurality of data lines DL1 to DLm insulately cross the plurality of scan lines SL1 to SLn.

Each of the plurality of pixels PX includes a corresponding one of the plurality of scan lines SL1 to SLn, a corresponding one of the plurality of light emitting lines EL1 to ELn, and the plurality of data lines. It is connected to corresponding data lines among the ones DL1 to DLm. 1 , each of the plurality of pixels PX may be connected to a plurality of scan lines among the plurality of scan lines SL1 to SLn. This will be described in more detail with reference to FIGS. 4 and 5 .

Each of the plurality of pixels PX includes an organic light emitting diode (not shown) and a circuit unit (not shown) for controlling light emission of the organic light emitting diode. The circuit unit may include a plurality of thin film transistors and capacitors. The plurality of pixels PX may include red pixels emitting a red color, green pixels emitting a green color, and blue pixels emitting a blue color. The organic light emitting diode of the red pixel, the organic light emitting diode of the green pixel, and the organic light emitting diode of the blue pixel may include organic light emitting layers of different materials.

The plurality of scan lines SL1 to SLn, the plurality of light emitting lines EL1 to ELn, and the plurality of data lines are formed on a base substrate (not shown) through a plurality of photolithography processes and a plurality of deposition processes. The pixels DL1 to DLm and the plurality of pixels PX may be formed. In addition, an encapsulation layer (not shown) protecting the plurality of pixels PX may be further formed on the base substrate.

The display panel unit DP receives the first voltage ELVDD and the second voltage ELVSS. The first voltage ELVDD may be provided to the plurality of pixels PX through a first voltage line PL1 . The second voltage ELVSS may be provided to the plurality of pixels PX through electrodes (not shown) or a power line (not shown) formed on the display panel unit DP.

In the present embodiment, the plurality of pixels PX may receive the second voltage ELVSS of the same level. In an embodiment of the present invention, the plurality of pixels PX may receive second voltages ELVSS having different levels according to the color to be emitted. For example, the red pixels, the green pixels, and the blue pixels may receive second voltages ELVSS having different levels.

The display panel unit DP receives the third voltage Vi1 and the fourth voltage Vi2. The third voltage Vi1 may be provided to the plurality of pixels PX through a second voltage line PL2 . The fourth voltage Vi2 may be provided to the plurality of pixels PX through a third voltage line PL3 . The display panel unit DP may receive the fourth voltage Vi2 whose level is changed according to frame sections.

In an embodiment of the present invention, the plurality of pixels PX may receive fourth voltages Vi2 having different levels according to the emitted color. In this case, the third voltage line PL3 is a voltage line providing any one of the fourth voltages to the red pixels, and a voltage line providing the other one of the second fourth voltages to the green pixels. , and a voltage line providing another one of the second and fourth voltages to the blue pixels.

4 is an equivalent circuit diagram of a pixel according to an embodiment of the present invention. FIG. 5 is a waveform diagram illustrating driving signals for driving the pixel illustrated in FIG. 4 .

4 shows an i-th scan line (not shown) among the plurality of scan lines SL1 to SLn (see FIG. 1), and an i-th light emitting line (not shown) among the plurality of light emitting lines EL1 to ELn (see FIG. 1). shown), and an equivalent circuit diagram of a pixel PXij connected to a j-th data line (not shown) among the plurality of data lines DL1 to DLm (refer to FIG. 1 ) is illustrated as an example. Each of the plurality of pixels PX shown in FIG. 1 may have the equivalent circuit shown in FIG. 4 .

The pixel PXij includes an organic light emitting diode ED and a circuit unit CP for controlling the organic light emitting diode. In this embodiment, the circuit part CP including seven transistors T1 to T7 and one capacitor Cst is illustrated as an example. Also, the seven transistors T1 to T7 are illustrated as p-type transistors. However, the pixel configuration of the present invention is not limited to FIG. 4 . The circuit part CP shown in FIG. 4 is only an example, and the configuration of the circuit part CP may be modified and implemented.

As shown in FIG. 4 , the circuit unit CP includes a first transistor connected between a node N2 to which the first voltage ELVDD is applied and an anode of the organic light emitting diode ED (hereinafter, referred to as a second node). (T1), a second transistor T2 connected between the j-th data line and the first transistor T1, and a second transistor T2 connected between the first node N1 and the output electrode of the first transistor T1 a third transistor T3, and a fourth transistor T4 connected between the first transistor T1 and the anode of the organic light emitting diode ED. In addition, the circuit unit CP includes a fifth transistor T5 connected between the second node N2 and the first transistor T1 , the first node N1 and the third voltage Vi1 , in FIG. 1) to which the sixth transistor T6 is connected between the third node N3, the anode of the organic light emitting diode ED, and the fourth node to which the fourth voltage Vi2 (refer to FIG. 1) is applied. a seventh transistor T7 connected between N4 , and a storage capacitor Cst connected between the first node N1 and the second node N2 .

The second node N2 may be defined as a point where the first power line PL1 (refer to FIG. 1 ) and the input electrode of the fifth transistor T5 are connected, and the third node N3 is the It may be defined as a point where the second power line PL2 (refer to FIG. 1 ) and the input electrode of the sixth transistor T6 are connected. The fourth node N4 may be defined as a point where the third power line PL3 (refer to FIG. 1 ) and the input electrode of the seventh transistor T7 are connected.

More specifically, the first transistor T1 includes an input electrode that receives the first voltage ELVDD via the fifth transistor T5 , a control electrode connected to the first node N1 , and an output including electrodes. The output electrode of the first transistor T1 provides the first voltage ELVDD to the organic light emitting diode ED via the fourth transistor T4 .

The first transistor T1 controls a driving current supplied to the organic light emitting diode ED in response to the potential of the first node N1 . The first transistor T1 may be defined as a driving transistor.

The second transistor T2 includes an input electrode connected to the j-th data line, a control electrode connected to the i-th scan line, and an output electrode connected to the input electrode of the first transistor T1 . The second transistor T2 is turned on by the scan signal GSi applied to the i-th scan line, and applies the data signal DSi applied to the j-th data line to the first node N1. to provide. The second transistor T2 may be defined as a switching transistor.

The third transistor T3 includes an input electrode connected to the output electrode of the first transistor T1 , a control electrode connected to the i-th scan line, and an output electrode connected to the first node N1 . do. The third transistor T3 is turned on in response to the scan signal GSi applied to the i-th scan line. The third transistor T3 may be defined as a first control transistor.

When the second transistor T2 and the third transistor T3 are turned on, the first transistor T1 is connected in a diode form between the second transistor T2 and the third transistor T3. do. Accordingly, the second transistor T2 is connected to the first node N1 via the first transistor T1 and the third transistor T3.

The fourth transistor T4 has an input electrode connected to the output electrode of the first transistor T1 , a control electrode connected to the i-th light emitting line, and an output electrode connected to the anode of the organic light emitting diode ED. includes

The fourth transistor T4 is turned on or off in response to the emission control signal ESi supplied from the i-th emission line. A current path is formed or blocked between the second node N2 and the organic light emitting diode ED according to the operation of the fourth transistor T4 . The fourth transistor T4 may be defined as a second control transistor.

The fifth transistor T5 includes an input electrode connected to the second node N2 , a control electrode connected to the i-th light emitting line, and an output electrode connected to the input electrode of the first transistor T1 . do. The fifth transistor T5 may be defined as a third control transistor.

The fifth transistor T5 is turned on or off in response to the emission control signal ESi supplied from the i-th emission line. A current path is formed or blocked between the second node N2 and the organic light emitting diode ED according to the operation of the fifth transistor T5 . In an embodiment of the present invention, the fifth transistor T5 may be omitted, and the input electrode of the first transistor T1 may be directly connected to the second node N2 .

The sixth transistor T6 is connected to an input electrode receiving the third voltage Vi1, a control electrode receiving the first discharge control signal GSi-1, and an anode of the organic light emitting diode ED. It includes an output electrode. The sixth transistor T6 is turned on in response to the first discharge control signal GSi-1, and provides the third voltage Vi1 to the first node N1.

The first node N1 is initialized by the third voltage Vi1. The sixth transistor T6 may be defined as a first discharge transistor. In an embodiment of the present invention, the sixth transistor T6 may be omitted.

The seventh transistor T7 is connected to an input electrode receiving the fourth voltage Vi2, a control electrode receiving the second discharge control signal GSi+1, and an anode of the organic light emitting diode ED. It includes an output electrode. The seventh transistor T7 is turned on in response to the second discharge control signal GSi+1, and provides the fourth voltage Vi2 to the anode of the organic light emitting diode ED.

The anode of the organic light emitting diode ED is initialized by the fourth voltage Vi2. The seventh transistor T7 may be defined as a second discharge transistor.

The storage capacitor Cst is connected between the first node N1 and the second node N2 . The storage capacitor Cst is charged with a voltage corresponding to the first voltage ELVDD and a voltage applied to the first node N1 .

Referring to FIG. 5 , the display device displays a unit image for each frame section Fk-1, Fk, and Fk+1. Each of the pixels PX shown in FIG. 1 receives a data signal corresponding to each of the frame sections Fk-1, Fk, and Fk+1.

5 illustrates frame sections Fk-1, Fk, and Fk+1 of the pixel PXij shown in FIG. 4 . Hereinafter, driving signals for driving the pixels PX based on the k-th frame period Fk will be described. The k-th frame section Fk may include successive first to fourth sections 1H to 4H. The k-th frame section Fk is not limited thereto, and the k-th frame section Fk includes sections other than the first to third sections 1H to 3H before the fourth section 4H. may include

The first discharge control signal GSi-1 is activated during the first period 1H. In this embodiment, the signals shown in Fig. 5 are described as being activated when they have a low level. The low level of the signals shown in FIG. 5 may be a turn-on voltage of a transistor to which the corresponding signals are applied.

The first node N1 is initialized to the third voltage Vi1 by the first discharge control signal GSi-1 activated in the first period 1H. The first period 1H may be defined as one discharge period.

The first discharge control signal GSi-1 may be a scan signal applied to a scan line disposed before the i-th scan line among the plurality of scan lines SL1 to SLn (refer to FIG. 1 ). In particular, the first discharge control signal GSi-1 may be a scan signal applied to the i-1th scan line disposed immediately before the i-th scan line.

The scan signal GSi applied to the i-th scan line is activated during a second period 2H defined after the first period 1H. The second transistor T2 is turned on by the scan signal GSi activated in the second period 2H, and the data signal DSi applied to the j-th data line is applied to the first node ( N1). The second period 2H may be defined as a scan period.

In response to the second discharge control signal GSi+1 activated during a third period 3H defined after the second period 2H, the anode of the organic light emitting diode ED becomes the fourth voltage Vi2 . is initialized to The third period 3H may be defined as a discharge period different from the first period 1H.

The second discharge control signal GSi+1 may be a scan signal applied to a scan line disposed after the i-th scan line among the plurality of scan lines SL1 to SLn. In particular, the second discharge control signal GSi+1 may be a scan signal applied to the i+1-th scan line disposed immediately after the i-th scan line.

A current path is formed between the second node N2 and the organic light emitting diode ED by the light emission control signal ESi activated during a fourth period 4H defined after the third period 3H. do. Accordingly, the organic light emitting diode ED emits light during the fourth period 4H. The fourth section 4H may be defined as an emission section.

The light emission control signal ESi is deactivated during the second period 2H and the third period 3H. That is, the light emission control signal ESi has a high level during the second period 2H and the third period 3H. The light emission control signal ESi has a high level before the first discharge control signal GSi-1 is activated. In an embodiment of the present invention, the light emission control signal ESi may have a high level during the entire first period 1H.

The operation of the pixel PXij will be described in more detail with reference to FIGS. 6A to 9B . 6A and 6B illustrate the operation of the pixel and waveforms of driving signals during the first period. 7A and 7B show waveforms of operation and driving signals of the pixel during the second period, FIGS. 8A and 8B show waveforms of operation and driving signals of the pixel during the third period, and FIGS. 9A and 9B show waveforms of the fourth period The operation of the pixel and waveforms of driving signals during the period are shown.

6A to 9B , the cathode of the organic light emitting diode ED of the pixel PXij receives the second voltage ELVSS. The second voltage ELVSS has a level selected from a predetermined voltage range according to a setting mode of the organic light emitting diode display. The level of the second voltage ELVSS may be changed to correspond to frame sections. Also, the level of the second voltage ELVSS may be changed according to a color emitted from the organic light emitting diode ED.

6A and 6B , the first discharge control signal GSi-1 activated during the first period 1H is applied to the fourth transistor T4. Accordingly, the third voltage Vi1 is transferred to the first node N1 . The third voltage Vi1 may be set to a level low enough to initialize the first node N1 , for example, a level lower than the threshold voltage of the first transistor T1 than the data signal of the highest grayscale. .

Accordingly, during the first period 1H, the first transistor T1 is turned on, and during a second period 2H continuous to the first period 1H, the first transistor T1 is turned on. A diode may be connected in a forward direction between the second transistor T2 and the third transistor T3 .

Next, as shown in FIGS. 7A and 7B , the scan signal GSi activated during the second period 2H is applied to the i-th scan line. Accordingly, the second transistor T2 and the third transistor T3 are turned on, and the first transistor T1 is diode-connected by the third transistor T3.

A data signal is supplied to the j-th data line during the second period 2H. The data signal is provided to the first node N1 via the second transistor T2 , the first transistor T1 , and the third transistor T3 . In this case, since the first transistor T1 is in a diode-connected state, a voltage difference between the data signal and the threshold voltage of the first transistor T1 is provided to the first node N1 . The voltage transferred to the first node N1 during the second period 2H is stored in the storage capacitor Cst.

Next, as shown in FIGS. 8A and 8B , the second discharge control signal GSi+1 activated during the third period 3H is applied to the control electrode of the seventh transistor T7 . Accordingly, the seventh transistor T7 is turned on, and the fourth voltage Vi2 is applied to the anode of the organic light emitting diode ED. The anode of the organic light emitting diode ED is initialized to the fourth voltage Vi2.

The fourth voltage Vi2 has a constant potential difference from the second voltage ELVSS. As described with reference to FIGS. 3A to 3C , the level of the fourth voltage Vi2 may be determined by the level of the selected second voltage ELVSS. In this case, the potential difference between the fourth voltage Vi2 and the second voltage ELVSS is smaller than the emission threshold voltage of the organic light emitting diode ED. Accordingly, even when the fourth voltage Vi2 is applied to the anode of the organic light emitting diode ED, the organic light emitting diode ED does not emit light. The pixel PXij displays a constant black luminance regardless of the level of the second voltage ELVSS for at least the third period 3H.

Next, as shown in FIGS. 9A and 9B , the emission control signal ESi activated during the fourth period 4H is applied to the i-th emission line. Accordingly, the fifth transistor T5 and the sixth transistor T6 are turned on. from the first voltage ELVDD to a second voltage ELVSS via the fifth transistor T5 , the first transistor T1 , the sixth transistor T6 , and the organic light emitting diode ED A current path is formed.

A driving current flowing through the organic light emitting diode ED is controlled by the potential of the first node N1 . The operation of the first transistor T1 is controlled according to the data signal applied to the first node N1 during the second period 2H.

The organic light emitting diode ED initialized by the fourth voltage Vi2 during the third period 3H emits light with a luminance corresponding to the data signal during the fourth period 4H. For example, the organic light emitting diode ED may display black with a constant luminance.

The pixel PXij receiving the data signal of the lowest grayscale may display the same luminance as the luminance of the third period 3H during the fourth period 4H. The pixel PXij may display a constant black luminance regardless of the level of the second voltage ELVSS. The pixel PXij may display low grayscales having a predetermined luminance difference from the black.

The organic light emitting diodes that generate light of different colors are respectively discharged by the received second voltage ELVSS and the fourth voltage Vi2 having a constant potential difference. Accordingly, the organic light emitting diodes can display black with a constant luminance regardless of the type thereof.

Although the above has been described with reference to the preferred embodiment of the present invention, those skilled in the art or those having ordinary knowledge in the technical field will not depart from the spirit and technical scope of the present invention described in the claims to be described later. It will be understood that various modifications and variations of the present invention can be made without departing from the scope of the present invention.

Accordingly, the technical scope of the present invention should not be limited to the contents described in the detailed description of the specification, but should be defined by the claims.

100: timing controller 200: scan driver
300: data driving unit DP: display panel unit
400: drive voltage generator 500: discharge voltage generator
ED: organic light emitting diode ELVDD: first voltage
ELVSS: second voltage Vi1: third voltage
Vi2: fourth voltage PX: pixel

Claims (17)

a plurality of scan lines;
a plurality of light emitting lines;
a plurality of data lines crossing the plurality of scan lines and the plurality of light emitting lines;
a plurality of pixels; and
a third voltage and a discharge voltage generator outputting a fourth voltage different from the third voltage to the pixels;
Each of the plurality of pixels,
a circuit unit configured to receive a first voltage, the third voltage, and the fourth voltage; and
An organic light emitting diode including an anode connected to the circuit unit and a cathode receiving a second voltage having a voltage level lower than the first voltage,
The fourth voltage is maintained to have a constant potential difference from the second voltage during a frame period, and the circuit unit applies the fourth voltage to the anode. According to claim 1, wherein the circuit unit,
and a control electrode, an input electrode, and an output electrode electrically connected between the second node to which the first voltage is applied and the anode of the organic light emitting diode and electrically connected to the first node to which the third voltage is applied. a driving transistor;
an input electrode electrically connected to the input electrode of the driving transistor and receiving data signals applied to a corresponding one of the data lines and a first scan signal applied to a corresponding one of the scan lines; a switching transistor comprising a receiving control electrode;
a storage capacitor electrically connected between the first node and the second node;
a first control comprising an input electrode electrically connected to the output electrode of the driving transistor, an output electrode electrically connected to the first node, and a control electrode receiving the first scan signal applied to the corresponding scan line transistor;
An input electrode electrically connected to the output electrode of the driving transistor, an output electrode electrically connected to the anode of the organic light emitting diode, and a control electrically connected to a corresponding light emitting line among the light emitting lines to which the first control signal is applied a second control transistor comprising an electrode; and
a first discharge transistor including an input electrode receiving the fourth voltage, an output electrode electrically connected to the anode of the organic light emitting diode, and a control electrode receiving a second control signal,
The first discharge transistor applies the fourth voltage to the anode of the organic light emitting diode. The organic light emitting diode display of claim 2 , wherein the second control signal includes a second scan signal applied to a scan line subsequent to the corresponding scan line. The method of claim 2, wherein the circuit unit,
an input electrode receiving the third voltage having a voltage lower than a voltage of the data signal applied to the corresponding data line, an output electrode electrically connected to the first node, and a control electrode receiving a third control signal; and a second discharge transistor configured to apply the third voltage to the first node. The organic light emitting diode display of claim 4 , wherein the third control signal includes a third scan signal applied to a scan line preceding the corresponding scan line. 5. The method of claim 4, wherein the circuit unit,
a third control including an input electrode electrically connected to the second node, an output electrode electrically connected to the input electrode of the driving transistor, and a control electrode receiving the first control signal applied to the corresponding light emitting line An organic light emitting display device further comprising a transistor. The method of claim 1, wherein the discharge voltage generator comprises a first discharge voltage generator that generates the fourth voltage;
The first discharge voltage generator includes an inverting input terminal for receiving a first reference voltage, a non-inverting input terminal for receiving a second reference voltage corresponding to the second voltage, and a combination of the first reference voltage and the second reference voltage. and a differential amplifier including an output terminal for outputting a voltage difference as the fourth voltage. The method of claim 1, wherein the discharge voltage generator comprises a second discharge voltage generator that generates the third voltage;
The second discharge voltage generator includes a plurality of resistors connected in series between the first voltage and the second voltage and includes a voltage divider circuit for outputting the third voltage divided from the plurality of resistors connected in series organic light emitting display device. The organic light emitting display device of claim 1 , wherein the second voltage is in a range of -4V to -2V. The organic light emitting diode display as claimed in claim 1 , wherein the potential difference between the second voltage and the fourth voltage is smaller than an emission threshold voltage of the organic light emitting diode. an organic light emitting diode including an anode and a cathode for receiving a second voltage; and
a circuit unit receiving a first voltage, applying a fourth voltage to the anode before the organic light emitting diode emits light during a frame period, and receiving a third voltage different from the fourth voltage;
The fourth voltage is maintained to have a constant potential difference between the second voltage and the frame period. The method of claim 11, wherein the circuit unit,
and a control electrode, an input electrode, and an output electrode electrically connected between the second node to which the first voltage is applied and the anode of the organic light emitting diode and electrically connected to the first node to which the third voltage is applied. a driving transistor;
a switching transistor comprising an input electrode for receiving a data signal, an output electrode electrically connected to the input electrode of the driving transistor, and a control electrode for receiving a scan signal;
a storage capacitor electrically connected between the first node and the second node;
a first control transistor including an input electrode electrically connected to the output electrode of the driving transistor, an output electrode electrically connected to the first node, and a control electrode for receiving the scan signal;
a second control transistor including an input electrode electrically connected to the output electrode of the driving transistor, an output electrode electrically connected to the anode of the organic light emitting diode, and a control electrode for receiving a first control signal; and
a first discharge transistor including an input electrode receiving the fourth voltage, an output electrode electrically connected to the anode of the organic light emitting diode, and a control electrode receiving a second control signal,
wherein the first discharge transistor applies the fourth voltage to the anode of the organic light emitting diode before the organic light emitting diode emits light during the frame period. 13. The method of claim 12, wherein the circuit unit
A second discharge transistor comprising an input electrode receiving the third voltage, an output electrode electrically connected to the first node, and a control electrode receiving a third control signal,
The second discharge transistor applies the third voltage to the first node before the organic light emitting diode emits light during the frame period. 14. The method of claim 13, wherein the circuit portion
and a third control transistor including an input electrode electrically connected to the second node, an output electrode electrically connected to the input electrode of the driving transistor, and a control electrode for receiving the first control signal. The pixel of claim 11 , wherein the second voltage is in a range of -4V to -2V. The pixel of claim 11 , wherein the potential difference between the second voltage and the fourth voltage is smaller than an emission threshold voltage of the organic light emitting diode. The pixel of claim 12 , wherein the third voltage is lower than a voltage of the data signal.

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