KR102322025B1 - 3d nand memory device and operation thereof - Google Patents

Abstract

The present invention relates to three-dimensional memory devices and methods for programming such devices, and more particularly to applying a first control voltage to a selection of horizontal structures in response to an indicator memory, and applying a second control voltage to the It relates to memory devices having control circuitry for applying a third control voltage to unselected horizontal structures and applying a third control voltage to the excluded ones of the horizontal structures.

Description

3D NAND memory device and its operation {3D NAND MEMORY DEVICE AND OPERATION THEREOF}

FIELD OF THE INVENTION The present invention relates to high-density memory devices, and more particularly to memory devices in which multiple planes of memory cells are arranged to provide a three-dimensional (3D) array.

As the critical dimensions of devices in integrated circuits shrink to the limits of conventional memory cell technologies, designers are turning to techniques for stacking multiple planes of memory cells to implement greater storage capacity and lower cost per bit. have been considering See, for example, "A Multi-Layer Stackable Thin-Film Transistor (TFT) NAND-Type Flash Memory," by Lai et al., wherein thin film transistor technologies are incorporated herein by reference. "(IEEE Int'l Electron Devices Meeting, 11-13 Dec. 2006); and Jung et al. “Three Dimensionally Stacked NAND Flash Memory Technology Using Stacking Single Crystal Si Layers on ILD and TANOS Structure for Beyond 30 nm Node)” (IEEE Int'l Electron Devices Meeting, 11-13 Dec. 2006, 20).

Also, cross-point array technologies are described in Johnson et al. "512 Mb PROM With a Three-Dimensional Array of Diode/Anti-fuse memory cells" ( IEEE J. of Solid-State Circuits, vol. 38, No. 11, November 2003) for anti-fuse memory. In the design described in Johnson et al., multiple layers of word lines and bit lines are provided with memory elements at the intersections. The memory elements include a p+ polysilicon anode coupled to the word line and an n-polysilicon cathode coupled to the bit line, the anode and cathode separated by an antifuse material.

In the processes described by Lai et al., Jung et al. and Johnson et al., there are several critical lithography steps for each memory layer. Thus, the number of critical lithographic steps required to fabricate the device is multiplied by the number of layers implemented. Accordingly, although higher density advantages are realized using 3D arrays, higher manufacturing costs limit the use of the technology.

Another architecture providing vertical NAND cells for charge trapping memory technology is "Bit Cost Scalable (BiCS) Technology with Punch and Plug Process for Ultra High Density" by Tanaka et al. Flash Memory)" (5, 2007 Symposium on VLSI Technology Digest of Technical Papers; 12-14 Jun. 2007, pages: 14-15). The structure described in Tanaka et al. is a multi-gate field effect transistor with vertical channels that behave similarly to NAND gates to create storage sites at each gate/vertical channel interface using a silicon-oxide-nitride oxide-silicon (SONOS) charge trapping technique. includes structure. The memory structure is based on pillars of semiconductor material arranged as vertical channels for a multi-gate cell having a bottom select gate adjacent the substrate and a top select gate on top. A plurality of horizontal control gates are formed using planar electrode layers crossing the pillars. The planar electrode layers used for the control gates do not require critical lithography, thereby reducing cost. However, many critical lithography steps are required for each vertical cell. There is also a limit to the number of control gates that can be layered in this way, which is determined by factors such as the conductivity of the vertical channel, program and erase processes used, and the like.

Another structure that provides vertical NAND cells for charge trapping memory technology is "Pipe BiCS Flash Memory with 16 Stacked Layers and Multi-Layer Level Cell Operation for Ultra-Density Storage Devices" by Katsumata et al., which is incorporated herein by reference. Pipe-shaped BiCS Flash Memory with 16 Stacked Layers and Multi-Level-Cell Operation for Ultra High Density Storage Devices)” (2009 Symposium on VLSI Technology Digest of Technical Papers, 2009). The structure described in Katsumata et al. includes a gate-all-around memory cell structure similar to BiCS, but the P-BiCS has a back gate to reduce parasitic resistance at the bottom. has a U-shaped NAND string. The select gate further has asymmetric source and drain structures to reduce off-current.

Although 3D stacked memory structures retain the prospect of significantly increased memory density, they, among other things, require etching very deep holes through many layers and critical processes such as filling semiconductor material and multiple dielectric layers to form the pillars. brings challenges. Such "punch and plug" processes are difficult to form a uniform shape or diameter of the pillars from the top to the bottom. Also, the thickness of the dielectric charge trapping structure changes with the pillar shape. Changes in shape and dielectric thickness increase the tail distribution of the threshold voltages of the memory cells, which leads to poor switching behavior and low reliability of the memory cells. Moreover, when the pass voltages are applied to the unselected word lines, the memory cells in the narrower portion of the non-uniform pillar not only suffer from electric field enhancement, but are also affected by the Vpass fluctuation.

Accordingly, it would be desirable to provide a 3D memory device and method of operation that can reduce the negative effects of non-uniform pillars on the device and can change the density of the device after a manufacturing process.

Briefly described, a memory device includes: a plurality of horizontal structures on a substrate including a conductive material, a semiconducting material, or both; a plurality of vertical structures disposed orthogonally to the plurality of horizontal structures and including a conductive material, a semiconducting material, or both; a plurality of memory cells positioned at intersections between the plurality of vertical and horizontal structures; an indicator memory programmable to indicate whether any of the horizontal structures are excluded from use during operation, for example, due to detection of defects that may affect the reliability of the memory cells within the indicated level; and a control circuit unit coupled to the horizontal structures, wherein the control circuit unit applies a first control voltage to selected ones of the horizontal structures in response to the indicator memory for reading and writing of the memory device; , a second control voltage is applied to the unselected of the horizontal conductive structures, and a third control voltage is applied to the excluded of the horizontal structures.

The foregoing summary of the invention is provided to provide a basic understanding of some aspects of the invention. The above summary is not intended to identify key or critical elements of the invention or to delineate the scope of the invention. Its sole purpose is to present some concepts of the invention in a simplified form as a prelude to the more detailed description that is presented later. Certain aspects of the invention are set forth in the claims, specification and drawings.

According to the present invention, a three-dimensional memory device capable of reducing the negative influence of non-uniform pillars on a memory device and changing the density of the memory device after a manufacturing process is provided, and an operating method thereof.

BRIEF DESCRIPTION OF THE DRAWINGS The invention will be described with reference to the drawings, specific embodiments thereof, in which:
1 is a simplified chip block diagram of an integrated circuit 175 including aspects of embodiments.
2 is a horizontal cross-sectional view of a column of memory cells in accordance with embodiments.
3 is a perspective view of a 3D vertical channel memory device.
4A and 4B show vertical cross-sectional views of a portion of the structure of FIG. 3 according to process variations.
5 is a schematic circuit diagram of a block of memory incorporating aspects of the present invention.
6 is a timing diagram of a program operation according to an exemplary embodiment.

The following description is presented to enable any person skilled in the art to make and use the present invention, and is provided in the context of specific applications and their requirements. Various modifications to the disclosed embodiments will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other embodiments and applications without departing from the spirit and scope of the invention. Accordingly, it is not intended that the invention be limited to the embodiments shown, but is to be accorded the widest scope consistent with the principles and features disclosed herein.

1 is a simplified chip block diagram of an integrated circuit 175 including aspects of embodiments. The integrated circuit 175 includes an indicator memory that identifies levels in the three-dimensional memory that are excluded from use during operation of the three-dimensional (3D) memory array 160 and the device implemented as described herein. (192).

The address decoder 156 includes a row decoder 161 , a column decoder 166 , and a level decoder 158 . The row decoder 161 is connected to a plurality of SSLs 162 arranged along columns in the memory array 160 . The column decoder 166 is coupled to a plurality of bit lines 164 arranged along rows in the memory array 160 for reading and programming data from the memory cells in the array 160 . Page buffers 163 are connected to data input circuits and data output circuits via lines 171 and 167 , and to read data from and write data to the memory array 160 . connected to a plurality of bit lines 164 arranged along the rows in 160 . Addresses are supplied to the page buffers via bus lines 165 by the address decoder 156 . In another embodiment, the page buffers may be integrated with the column decoder 166 . The level decoder 158 is coupled to a plurality of levels in the memory array 160 via word line connectors 159 . The indicator memory 192 is connected to the address decoder 156 and/or the controller, and stores information indicating the excluded level(s). In still other embodiments, the indicator memory 192 may be included in the address decoder 156 . The indicator memory 192 may be configured in the form of a mask that obscures the levels in the 3D blocks while indicating that the hidden levels require biasing designed for the excluded levels.

Other circuitry 174 may be included on the chip to support mission functions utilizing the memory. In this example, a controller implemented as a state machine 169 is a voltage in block 168, such as the voltages to read, erase, program, erase confirm, and program verify to perform the various operations described herein. Provides signals that control the application of bias arrangement supply voltages generated or provided through the supply or supplies. A configuration register 191 is coupled to the state machine 169 to set the voltage levels to be applied to the program, erase and read operations, and to set the voltage levels to be applied to the excluded levels. The controller may be implemented using a dedicated logic circuit, as is known in the art. In alternative embodiments, the controller comprises a general purpose processor, which may be implemented on the same integrated circuit, and executes a computer program that controls operations of the device. In still other embodiments, a combination of dedicated logic circuitry and a general-purpose processor may be utilized for implementation of the controller. The controller may disable the other circuitry 174 and the function of the state machine 169 to vary the voltages via a voltage supply or supplies within the block 168 .

2 illustrates a horizontal cross-section of a column of memory cells in accordance with embodiments. The structure comprises a stack of alternating active levels of insulating structures 215, eg, a central core of semiconductor material extending vertically through an alternatingly deposited word line layer and an insulating layer ( and a pillar 15 having 210 . The core 210 may have a center-through seam 211 resulting from a deposition technique. For example, a dielectric charge trapping structure comprising a first layer 212 of silicon oxide, a layer 213 of silicon nitride and a second layer 214 of silicon oxide (referred to as ONO), or other multi-layer dielectric charge A trapping structure may surround the core 210 . Series connected memory cells are located at intersections between the pillar and each of the active levels. Because of variations in the diameter of the pillar at the levels of the structure, for example, memory cells in some levels may have performance characteristics that fall outside the acceptable range making their use to an unreliable or impossible level. have. Such levels may be indicated by programming the indicator memory and then excluding them from data storage operations.

3 is a perspective view of a 3D vertical channel memory device. It comprises a plurality of active levels (11) each parallel to the substrate, for example word line layers and a plurality of pillars (15) oriented orthogonal to the substrate, each of said pillars comprising said pillars and a plurality of series-connected memory cells positioned at intersections between the active levels. A plurality of string select lines (SSL) 12 are parallel to the substrate and oriented above the active levels 11 , and each of the string select lines intersects a respective column of the pillars. Each intersection of a pillar and a string select line defines a string select gate (SSG) of the pillar. The structure is also oriented parallel to the substrate, and ground select lines (GSLs) 13 (sometimes referred to as lower select lines) forming a layer below the active levels 11, which are at the lower end of the pillar located) are included. Each intersection of pillar and ground select line 13 defines a ground select gate (GSG) (sometimes referred to as a bottom select gate (LSG)) of the pillar. A common source line (CSL) 10 is parallel to the substrate and is formed in a layer below the GSLs. The structure also includes a plurality of parallel bit lines 20 in a layer parallel to the substrate and above the string select lines. Each of the bit lines 20 overlaps a respective row of the pillars, and each of the pillars 15 underlies one of the bit lines. The pillars 15 may be configured as described above with respect to FIG. 2 .

3 , the memory device includes a stairstep contact structure with respect to the active levels. A deep etch is done through the structure to form contacts 22 connecting the active level connection regions 26A, 26B to the metal interconnects 24 thereon. Each of the connection regions 26A or 26B defines a block of memory cells. Accordingly, respective GSL connection areas 28A, 28B are provided. Thus, to read data from a particular block of memory, the control circuitry activates the active level connection regions 26A, 26B to select a particular block of cells and a particular layer of the stack, and select a string to select a particular column. Line 12 is further activated. The ground select gate is also activated. A row of cells is then read out in parallel through the bit lines 20 into a page buffer (not shown) (as used herein, "activate" means to connected cells or switches). It means to apply a specific bias to give it an effect (the bias can be high or low depending on the memory design). Depending on the specifications and design of the product, the page buffer may hold two or more columns of data, in which case a full page read operation may involve successive activation of two or more SSLs 12 . .

With a punch and plug process, the pillars are formed perpendicularly through all the semiconducting layers, which connect the plurality of active levels 11 , SSLs 12 and GSLs 13 . include It is very important to form pillars having a uniform width from the top to the bottom. The higher the aspect ratio of the pillar, the less uniform the width of the pillar. Changes in the widths of the pillar result in changes in the threshold voltages. The lowermost layer of the semiconducting layer is the GSL, and the intersection of the pillars and the GSLs is a ground select gate (GSG), which is performed as a switch to select each pillar. Above the GSL are the active levels, and the intersection of the pillar and the active levels are memory cells. The GSL located within the bottom layer may have the smallest pillar width, but since all of the GSGs are at the same level, the distribution of threshold voltages of the GSGs will not be significantly affected by the width change. In contrast, memory cells are located at different levels, and the threshold voltages may be affected by the pillar width or diameter or other characteristics.

With the changes in the pillar, the distribution of the threshold voltages may be widened, so that tail bits are generated. In general, the memory cells in the array undergo process variations, resulting in threshold voltages distributed in a Gaussian or normal distribution. Memory cells do not follow the normal distribution, resulting in tails within the programmed and erased threshold voltage distribution. These bits are referred to as tail bits, and they affect the reliability of the memory.

4A and 4B show vertical cross-sections of a portion of the structure of FIG. 3 as a result of manufacturing process variations. In FIG. 4A , the width of the pillar decreases sharply, particularly around the lowermost active levels 11 in the block 111 . As a result of the narrower width in block 111, tail bits with larger threshold voltages may be generated. To prevent these tail bits from affecting the reliability of the memory, the active level in the block 111 is marked as excluded. In the memory device, the width of the pillar crossing the exclusion of the active levels may be smaller than the width of the pillar crossing the selected and unselected active levels, which is an operating characteristic causing the tail bit problem. can bring about changes in

In another example, as shown in FIG. 4B , the width of the pillar is gradually decreased from the top to the bottom. Thus, the difference in the width of the pillar around the top and bottom active levels (see blocks 112 and 113 ) will broaden the distribution of the threshold voltages to have tail bits with higher threshold voltages. Likewise, the active levels in blocks 112 and 113 may be marked as excluded levels to avoid tail bits resulting from a wide distribution resulting in a narrower or wider width of the pillar.

5 is a schematic circuit diagram of a block of memory incorporating aspects of the present invention. As shown, the block of memory includes an N _{N ×P} number of strings 615 of series-connected memory cells 604 . Each string 615 has N _M number of memory cells 604 . Each of the memory cells 604 is structured as shown in FIG. 1 and electrically includes a source, a drain and a control gate. Because of the electrical compatibility of the source and drain in many transistors, these two terminals are sometimes collectively referred to herein as "current path terminals".

Each of the strings 615 also includes a string select gate 606 and a ground select gate 608 coupled in series on opposite sides of the memory cells 604 of the string. The string select gate 606 is for string select, and the ground select gate 608 prevents cell current through the string during a program operation. More specifically, each string select gate 606 and ground select gate 608 functions as the control gate electrodes, which are current path terminals of the string.

The block of memory device includes separate active levels 611 of _{N WL} corresponding to each of the memory cells 604 in a string 615 . Each of the active levels 611 functions as a control gate electrode of the corresponding memory cell 604 at a level within every string 615 in the block. The active levels are coupled to the controller responsive to the indicator memory to identify the excluded levels. A memory device as described herein includes an indicator memory that can be programmed to ascertain whether any of the above active levels are excluded. The indicator may identify the same excluded levels in all blocks of the memory device or other excluded levels in each block of the memory device.

_{The block of memory device includes separate string select lines 612 of N SSL} coupled to the SSL decoder, which serve as control gate electrodes of the corresponding string select gates 606 .

The block of memory device _{includes separate bit lines of N BL} , which are coupled to one of the current path terminals of the corresponding string select gates 606 .

The block of the memory device includes a ground select line (GSL). The GSL is the control gate electrode of all ground select gates 608 in the block.

In an alternative embodiment, the block of memory device may include one or more ground select lines, and the ground select gates 608 in the memory may include a different N _GSL >1 number of ground select gates 608. divided into distinct non-null subsets of For example, when N _GSL =2, each subset of ground select gates 608 includes half of the ground select gates of the strings 615 . The separate ground select lines of each N _GSL are the control gate electrode of all the ground select gates in a corresponding one of the subsets of ground select gates 608 .

5, the pages are made up of the N × N _{SSL BL} bit block consists of bits of the _BL N × N × N _{SSL WL.} When the indicator memory indicates that WL _M is excluded, the block of the memory device _{identifies one active level WL M} to be excluded, and the number of bits in the block is N _BL × N _SSL × (N _WL -1) is reduced to The indicator memory _M WL and WL _{M -} the number of _1, the active level of the WL and WL _{M -1} and _M check, bits in the block that is excluded the case indicated that the block of the memory device is to exclude the N _It is reduced to BL × N _SSL × (N _{WL -2).} The density of the block may be adjusted by ascertaining the number of excluded active levels. The excluded level need not be the lowest active level, but may be any of the active levels. _{If a memory device defines the number of active levels of N EX} excluded in all blocks, the density of the memory device becomes N _BL ×N _SSL ×(N _WL -N _EX )×N _BLOCK . When N _EX ≧2, the excluded levels may be active levels arranged in series, or active levels arranged randomly.

In another alternative embodiment, the indicator memory may indicate 1/2, 1/4 or 1/8 of the excluded active levels.

The indicator memory includes an electrically programmed fuse (eFuse), flash, ROM, RAM or the like.

Control circuitry is coupled to the active levels. In the operation of reading or programming the 3D memory device, the control circuit unit applies a first control voltage to selected ones of the active levels in response to the indicator memory, and applies a second control voltage to unselected ones of the active levels. , and a third control voltage is applied to the negative of the active levels.

The first, second and third control voltages are different. The first control voltage is the program or read voltage applied to the selected active level. The second control voltage is the pass voltage (Vpass) applied to the unselected active levels. The third control voltage is a selective pass voltage V'pass applied to the excluded level.

The third control voltage may be adjusted in response to a time period or number of cycles according to information on the operating time or cycles stored in the configuration register. For example, the state machine may receive signals from the configuration register and may change the third control voltage after the memory device has operated, eg, one year or 1K cycles.

The memory device may include a plurality of horizontal structures on a substrate; a plurality of vertical structures arranged orthogonally to the plurality of horizontal structures; a plurality of memory cells positioned at intersections between the plurality of vertical and horizontal structures; an indicator memory programmable to ascertain whether any of the horizontal structures are excluded; and control circuitry coupled to the plurality of horizontal structures, wherein for reading or writing of the memory device, the control circuitry in response to the indicator memory applies a first control voltage to selected ones of the horizontal lines; , a second control voltage is applied to the unselected of the horizontal lines, and a third control voltage is applied to the negative of the horizontal levels.

The indicator memory is also used to erase the memory device.

In one embodiment, such as a 3D vertical channel structure, the plurality of horizontal structures may include a conductive material, a semiconducting material, or both, and the plurality of horizontal structures may be the active levels, such as word lines. The plurality of vertical structures may include a conductive material, a semiconducting material, or both, and the plurality of vertical structures may be the pillars.

In an alternative embodiment, such as a 3D vertical gate structure, the plurality of horizontal structures may include a conductive material, a semiconducting material, or both, wherein the plurality of horizontal structures may be the active levels, such as bit lines. . The plurality of vertical structures may include a conductive material, a semiconducting material, or both, and the plurality of vertical structures may be word lines.

Referring to FIG. 5 , a description of a programming operation in which a target cell is marked cell A and the excluded active level is WLM _{M is described.} Prior to programming, the entire block is erased to lower the threshold voltage to an erase voltage at which the NAND can be at a voltage level lower than zero. During the program pulse for the selected cell A, the selected bit line BL ₂ receives a bias of about 0V, and the unselected bit lines BL ₁ and BL ₃ -BL _N receive inhibit bias voltages. do. Similarly, the selected string select line SSL ₂ receives a bias of about 3V, and the unselected string select lines SSL ₁ and SSL ₃ -SSL _P receive inhibit bias voltages. The selected active level WL ₁ receives the program pulse, the unselected active levels WL ₂ -WL _M-1 receive the pass voltages Vpass, and the excluded active level WL _M receives the Vpass The NAND string is turned on by receiving a different pass voltage V'pass.

The path voltage fluctuation problem in 3D NAND is larger than in 2D NAND because the number of path voltage fluctuations is proportional to the number of SSLs. The Vpass level must be higher than the threshold voltage, but lower than for programming the cell. Due to changes in the pillar width, the V'pass may be higher than the Vpass since the threshold voltages of the cells in the excluded active levels may be higher than that of cells in the unselected active levels. . However, a higher pass voltage will cause larger fluctuations, and cells with smaller pillar widths are more easily affected by the pass voltage fluctuations. If the fluctuation is sufficient to change the threshold voltages of the fluctuated cells from the low threshold voltage to the high threshold voltage, then cells in the excluded level are erased to have a negative threshold, V'pass lower than Vpass becomes the result of

The read operation is similar to the programming operation in determining the pass voltages Vpass and V'pass to reach the pass voltage variation and to be applied to the unselected active levels and excluded levels.

6 is a timing diagram of a programming operation executed at three intervals in accordance with this embodiment.

At the beginning of phase T1, the circuitry applies a voltage sufficient (eg, 4.5V) to turn on the unselected SSLs switches and applies a low voltage of about 0V to turn on the selected SSL switches. approve The selected WL remains at about 0V as in the case of the unselected WLs and GSL. The circuitry also applies about 3 volts to the selected and unselected bit lines. Since the cells are erased to have a negative threshold voltage before this phase, the pass voltage V'pass applied to the excluded active level has a potential of about 3V sufficient to turn on cells in the excluded level. is in At the end of phase T1, the unselected SSLs and the selected bit lines return to about 0V, while the voltages on the excluded WL remain at the pass voltage V'pass of about 3V. In one embodiment, phase T1 may last for about 5 μs.

In phase T2, the circuitry applies about 4.5V to the SSL line to turn on the selected SSL switch. The selected bit line remains at about 0V as in the case of unselected WLs, GSLs and unselected SSLs. The unselected bit lines remain at about 3V. This allows current to flow in the strings connected to the selected bit lines, while blocking current flow in the strings connected to the unselected bit lines. At the end of phase T2, the voltage on the selected SSL is reduced to about 3V. In one example, phase T2 may last for about 5 μs.

At the beginning of phase T3, the voltage on the selected word line level is boosted to a program potential (program pulse) of about 20V. The pass voltage is lower than would be required to program the cell A. In this example, the pass voltage Vpass on the unselected WLs may be 9V, and the pass voltage V'pass on the excluded WLs may be 3V. During phase T3, cell A is programmed. In one embodiment, phase T3 may last for about 10 μs.

A method for reading or programming a three-dimensional device comprising active levels as shown in FIG. 5 and pillars extending through the active levels is described, the method comprising applying a first control voltage to a selected one of the active levels. applying a second control voltage to the unselected of the active levels, and applying a third control voltage different from the second control voltage to the excluded of the active levels. In this method, the second control voltage turns on memory cells at intersections between the pillars and the unselected of the active levels, and the third control voltage is excluding the pillars and the active levels. turns on the memory cells at the intersections between The method further includes programming the indicator memory with an indication of the excluded active level. It is applied in response to an indicator memory confirming the excluded active level. The indicator is also used to clear the 3D device.

The first, second and third control voltages are different. The first control voltage is the program or read voltage applied to the selected active level. The second control voltage is the pass voltage Vpass applied to all the unselected active levels. The third control voltage is a selective pass voltage V'pass applied to the excluded level.

The foregoing description of embodiments of the present invention is provided for purposes of illustration and description. It is not intended to be exhaustive or to limit the invention to the precise forms disclosed. Obviously, many modifications and variations will be apparent to those skilled in the art. For example, although embodiments herein have been described using vertical channel charge storage memory cells, pillars having other types of memory cells may also utilize aspects of the present invention, although not necessarily implementing all of the aforementioned advantages. can In particular, without limitation, any or all modifications disclosed, suggested, or incorporated by reference in the background portion of this patent application may be specifically incorporated by reference in the description of embodiments of the invention herein. Also, any and all modifications described, shown, or incorporated herein by reference to any one embodiment are to be considered guidelines for all other embodiments. The embodiments set forth herein were chosen and described in order to best explain the principles of the invention and its practical applications, and thus those skilled in the art will recognize the various embodiments as appropriate for the particular use contemplated and for those skilled in the art. The present invention may be understood with various modifications as such. It is intended that the scope of the present invention be defined by the following claims and their equivalents.

10: Common source line 11: Active level
12: String selection line 13: Ground selection line
15: pillar 20: beat line
22: Contact 24: Metal Interconnect
26A, 26B: Active level connection area 28A, 28B: GSL connection area
156: address decoder 158: level decoder
160: memory array 161: row decoder
162: string selection line 163: page buffer
164: bit line 165: bus line
166: column decoder 169: state machine
174: other circuit part 175: integrated circuit
191: Configuration register 192: Indicator memory
210: core 211: core
212: first layer of silicon oxide 213: layer of silicon nitride
214: silicon oxide second layer 215: insulating structure
604: memory cell 606: string select gate
608: Ground select gate 611: Active level
615: String

Claims (20)

A memory device comprising:
a plurality of horizontal structures on a substrate, the plurality of horizontal structures comprising a conductive material, a semiconductive material, or both;
a plurality of vertical structures disposed orthogonally to the plurality of horizontal structures, wherein the plurality of vertical structures include a conductive material, a semi-conductive material, or both;
a plurality of memory cells located at intersections between the plurality of vertical and horizontal structures;
an indicator memory indicating whether any of the horizontal structures are excluded;
and a control circuit connected to the plurality of horizontal structures,
For reading or programming of the memory device, the control circuitry in response to the indicator memory applies a first control voltage to selected ones of the horizontal structures and applies a second control voltage to unselected ones of the horizontal structures; , applying a third control voltage to the exclusion of the horizontal structures,
and a width of the vertical structures intersecting the excluded of the horizontal structures is less than a width of the vertical structures intersecting the selected and unselected of the horizontal structures. The apparatus of claim 1, wherein the first, second and third control voltages are all different. 2. The apparatus of claim 1, wherein the second control voltage is applied to all unselected horizontal structures. The apparatus of claim 1 , wherein the first control voltage comprises a program voltage or a read voltage. delete 2. The apparatus of claim 1, wherein the plurality of horizontal structures comprises word lines. 7. The apparatus of claim 6, wherein the plurality of vertical structures comprises pillars. 2. The apparatus of claim 1, wherein the plurality of horizontal structures comprises bit lines. 9. The apparatus of claim 8, wherein the plurality of vertical structures comprises word lines. In a semiconductor device,
a plurality of active levels;
a plurality of pillars extending vertically through the plurality of active levels;
a plurality of series-connected memory cells positioned at intersections between the plurality of pillars and the active levels; and
a control circuit connected to the plurality of active levels;
For reading or programming of the semiconductor device, the control circuit unit applies a first control voltage to selected ones of the active levels, applies a second control voltage to unselected ones of the active levels, and applies a third control voltage to apply to the exclusion of the active levels;
The semiconductor device according to claim 1, wherein a width of a pillar of the excluding of the active levels is smaller than a width of a pillar of the selected or unselected active levels. 11. The apparatus of claim 10, further comprising an indicator memory indicating whether any of the active levels are excluded. 11. The apparatus of claim 10, wherein the first, second and third control voltages are all different. 11. The apparatus of claim 10, wherein the second control voltage is applied to all unselected active levels. 12. The apparatus of claim 11, wherein the control circuitry applies the third control voltage to the minus of the active levels in response to the indicator memory. 11. The apparatus of claim 10, wherein the excluded active level comprises a topmost layer or a bottommost layer within the plurality of active levels. delete A method for reading or programming a three-dimensional device having active levels and pillars extending through the active levels, the method comprising:
applying a first control voltage to a selected one of the active levels;
applying a second control voltage to the unselected of the active levels; and
applying a third control voltage different from the second control voltage to the exclusion of the active levels;
The second control voltage turns on memory cells at intersections between the pillars and the unselected of the active levels, and the third control voltage turns on the memory cells at the intersections between the pillars and the excluded of the active levels. turn on the memory cells in the
and the width of the pillar of the excluded of the active levels is less than the width of the pillar of the selected and unselected active levels. 18. The method of claim 17, wherein the second control voltage is applied to all unselected active levels. 18. The method of claim 17, wherein the third control voltage is applied in response to an indicator memory that identifies the excluded active level. 18. The method of claim 17, further comprising programming an indicator memory with an indication of the excluded active level.

Images