KR102306249B1 - Semiconductor apparatus and readout method - Google Patents

Abstract

Provided is a semiconductor device for compensating for the reset of a latch circuit while achieving high-speed data output. A reading method of a NAND-type flash memory of the present invention includes the steps of: precharging a bit line and a NAND string connected to the bit line through a sense node (SNS); resetting a latch circuit after the precharging; and, after the resetting, discharging the NAND string.

Description

Semiconductor device and readout method

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device including a flash memory and the like, and more particularly, to a continuous reading operation of a page.

The NAND-type flash memory is equipped with a continuous read function (burst read function) for sequentially reading a plurality of pages in response to an external command. The page buffer/sense circuit includes, for example, two latches, and enables output of data held in the other latch while holding data read from the array in one latch when consecutive read operations are performed (For example, Patent Documents 1, 2, 3, etc.).

Japanese Laid-Open Patent Publication No. 5323170 Japanese Laid-Open Patent Publication No. 5667143 US Patent Application US2014/0104947A1

Fig. 1 shows a schematic configuration of a NAND-type flash memory equipped with an on-chip ECC function. The flash memory includes a memory cell array 10 including a NAND string, a page buffer/sense circuit 20 , data transfer circuits 30 and 32 , an error detection and correction circuit (hereinafter referred to as an ECC circuit) 40 and , and an input/output circuit 50 . The page buffer/sense circuit 20 includes two latches L1 and L2 (one latch, for example, 4 KB) for holding read data or input data to be programmed, and the latches L1 and L2 are Each includes a first cache (C0) and a second cache (C1) (one cache, for example, 2KB).

Fig. 2 shows a timing chart when consecutive reading of a plurality of pages is performed. 2 shows an example in which the page P0 is used as the start address. The start address can be selected arbitrarily. First, an array read of the page P0 is performed, and data of the page P0 is held in the first and second caches C0 and C1 of the latch L1 (P0C0 and P0C1). Subsequently, the data in the first and second caches (C0, C1) of the latch (L1) are transmitted to the first and second caches (C0, C1) of the latch (L2), and the first and second caches (C0, C1) When the data of C1) is ECC decoded by the ECC circuit 40 and an error is detected, the data of the first and second caches C0 and C1 of the latch L2 are corrected.

In continuous read, the row address counter is automatically incremented to read the next page P1, and the read data is transferred to the first and second caches C0 and C1 of the latch L1. In the meantime, the data of the first cache C0 of the latch L2 is transferred to the input/output circuit 50 , and the data held in the input/output circuit 50 is output in synchronization with the external clock signal ExCLK supplied from the outside. . Subsequently, the data of the second cache C1 of the latch L2 is output in synchronization with the external clock signal ExCLK from the input/output circuit 50 , and during this time, the data of the first cache C0 of the latch L1 is transferred to the latch It is transmitted to (L2) and ECC processing is performed by the ECC circuit (40).

While the second cache (C1) data of the latch (L1) is transferred to the latch (L2), and the first cache (C0) data of the latch (L2) is output from the input/output circuit 50, the second cache (C1) data of the latch (L2) 2 The cache (C1) data is ECC-processed, and then, while the second cache (C1) data of the latch L2 is output from the input/output circuit 50, the next page P2 is read from the array, and the latch L1 ) is transmitted to the first and second caches (C0, C1), and the first cache (C0) data is transmitted to the latch (L2) for ECC processing.

In this way, continuous reading of a page of the memory cell array is performed while data is output from the latch L2, and ECC processing of the second cache C1 is performed while data is output from the first cache C0, ECC processing of the first cache (C0) is performed while the second cache (C1) data is output.

Here, the read of the array is operated using the internal clock signal according to the determined timing, while the data output is operated by the external clock signal ExCLK asynchronous with the internal clock signal. Therefore, the continuous read operation has a limitation expressed in Equation (1) below.

tARRAY+tECC < Tdout … (One)

Here, tARRAY is a time required to read a selected page from the memory cell array, tECC is a time required for ECC processing of 1/2 page, and tDOUT is a time required to output all data of one page. tARRAY and maximum tECC (maximum time required for ECC decode operation and data correction) are constant times, and tDOUT is calculated by the frequency of the external clock signal ExCLK.

In order to read a large amount of data in a short time, it is necessary to increase the frequency of the external clock signal ExCLK. In this case, as shown in Equation (1), the time of tARRAY + tECC must be shortened. On the other hand, in the read operation, the latch L1 needs reset in order to more accurately receive the electric charge from the sense node, and the reset is performed before the pre-charge period of the bit line. In the continuous read operation, the reset of the latch L1 must be performed after the data of the latch L1 is transferred to the latch L2. That is, the reset of the latch L1 must be performed after the data of the latch L1 is transferred to the latch L2 and before the precharge period of the bit line for reading the next page. For this reason, if the start timing of tARRAY is to be advanced, there is a risk that the time for resetting the latch L1 may not be sufficiently secured. 2 , when the second cache C1 data of the page P2 of the latch L1 is transferred to the latch L2 is ts, the precharge of the bit line at the start timing of reading the array of the page P3 is ts. If the period until completion is tp, the latch L1 must be reset within the period tx. If the read start timing of the next page is advanced, the period tx may become shorter and the reset of the latch L1 may not be compensated for.

SUMMARY OF THE INVENTION An object of the present invention is to provide a semiconductor device and a readout method for compensating for reset of a latch circuit while solving such a conventional problem and achieving high-speed data output.

A method of reading a NAND-type flash memory according to the present invention includes the steps of precharging a bit line and a NAND string connected to the bit line through a sense node, and after precharging the node of the latch circuit to a reference potential through the sense node. and resetting the latch circuit by connecting to , and discharging the NAND string after the reset. Furthermore, the method of reading a NAND-type flash memory according to the present invention includes the steps of precharging a bit line and a NAND string connected to the bit line through a sense node; and resetting the latch circuit by electrically connecting to a reference potential through a node.

In some embodiments, the precharging comprises generating a precharge voltage at a voltage supply node, electrically connecting the voltage supply node to the sense node through a first select transistor, and selecting the sense node a second time. electrically connecting to a bit line through a transistor, wherein resetting comprises: generating the reference voltage with the voltage supply node; electrically connecting the voltage supply node to the latch circuit through the first select transistor and electrically isolating the sense node through the second transistor.

In some embodiments, each of the steps is performed in sequential reading of a page. In some embodiments, the sequential reading of the page holds data read from the selected page of the memory cell array in the latch circuit, transfers the data held in the latch circuit to another latch circuit, and then reads from the next selected page and holding the stored data in the latch circuit and continuously outputting the data held in the other latch circuit to the outside in synchronization with an external clock signal. In some embodiments, the continuous reading of the page further outputs the ECC-processed data of the second part to the outside while error detection/correction (ECC process) of the data of the first part of the other latch circuit is performed, and ECC-processing the data of the second part while outputting the ECC-processed data of the first part to the outside. In some embodiments, after outputting the ECC-processed data of the first part of the other latch circuit to the outside, the data of the next selected page of the first part of the latch circuit is transferred to the first part of the other latch circuit and outputting the ECC-processed data of the second part of the other latch circuit to the outside, and then transferring the data of the next selected page of the second part of the latch circuit to the second part of the other latch circuit. . In some embodiments, the continuous read is a first continuous read with a constraint expressed by tARRAY + tECC < tDOUT (the data of the first part and the second part are each 1/2 page of data, tARRAY is the time required to read the selected page , tECC is the time required to ECC processing 1/2 page, tDOUT is the time required to output all data of 1 page). In some embodiments, the continuous read is a second continuous read with a constraint expressed by tARRAY < tDOUT, tECC < tDOUT (1/2 page) (the data of the first part and the second part are each 1/2 page of data , tARRAY is the time required to read the selected page, tECC is the time required to ECC processing 1/2 page, tDOUT is the time required to output all data of 1 page, tDOUT (1/2 page) is the time required to ECC processing 1/2 page time required to output data). In some embodiments, the read timing of the selected page of the memory cell array is faster in the second continuous read compared to the first continuous read.

A semiconductor device according to the present invention includes a NAND type memory cell array, a reading unit for reading data from a selected page of the memory cell array, and an output unit for outputting the data read by the reading unit to the outside; The reading means includes a page buffer/sense circuit connected to the memory cell array through a bit line, and the reading means resets a latch circuit included in the page buffer/sense circuit when consecutive reading of pages is performed. It is performed between the pre-charge period of the line and the discharge period of the NAND string. Furthermore, the semiconductor device according to the present invention includes a NAND type memory cell array, a reading unit for reading data from a selected page of the memory cell array, and an output unit for outputting the data read by the reading unit to the outside. wherein the reading means includes a page buffer/sense circuit connected to the memory cell array through a bit line, and the reading means includes a latch circuit included in the page buffer/sense circuit when consecutive reading of pages is performed. The reset is performed during the discharge period of the NAND string after the bit line is precharged.

In some embodiments, the page buffer/sense circuit comprises a voltage supply node, a sense node, a latch circuit, a first select transistor connected between the voltage supply node and the sense node, and a second selection transistor connected between the sense node and a bit line. a second selection transistor, a third selection transistor connected between the sense node and the latch circuit; The latch circuit is reset by electrically connecting to the reference potential of the voltage supply node. In some embodiments, the reading means conducts the first and second selection transistors, makes the third selection transistor non-conductive, and precharges the voltage of the voltage supply node to the bit line. In some embodiments, when the reading means performs continuous reading of pages, the outputting means continuously outputs the read data in synchronization with an external clock signal. In some embodiments, the page buffer/sense circuit further includes another latch circuit for receiving data held in the latch circuit, and when the reading means performs continuous reading, the data of the other latch circuit is output data read from the next selected page of the memory cell array is held in the latch circuit. In some embodiments, the semiconductor device further includes an ECC circuit for performing error detection/correction of data, and the reading means is configured such that, when performing continuous reading, the data held in the first part of the other latch circuit is During ECC processing by the ECC circuit, the ECC-processed data held in the second portion of the other latch circuit is output.

According to the present invention, since the reset of the latch circuit included in the page buffer/sense circuit is performed between the pre-charge period of the bit line and the discharge period of the NAND string, the reset of the latch circuit is compensated for while increasing the data output speed. can do.

1 is a diagram showing a schematic configuration of a conventional NAND type flash memory.
Fig. 2 is a timing chart when sequential reading of pages is performed for a conventional NAND-type flash memory.
3 is a block diagram showing the configuration of a NAND-type flash memory according to an embodiment of the present invention.
4 is a diagram showing a configuration example of a NAND string of a flash memory according to an embodiment of the present invention.
5 is a diagram showing the configuration of a bit line selection circuit of a flash memory according to an embodiment of the present invention.
6 is a diagram showing the configuration of a page buffer/sensing circuit of a flash memory according to an embodiment of the present invention.
7 is a timing chart showing a reset operation of a latch circuit in a flash memory according to an embodiment of the present invention.
8 is a timing chart when a continuous reading operation of a page is performed according to an embodiment of the present invention.

EMBODIMENT OF THE INVENTION Next, embodiment of this invention is described in detail with reference to drawings. The semiconductor device according to the present invention is, for example, a NAND-type flash memory, or a microprocessor embedding such flash memory, a microcontroller, a logic, an ASIC, a processor for processing images or audio, a processor for processing signals such as radio signals, etc. etc. In the following description, a NAND-type flash memory is exemplified. In one embodiment, the NAND-type flash memory is equipped with an SPI (Serial Peripheral Interface) for compatibility with the NOR-type flash memory, and enables continuous reading of a plurality of pages in synchronization with an external clock signal.

[Example]

3 is a diagram showing the configuration of a NAND-type flash memory according to an embodiment of the present invention. The flash memory 100 according to the present embodiment includes a memory cell array 110 in which a plurality of memory cells are arranged in a matrix, is connected to an external input/output terminal, and outputs read data in response to an external clock signal ExCLK. An input/output circuit 120 for outputting or receiving data input from the outside, an ECC circuit 130 for generating a code of data to be programmed or error detection/correction of read data, and an input/output circuit 120 The address register 140 receives address data through the input/output circuit 120 , the controller 150 controls each unit based on the command data received through the input/output circuit 120 or a control signal applied to the terminal, and the address register 140 A word line selection circuit 160 that receives the row address information Ax, decodes the row address information Ax, and performs block selection or word line selection based on the decoding result, and the word line selection circuit 160 ) receives the column address information Ay from the page buffer/sensing circuit 170 for holding data read from the page selected by The column selection circuit 180 decodes the information Ay and selects columns in the page buffer/sense circuit 170 based on the decoding result, and various types of data necessary for reading, programming, and erasing data. and an internal voltage generating circuit 190 for generating voltages (base voltage Vpgm, pass voltage Vpass, read pass voltage Vread, erase voltage Vers, etc.).

The memory cell array 110 includes, for example, m memory blocks BLK(0), BLK(1), ..., BLK(m-1) arranged in the column direction. A plurality of NAND strings in which a plurality of memory cells are connected in series are formed in one memory block. As shown in FIG. 4, one NAND string NU includes a plurality of serially connected memory cells MCi (i=0, 1, ..., 31), a bit line side selection transistor TD, and a source line side selection transistor TS. The drain of the bit line side selection transistor TD is connected to one corresponding bit line GBL, and the source of the source line side selection transistor TS is connected to a common source line SL. The control gate of the memory cell MCi is connected to the word line WLi, and the gates of the bit line side select transistor TD and the source line side select transistor TS are respectively connected to the select gate lines SGD and SGS. The word line selection circuit 160 drives the bit line side selection transistor TD and the source line side selection transistor TS through the selection gate lines SGD and SGS based on the row address information Ax, and selects a block or a word. choose

The NAND string may be formed two-dimensionally on the substrate surface or may be formed three-dimensionally on the substrate surface. Further, the memory cell may be an SLC type that stores one bit (binary data) or an MLC type that stores many bits.

Fig. 5 shows the configuration of the bit line selection circuit. The same figure illustrates one page buffer/sense circuit 170 shared by one even bit line GBLe and one odd bit line GBLo, and a bit line selection circuit 200 connected thereto.

The bit line selection circuit 200 connects the transistor BLSe for selecting the even bit line GBLe, the transistor BLSo for selecting the odd bit line GBLo, and the virtual power VIRPWR to the even bit line GBLe. a transistor YBLe for connecting to , a transistor YBLo for connecting the virtual power supply VIRPWR to the odd bit line GBLo, and a NAND string between the even bit line GBLe and the source line SL. connected, and a NAND string is connected between the odd bit line GBLo and the source line SL. For example, in the read operation, the shield read is performed, the odd bit line GBLo is not selected when the even bit line GBLe is selected, and the even bit line GBLe is selected when the odd bit line GBLo is selected. This is not selected. The unselected bit line is connected to the GND level through the virtual power supply VIRPWR.

Fig. 6(a) shows the configuration of the page buffer/sensing circuit 170. As shown in Figs. The same figure shows one page buffer/sense circuit. For convenience, it is assumed that a signal applied to the gate of a transistor represents the transistor. The page buffer/sense circuit 170 includes two latches L1 and L2, and a transfer gate (transistor CACHE) is connected between the latches L1 and L2, and a latch is made by turning on the transfer gate. Bidirectional data transfer from (L1) to latch (L2) or from latch (L2) to latch (L1) becomes possible.

The latch L1 includes a pair of cross-coupled inverters, the node SLR1 of the latch L1 is connected to the common S/D of the transistor BLCD1 and the transistor DTG, and the node SLS1 is It is connected to the determination circuit 210 . The determination circuit 210 determines whether, for example, program verify or erase verify is appropriate. The transistor DTG becomes conductive when the voltage supply node V2 selectively charges the node SLR1 to Vdd or selectively discharges the node SLR1 to GND in the program verify or the like. Moreover, the latch L1 can short-circuit the nodes SLR1 and SLS1 by the transistor EQ.

Nodes SLR1 and SLS1 of latch L1 are respectively connected to nodes SLS2 and SLR2 of latch L2 through transistor CACHE. The node SLR2 of the latch L2 is connected to the sense node SNS through the transistor BLCD2, and the node SLS2 is connected to the transistor RESET2. Transistor RESET2 becomes conductive when latch L2 is reset. Also, the nodes SLS2 and SLR2 are connected to the differential sense amplifier SA through the data lines DL and /DL, and the output of the differential sense amplifier SA is connected to the input/output circuit 120 .

A transistor VG and a transistor REG are connected in series between the voltage supply node V2 and the sense node SNS, and a gate of the transistor VG is connected to S/D of the transistor DTG. The voltage supply node V1 is connected to the sense node SNS through the transistor BLPRE. The voltage supply node V1 supplies the internal supply voltage Vdd when precharging the bit line, and supplies the GND potential when resetting the latch L1, as will be described later. A transistor BLCN and a transistor BLCLAMP are connected in series between the sense node SNS and the node BLS of the bit line selection circuit 200 .

Fig. 6(b) shows the configuration of one inverter circuit constituting the latch L1. The inverter includes four transistors connected in series, that is, P-type transistors PT1 and PT2 and N-type transistors NT1 and NT2, and a latch enable signal is provided at each gate of the transistors PT1 and NT2. (/LAT1, LAT1) are inputted, respectively, and the voltage of the node SLS1/SLR1 is inputted to the common gate of the transistors PT2 and NT1. When the latch enable signal LAT1 is at H level, the inverter is operable, and when the latch enable signal LAT1 is at L level, the transistors PT2 and NT1 are disconnected from the internal supply voltage Vdd and GND. It enters a tri-state state, enabling inverter reset. Since the reset of the latch L1 is performed using a current path passing through the sense node SNS, the reset is performed when the sense node SNS is free, that is, when the sense node SNS does not adversely affect it.

The word line selection circuit 160 and the column selection circuit 180 (refer to FIG. 3 ) select a data read start position in a page according to the row address information Ax and the column address information Ay, or the row address and column Data is automatically read from the beginning of the page without using an address. Furthermore, the word line selection circuit 160 and the column selection circuit 180 may include a row address counter and a column address counter that increment a row address and a column address in response to a clock signal.

In the read operation of the flash memory, a certain positive voltage is applied to the bit line, a certain voltage (eg, 0V) is applied to the selected word line, and a pass voltage Vpass (eg, 4.5) is applied to the unselected word line. V), a positive voltage (for example, 4.5 V) is applied to the selection gate lines SGD and SGS, and the bit line side selection transistor TD and the source line side selection transistor TS are turned on to the common source line. Apply 0V. In the programming operation, a high-voltage programming voltage (Vpgm (15 to 20 V)) is applied to the selected word line, an intermediate potential (for example, 10 V) is applied to the unselected word line, and the bit line side selection transistor (TD) is applied. ) is turned on and the source line side selection transistor TS is turned off to supply a potential corresponding to the data of “0” or “1” to the bit line. In the erase operation, 0V is applied to the selected word line in the block, a high voltage (for example, 20V) is applied to the P well, electrons from the floating gate are removed from the substrate, and data is erased in block units.

Next, a continuous read operation of a plurality of pages of the flash memory according to the present embodiment will be described. When the controller 150 receives a command for continuous reading of pages through the input/output circuit 120 , the controller 150 controls continuous reading of a plurality of pages at the start address. Terminate reading. In the continuous page read operation, as described with reference to FIGS. 1 and 2 , data read from the selected page of the memory cell array is transferred to the latch L1 while data is output from the latch L2 . Data transfer from the latch L1 to the latch L2 is not performed in units of one page, but is divided into 1/2 pages (first or second cache), and one cache data of the latch L2 is stored in the input/output circuit 120 ) while being transmitted, the data in the other cache is processed in the ECC circuit 130 . Data transmitted to the input/output circuit 120 is outputted from the external input/output terminal to the outside in synchronization with the external clock signal ExCLK (eg, rising edge and falling edge). Reading data from the memory cell array and data transfer from the latch L1 to the latch L2 are performed based on an internal clock signal, and data transfer between the latch L2 and the input/output circuit 120 and the input/output circuit 120 ) is output based on the external clock signal ExCLK, and data transfer between the latch L2 and the ECC circuit 130 and the operation of the ECC circuit are performed using another internal clock signal or an external clock signal ExCLK. This is done based on the frequency-divided clock signal.

When a selected page of the memory cell array is read, the sense node SNS senses the potential of the selected bit line, and then, the charge of the sense node SNS is transferred to the node SLR1 of the latch L1 through the transistor BLCD1. is sent to The latch L1 determines data "1" if the transferred charge is equal to or greater than the threshold value, and data "0" if it is less than the threshold value, and holds the data. The latch L1 resets the potential of the node SLR1 to the GND level so that the charge transferred from the sense node SNS is accurately reflected. When the latch L1 is reset, the voltage supply node V1 is transitioned to GND, the transistor BLCD1 and the transistor BLPRE are conducted to electrically connect the node SLR1 to the voltage supply node V1. .

In the conventional continuous readout of the flash memory, the reset of the latch L1 is performed before the bit line precharge when the next page is read. However, the reset of the latch L1 must be performed after the data of the latch L1 is transferred to the latch L2, and if the data output speed is increased, the time for resetting the latch L1 cannot be sufficiently secured. is a concern. In order to avoid this, in the continuous page read operation of this embodiment, the reset of the latch L1 is performed after the end of the precharge of the bit line and before the start of the discharge of the NAND string cell.

Fig. 7 shows a timing chart when resetting the latch L1. Since the precharging of the bit line is performed as in the prior art, it is not described in detail here, but is performed as follows. First, the voltage supply node V1 transitions to the supply voltage Vdd, and the transistor BLPRE conducts to charge the sense node SNS to the Vdd level. Further, the transistor BLCLAMP and the transistor BLCN are turned on, and the node BLS is charged to VCLMP1. There is a relationship between Vdd and VCLMP1. At this time, the transistors BLCD1 and BLCD2 and the transistor REG are made non-conductive. Furthermore, the transistor BLSe is conducted (here, it is assumed that the even bit line GBLe is selected), and the node BLS is electrically connected to the even bit line GBLe. The bit line side selection transistor TD of the NAND string connected to the even bit line GBLe is made conductive, the source line side selection transistor TS is made non-conductive, and a pass voltage is applied to the selected page and the unselected page. For this reason, the clamp voltage VCLMP1 is precharged on the even bit line GBLe. On the other hand, the unselected odd bit line GBLo is electrically connected to the GND of the virtual power supply VIRPWR through the transistor YBLo.

When the precharge of the bit line is finished, the latch L1 is reset. During the reset period, the transistor BLPRE, the transistor BLCN, and the transistor BLCLAMP are in a conductive state. As shown in FIG. 7 , at time t1 , the transistor BLSe is made non-conductive, and the even bit line GBLe is electrically disconnected from the page buffer/sense circuit 170 . Then, at time t2, the voltage supply node V1 transitions to GND. Accordingly, the sense node SNS drops from the supply voltage Vdd to the GND level, and the node TOBL and the node BLS drop from the clamp voltage VCLMP1 to the GND level.

Subsequently, at time t3, the latch enable signal LAT1 for resetting the latch L1 transitions from the H level to the L level, and the latch L1 is placed in a resettable state. Next, at time t4, the transistor EQ is made conductive for a certain period, the nodes SLR1 and SLS1 are short-circuited to the same potential, and then, at a time t5, the transistor BLCD1 is made conductive for a certain period. Accordingly, the charge of the node SLR1 is discharged to the GND of the voltage supply node V1 through the sense node SNS, and the reset of the latch L1 is completed.

After the latch L1 is reset, the sense node SNS and the like are recovered. That is, by recharging the sense node SNS, the node TOBL, and the node BLS, the voltages of these nodes are restored to the precharge state before the reset of the latch L1. At time t6, the voltage supply node V1 transitions from GND to the supply voltage Vdd, which causes the sense node SNS to be recharged to Vdd so that the node TOBL and the node BLS are connected to the clamp voltage VCLMP1. ) is recharged. Then, at time t7 , the transistor BLSe is turned on, and the even bit line GBLe is electrically connected to the page buffer/sense circuit 170 .

Discharging and sensing of the NAND string performed after the reset of the latch L1 is performed in the same manner as in the prior art (not shown). That is, in the NAND string discharge, the transistor BLSe is made non-conductive, the source line side selection transistor TS of the NAND string is conductive, and the NAND string is electrically connected to the source line SL. Furthermore, a gate voltage for generating a clamp voltage VCLMP2 is applied to the node TOBL to the transistor BLCLAMP. VCLMP1>VCLMP2. After that, the transistor BLSe is made conductive for a certain period of time, so that potentials corresponding to data "0" and "1" of the selected memory cell appear in the sense node SNS. When the selected memory cell holds data “0”, the potential of the bit line is not discharged to the source line SL and the potential of the sense node SNS is mostly unchanged. Then, the potential of the bit line is discharged to the source line SL, and the potential of the sense node SNS decreases. In this way, the sense node SNS senses charges according to data “0” and “1” of the selected memory cell. Thereafter, the charge sensed by the sense node SNS is transferred to the node SLR1 of the latch L1 through the transistor BLCD1.

In this embodiment, since the reset of the latch L1 is performed between the precharge period of the bit line and the discharge period of the NAND string, the reset of the latch L1 can be guaranteed and the reliability of data retention in the latch L1 can be improved Moreover, array reading can be started immediately as soon as data from the latch L1 is transferred to the latch L2.

Next, the improved continuous reading of the page to which the reset of the latch L1 according to the present embodiment is applied will be described. 8 is a timing chart when continuous reading of an improved page is performed. Fig. 8 shows an example in which the page P0 is used as the start address. This start address can be selected arbitrarily. tp is the period from the start timing of array read to the completion of precharging of the bit line, and tx is the period required for resetting the latch L1. As shown in the same figure, the substantially continuous read using the latches L1 and L2 starts from the read of the page P2, and the start timing of the array read of the page P2 is performed earlier than the conventional one shown in FIG. In the continuous read shown in FIG. 2 , the start timing of reading the array of the page P2 is the time when the transfer of the data P1C1 of the page P1 from the latch L1 to the latch L2 is finished. That is, after the latch L2 holds the data of the page P1, the data of the next page P2 is transferred to the latch L1.

In contrast, in the improved continuous read, the start timing of the array read of the page P2 is the timing of transferring the page P1 data P1C0 of the first cache C0 of the latch L1 to the latch L2. equal As described above, even if the array read timing of the page P2 is advanced, a certain time is actually required to read the array. When the read page P2 data is transferred to the latch L1, the transfer of the page P1 data P1C1 from the latch L1 to the latch L2 has already been completed. In addition, since the reset of the latch L1 is performed during the array read period, even if the start timing of the array read is increased, the reset of the latch L1 has no effect.

In the improved continuous read, the array read time tARRAY is defined according to the start timing of the array read and the end timing of the array read. The array read end timing of the page P2 is the array read start timing of the next page P3, and when the pages of the pages P2, P3, P4 ... are successively read, the array read time tARRAY is also continuous. .

In the improved continuous read operation, by advancing the start timing of the memory cell array read operation, the constraint of Equation (1) of the conventional continuous read operation is relaxed as shown in Equation (2), and an external clock signal having a high frequency Data output using (ExCLK) becomes possible.

tARRAY < Tdout (page 1),

tECC < tDOUT (Page 1/2) … (2)

That is, if the time (tDOUT) to output one page of data is greater than the array read time (tARRAY) and the time (tDOUT) to output 1/2 page of data is greater than the ECC processing time (tECC), It is possible to achieve higher speed of continuous reading than in the prior art. In FIG. 8 , the first cache (C0) data of the next page (P2) is transferred from the latch (L1) to the latch (L2) at the time when the data of the first cache (C0) of the page (P1) is started to be transferred from the latch (L1) ) to the time to output the data of the second cache of the page P0 and the first cache of the page P1 than the array read time tARRAY of the page P2 from the time of starting the transfer to the latch L2 The output time (tDOUT), which is the sum of the time to output the data of , is larger, and the second cache (C1) data of the latch (L2) is larger than the time (tECC) for ECC processing the first cache (C0) data of the latch (L2) It is exemplified that the time for outputting tDOUT is large.

In the improved continuous read operation, since the timing at which the reset of the latch L1 is started is after the precharging of the bit line is completed, the period from the start timing of the array read to just before the reset of the latch L1 is started is tp , in addition to the equation (2), the constraint of the equation (3) is added. That is, the data of the latch L1 needs to be transferred to the latch L2.

tDOUT (page 1/2) < tp … (3)

However, since the precharge period of the bit line is sufficiently long, as long as the equations (2) and (3) are satisfied, the improved continuous read speed shown in Fig. 8 can be achieved.

In this way, even in the improved continuous read operation, it is possible to achieve high-speed read data while ensuring the reset of the latch L1.

Next, another embodiment of the present invention will be described. In the above embodiment, the reset of the latch L1 is performed between the precharge operation of the bit line and the discharge operation of the NAND string, but in the other embodiment, the reset of the latch L1 is performed during the discharge operation of the NAND string. will do

As described above, the reset of the latch L1 can be performed if the sense node is in a free state without being influenced from the outside. During the discharge operation period of the NAND string, the transistor BLSe is non-conductive, and the sense node SNS is electrically isolated from the bit line. For this reason, it is possible to perform the reset operation of the latch L1 shown at times t2 to t6 shown in Fig. 7 in parallel with the discharge operation of the NAND string in time.

According to the present embodiment, by performing the reset of the latch L1 in parallel during the discharge period of the NAND string, the reset of the latch L1 is performed between the precharge operation of the bit line and the discharge operation of the NAND string. In comparison, in fact, it is possible to shorten the array read time tARRAY and to speed up data output according to continuous read.

Although the preferred embodiment of the present invention has been described above, the present invention is not limited to the specific embodiment, it is within the scope of the gist of the present invention described in the claims, and various modifications and changes are possible.

100: flash memory
110: memory cell array
120: input/output circuit
130: ECC circuit
140: address register
150: controller
160: word line selection circuit
170: page buffer / sense circuit
180: column selection circuit
190: internal voltage generation circuit
200: bit line selection circuit

Claims (17)

As a method of reading NAND-type flash memory,
precharging a bit line and a NAND string connected to the bit line through a sense node;
resetting the latch circuit by electrically connecting a node of the latch circuit to a reference potential through the sense node after precharging;
after reset, discharging the NAND string;
Including, a reading method. As a method of reading NAND-type flash memory,
precharging a bit line and a NAND string connected to the bit line through a sense node;
resetting the latch circuit by electrically connecting a node of the latch circuit to a reference potential through the sense node during the discharge period of the NAND string;
Including, a reading method. 3. The method of claim 2,
The precharging step is
generating a precharge voltage at the voltage supply node;
electrically connecting the voltage supply node to the sense node through a first select transistor; and
electrically connecting the sense node to a bit line through a second select transistor
including,
The resetting step is
generating a reference voltage with the voltage supply node;
electrically connecting the voltage supply node to the latch circuit through the first select transistor; and
electrically isolating the sense node through the second select transistor
Including, a reading method. 3. The method of claim 2,
and each of the steps is performed in continuous reading of a page. 5. The method of claim 4,
In the sequential reading of the page, data read from the selected page of the memory cell array is held in the latch circuit, the data held in the latch circuit is transferred to another latch circuit, and then the data read from the next selected page is latched into the latch circuit. keeping in the circuit,
continuously outputting data held in the other latch circuit to the outside in synchronization with an external clock signal;
Including, a reading method. 6. The method of claim 5,
The continuous reading of the page further outputs the ECC-processed data of the second part to the outside while error detection/correction (ECC process) of the data of the first part of the other latch circuit is performed, and the ECC of the first part and performing ECC processing on the data of the second part while outputting the processed data to the outside. 7. The method of claim 6,
after outputting the ECC-processed data of the first part of the other latch circuit to the outside, transferring the data of the next selected page of the first part of the latch circuit to the first part of the other latch circuit;
after outputting the ECC-processed data of the second part of the other latch circuit to the outside, transferring the data of the next selected page of the second part of the latch circuit to the second part of the other latch circuit;
Including, a reading method. 8. The method of claim 6 or 7,
The continuous read is a first continuous read having a constraint expressed by tARRAY + tECC < tDOUT (each of the data of the first part and the second part is 1/2 page of data, tARRAY is the time required to read the selected page, tECC is 1/ Time required for ECC processing of page 2, tDOUT is time required to output all data of page 1), reading method. 8. The method of claim 6 or 7,
The continuous read is a second continuous read with a constraint expressed by tARRAY < tDOUT, tECC < tDOUT (1/2 page) (the data of the first part and the second part are each 1/2 page of data, tARRAY is the selected page) time required to read , tECC is the time required to process 1/2 page ECC, tDOUT is the time required to output all data of 1 page, tDOUT (1/2 page) is the time required to output 1/2 page data time), reading method. 10. The method of claim 9,
The second continuous reading is
Compared with the first continuous read, the read timing of the selected page of the memory cell array is faster,
The first continuous reading is
With the constraint expressed as tARRAY + tECC < Tdout,
reading method. NAND type memory cell array;
reading means for reading data from a selected page of the memory cell array;
Output means for outputting the data read by the reading means to the outside
including,
The reading means is
Page buffer/sense circuit connected to the memory cell array via bit lines
including,
The reading means is
When sequential reading of a page is performed, reset of the latch circuit included in the page buffer/sense circuit is performed between the precharge period of the bit line and the discharge period of the NAND string;
The reset of the latch circuit is
electrically connecting a node of the latch circuit to a reference potential through a sense node,
semiconductor device. NAND type memory cell array;
reading means for reading data from a selected page of the memory cell array;
an output means for outputting the data read by the reading means to the outside;
the reading means includes a page buffer/sense circuit connected to the memory cell array through a bit line;
wherein the reading means resets a latch circuit included in the page buffer/sense circuit during a discharge period of the NAND string after the bit line is precharged when consecutive reading of the page is performed. 13. The method of claim 12,
The page buffer/sense circuit includes a voltage supply node, a sense node, a latch circuit, a first selection transistor connected between the voltage supply node and the sense node, a second selection transistor connected between the sense node and a bit line, and a third selection transistor connected between the sense node and the latch circuit;
and resetting the latch circuit by making the first and third selection transistors conductive, making the second selection transistor non-conducting, and electrically connecting the latch circuit to a reference potential of the voltage supply node. 14. The method of claim 13,
and the reading means conducts the first and second selection transistors, makes the third selection transistor non-conductive, and precharges the voltage of the voltage supply node to the bit line. 13. The method of claim 12,
and the output means continuously outputs the read data in synchronization with an external clock signal when the reading means continuously reads a page. 13. The method of claim 12,
the page buffer/sense circuit further comprises another latch circuit for receiving data held in the latch circuit;
and the reading means holds, in the latch circuit, data read from a next selected page of the memory cell array while the data of the other latch circuit is output, when consecutive reading is performed. 17. The method of claim 16,
The semiconductor device further includes an ECC circuit that performs error detection and correction of data;
The read means, when performing continuous read, reads the ECC-processed data held in the second part of the other latch circuit while the data held in the first part of the other latch circuit is ECC-processed by the ECC circuit. A semiconductor device that outputs.

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