KR102303928B1 - Memory device and refresh method thereof - Google Patents

Abstract

There is no need to perform the calculation of the word line address requiring refresh by a Row Hammer in the redundancy area, thereby reducing the area of the refresh address calculator. A memory device capable of being reduced and a refresh method thereof are provided. A memory device includes a memory cell array and a controller. The memory cell array has a plurality of normal regions and a redundancy region adjacent to the plurality of normal regions. The redundancy area has a plurality of redundancy word lines. The memory cell array arranges a plurality of boundary word lines at the boundary between the normal area and the redundancy area. The controller sequentially refreshes the plurality of redundancy wordlines, sequentially refreshes the plurality of redundancy wordlines, and then sequentially refreshes the plurality of boundary wordlines.

Description

MEMORY DEVICE AND REFRESH METHOD THEREOF

The present invention relates to a memory device and a method for refreshing the same, and more particularly to a memory device for refreshing a redundancy area word line and a method for refreshing the same.

When a specific word line (also referred to as an 'applicable word line') that is valid repeatedly a plurality of times exists in a dynamic random access memory (DRAM), a word line adjacent to the attack word line ('damage The memory cells on the word line (also referred to as 'word line') may lose stored data due to cross talk or coupling effect, and this interference phenomenon is called the Row Hammer phenomenon. .

The prior art avoids the low hammer phenomenon by separately refreshing the damaged word line. That is, the damaged word line has a relatively high refresh rate. However, in some DRAM structures with high memory cell densities, the calculation of the address of the victim word line is relatively complex, so a larger area refresh address calculator ('low hammer address calculator') is used to calculate the address of the damaged word line. also called) is required.

The present invention provides a memory device capable of reducing the area of a refresh address calculator by eliminating the need to perform calculation of a word line address requiring refresh by means of a row hammer in a redundancy area, and a refresh method therefor do.

An embodiment of the present invention provides a memory device, the memory device including a memory cell array and a controller. The memory cell array has a plurality of normal regions and a redundancy region adjacent to the plurality of normal regions. The redundancy area has a plurality of redundancy word lines, and the memory cell array arranges a plurality of boundary word lines at a boundary between a normal area and a redundancy area. The controller sequentially refreshes the plurality of redundancy wordlines, sequentially refreshes the plurality of redundancy wordlines, and then sequentially refreshes the plurality of boundary wordlines.

An embodiment of the present invention provides a refresh method applied to a memory device. A memory device includes a memory cell array and a controller, wherein the memory cell array has a plurality of normal regions and a redundancy region adjacent to the plurality of normal regions. The redundancy area has a plurality of redundancy word lines, and the memory cell array arranges a plurality of boundary word lines at the boundary between the normal area and the redundancy area. The refresh method includes sequentially refreshing a plurality of redundancy wordlines, sequentially refreshing the plurality of redundancy wordlines, and then sequentially refreshing the plurality of boundary wordlines.

Based on the above, in some embodiments of the present invention, the memory device and the refresh method thereof can reduce the area of the refresh address calculator. Since the controller does not need to sequentially refresh the redundancy wordlines and boundary wordlines in the memory cell array and calculate the wordline addresses that require refresh by row hammer in the redundancy area, the area of the refresh address calculator is can be reduced

(FIG. 1) is an explanatory diagram of a memory device according to an embodiment of the present invention.
(FIG. 2) is an explanatory diagram of a layout of word lines in a memory cell array according to an embodiment of the present invention.
(FIG. 3) is an explanatory diagram of a redundancy area refresh address control circuit according to another embodiment of the present invention.
(FIG. 4) is an operation timing diagram of a controller according to an embodiment of the present invention.
(FIG. 5) is a flowchart of a refresh method according to an embodiment of the present invention.

In order to make the above characteristics and advantages of the present invention easy to understand, it will be described in detail below with reference to the drawings by way of examples.

Referring to FIG. 1 , in an embodiment, a memory device 100 includes a controller 110 and a memory cell array 120 . A controller 110 is coupled to the memory cell array 120 , and the controller 110 includes a refresh address calculator 130 , a refresh address multiplexer 170 , a row address multiplexer 180 , and a row address It includes a decoder 190 . The controller 110 is typically arranged to provide the word line address WL to the memory cell array 120 based on the command signal ACT, the reference command signal AREF, and the address ADD.

The memory cell array 120 includes, for example, a plurality of dynamic random access memory cells, and the present invention does not limit the type and structure of the memory cell array 120 . 2 , in one embodiment, the memory cell array 120 includes a normal region 210 and a redundancy region 220 adjacent the normal region 210 , the number of the normal regions 210 , and The adjacent relationship between the normal area 210 and the redundancy area 220 is only an example, and is not limited thereto. A redundancy row and a redundancy column are disposed in the redundancy region 220 , and the redundancy row and the redundancy column have redundancy memory cells, and replace defective or damaged memory cells in the normal region 210 , so that the normal state of the memory device 100 . It is used to maintain function. The memory cell array 120 receives the word line address WL to refresh the memory cells in the memory cell array 120 and avoids damage to the memory data due to the row hammer phenomenon. In one embodiment, the redundancy region 220 has a plurality of redundancy wordlines R1 to R48, and the plurality of boundary wordlines B1 to B4 includes a plurality of normal regions 210 and a redundancy region 220 . ), the boundary wordlines B1 and B4 are arranged in the normal region 210 , and the boundary wordlines B2 and B3 are arranged in the redundancy region 220 . The boundary word lines B1 and B4 can be used as normal word lines, and the boundary word lines B2 and B3 can be used as redundancy word lines. The number of redundancy wordlines R1 to R48 and boundary wordlines B1 to B4 depends on the structure of the plurality of normal regions 210 and redundancy regions 220, and the present invention is not limited thereto.

The refresh address calculator 130 multiplexes the normal area refresh address NRADD and the redundancy area refresh address RRADD based on the normal command signal ACT, the reference command signal AREF and the address ADD to the refresh address multiplex. It is arranged to provide to the lexer 170 . The refresh address calculator 130 further calculates the number of pulses of the reference command signal AREF, and provides the refresh count address RCADD to the refresh address multiplexer 170 to provide a selection signal S1 and a selection signal S2. ) and the refresh status signal RS to the refresh address multiplexer 170 , the row address multiplexer 180 , and the row address decoder 190 , respectively. Specifically, the refresh address calculator 130 includes a normal area refresh address control circuit 140 and a redundancy area refresh address control circuit 150 . The normal region refresh address control circuit 140 provides the normal region refresh address NRADD to the refresh address multiplexer 170 based on the normal command signal ACT and the address ADD, and the normal region 210 . It is arranged to provide an address that needs to be refreshed to the refresh address multiplexer 170 . The redundancy area refresh address control circuit 150 receives the reference command signal AREF, and receives the reference command signal AREF, a plurality of redundancy word line addresses RA1 to RA48, and a plurality of boundary word line addresses BA1 to BA4. Based on this, a plurality of redundancy area refresh addresses RRADD are sequentially generated in the refresh address multiplexer 170 , and the redundancy area 220 is arranged to provide an address required to be refreshed. The plurality of redundancy word line addresses RA1 to RA48 and the plurality of boundary word line addresses BA1-BA4 are addresses corresponding to the plurality of redundancy word lines R1 to R48 and the plurality of boundary word lines B1 to B4. am. In one embodiment, the controller 110 sequentially refreshes the redundancy word lines R1 to R48 based on the plurality of redundancy area refresh addresses RRADD, and after sequentially refreshing the redundancy word lines R1 to R48, the boundary The word lines (B1 to B4) are sequentially refreshed.

The refresh address multiplexer 170 is coupled to the refresh address calculator 130, and the refresh address multiplexer 170 includes a normal area refresh address (NRADD), a redundancy area refresh address (RRADD), and a refresh count address ( RCADD) and the selection signal S1 , select an address based on the selection signal S1 , and output the refresh address RADD to the row address multiplexer 180 .

The row address multiplexer 180 is coupled to the refresh address multiplexer 170, and the row address multiplexer 180 receives the refresh address RADD and the select signal S2, and receives the select signal S2. It is arranged to select an address based on S2) and output the row address RA to the row address decoder 190 .

The row address decoder 190 is coupled to the row address multiplexer 180 and receives a row address RA and a refresh status signal RS, based on the row address RA and the refresh status signal RS. It is arranged to provide a word line address WL to the memory cell array 120 by performing decoding, and to refresh a corresponding word line in the memory cell array 120 . The refresh status signal RS is used to determine the refresh timing of the redundancy word lines R1 to R48 and the boundary word lines B1 to B4.

In one embodiment, the refresh method of the controller 110 sequentially refreshes the redundancy word lines R1 to R48, sequentially refreshes the redundancy word lines R1 to R48, and then sequentially refreshes the boundary word lines B1 to B4. is to refresh For example, the controller 110 first refreshes the redundancy wordline R1, then continues to refresh the redundancy wordline R2, and finally refreshes the redundancy wordline R48. After the controller 110 sequentially refreshes the redundancy word lines R1 to R48, the controller 110 sequentially refreshes the boundary word lines B1 to B4, for example, first the boundary word line B1. Refresh, then continue to refresh the boundary word line B2, and finally refresh the boundary word line B4. Note that the order in which the controller 110 refreshes the redundancy word lines R1 to R48 and the boundary word lines B1 to B4 is only an example, and the present invention is not limited thereto. In another embodiment, the refresh order of controller 110 may refresh from redundancy wordline R48 to redundancy wordline R1 or boundary wordline B4 to boundary wordline B1, and controller 110 ) may refresh the boundary word lines B1 to B4 first, and then refresh the redundancy word lines R1 to R48. Alternatively, the controller 110 may insert the refresh timing of the boundary word lines B1 to B4 within the refresh timing of the redundancy word lines R1 to R48, and the present invention does not limit the refresh order.

3 and 4 , the redundancy area refresh address control circuit 150 includes a reference instruction counter 310 , a redundancy wordline address selector 320 , a logic circuit 330 , and a multiplexer 340 . do. The reference command counter 310 is arranged to receive the reference command signal AREF and generate a redundancy flag RFLAG based on the reference command signal AREF. In one embodiment, the reference instruction counter 310 may be a synchronous counter or an asynchronous counter, and the present invention is not limited thereto. The reference command counter 310 calculates the number of pulses of the reference command signal AREF to generate a reference command signal pulse number, and whenever the reference command signal pulse number is equal to the first number, the reference command counter 310 is , generate a pulse of the redundancy flag (RFLAG). In one embodiment, the refresh period of the redundancy area is set to the time of issuing the reference command signal AREF 16 times. For example, when the reference command counter 310 receives the pulse AREF1 as the reference command signal AREF, the accumulated number of pulses of the reference command signal AREF reaches 16, and then The reference command counter 310 generates a pulse F1 of the redundancy flag RFLAG, and the counted number of pulses of the reference command signal AREF is returned to zero. When the reference command counter 310 receives the pulse AREF2 as the reference command signal AREF, the accumulated reference command signal AREF pulse number is 1, and the pulse AREF3 of the reference command signal AREF is When receiving, the number of pulses of the reference command signal AREF that is accumulated is two, and thus, as inferred, when the reference command counter 310 receives the pulses AREF17 of the reference command signal AREF, the cumulative The pulse of the reference command signal AREF being 16 is 16, and the reference command counter 310 generates a pulse F2 of the redundancy flag RFLAG, and returns the number of pulses of the reference command signal AREF to zero. do.

The redundancy wordline address selector 320 is coupled to the reference instruction counter 310, and the redundancy wordline address selector 320 is configured to generate a redundancy wordline address select signal RSEL based on the redundancy flag RFLAG. are placed In one embodiment, whenever the reference instruction counter 310 generates a pulse of the redundancy flag RFLAG, the redundancy wordline address selector 320 generates a redundancy wordline address select signal based on the redundancy flag RFLAG. RSEL) timing can be shifted. For example, after the reference instruction counter 310 generates a pulse F1 of the redundancy flag, the redundancy wordline address selector 320 generates a redundancy wordline address selection signal at the falling edge of the pulse F1 of the redundancy flag. By shifting the timing of RSEL, the redundancy wordline address selection signal RSEL is inferred accordingly, such as shifting the redundancy wordline address selection signal RSEL from one corresponding to the redundancy wordline address RA1 to one corresponding to the redundancy wordline address RA2.

The multiplexer 340 is coupled to the redundancy wordline address selector 320 to select the redundancy wordline address select signal RSEL, the redundancy wordline addresses RA1 to RA48, and the boundary wordline addresses BA1 to BA4. received and based on them, it is arranged to sequentially generate a plurality of redundancy area refresh addresses RRADD. For example, when the redundancy wordline address selection signal RSEL received by the multiplexer 340 from the redundancy wordline address selector 320 corresponds to the redundancy wordline address RA1, the multiplexer 340 , the redundancy word line address RA1 is selected to output one redundancy area refresh address RRADD. When the redundancy wordline address selection signal RSEL received by the multiplexer 340 from the redundancy wordline address selector 320 corresponds to the redundancy wordline address RA2, the multiplexer 340 controls the redundancy wordline The address RA2 is selected to output the next redundancy area refresh address RRADD.

A logic circuit 330 is coupled to the reference instruction counter 310 to receive a reference instruction signal AREF and a redundancy flag RFLAG, and perform a logic operation based on the reference instruction signal AREF and the redundancy flag RFLAG. to generate the refresh status signal RS. The refresh status signal RS is used to determine the timing to refresh the redundancy word lines R1 to R48 and the boundary word lines B1 to B4. In one embodiment, the pulses of the refresh status signal RS generally correspond to the pulses of the reference command signal AREF, but whenever the cumulative number of pulses of the reference command signal AREF equals 16, the logic circuit 330 The next refresh status signal RS generated by A includes a pulse corresponding to one reference command signal AREF and one redundancy area refresh pulse thereafter. For example, when the reference command counter 310 receives the pulse AREF1 of the reference command signal AREF, the pulse RS1 of the refresh status signal RS is the pulse AREF1 of the reference command signal AREF. ) corresponds to Subsequently, when the number of pulses of the counted reference command signal AREF reaches 16, the reference command counter 310 generates a pulse F1 of the redundancy flag RFLAG, and the logic circuit 330 generates a pulse ( One redundancy area refresh pulse RREF1 is generated after the pulse AREF2 based on AREF1) and the pulse F1, and the redundancy area refresh pulse RREF1 corresponds to the redundancy wordline address RA1, and Accordingly, the pulse RS2 of the refresh status signal RS corresponds to the pulse AREF2 of the reference command signal AREF and the redundancy area refresh pulse RREF1. Next, when the reference command counter 310 receives the pulse AREF3 of the reference command signal AREF, the pulse RS3 of the refresh status signal RS corresponds to the pulse AREF3, Inferred from this When the reference command counter 310 receives the pulse AREF17 of the reference command signal AREF, the pulse RS17 of the refresh status signal RS corresponds to the pulse AREF17, and the reference command signal to be counted at this time When the number of pulses of (AREF) reaches 16, the reference instruction counter 310 generates a pulse F2 of the redundancy flag RFLAG. The logic circuit 330 generates one redundancy area refresh pulse RREF2 after the pulse AREF18 of the next reference command signal AREF based on the pulses AREF17 and F2, and refreshes the redundancy area. The pulse RREF2 corresponds to the redundancy word line address RA2, and the pulse RS2 of the refresh status signal RS corresponds to the pulse AREF18 and the redundancy area refresh pulse RREF2.

On the other hand, the refresh address calculator 130 calculates the number of refreshes of the normal area, provides the refresh count address RCADD to the refresh address multiplexer 170 , and the refresh address multiplexer 170 uses the refresh count address. Based on (RCADD), it is possible to recognize the current number of refreshes. For example, when the refresh address calculator 130 receives the pulse AREF1 of the reference command signal, the refresh count address RCADD is 1, and the refresh address calculator 130 receives the pulse AREF2 of the reference command signal. When receiving , the refresh count address RCADD is 2, and when the refresh address calculator 130 receives the pulse AREF3 of the reference command signal, the refresh count address RCADD is 3, and Inferred from this When the refresh address calculator 130 receives the pulse AREF18 of the reference command signal, the refresh count address RCADD is 18.

5 is a flowchart of a refresh method according to an embodiment of the present invention. In step S510, the controller 110 sequentially refreshes the redundancy word lines R1 to R48. Next, in step S520 , the controller 110 sequentially refreshes the redundancy word lines R1 to R48 and then sequentially refreshes the boundary word lines B1 to B4 . For details of the above steps S510 and S520, reference may be made to the embodiments of FIGS. 1 to 4, which will not be described again herein.

Taken together, in some embodiments of the present invention, the memory device and the refresh method thereof can reduce the area of the refresh address calculator. The controller sequentially refreshes the redundancy wordlines and boundary wordlines in the memory cell array, and in the redundancy area, there is no need to calculate the wordline address that needs to be refreshed by means of a row hammer in the redundancy area, so the area of the refresh address calculator can be reduced. have.

Although the present invention has disclosed the Example as described above, it is not intended to limit the present invention, and those skilled in the art can make slight changes and modifications without departing from the spirit and scope of the present invention, , Therefore, the protection scope of the present invention is based on what is defined by the claims to be described later.

100: memory device
110: controller
120: memory cell array
130: refresh address calculator
140: normal area refresh address control circuit
150: redundancy area refresh address control circuit
170: refresh address multiplexer
180: row address multiplexer
190: row address decoder
210: normal area
220: redundancy area
310: reference command counter
320: redundancy word line address selector
330: logic circuit
340: multiplexer
ACT: Normal command signal
ADD: address
AREF: Reference command signal
AREF1, AREF2, AREF3, AREF17, AREF18: Pulse of reference command signal
B1~B4: Boundary word line
BA1 to BA4: boundary word line addresses
F1, F2: Redundancy flag pulse
NRADD: Normal area refresh address
R1-R48: Redundancy word line
RA1 to RA48: Redundancy word line addresses
RA: row address
RADD: refresh address
RCADD: refresh count address
RFLAG: Redundancy flag
RRADD: Redundancy area refresh address
RS: Refresh status signal
RS1, RS2, RS3, RS17, RS18: Refresh status signal pulse
RREF1, RREF2, RREF18: Redundancy area refresh pulse
RSEL: Redundancy Wordline Address Select Signal
S1, S2: selection signal
WL: word line address
S510~S520: Step

Claims (16)

A memory device comprising:
a plurality of normal regions, and a redundancy region adjacent to the plurality of normal regions, each of the normal regions having a boundary normal wordline adjacent to the redundancy region, the redundancy region comprising: a plurality of central redundancy wordlines; a memory cell array having a plurality of boundary redundancy word lines adjacent to the plurality of normal regions;
coupled to the memory cell array;
all the plurality of central redundancy wordlines in the redundancy area, the plurality of border normal wordlines adjacent to the redundancy area, and all the plurality of boundary redundancy words in the redundancy area based on a refresh timing determined by a refresh status signal Controller placed to refresh the line
including,
The controller is
Receive a reference command signal, and sequentially generate a plurality of redundancy area refresh addresses based on a redundancy flag, the refresh status signal, a plurality of center redundancy wordline addresses, a plurality of boundary redundancy wordline addresses, and a plurality of boundary normal wordline addresses a redundancy area refresh address control circuit arranged to
including,
The plurality of redundancy area refresh addresses are:
disposed to represent all of the plurality of central redundancy wordlines within the redundancy area, a plurality of the border normal wordlines adjacent to the redundancy area, and all of the plurality of border redundancy wordlines within the redundancy area;
The redundancy area refresh address control circuit comprises:
receiving the reference command signal, counting the number of pulses of the reference command signal to generate the cumulative number of pulses of the reference command signal, the pulse of the redundancy flag whenever the cumulative number of pulses of the reference command signal is equal to the first number Reference command counter arranged to generate
A memory device comprising a. According to claim 1,
The controller is
According to the plurality of redundancy area refresh addresses, the plurality of central redundancy word lines are sequentially refreshed, and after the plurality of central redundancy word lines are sequentially refreshed, the plurality of border normal word lines and the plurality of border redundancy word lines are refreshed. A sequentially refreshed memory device. According to claim 1,
The redundancy area refresh address control circuit comprises:
a redundancy wordline address selector coupled to the reference instruction counter and arranged to generate a redundancy wordline address select signal based on the redundancy flag;
coupled to the redundancy wordline address selector to receive the redundancy wordline address select signal, the plurality of center redundancy wordline addresses, the plurality of boundary redundancy wordline addresses, and the plurality of boundary normal wordline addresses; a multiple arranged to sequentially generate the plurality of redundancy area refresh addresses based on a wordline address selection signal, the plurality of center redundancy wordline addresses, the plurality of boundary redundancy wordline addresses, and the plurality of boundary normal wordline addresses lexer and
Logic circuit coupled to the reference command counter and arranged to receive the reference command signal and the redundancy flag, and to generate the refresh status signal based on the reference command signal and the redundancy flag
A memory device further comprising a. 4. The method of claim 3,
Whenever the reference command counter generates a pulse of the redundancy flag,
The redundancy word line address selector comprises:
and shifting the timing of the redundancy wordline address selection signal based on the redundancy flag. 4. The method of claim 3,
The multiplexer is
According to the redundancy wordline address selection signal, the plurality of center redundancy wordline addresses, the plurality of boundary redundancy wordline addresses, and the plurality of boundary normal wordline addresses are sequentially selected, and the plurality of redundancy area refresh addresses are sequentially selected. creating a memory device. 4. The method of claim 3,
The refresh timing determined by the refresh status signal is
sequentially updating all the plurality of central redundancy wordlines in the redundancy area, then updating one of the plurality of border normal wordlines, and then sequentially updating all the plurality of boundary redundancy wordlines in the redundancy area update and then update the other one of a plurality of said boundary normal wordlines, or
sequentially updating all of the plurality of central redundancy wordlines in the redundancy area, and inserting refresh timings of the plurality of boundary redundancy wordlines and the plurality of boundary normal wordlines among refresh timings of the plurality of central redundancy wordlines; one of them,
memory device. A refresh method applied to a memory device, comprising:
The memory device is
a memory cell array and a controller;
The memory cell array,
a plurality of normal areas;
having a redundancy region adjacent to the plurality of normal regions;
The normal area is
having a bordered normal wordline adjacent to the redundancy region;
The redundancy area is
a plurality of central redundancy wordlines;
having a plurality of boundary redundancy wordlines adjacent to the plurality of normal regions;
The refresh method is
all the plurality of central redundancy wordlines in the redundancy area, the plurality of border normal wordlines adjacent to the redundancy area, and all the plurality of boundary redundancy words in the redundancy area based on a refresh timing determined by a refresh status signal step to refresh the line
including,
The refresh method is
Receive a reference command signal, count the number of pulses of the reference command signal to generate a cumulative pulse number of the reference command signal, and generate a pulse of a redundancy flag whenever the cumulative pulse number of the reference command signal is equal to the first number step and
sequentially generating a plurality of redundancy area refresh addresses based on the redundancy flag, the refresh status signal, a plurality of center redundancy wordline addresses, a plurality of boundary redundancy wordline addresses, and a plurality of boundary normal wordline addresses;
further comprising,
The plurality of redundancy area refresh addresses are:
arranged to represent all of the plurality of central redundancy wordlines within the redundancy area, a plurality of the border normal wordlines adjacent the redundancy area, and all of the plurality of border redundancy wordlines within the redundancy area;
How to refresh. 8. The method of claim 7,
According to the plurality of redundancy area refresh addresses, the plurality of central redundancy word lines are sequentially refreshed, and after the plurality of central redundancy word lines are sequentially refreshed, the plurality of border normal word lines and the plurality of border redundancy word lines are refreshed. Steps to refresh sequentially
A refresh method further comprising a. 8. The method of claim 7,
sequentially generating the plurality of redundancy area refresh addresses based on the redundancy flag, the refresh status signal, the plurality of central redundancy word line addresses, the plurality of boundary redundancy word line addresses, and the plurality of boundary normal word line addresses; step is,
generating a redundancy word line address selection signal based on the redundancy flag;
receive the redundancy wordline address selection signal, the plurality of center redundancy wordline addresses, the plurality of boundary redundancy wordline addresses, and the plurality of boundary normal wordline addresses, the redundancy wordline address selection signal, the plurality of sequentially generating the plurality of redundancy area refresh addresses based on a central redundancy wordline address, the plurality of boundary redundancy wordline addresses, and the plurality of boundary normal wordline addresses;
A refresh method comprising a. 9. The method of claim 8,
According to the plurality of redundancy area refresh addresses, the plurality of central redundancy word lines are sequentially refreshed, and after the plurality of central redundancy word lines are sequentially refreshed, the plurality of border normal word lines and the plurality of border redundancy word lines are refreshed. The sequential refresh steps are:
receiving the reference command signal and the redundancy flag, and generating the refresh status signal based on the reference command signal and the redundancy flag;
A refresh method comprising a. 10. The method of claim 9,
generating the redundancy word line address selection signal based on the redundancy flag;
every time the pulse of the redundancy flag is generated, shifting the timing of the redundancy word line address selection signal based on the redundancy flag;
A refresh method comprising a. 10. The method of claim 9,
receive the redundancy wordline address selection signal, the plurality of center redundancy wordline addresses, the plurality of boundary redundancy wordline addresses, and the plurality of boundary normal wordline addresses, the redundancy wordline address selection signal, the plurality of The sequentially generating the plurality of redundancy area refresh addresses based on a central redundancy wordline address, the plurality of boundary redundancy wordline addresses, and the plurality of boundary normal wordline addresses includes:
According to the redundancy wordline address selection signal, the plurality of center redundancy wordline addresses, the plurality of boundary redundancy wordline addresses, and the plurality of normal boundary wordline addresses are sequentially selected, and the plurality of redundancy area refresh addresses are selected in sequence. Steps to create sequential
A refresh method comprising a. 11. The method of claim 10,
The refresh timing determined by the refresh status signal is
sequentially updating all the plurality of central redundancy wordlines in the redundancy area, then updating one of the plurality of border normal wordlines, and then sequentially updating all the plurality of boundary redundancy wordlines in the redundancy area update and then update the other one of a plurality of said boundary normal wordlines, or
sequentially updating all of the plurality of central redundancy wordlines in the redundancy area, and inserting refresh timings of the plurality of boundary redundancy wordlines and the plurality of boundary normal wordlines among refresh timings of the plurality of central redundancy wordlines; one of them,
How to refresh. delete delete delete

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