KR102302433B1 - Nonvolatile memory device and erasing method thereof - Google Patents

Abstract

A nonvolatile memory device according to the present invention includes a plurality of cell strings, each cell string includes a plurality of memory cells stacked in a direction perpendicular to a substrate, and a ground selection transistor provided between the plurality of memory cells and the substrate. , and a memory cell array including a string select transistor provided between the plurality of memory cells and a bit line, providing an erase voltage to the substrate during an erase operation, and the ground select transistor after a specific time after the erase voltage is provided an address decoder floating a ground selection line connected to , generating the erase voltage that changes according to temperature based on first temperature information, and selecting a ground based on a feedback voltage corresponding to the erase voltage and second temperature information a voltage generator generating line (GSL) transition information, and control logic generating a ground selection line (GSL) control signal based on the GSL transition information, wherein the address decoder selects the ground according to the GSL control signal. Plot the line.

Description

NONVOLATILE MEMORY DEVICE AND ERASING METHOD THEREOF

The present invention relates to a semiconductor memory, and more particularly, to a nonvolatile memory device and an erasing method thereof.

A semiconductor memory device is largely divided into a volatile memory device and a non-volatile memory device. Volatile memory devices have a fast read and write speed, but have a disadvantage in that the stored contents are lost when the external power supply is cut off. On the other hand, the nonvolatile memory device retains its contents even when external power supply is interrupted. Therefore, nonvolatile memory devices are used to store contents to be preserved regardless of whether power is supplied or not. In particular, among nonvolatile memories, a flash memory has a higher degree of integration than a conventional EEPROM, so it is very advantageous for application as a mass auxiliary storage device.

Recently, in order to improve the degree of integration of a semiconductor memory device, a semiconductor memory device having a three-dimensional structure has been studied. A three-dimensional semiconductor memory device has structural characteristics different from those of a conventional two-dimensional semiconductor memory device. Due to the structural difference between the 3D semiconductor memory device and the 2D semiconductor memory device, various driving methods for driving the 3D semiconductor memory are being studied.

SUMMARY OF THE INVENTION It is an object of the present invention to provide a nonvolatile memory device for improving a threshold voltage distribution in an erase state during an erase operation, and an erase method thereof.

A nonvolatile memory device according to the present invention for achieving the above object includes a plurality of cell strings, each cell string including a plurality of memory cells stacked in a direction perpendicular to a substrate, and between the plurality of memory cells and the substrate A memory cell array including a ground select transistor provided to a ground select transistor, and a string select transistor provided between the plurality of memory cells and a bit line, providing an erase voltage to the substrate during an erase operation, and providing a specific value after the erase voltage is provided. an address decoder that floats a ground select line connected to the ground select transistor after a time, generates the erase voltage that changes with temperature based on first temperature information, and a feedback voltage corresponding to the erase voltage and a second temperature a voltage generator configured to generate ground selection line (GSL) transition information based on the information, and control logic configured to generate a ground selection line (GSL) control signal based on the GSL transition information, wherein the address decoder controls the GSL Float the ground select line according to the signal.

According to another aspect of the present invention, there is provided a nonvolatile memory device with word lines connected to a plurality of memory cells stacked in a direction perpendicular to a substrate, and a ground selection transistor provided between the plurality of memory cells and the substrate. and a ground selection line connected to , and a string selection line connected to a string selection transistor provided between the plurality of memory cells and a bit line, wherein during an erase operation, the ground selection line is disposed after an erase voltage is applied to the substrate. It floats after a specific time, and the ground selection line floats at different times depending on the temperature.

According to an aspect of the present invention, an erasing method of a nonvolatile memory device includes a plurality of cell strings, each cell string having a plurality of memory cells stacked in a direction perpendicular to a substrate, the plurality of memory cells, A nonvolatile memory device comprising a ground select transistor provided between the substrates and a string select transistor provided between the plurality of memory cells and a bit line, the method comprising: receiving first temperature information and an erase target voltage; Compensating the erase target voltage based on the first temperature information; generating a pump control signal by comparing the compensated erase target voltage with a feedback voltage corresponding to the erase voltage supplied to the substrate; , generating the erase voltage based on the pump control signal, receiving second temperature information and a ground selection line (GSL) target voltage, and compensating for the GSL target voltage based on the second temperature information. , generating ground selection line (GSL) transition information by comparing the compensated GSL target voltage with the feedback voltage, wherein a floating point of the ground selection line connected to the ground selection transistor is determined according to the GSL transition information do.

According to an embodiment of the present invention, it is possible to provide a nonvolatile memory device and an erase method for improving a threshold voltage distribution in an erase state by controlling a floating time point of a ground selection line according to a temperature during an erase operation.

1 is a block diagram illustrating a nonvolatile memory device according to the present invention.
FIG. 2 is a block diagram illustrating the memory cell array of FIG. 1 .
3 is a circuit diagram illustrating one BLKi of the memory blocks BLK1 to BLKz of FIG. 2 .
4 is a perspective view illustrating an embodiment of a structure corresponding to the memory block BLKi of FIG. 3 .
5 is a timing diagram exemplarily illustrating a voltage change of the memory block BLKi of FIG. 4 during an erase operation.
6 is a timing diagram illustrating voltage changes of the substrate SUB and the ground selection line GSL during an erase operation according to an embodiment of the present invention.
7 is a circuit diagram illustrating a voltage generating circuit and a GSL transition determining circuit of FIG. 1 according to an embodiment of the present invention.
8 is a flowchart illustrating a GSL transition method during an erase operation according to an embodiment of the present invention.
9 is a circuit diagram illustrating a circuit for determining the substrate voltage generator and the GSL voltage transition of FIG. 1 according to another embodiment of the present invention.
FIG. 10 is a view showing states of switches SW1 to SW3 of FIG. 9 according to operation modes.
11 is a block diagram illustrating an SSD according to an embodiment of the present invention.
12 is a block diagram illustrating an eMMC according to an embodiment of the present invention.
13 is a block diagram exemplarily showing a UFS system according to an embodiment of the present invention.
14 is a block diagram exemplarily illustrating a mobile device according to an embodiment of the present invention.

It is to be understood that both the foregoing general description and the following detailed description are exemplary, and it is to be considered that an additional description of the claimed invention is provided. Reference numerals are indicated in detail to preferred embodiments of the present invention, examples of which are indicated in the reference drawings. Wherever possible, the same reference numbers are used in the description and drawings to refer to the same or like parts.

Hereinafter, a nonvolatile memory device will be used as an example of a storage device or an electronic device for describing the features and functions of the present invention. However, one skilled in the art will readily appreciate other advantages and capabilities of the present invention in accordance with the teachings herein. In addition, the present invention may be implemented or applied through other embodiments. Moreover, the detailed description may be modified or changed according to the viewpoint and application without departing significantly from the scope, spirit and other objects of the present invention.

As an embodiment according to the concept of the present invention, a three-dimensional memory array is provided. A three-dimensional memory array may be formed monolithically on one or more physical levels of an array of memory cells having an active area disposed over a silicon substrate and circuitry associated with the operation of the memory cells. The circuitry involved in the operation of the memory cells may be located in or on the substrate. The term monolithic means that the layers of each level of the three-dimensional array are deposited directly over the layers of the lower level of the three-dimensional array.

As an embodiment according to the concept of the present invention, the 3D memory array has vertical directionality and includes vertical NAND strings in which at least one memory cell is positioned on another memory cell. At least one memory cell includes a charge trap layer. Each vertical NAND string may include at least one select transistor positioned over memory cells. The at least one selection transistor may have the same structure as the memory cells, and may be monolithically formed together with the memory cells.

A three-dimensional memory array is composed of a plurality of levels, has word lines or bit lines shared between the levels, and a configuration suitable for a three-dimensional memory array is described in U.S. Patent No. 7,679,133, U.S. Patent No. 8,553,466. No. 8,654,587, U.S. Patent No. 8,559,235, and U.S. Patent Publication No. 2011/0233648, which are incorporated herein by reference.

1 is a block diagram illustrating a nonvolatile memory device according to the present invention. Referring to FIG. 1 , the nonvolatile memory device 100 may include a memory cell array 110 , an address decoder 120 , a voltage generator 130 , a read and write circuit 140 , and a control logic 150 . can Physical characteristics of the nonvolatile memory device 100 may vary according to temperature. As the physical characteristics of the nonvolatile memory device 100 change, the threshold voltage distribution of the memory cells after the erase operation may also change. Accordingly, in order to improve the threshold voltage distribution of the memory cells during the erase operation, the floating point of the ground selection line GSL needs to be changed according to the temperature.

The memory cell array 110 is connected to the address decoder 120 through string select lines (SSL), word lines (WL), and ground select lines (GSL), , may be connected to the read and write circuit 140 through bit lines BL. The memory cell array 110 may include a plurality of memory blocks. Memory cells of each memory block may form a two-dimensional structure. Also, the memory cells of each memory block may be stacked in a direction perpendicular to the substrate to form a three-dimensional structure. Each memory block may include a plurality of memory cells and a plurality of selection transistors. The memory cells may be connected to the word lines WL, and the selection transistors may be connected to the string selection lines SSL or the ground selection lines GSL. The memory cells of each memory block may store one or more bits.

The address decoder 120 may be connected to the memory cell array 110 through string select lines SSL, word lines WL, and ground select lines GSL. The address decoder 120 may be configured to operate in response to the control of the control logic 150 . The address decoder 120 may receive an address ADDR from a controller (not shown). For example, the controller may receive a command and an address ADDR from the host to control the overall operation of the nonvolatile memory device 100 .

The address decoder 120 may be configured to decode a row address among the received addresses ADDR. Using the decoded row address, the address decoder 120 may select the string select lines SSL, the word lines WL, and the ground select lines GSL. The address decoder 120 receives various voltages from the voltage generator 130 , and applies the received voltages to the selected and unselected string select lines SSL, the word lines WL, and the ground select lines GSL, respectively. can transmit For example, the address decoder 120 may transfer the erase voltage Vers generated by the voltage generation circuit 131 to the substrate of the memory cell array 110 during an erase operation. In addition, the address decoder 120 may adjust the floating timing of the ground selection lines GSL according to the control of the control logic 150 during an erase operation.

The address decoder 120 may be configured to decode a column address among the transferred addresses ADDR. The decoded column address may be transmitted to the read and write circuit 130 . For example, the address decoder 120 may include components such as a row decoder, a column decoder, and an address buffer.

The voltage generator 130 may be configured to generate various voltages required by the nonvolatile memory device 100 . For example, the voltage generator 130 may generate a plurality of program voltages, a plurality of pass voltages, a plurality of selective read voltages, and a plurality of non-selective read voltages. The program voltages are applied to the selected word line during the program operation. The pass voltages are applied to the unselected word line during the program operation. Select read voltages are applied to the selected word line during a read operation. The unselected read voltage is applied to the unselected word line during a read operation.

The voltage generator 130 may include a voltage generation circuit 131 and a GSL transition determination circuit 132 . The voltage generation circuit 131 may generate various voltages required by the nonvolatile memory device 100 . For example, the voltage generation circuit 131 may generate an erase voltage Vers to be supplied to the substrate during an erase operation. Also, the voltage generation circuit 131 may generate erase voltages Vers having different levels according to temperature. The voltage generation circuit 131 may generate erase voltages Vers having different levels based on the first temperature information TMIF1 .

The GSL transition determining circuit 132 may receive a feedback voltage corresponding to the erase voltage Vers from the voltage generating circuit 131 . The GSL transition determining circuit 132 may compare the feedback voltage with a predetermined reference voltage and output GSL transition information showing a magnitude relationship between the erase voltage Vers and the predetermined reference voltage. Also, the GSL transition determining circuit 132 may change the GSL transition information based on the second temperature information TMIF2 . The GSL transition information may be provided to the control logic 150 to determine a floating point of the ground selection line GSL.

The read/write circuit 140 may be connected to the memory cell array 110 through bit lines BL, and may exchange data DATA with the controller. The read and write circuit 140 may operate in response to the control of the control logic 150 .

For example, the read/write circuit 140 may receive data DATA from the outside and write the received data DATA to the memory cell array 110 . The read/write circuit 140 may read data DATA from the memory cell array 110 and transmit the read data DATA to the outside. The read/write circuit 140 may read data from the first storage area of the memory cell array 110 and write the read data to the second storage area of the memory cell array 110 . For example, the read and write circuit 140 may be configured to perform a copy-back operation.

For example, the read/write circuit 140 may include components such as a page buffer (or page register), a column selection circuit, and a data buffer. As another example, the read/write circuit 140 may include components such as a sense amplifier, a write driver, a column selection circuit, and a data buffer.

The control logic 150 may be connected to the address decoder 120 , the voltage generator 130 , and the read/write circuit 140 . The control logic 150 may be configured to control overall operations of the nonvolatile memory device 100 . The control logic 150 may operate in response to the control signal CTRL transmitted from the controller.

The control logic 150 may receive GSL transition information from the GSL transition determining circuit 132 . The control logic 150 may generate a GSL control signal for controlling a floating point of the ground selection line GSL during an erase operation in response to the GSL transition information. During the erase operation, the address decoder 120 may float the ground selection lines GSL according to the GSL control signal.

During the erase operation, the nonvolatile memory device 100 according to an embodiment of the present invention may adjust the erase voltage Vers supplied to the substrate according to the temperature based on the first temperature information TMIF1 . Also, the nonvolatile memory device 100 may adjust the GSL transition information according to the temperature based on the second temperature information TMIF2 using a feedback voltage to which the first temperature information TMIF1 is reflected. Accordingly, during the erase operation, the nonvolatile memory device 100 may control the floating timing of the ground selection line GSL according to the temperature. In addition, by applying the offset with respect to the temperature twice, the range and linearity of the floating point of the ground selection line GSL during the erase operation may be improved.

FIG. 2 is a block diagram illustrating the memory cell array 110 of FIG. 1 . Referring to FIG. 2 , the memory cell array 110 may include a plurality of memory blocks BLK1 to BLKz. Each memory block may have a three-dimensional structure. For example, each memory block may include structures extending along first to third directions. Each memory block may include a plurality of NAND strings NS extending in the second direction. A plurality of NAND strings NS may be provided along the first and third directions.

Each memory block is connected to a plurality of bit lines BL, a plurality of string select lines SSL, a plurality of ground select lines GSL, a plurality of word lines WL, and a common source line CSL. can be connected Each NAND string NS may be connected to a bit line BL, a string select line SSL, a ground select line GSL, word lines WL, and a common source line CSL.

The memory blocks BLK1 to BLKz may be selected by the address decoder 120 illustrated in FIG. 1 . For example, the address decoder 120 may be configured to select a memory block BLK corresponding to a decoded row address from among the memory blocks BLK1 to BLKz.

3 is a circuit diagram illustrating one BLKi of the memory blocks BLK1 to BLKz of FIG. 2 . Referring to FIG. 3 , NAND strings NS11 to NS31 may be provided between the first bit line BL1 and the common source line CSL. NAND strings NS12 , NS22 , and NS32 may be provided between the second bit line BL2 and the common source line CSL. NAND strings NS13 , NS23 , and NS33 may be provided between the third bit line BL3 and the common source line CSL.

Each NAND string NS may include a string select transistor SST, a ground select transistor GST, and a plurality of memory cells MC connected between the string select transistor SST and the ground select transistor GST. . The string select transistor SST of each NAND string NS may be connected to a corresponding bit line BL. The ground selection transistor GST of each NAND string NS may be connected to the common source line CSL.

Hereinafter, NAND strings NS are defined in units of rows and columns. NAND strings NS commonly connected to one bit line BL form one column. For example, the NAND strings NS11 to NS31 connected to the first bit line BL1 may correspond to the first column. The NAND strings NS12 to NS32 connected to the second bit line BL2 may correspond to the second column. The NAND strings NS13 to NS33 connected to the third bit line BL3 may correspond to the third column.

The NAND strings NS connected to one string selection line SSL form one row. For example, the NAND strings NS11 to NS13 connected to the first string selection line SSL1 form a first row. The NAND strings NS21 to NS23 connected to the second string selection line SSL2 form a second row. The NAND strings NS31 to NS33 connected to the third string selection line SSL3 form a third row.

In each NAND string NS, a height is defined. For example, in each NAND string NS, the height of the memory cell MC1 adjacent to the ground select transistor GST is 1 . In each NAND string NS, the height of the memory cell increases as it is adjacent to the string select transistor SST. In each NAND string NS, the height of the memory cell MC7 adjacent to the string select transistor SST is 7 .

NAND strings NS in the same row share a string select line SSL. NAND strings NS of different rows are connected to different string select lines SSL. The NAND strings NS11 to NS13, NS21 to NS22, and NS31 to NS33 share a ground selection line GSL. Memory cells of the same height of the NAND strings NS in the same row share a word line. At the same height, the word lines WL of the NAND strings NS in different rows are commonly connected. The common source line CSL is commonly connected to the NAND strings NS.

As shown in FIG. 3 , the word lines WL having the same height are connected in common. Accordingly, when a specific word line WL is selected, all NAND strings NS connected to the specific word line WL will be selected. NAND strings NS of different rows are connected to different string select lines SSL. Accordingly, by selecting the string selection lines SSL1 to SSL3 , the NAND strings NS of an unselected row among the NAND strings NS connected to the same word line WL are transferred from the bit lines BL1 to BL3. can be separated. That is, a row of the NAND strings NS may be selected by selecting the string selection lines SSL1 to SSL3 . Also, by selecting the bit lines BL1 to BL3, the NAND strings NS of the selected row may be selected in units of columns.

4 is a perspective view illustrating an embodiment of a structure corresponding to the memory block BLKi of FIG. 3 . Referring to FIG. 4 , the memory block BLKi may be formed in a direction perpendicular to the substrate SUB. An n+ doped region may be formed in the substrate SUB.

A gate electrode layer and an insulation layer may be alternately deposited on the substrate SUB. An information storage layer may be formed between the gate electrode layer and the insulation layer. When the gate electrode layer and the insulating layer are vertically patterned, a V-shaped pillar may be formed. The pillar may be connected to the substrate SUB through the gate electrode layer and the insulating layer. The inside of the pillar may be formed of an insulating material such as silicon oxide as a filling dielectric pattern. The outside of the pillar may be formed of a channel semiconductor in a vertical active pattern.

A gate electrode layer of the memory block BLKi may be connected to a ground select line GSL, a plurality of word lines WL1 to WL7, and a string select line SSL. In addition, a pillar of the memory block BLKi may be connected to the plurality of bit lines BL1 to BL3 . In FIG. 4 , one memory block BLKi is illustrated as having two selection lines GSL and SSL, seven word lines WL1 to WL7, and three bit lines BL1 to BL3. may be more or less than these.

5 is a timing diagram exemplarily illustrating a voltage change of the memory block BLKi of FIG. 4 during an erase operation. 1 to 5 , after a predetermined time elapses from a time point t1 when the erase voltage Vers is applied to the substrate SUB, the ground selection line GSL may float. This is to ensure that the erase voltage Vers is smoothly supplied to the channel during the erase operation. For example, when the erase voltage Vers is supplied to the substrate SUB, the erase voltage Vers is supplied to the channel region along the holes. Meanwhile, when the ground selection line GSL floats at the first time point t1 and the voltage increases due to coupling with the substrate SUB, it may not be easy to transfer the erase voltage Vers to the channel region. Accordingly, in order to facilitate voltage transfer through a hole, the ground selection line GSL may be floated after a predetermined time elapses from the first time point t1 .

At a first time point t1 , the erase voltage Vers starts to be applied to the substrate SUB. The erase voltage Vers may be a high voltage. At a time point t1 when the erase voltage Vers is applied, the ground selection line voltage Vgsl is applied to the ground selection line GSL. The ground selection line voltage Vgsl may be applied to the ground selection line GSL until the second time point t2. At a point in time t1 when the erase voltage Vers starts to be applied, the word line erase voltage Vwe is applied to the word lines WL.

The ground select line voltage Vgsl and the word line erase voltage Vwe are low voltages. For example, the ground select line voltage Vgsl and the word line erase voltage Vwe may be the ground voltage (0V). Between the first time point t1 and the second time point t2 , the difference between the ground selection line voltage Vgsl and the word line erase voltage Vwe and the erase voltage Vers may be maintained. Accordingly, the rising erase voltage Vers may be stably transferred to a vertical active pattern corresponding to the memory cells MC1 to MC7 .

The string selection line SSL is floated from a time point t1 when the erase voltage Vers is applied. The voltage of the string select line SSL will increase due to the influence of coupling. The string select transistor SST may be erase-inhibited.

At a second time point t2, the GSL control signal may be changed from a low level to a high level. Accordingly, the ground selection line GSL will float according to the GSL control signal at the second time point t2. Due to the influence of the coupling, the voltage of the ground select line GSL will rise. No Fowler-Nordheim tunneling will occur in the ground select transistor (GST). The ground select transistor GST will be erase-inhibited.

Meanwhile, a difference between the erase voltage Vers and the word line erase voltage Vwe after the second time t2 may cause Fowler-Nordheim tunneling in the memory cells MC. Accordingly, data of the memory cells MC will be erased.

6 is a timing diagram illustrating voltage changes of the substrate SUB and the ground selection line GSL during an erase operation according to an embodiment of the present invention. 1 and 6 , different erase voltages Vers may be applied to the substrate SUB according to temperature. Hereinafter, it is assumed that the first temperature TEMP1 is greater than the second temperature TEMP2.

At a first time point t1 , the erase voltage Vers starts to be applied to the substrate SUB. For example, the first erase voltage Vers_TEMP1 may be applied to the substrate SUB at the first temperature TEMP1 . At the second temperature TEMP2 , the second erase voltage Vers_TEMP2 may be applied to the substrate SUB. That is, a higher erase voltage Vers may be applied at a low temperature. The voltage generation circuit 131 may generate different erase voltages Vers according to the temperature by using the first temperature information TMIF1 .

At a first time point t1 , a ground selection line voltage Vgsl may be applied to the ground selection line GSL. The ground selection line voltage Vgsl may be maintained for a predetermined time. For example, at the first temperature TEMP1 , the ground selection line GSL may be maintained at the ground selection line voltage Vgsl until the second time point t2_1 . At the second temperature TEMP2 , the ground selection line GSL may be maintained at the ground selection line voltage Vgsl until the second time t2_2 . For example, the ground selection line voltage Vgsl may be a ground voltage 0V.

The GSL transition determining circuit 132 may generate GSL transition information using the second temperature information TMIF2 . The control logic 150 may generate a GSL control signal according to the GSL transition information. The GSL control signal may transition at different times depending on the temperature. For example, at the first temperature TEMP1 , the GSL control signal may transition to a high level at the second time point t2_1 . At the second temperature TEMP2 , the GSL control signal may transition to a high level at a second time point t2_2 .

The address decoder 120 may float the ground selection line GSL according to a GSL control signal. For example, at the first temperature TEMP1 , the ground selection line GSL may float at the second time point t2_1 . At the second temperature TEMP2 , the ground selection line GSL may float at the second time point t2_2 .

As described above, during the erase operation, the floating time of the ground selection line GSL may be controlled differently depending on the temperature. In addition, by applying the offset with respect to the temperature twice, the range and linearity of the floating point of the ground selection line GSL during the erase operation may be improved.

7 is a circuit diagram illustrating a voltage generating circuit and a GSL transition determining circuit of FIG. 1 according to an embodiment of the present invention. Referring to FIG. 7 , the voltage generation circuit 131 may include a first regulator 131-1 and a charge pump 131-2. For example, the voltage generation circuit 131 may generate an erase voltage Vers supplied to the substrate during an erase operation. Also, the voltage generating circuit 131 may generate necessary voltages during another operation (ie, a program or read operation). The GSL transition determining circuit 132 may include a second regulator 132-1. The voltage generating circuit 131 and the GSL transition determining circuit 132 may be connected through the first switch SW1 . The first switch SW1 may be turned on during an erase operation. The first switch SW1 may be turned off during a program or read operation. Accordingly, the GSL transition determining circuit 132 may be connected to the voltage generating circuit 131 only during an erase operation.

During an erase operation, the voltage generation circuit 131 may generate an erase voltage Vers under the control of the control logic 150 . For example, the first regulator 131-1 may receive the erase target voltage ERS_tg, the feedback voltage Vfb, and the first temperature information TMIF1. The first regulator 131-1 may compensate the erase target voltage ERS_tg based on the first temperature information TMIF1 . For example, the first regulator 131-1 may increase or decrease the erase target voltage ERS_tg according to the first temperature information TMIF1 . The first regulator 131-1 may compensate to increase the erase target voltage ERS_tg at the second temperature TEMP2 than at the first temperature TEMP1 . The first regulator 131-1 may generate the pump control signal PUMP_con by comparing the feedback voltage Vfb with the compensated erase target voltage ERS_tg. For example, the feedback voltage Vfb is a voltage divided by the first and second resistors R1 and R2 and corresponds to the erase voltage Vers.

The charge pump 131 - 2 may control the erase voltage Vers according to the pump control signal PUMP_con. For example, when the feedback voltage Vfb is less than the compensated erase target voltage ERS_tg, the erase voltage Vers may be increased. When the feedback voltage Vfb is greater than or equal to the compensated erase target voltage ERS_tg, the erase voltage Vers may be maintained at a constant value.

During the erase operation, the second regulator 132-1 may receive the GSL target voltage GSL_tg, the feedback voltage Vfb, and the second temperature information TMIF2. The second regulator 132-1 may compensate the GSL target voltage GSL_tg based on the second temperature information TMIF2 . For example, the second regulator 132-1 may increase or decrease the GSL target voltage GSL_tg according to the second temperature information TMIF2 . The second regulator 132-1 may compensate to increase the GSL target voltage ERS_tg in the case of the second temperature TEMP2 than in the case of the first temperature TEMP1. The second regulator 132-1 may generate GSL transition information GSL_con by comparing the feedback voltage Vfb with the compensated GSL target voltage GSL_tg. For example, when the feedback voltage Vfb is smaller than the compensated GSL target voltage GSL_tg, the GSL transition information GSL_con may have a low level. When the feedback voltage Vfb is greater than or equal to the compensated GSL target voltage GSL_tg, the GSL transition information GSL_con may have a high level.

The control logic 150 may generate a GSL control signal based on the GSL transition information GSL_con. For example, when the GSL transition information GSL_con is changed from a low level to a high level, the GSL control signal may be changed from a low level to a high level. When the GSL transition information GSL_con is changed from the high level to the low level, the GSL control signal may be changed from the high level to the low level. The address decoder 120 may float the ground selection line GSL according to the GSL control signal.

As described above, the nonvolatile memory device 100 according to an embodiment of the present invention may control the floating timing of the ground selection line GSL according to the temperature during the erase operation. In addition, by applying the offset with respect to the temperature twice, the range and linearity of the floating point of the ground selection line GSL during the erase operation may be improved.

8 is a flowchart illustrating a GSL transition method during an erase operation according to an embodiment of the present invention. Physical characteristics of the nonvolatile memory device 100 may vary according to temperature. Therefore, during the erase operation, the floating point of the ground selection line GSL needs to be changed according to the temperature. 1, 7, and 8 , the nonvolatile memory device 100 may change the floating point of the ground selection line GSL according to the temperature.

In operation S110 , the voltage generation circuit 131 may receive the first temperature information TMIF1 and the erase target voltage ERS_tg. For example, the first temperature information TMIF1 may be offset values for compensating for the erase target voltage ERS_tg according to the temperature.

In operation S120 , the voltage generation circuit 131 may compensate the erase target voltage ERS_tg based on the first temperature information TMIF1 . For example, the first regulator 131-1 may receive the erase target voltage ERS_tg, the feedback voltage Vfb, and the first temperature information TMIF1. The first regulator 131-1 may compensate the erase target voltage ERS_tg based on the first temperature information TMIF1 . For example, the first regulator 131-1 may increase or decrease the erase target voltage ERS_tg according to the first temperature information TMIF1 . The first regulator 131-1 may compensate to increase the erase target voltage ERS_tg at the second temperature TEMP2 than at the first temperature TEMP1 .

In operation S130 , the voltage generation circuit 131 may compare the feedback voltage Vfb corresponding to the erase voltage Vers with the compensated erase target voltage ERS_tg to generate the pump control signal PUMP_con. For example, the first regulator 131-1 may generate the pump control signal PUMP_con by comparing the feedback voltage Vfb with the compensated erase target voltage ERS_tg. The feedback voltage Vfb is a voltage divided by the first and second resistors R1 and R2 and corresponds to the erase voltage Vers.

In operation S140 , the voltage generation circuit 131 may generate an erase voltage Vers based on the pump control signal PUMP_con. For example, the charge pump 131 - 2 may control the erase voltage Vers according to the pump control signal PUMP_con. When the feedback voltage Vfb is less than the compensated erase target voltage ERS_tg, the erase voltage Vers may be increased. When the feedback voltage Vfb is greater than or equal to the compensated erase target voltage ERS_tg, the erase voltage Vers may be maintained at a constant value.

In operation S150 , the GSL transition determining circuit 132 may receive the second temperature information TMIF2 and the GSL target voltage GSL_tg. For example, the second temperature information TMIF2 may be offset values for compensating the GSL target voltage ERS_tg according to the temperature.

In operation S160 , the GSL transition determining circuit 132 may compensate the GSL target voltage GSL_tg based on the second temperature information TMIF2 . For example, the second regulator 132-1 may compensate the GSL target voltage GSL_tg based on the second temperature information TMIF2 . The second regulator 132-1 may increase or decrease the GSL target voltage GSL_tg according to the second temperature information TMIF2 . The second regulator 132-1 may compensate to increase the GSL target voltage ERS_tg in the case of the second temperature TEMP2 than in the case of the first temperature TEMP1.

In operation S170 , the GSL transition determining circuit 132 may compare the feedback voltage Vfb corresponding to the erase voltage Vers with the compensated GSL target voltage GSL_tg to generate the GSL transition information GSL_con. For example, the second regulator 132-1 may generate the GSL transition information GSL_con by comparing the feedback voltage Vfb with the compensated GSL target voltage GSL_tg. When the feedback voltage Vfb is less than the compensated GSL target voltage GSL_tg, the GSL transition information GSL_con may have a low level. When the feedback voltage Vfb is greater than or equal to the compensated GSL target voltage GSL_tg, the GSL transition information GSL_con may have a high level.

In operation S180 , the control logic 150 may generate a GSL control signal based on the GSL transition information GSL_con. The GSL control signal may indicate when the ground selection line GSL floats. For example, when the GSL transition information GSL_con is changed from a low level to a high level, the GSL control signal may be changed from a low level to a high level. When the GSL transition information GSL_con is changed from the high level to the low level, the GSL control signal may be changed from the high level to the low level. The address decoder 120 may float the ground selection line GSL when the GSL control signal rises to a high level.

As described above, the nonvolatile memory device 100 according to an embodiment of the present invention may control the floating timing of the ground selection line GSL according to the temperature during the erase operation. In addition, by applying the offset with respect to the temperature twice, the range and linearity of the floating point of the ground selection line GSL during the erase operation may be improved.

9 is a circuit diagram illustrating a circuit for determining a substrate voltage generator and a GSL voltage transition of FIG. 1 according to another embodiment of the present invention. FIG. 10 is a view showing states of switches SW1 to SW3 of FIG. 9 according to operation modes. 9 and 10 , the voltage generating circuit 131 and the GSL transition determining circuit 132 may operate in an erase mode or a trim mode.

In the erase mode, the first and second switches SW1 and SW2 may be turned on, and the third switch SW3 may be turned off. In this case, the voltage generating circuit 131 and the GSL transition determining circuit 132 may perform the normal erase operation described above.

In the trim mode, the first and third switches SW1 and SW3 may be turned on, and the second switch SW2 may be turned off. At this time, the charge pump 131 - 2 receives the GSL transition information GSL_con instead of the pump control signal PUMP_con. Accordingly, the charge pump 131 - 2 may output an erase voltage Vers corresponding to the GSL target voltage GSL_tg. The nonvolatile memory device 100 may determine the suitability of the GSL target voltage GSL_tg by checking the level of the erase voltage Vers corresponding to the GSL target voltage GSL_tg.

11 is a block diagram illustrating an SSD according to an embodiment of the present invention. Referring to FIG. 11 , the SSD 1000 may include a plurality of nonvolatile memory devices 1100 and an SSD controller 1200 .

The nonvolatile memory devices 1100 may be implemented to selectively receive an external high voltage VPPx. Each of the nonvolatile memory devices 1100 may control the floating timing of the ground selection line GSL according to the temperature during the erase operation as described with reference to FIGS. 1 to 10 . In addition, by applying the offset with respect to the temperature twice, the range and linearity of the floating point of the ground selection line GSL during the erase operation may be improved.

The SSD controller 1200 may be connected to the nonvolatile memory devices 1100 through a plurality of channels (CH1 to CHi, where i is an integer greater than or equal to 2). The SSD controller 1200 may include at least one processor 1210 , a buffer memory 1220 , an error correction circuit 1230 , a host interface 1240 , and a nonvolatile memory interface 1250 .

The buffer memory 1220 may temporarily store data necessary for driving the memory controller 1200 . The buffer memory 1220 may include a plurality of memory lines for storing data or commands.

The error correction circuit 1230 calculates an error correction code value of data to be programmed in a write operation, corrects data read in a read operation based on the error correction code value, and performs an error correction in the data recovery operation of the nonvolatile memory device 1100 ) can correct errors in data recovered from Although not shown, a code memory for storing code data required for driving the memory controller 1200 may be further included. The code memory may be implemented as a nonvolatile memory device.

The host interface 1240 may provide an interface function with an external device. Here, the host interface 1240 may be a NAND interface. The nonvolatile memory interface 1250 may provide an interface function with the nonvolatile memory device 1100 .

12 is a block diagram illustrating an eMMC according to an embodiment of the present invention. Referring to FIG. 12 , the eMMC 2000 may include at least one NAND flash memory device 2100 and a controller 2200 .

The NAND flash memory device 2100 may be a single data rate (SDR) NAND or a double data rate (DDR) NAND. Alternatively, the NAND flash memory device 2100 may be a vertical NAND flash memory device (VNAND). As described with reference to FIGS. 1 to 10 , the NAND flash memory device 2100 may control the floating timing of the ground selection line GSL according to the temperature during the erase operation. In addition, by applying the offset with respect to the temperature twice, the range and linearity of the floating point of the ground selection line GSL during the erase operation may be improved.

The controller 2200 may be connected to the NAND flash memory device 2100 through a plurality of channels. The controller 2200 may include at least one controller core 2210 , a host interface 2240 , and a NAND interface 2250 . At least one controller core 2210 may control the overall operation of the eMMC 2000 . The host interface 2240 may perform interfacing between the controller 2210 and the host. The NAND interface 2250 interfaces the NAND flash memory device 2100 and the controller 2200 . In an embodiment, the host interface 2240 may be a parallel interface (eg, an MMC interface). In another embodiment, the host interface 2240 of the eMMC 2000 may be a serial interface (eg, UHS-II, UFS interface).

The eMMC 2000 may receive power supply voltages Vcc and Vccq from the host. Here, the first power voltage (Vcc, for example, 3.3V) is provided to the NAND flash memory device 2100 and the NAND interface 2250 , and the second power voltage (Vccq, for example, 1.8V/3.3V) is It may be provided to the controller 2200 . In an embodiment, the eMMC 2000 may selectively receive an external high voltage VPPx.

The present invention is also applicable to a UFS (Universal Flash Storage) system. 13 is a block diagram exemplarily showing a UFS system according to an embodiment of the present invention. Referring to FIG. 13 , the UFS system 3000 may include a UFS host 3100 and a UFS device 3200 .

The UFS host 3100 may include an application 3110 , a device driver 3120 , a host controller 3130 , and a buffer RAM 3140 . In addition, the host controller 3130 may include a command queue (CMD queue) 3131 , a host DMA 3132 , and a power manager 3133 . The command queue 3131 , the host DMA 3132 , and the power manager 3133 may operate in the host controller 3130 as an algorithm, software, or firmware.

A command (eg, a write command) generated by the application 3110 and the device driver 3120 of the UFS host 3100 may be input to the command queue 3131 of the host controller 3130 . The command queue 3131 may sequentially store commands to be provided to the UFS device 3200 . The command stored in the command queue 3131 may be provided to the host DMA 3132 . The host DMA 3132 sends a command to the UFS device 3200 through the host interface 3101 .

Continuing to refer to FIG. 13 , the UFS device 3200 may include a flash memory 3210 , a device controller 3230 , and a buffer RAM 3240 . And the device controller 3230 is a central processing unit (CPU, 3231), a command manager (CMD manager, 3232), flash DMA (3233), security manager (security manager, 3234), buffer manager (3235), flash conversion layer ( A Flash Translation Layer (FTL) 3236 , and a flash manager 3237 . Here, the command manager 3232 , the security manager 3234 , the buffer manager 3235 , the flash translation layer 3236 , and the flash manager 3237 operate as algorithms, software, or firmware within the device controller 3230 . can do.

The flash memory 3210 may control the floating timing of the ground selection line GSL according to the temperature during the erase operation as described with reference to FIGS. 1 to 10 . In addition, by applying the offset with respect to the temperature twice, the range and linearity of the floating point of the ground selection line GSL during the erase operation may be improved.

A command input from the UFS host 3100 to the UFS device 3200 may be provided to the command manager 3232 through the device interface 3201 . The command manager 3232 may interpret a command provided from the UFS host 3100 and authenticate the input command using the security manager 3234 . The command manager 3232 may allocate the buffer RAM 3240 to receive data through the buffer manager 3235 . When the data transmission preparation is completed, the command manager 3232 sends a READY_TO_TRANSFER (RTT) UPIU to the UFS host 3100 .

The UFS host 3100 may transmit data to the UFS device 3200 in response to the RTT UPIU. Data may be transmitted to the UFS device 3200 through the host DMA 3132 and the host interface 3101 . The UFS device 3200 may store the received data in the buffer RAM 3240 through the buffer manager 3235 . Data stored in the buffer RAM 3240 may be provided to the flash manager 3237 through the flash DMA 3233 . The flash manager 3237 may store data at a selected address of the flash memory 3210 by referring to address mapping information of the flash translation layer 3236 .

When the transmission of data required for the command and the program are completed, the UFS device 3200 sends a response signal to the UFS host 3100 through the interface and notifies the completion of the command. The UFS host 3100 may notify the device driver 3120 and the application 3110 of whether the command to which the response signal has been received has been completed, and terminate the operation for the command.

The present invention is also applicable to mobile devices. 14 is a block diagram exemplarily illustrating a mobile device according to an embodiment of the present invention. Referring to FIG. 14 , a mobile device 4000 may include an application processor 4100 , a communication module 4200 , a display/touch module 4300 , a storage device 4400 , and a mobile RAM 4500 .

The application processor 4100 may control the overall operation of the mobile device 4000 . The communication module 4200 will be implemented to control wired/wireless communication with the outside. The display/touch module 4300 may be implemented to display data processed by the application processor 4100 or to receive data from a touch panel. The storage device 4400 may be implemented to store user data. The storage device 4400 may be an eMMC, SSD, or UFS device. The mobile RAM 4500 may be implemented to temporarily store data necessary for a processing operation of the mobile device 4000 .

As described with reference to FIGS. 1 to 10 , the storage device 4400 may control the floating point of the ground selection line GSL according to the temperature during the erase operation. In addition, by applying the offset with respect to the temperature twice, the range and linearity of the floating point of the ground selection line GSL during the erase operation may be improved.

The memory system or storage device according to an embodiment of the present invention may be mounted using various types of packages. For example, the memory system or storage device according to an embodiment of the present invention is a PoP (Package on Package), Ball grid arrays (BGAs), Chip scale packages (CSPs), Plastic Leaded Chip Carrier (PLCC), Plastic Dual In- Line Package(PDIP), Die in Waffle Pack, Die in Wafer Form, Chip On Board(COB), Ceramic Dual In-Line Package(CERDIP), Plastic Metric Quad Flat Pack(MQFP), Thin Quad Flatpack(TQFP), Small Outline(SOIC), Shrink Small Outline Package(SSOP), Thin Small Outline(TSOP), Thin Quad Flatpack(TQFP), System In Package(SIP), Multi Chip Package(MCP), Wafer-level Fabricated Package(WFP), It may be mounted using packages such as Wafer-Level Processed Stack Package (WSP).

As described above, embodiments have been disclosed in the drawings and the specification. Although specific terms are used herein, they are used only for the purpose of describing the present invention and are not used to limit the meaning or the scope of the present invention described in the claims. Therefore, it will be understood by those of ordinary skill in the art that various modifications and equivalent other embodiments are possible therefrom. Therefore, the true technical protection scope of the present invention should be determined by the technical spirit of the appended claims.

100: non-volatile memory device
110: memory cell array
120: address decoder
130: voltage generator
131: voltage generation circuit
132: GSL transition decision circuit
140: read and write circuit
150: control logic
1000 : SSD
2000: eMMC
3000: UFS system
4000 : mobile device

Claims (10)

a plurality of cell strings, wherein each cell string includes a plurality of memory cells stacked in a direction perpendicular to a substrate, a ground select transistor provided between the plurality of memory cells and the substrate, and the plurality of memory cells and a bit a memory cell array including a string select transistor provided between the lines;
an address decoder that provides an erase voltage to the substrate during an erase operation, and floats a ground select line connected to the ground select transistor after a specific time after the erase voltage is applied;
generating the erase voltage that changes according to temperature based on first temperature information, and generates ground selection line transition information that varies according to the temperature based on a feedback voltage corresponding to the erase voltage and second temperature information voltage generator; and
a control logic for generating a ground selection line control signal based on the ground selection line transition information;
and the address decoder floats the ground selection line at a time point that varies according to the temperature according to the ground selection line control signal. The method of claim 1,
The voltage generator is
a voltage generating circuit generating the erase voltage and the feedback voltage; and
and a ground selection line transition determining circuit configured to generate the ground selection line transition information. 3. The method of claim 2,
the voltage generating circuit includes a regulator receiving an erase target voltage and compensating the erase target voltage according to the first temperature information;
and the regulator compares the compensated erase target voltage and the feedback voltage to generate a pump control signal. 4. The method of claim 3,
and the voltage generator circuit includes a charge pump configured to generate the erase voltage according to the pump control signal. 3. The method of claim 2,
the ground selection line transition determining circuit includes a regulator receiving a ground selection line target voltage and compensating for the ground selection line target voltage according to the second temperature information;
and the regulator compares the compensated ground select line target voltage and the feedback voltage to generate the ground select line transition information. 6. The method of claim 5,
When the feedback voltage is less than the compensated ground select line target voltage, the ground select line transition information has a first level;
When the feedback voltage is greater than or equal to the compensated ground selection line target voltage, the ground selection line transition information has a second level. word lines connected to a plurality of memory cells stacked in a direction perpendicular to the substrate;
a ground selection line connected to a ground selection transistor provided between the plurality of memory cells and the substrate; and
a string select line connected to a string select transistor provided between the plurality of memory cells and a bit line;
In an erase operation, the ground select line floats a specific time after an erase voltage is applied to the substrate;
The specific time is a nonvolatile memory device that varies according to temperature. 8. The method of claim 7,
The erase voltage is controlled to increase or decrease by an offset voltage according to a temperature based on the first temperature information. 9. The method of claim 8,
The ground selection line transition information is generated based on a feedback voltage corresponding to the erase voltage compensated by the first temperature information and second temperature information,
The ground selection line is floated at different times according to temperature based on the ground selection line transition information. 8. The method of claim 7,
the first temperature is higher than the second temperature, and the erase voltage is generated to have a higher level at the second temperature than the first temperature;
The ground selection line is floated at a later point in time at the second temperature than at the first temperature.

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