KR102301144B1 - Device for processing short time fourier transform of low complexity and method thereof - Google Patents

Abstract

The present invention relates to a low-complexity short-time Fourier transform processing apparatus and method, and a technical problem to be solved is to provide a length of a variable window function and a variable overlap size to minimize information loss according to the type of the window function. to provide a variety of time and frequency resolutions.
As an example, one channel of stream data is received and sequentially delayed at different rates to generate stream data of 4 channels that are overlapped at a certain rate between delayed stream data and arranged in parallel with each other, and the stream data of 4 channels are windowed. a DMM for outputting 4-channel stream data reconstructed according to the length of each window function by performing a multiplication operation with a type of window function according to the length; an R4BM for performing an STFT operation on the stream data output through the DMM according to a preset type of window function to output the STFT-calculated 4-channel stream data; a DRM for receiving the STFT-calculated 4-channel stream data from the R4BM, reconstructing it according to the input structure of the 1-channel stream data, and outputting it; and a MUX for receiving the stream data of 4 channels output through the DMM and outputting the data to any one of the R4BMs to perform an STFT operation according to a window length.

Description

Low-complexity short-time Fourier transform processing apparatus and method

An embodiment of the present invention relates to a low-complexity short-time Fourier transform processing apparatus and method.

STFT (short time Fourier transform) performs a fast Fourier transform (FFT) operation on an input non-stationary signal by moving a window function on a frame-by-frame basis to change the frequency of a signal according to time can be observed.

Due to these characteristics, STFT is widely used in various fields that require frequency measurement over time, such as radar systems, voice signal processing systems, and RFID systems.

In order to measure the frequency of a continuously incoming abnormal signal in real time, it is essential to implement the STFT algorithm into a hardware processor.

The STFT processor is composed of a window function and an FFT processor. The window function divides an abnormal signal into frames of a certain length and allows the user to obtain time information. It serves to reduce data leakage. In particular, the type and length of the window function in the STFT processor are closely related to the performance, and the type and length of the window function appropriate for each application are different.

In the STFT processor, the length of the window function is related to the resolution of the signal, and as the length of the window function is longer, high frequency resolution is supported, but the time resolution is lowered. In particular, since the resolution of time and frequency required for each field to which the STFT processor is applied is different, the length of the window function must be variably determined to support various resolutions of time and frequency.

The type of window function of the STFT processor is related to data loss, and various types of tapering window functions are used to reduce spectral loss due to side lobe.

However, since the taper window function is usually very small or zero at the beginning and the end, data loss occurs near the boundary. To solve this problem, data loss should be minimized by overlapping window functions. Each type of window function has a different size of overlap that minimizes data loss.

In order to minimize the loss of data when using the window function, the window function is generally used with overlap of 0% to 75%. Therefore, it should be possible to change the nesting size variably so as to support the overlapping size that minimizes data loss according to the type of the window function.

In addition, in order to implement a real-time STFT processor capable of variably changing the overlapping size, a minimum 4-channel FFT processor is required. In a multi-channel structure, a method of implementing an FFT processor of the single-path delay feedback (SDF) method having the feature of minimizing the most complex non-simple multiplication in a single path as much as the data path is commonly used.

However, there is a problem in that the hardware complexity increases linearly with the number of data paths. In order to solve this problem, conventionally, a method for reducing complexity by processing multiple data paths with one FFT processor using a multi-path delay commutator (MDC) type FFT processor has been proposed.

In order to improve the performance of the STFT, many studies are still in progress.

On the other hand, Zhang proposed a method of implementing the STFT processor in parallel with FFT modules having multiple pipeline structures. In this way, the STFT processor multiplies the input signal with a window function and provides the result as an input to the FFT processor. By applying the method, each FFT processor can simultaneously measure the frequency at a specific time, and since the multiplication operation of the window function is separated from the FFT operation, there is an advantage that various window functions can be used.

However, since such an STFT processor needs to implement a large number of FFT modules in parallel, it has a disadvantage in that it requires a large area in terms of hardware.

In addition, Nagapuri proposed a method of implementing the STFT processor as an FFT module of a pipeline structure. This method has the advantage of reducing the area and latency of hardware by reusing the FFT operation result.

However, this STFT processor can be used only in the case of a rectangular window, and has the disadvantage of supporting only 50% overlap.

1. L. Liu, D. McLernon, M. Ghogho, W. Hu, J. Huang, “Ballistic missile detection via micro-Doppler frequency estimation from radar return,” Digital Signal Processing, vol. 22, no. 1, pp. 87-95, Jan. 2012. 2. Ahmet Elbir, Hamza Osman Ilhan, Gorkem Serbes, Nizamettin Aydin, “Short Time Fourier Transform based music Genre classification,” 2018 Electric Electronics Computer Science Biomedical Engineerings` Meeting (EBBT), 2018. 3. Rubayet-E-Azim, N. Karmakar, E. Amin, “Short Time Fourier Transform (STFT) for collision detection in chipless RFID systems,” 2015 International Symposium on Antennas and Prpagation (ISAP), pp. 1-4, Nov 2015. 4. N. A. Khan, M. N. Jafri, S. A. Qazi, “Improved resolution short-time Fourier transform,” Emerging Technologies (ICET), pp. 1-3, 2011. 5. C. Mateo, J. A. Talavera, “Short-time Fourier transform with the window size fixed in the frequency domain,” Digital Signal Processing, vol. 77, pp 13-21, June. 2018 6. Q. Yin, L. Shen, M. Lu, X. Wang, Z. Liu, “Selection of optimal window length using STFT for quantitative SNR analysis of LFM signal,” J. Syst. Eng. Electron., vol. 24, no. 1, pp. 26-35, Feb. 2013 7. G. Heinzel, A. Rudiger, R. Schilling, “Spectrum and spectral density estimation by the discrete Fourier transform (DFT) including a comprehensive list of window functions and some new at-top windows,” Albert-Einstein-Institut, Feb. 2002 8. S. He, M. Torkelson, “A new approach to pipeline FFT processor,” Proc. of IPPS, pp. 766-770, 1996. 9. T. Sansaloni, A. Perez-Pascual, V. Torres, J. Valls, “Efficient pipeline FFT processors for WLAN MIMO-OFDM systems,” Electron. Lett., vol. 41, no. 19, pp. 1043-1044, Sep. 2005. 10. S. Zhang, D. Yu, S. Sheng, “A discrete STFT processor for realtime spectrum anlysis,” APCCAS - Asia Pacific Conference on Circuits and Systems, 2006. 11. N. Srinivas, P. K. Kumar, G. Pradhan, “Low latency architecture design and implementation for short-time fourier transform algorithm on fpga,” Microwaves Antennas Communications and Electronic Systems (COMCAS) 2017 IEEE international Conference on, pp. 1-5, 2017. 12. Y. Jung, H. Yoon, J. Kim, “New efficient FFT algorithm and pipeline implementation results for OFDM/DMT applications,” IEEE Trans. Consumer Electron., vol. 49, pp. 14-20, Feb. 2003. 13. S. Yoshizawa, A. Orikasa, Y. Miyanaga, “An area and power efficient pipeline fft processor for \$8 times 8\$ mimo-ofdm systems,” IEEE int. Symp. Circuits and Systems (ISCAS) 2011, pp. 2705-2708, 2011.

An embodiment of the present invention provides a length of a variable window function and supports a variable overlap size to minimize loss of information according to the type of the window function, thereby providing various time and frequency resolutions for a short time with low complexity. A Fourier transform processing apparatus and method are provided.

A low-complexity short-time Fourier transform apparatus according to an embodiment of the present invention receives stream data of one channel, sequentially delays it at different rates, overlaps between delayed stream data at a certain rate, and parallel-aligns stream data of four channels a DMM (Data Matching Module) for generating and outputting 4-channel stream data reconstructed according to the length of each window function by multiplying the 4-channel stream data with a window function of a type according to a window length; a plurality of Radix-4 Butterfly Modules (R4BMs) that perform a Short Time Fourier Transform (STFT) operation on the stream data output through the DMM according to a preset type of window function to output STFT-calculated 4-channel stream data; and a Data Reordering Module (DRM) for receiving the STFT-calculated 4-channel stream data from the R4BM, reconstructing it according to the input structure of the 1-channel stream data, and outputting it.

In addition, it may further include a MUX (multiplexer) for outputting the stream data of 4 channels output through the DMM to the R4BM to perform the STFT operation according to the window length.

In addition, the DMM receives the stream data of one channel, the first channel stream data delayed by 75% compared to the input stream data of one channel, the second channel stream data delayed by 50%, the third channel stream data delayed by 25%, 4 channel stream data with a 0% delay is generated between the first channel stream data and the second channel stream data, between the second channel stream data and the third channel stream data, and between the third channel stream data and the The fourth channel stream data may overlap each other by 75%.

In addition, the DMM is configured to align the first channel stream data, the second channel stream data, the third channel stream data, and the fourth channel stream data in a mutually parallel pattern, 4, 16, 64, 256 and multiplication operation with any one of the window functions according to the window length of 1024 points to generate and output 4-channel stream data reconstructed according to the length of the set window function.

In addition, the R4BM uses a 4-channel (Radix-4) MDC (Multi-path Delay Commutator) FFT processor to perform an FFT operation supporting window lengths of 4, 16, 64, 256 and 1024 points, respectively. can

In addition, the STFT operation is defined according to Equation 1 below,

[수식 1]

[Formula 1]

은

을 나타내는 것으로, 복소 평면에서 km값이 증가함에 따라 N단계에 걸쳐 시계방향으로 회전할 때의 트위터 팩터(twiddle factor)이며, 상기 x[n+m]의 신호가 윈도우 함수인 w[m]과 곱셈 연산되어 x⁽ⁿ⁾[m]의 신호로 됨으로써, 상기 STFT 연산은 x⁽ⁿ⁾[m]의 신호에 대한 FFT 연산을 수행할 수 있다.Wherein n is the starting point of an abnormal signal, represented by n=lN, where l has a range of ∞≤l≤∞, wherein k is a frequency index, m is a discrete variable, and N is the length of the window function. indicate, and

silver

is a tweeter factor when rotating clockwise over N steps as the value of km increases in the complex plane, and the signal of x[n+m] is the window function w[m] and Since the multiplication operation is performed to obtain ^{a signal of x (n)} [m], the STFT operation may perform an FFT operation on the signal of ^{x (n) [m].}

In addition, m and k in Equation 1 may be defined as in Equation 2 below using an index decomposition method.

[수식 2]

[Formula 2]

In addition, the FFT operation having a window length of 1024 points is defined as Equation 3 below by substituting Equation 2 into Equation 1,

[수식 3]

[Equation 3]

The variable A may _{have a value of A=256m 1} +64m ₂ +16m ₃ +4m ₄ +m ₅ , and the variable B may have a value of B=k ₁ +4k ₂ +16k ₃ +64k ₄ +256k ₅ have.

In addition, an FFT operation having a window length of 256 points may be defined according to Equation 4 below.

[수식 4]

[Equation 4]

Also, an FFT operation having a window length of 64 points may be defined according to Equation 5 below.

[수식 5]

[Equation 5]

In addition, an FFT operation having a window length of 16 points may be defined according to Equation 6 below.

[수식 6]

[Equation 6]

In addition, an FFT operation having a window length of 4 points may be defined according to Equation 7 below.

[수식 7]

[Equation 7]

In addition, through Equation 3, the FFT operation having a window length of 1024 points can be calculated by adding a radix-4 butterfly operation to Equation 4 above.

In addition, through Equation 4, the FFT operation having a window length of 256 points can be calculated by adding a radix-4 butterfly operation to Equation 5 above.

In addition, through Equation 5, the FFT operation having a window length of 64 points can be calculated by adding a radix-4 butterfly operation to Equation 6 above.

In addition, through Equation 6, the FFT operation having a window length of 16 points can be calculated by adding a radix-4 butterfly operation to Equation 7 above.

In addition, among the first output channel stream data, the second output channel stream data, the third output channel stream data, and the fourth output channel stream data output through the DRM, the first output channel stream data, the second output channel If the stream data, the third output channel stream data, and the fourth output channel stream data are selected in order, an overlapping FFT result of 75% may be provided.

In addition, among the first output channel stream data, second output channel stream data, third output channel stream data, and fourth output channel stream data output through the DRM, the first output channel stream data and the third output channel Choosing in order of stream data can give 50% overlapping FFT results.

In addition, among the first output channel stream data, the second output channel stream data, the third output channel stream data, and the fourth output channel stream data output through the DRM, the first output channel stream data and the fourth output channel If the stream data, the third output channel stream data, and the second output channel stream data are selected in this order, an overlapping FFT result of 25% may be provided.

In addition, if only the first output channel stream data is selected in the order of the first output channel stream data, the second output channel stream data, the third output channel stream data, and the fourth output channel stream data output through the DRM, 0 % of the superimposed FFT results.

In addition, when the first output channel stream data, the second output channel stream data, the third output channel stream data, and the fourth output channel stream data are selected in order, an overlapping FFT result of 75% is provided, When the first output channel stream data and the third output channel stream data are selected in order, an overlapping FFT result of 50% is provided, the first output channel stream data, the fourth output channel stream data, and the third output channel stream Selecting in the order of data and the second output channel stream data provides an overlapping FFT result of 25%, and selecting only the first output channel stream data in order provides an overlapping FFT result of 0%, 0%, It can provide FFT for 4 channel stream data with variable overlap size of 25%, 50% and 75%.

A low-complexity short-time Fourier transform processing method according to another embodiment of the present invention includes a Data Matching Module (DMM), a plurality of Radix-4 Butterfly Modules (R4BMs), a Data Reordering Module (DRM), and a Multiplexer (MUX). A method of processing a short-time Fourier transform using a short-time Fourier transform processing method, wherein, using the DMM, stream data of one channel is received and sequentially delayed at different rates to overlap the delayed stream data at a certain rate Data that generates 4-channel stream data aligned in parallel with each other, and multiplies the 4-channel stream data with a window function of a type according to the window length to output 4-channel stream data reconstructed according to the length of each window function matching step; an STFT operation step of outputting the STFT-calculated 4-channel stream data by performing an STFT (Short Time Fourier Transform) operation according to a preset type of window function using the R4BM on the stream data output through the DMM; and using the DRM, the STFT-calculated 4-channel stream data may be received from the R4BM, reconstructed according to an input structure of the 1-channel stream data, and output.

In addition, between the data matching step and the STFT operation step, an R4BM selection step of outputting the 4-channel stream data output through the DMM to the R4BM using the MUX so that the STFT operation according to the window length is performed is further performed. may include

In addition, the data matching step includes receiving, using the DMM, stream data of one channel, first channel stream data delayed by 75% compared to the input stream data of one channel, second channel stream data delayed by 50%, 25 % delayed third channel stream data, 0% delayed fourth channel stream data is generated between the first channel stream data and the second channel stream data, between the second channel stream data and the third channel stream data, and The third channel stream data and the fourth channel stream data may overlap each other by 75%.

In addition, the data matching step may include aligning the first channel stream data, the second channel stream data, the third channel stream data, and the fourth channel stream data in a mutually parallel pattern using the DMM. , 4, 16, 64, 256, and 1024 points may be multiplied with any one of the window functions according to the window length to generate and output 4-channel stream data reconstructed according to the length of the set window function.

In addition, the STFT operation step uses the R4BM to determine the window lengths of 4, 16, 64, 256 and 1024 points using an FFT processor of a 4-channel (Radix-4) MDC (Multi-path Delay Commutator) method. Each supported FFT operation can be performed.

In addition, the STFT operation is defined according to Equation 1 below,

[수식 1]

[Formula 1]

은

을 나타내는 것으로, 복소 평면에서 km값이 증가함에 따라 N단계에 걸쳐 시계방향으로 회전할 때의 트위터 팩터(twiddle factor)이며, 상기 x[n+m]의 신호가 윈도우 함수인 w[m]과 곱셈 연산되어 x⁽ⁿ⁾[m]의 신호로 됨으로써, 상기 STFT 연산은 x⁽ⁿ⁾[m]의 신호에 대한 FFT 연산을 수행할 수 있다.Wherein n is the starting point of an abnormal signal, represented by n=lN, where l has a range of ∞≤l≤∞, wherein k is a frequency index, m is a discrete variable, and N is the length of the window function. indicate, and

silver

is a tweeter factor when rotating clockwise over N steps as the value of km increases in the complex plane, and the signal of x[n+m] is the window function w[m] and Since the multiplication operation is performed to obtain ^{a signal of x (n)} [m], the STFT operation may perform an FFT operation on the signal of ^{x (n) [m].}

In addition, m and k in Equation 1 may be defined as in Equation 2 below using an index decomposition method.

[수식 2]

[Formula 2]

In addition, the FFT operation having a window length of 1024 points is defined as Equation 3 below by substituting Equation 2 into Equation 1,

[수식 3]

[Equation 3]

The variable A may _{have a value of A=256m 1} +64m ₂ +16m ₃ +4m ₄ +m ₅ , and the variable B may have a value of B=k ₁ +4k ₂ +16k ₃ +64k ₄ +256k ₅ have.

In addition, an FFT operation having a window length of 256 points may be defined according to Equation 4 below.

[수식 4]

[Equation 4]

Also, an FFT operation having a window length of 64 points may be defined according to Equation 5 below.

[수식 5]

[Equation 5]

In addition, an FFT operation having a window length of 16 points may be defined according to Equation 6 below.

[수식 6]

[Equation 6]

In addition, an FFT operation having a window length of 4 points may be defined according to Equation 7 below.

[수식 7]

[Equation 7]

In addition, through Equation 3, the FFT operation having a window length of 1024 points can be calculated by adding a radix-4 butterfly operation to Equation 4 above.

In addition, through Equation 4, the FFT operation having a window length of 256 points can be calculated by adding a radix-4 butterfly operation to Equation 5 above.

In addition, through Equation 5, the FFT operation having a window length of 64 points can be calculated by adding a radix-4 butterfly operation to Equation 6 above.

In addition, through Equation 6, the FFT operation having a window length of 16 points can be calculated by adding a radix-4 butterfly operation to Equation 7 above.

In addition, among the first output channel stream data, the second output channel stream data, the third output channel stream data, and the fourth output channel stream data output through the DRM, the first output channel stream data, the second output channel If the stream data, the third output channel stream data, and the fourth output channel stream data are selected in order, an overlapping FFT result of 75% may be provided.

In addition, among the first output channel stream data, second output channel stream data, third output channel stream data, and fourth output channel stream data output through the DRM, the first output channel stream data and the third output channel Choosing in order of stream data can give 50% overlapping FFT results.

In addition, among the first output channel stream data, the second output channel stream data, the third output channel stream data, and the fourth output channel stream data output through the DRM, the first output channel stream data and the fourth output channel If the stream data, the third output channel stream data, and the second output channel stream data are selected in this order, an overlapping FFT result of 25% may be provided.

In addition, if only the first output channel stream data is selected in the order of the first output channel stream data, the second output channel stream data, the third output channel stream data, and the fourth output channel stream data output through the DRM, 0 % of the superimposed FFT results.

In addition, when the first output channel stream data, the second output channel stream data, the third output channel stream data, and the fourth output channel stream data are selected in order, an overlapping FFT result of 75% is provided, When the first output channel stream data and the third output channel stream data are selected in order, an overlapping FFT result of 50% is provided, the first output channel stream data, the fourth output channel stream data, and the third output channel stream Selecting in the order of data and the second output channel stream data provides an overlapping FFT result of 25%, and selecting only the first output channel stream data in order provides an overlapping FFT result of 0%, 0%, It can provide FFT for 4 channel stream data with variable overlap size of 25%, 50% and 75%.

According to the present invention, a low-complexity short-time Fourier transform capable of providing various time and frequency resolutions by providing a length of a variable window function and supporting a variable overlap size to minimize information loss according to the type of window function A processing apparatus and a method thereof can be provided.

1 is a diagram showing the overall configuration of a short-time Fourier transform processing apparatus according to an embodiment of the present invention.
2 is a diagram illustrating a data flow of input and output of a DMM according to an embodiment of the present invention.
3 is a diagram illustrating overlap between adjacent stream data channels according to an embodiment of the present invention.
4 is a diagram illustrating an output data flow according to an FFT operation according to an embodiment of the present invention.
5 is a diagram illustrating an internal circuit configuration of a DMM according to an embodiment of the present invention.
6 is a diagram illustrating an internal circuit configuration of an R4BM according to an embodiment of the present invention.
7 is a diagram illustrating an internal circuit configuration of a DRM according to an embodiment of the present invention.
8 is a flowchart illustrating a short-time Fourier transform processing method according to an embodiment of the present invention.

Terms used in this specification will be briefly described, and the present invention will be described in detail.

The terms used in the present invention have been selected as currently widely used general terms as possible while considering the functions in the present invention, but these may vary depending on the intention or precedent of a person skilled in the art, the emergence of new technology, and the like. In addition, in a specific case, there is a term arbitrarily selected by the applicant, and in this case, the meaning will be described in detail in the description of the corresponding invention. Therefore, the term used in the present invention should be defined based on the meaning of the term and the overall content of the present invention, rather than the name of a simple term.

When a part "includes" a certain element throughout the specification, this means that other elements may be further included, rather than excluding other elements, unless otherwise stated. In addition, terms such as "...unit" and "module" described in the specification mean a unit that processes at least one function or operation, which may be implemented as hardware or software, or a combination of hardware and software. .

Hereinafter, with reference to the accompanying drawings, embodiments of the present invention will be described in detail so that those of ordinary skill in the art can easily carry out the embodiments of the present invention. However, the present invention may be embodied in many different forms and is not limited to the embodiments described herein. And in order to clearly explain the present invention in the drawings, parts irrelevant to the description are omitted, and similar reference numerals are attached to similar parts throughout the specification.

1 is a diagram showing the overall configuration of a short-time Fourier transform processing apparatus according to an embodiment of the present invention, FIG. 2 is a diagram illustrating an input and output data flow of a DMM according to an embodiment of the present invention, FIG. 3 is a diagram illustrating overlap between adjacent stream data channels according to an embodiment of the present invention, FIG. 4 is a diagram illustrating an output data flow according to an FFT operation according to an embodiment of the present invention, and FIG. 5 is a diagram illustrating the present invention is a diagram showing the internal circuit configuration of the DMM according to the embodiment of the present invention, Figure 6 is a diagram showing the internal circuit configuration of the R4BM according to the embodiment of the present invention, Figure 7 is the internal circuit configuration of the DRM according to the embodiment of the present invention is a diagram showing

Referring to FIG. 1 , a low-complexity short-time Fourier transform processing apparatus 100 according to an embodiment of the present invention includes a Data Matching Module (DMM) 110 , a Radix-4 Butterfly Module (R4BM) 120 , and Data Reordering (DRM). Module) 130 and a Multiplexer (MUX) 140 .

The DMM 110 (or DMM1) can perform an FFT operation by supporting the length of a variable window function, and the DMM2 112 and DMM3 113 installed between the R4BM 130 in addition to the DMM 110 . , DMM4 114 , and DMM5 115 may also be configured. These DMM2 (112), DMM3 (113), DMM4 (114), and DMM5 (115) serve to reconstruct the input of the 4-channel stream data into an input data structure required for the R4BM 130 of the next stage, and a delay element and a commutator. These DMM2 112 , DMM3 113 , DMM4 114 , and DMM5 115 are configured similarly to each other, but the length of the shift register is different because the input data structure required for the next R4BM 130 is different. there may be

In particular, the DMM 110 receives stream data of one channel and sequentially delays it at different rates to generate stream data of four channels that are overlapped at a certain rate between the delayed stream data and arranged in parallel with each other, By multiplying stream data with a window function of a type according to the window length, it is possible to output 4-channel stream data reconstructed according to the length of each window function.

As shown in FIG. 2 , the DMM 110 receives the stream data of one channel (Input), and the first channel stream data (Output1), which is delayed by 75% compared to the input stream data of one channel (Input1), 50 The % delayed second channel stream data (Output2), the 25% delayed third channel stream data (Output3), and the 0% delayed fourth channel stream data (Output4) are generated to generate the output first channel as shown in FIG. 3 . Between the stream data (Channel1) and the second channel stream data (Channel2), between the second channel stream data (Channel2) and the third channel stream data (Channel3), and between the third channel stream data (Channel3) and the fourth channel stream data (Channel4) The livers can each overlap 75%.

In this embodiment, in order to implement an STFT processor with variable 0, 25, 50 and 75% overlap size, it is necessary to put an input with 75% overlap to each channel of the 4-channel FFT processor, and partially select the output channel of the FFT processor. Thus, the nesting size can be varied. As stream data enters the STFT processor through one channel, it can receive one stream data and create four stream data overlapping 75%, and when the window length is N-point, The flow is as shown in FIG. 1 . At this time, the 1-channel output stream data of the DMM is output with the input stream data delayed by 3N/4 cycles, the 2-channel output stream data is output with the input stream data delayed by N/2 cycles, and the 3-channel output stream data is output with the input stream data is output with N/4 cycle delay, and finally, 4 channel output stream data is output without input stream data delayed. FFT operation starts after the first data of 1 channel is delayed by 3N/4 cycle are each overlapped by 75%. That is, stream data superimposed 75% on each channel of the FFT processor enters the input. Stream data entered as input with 75% overlap in each channel of the FFT processor goes through the operation of the 4-channel FFT processor, and the output result is also overlapped by 75% in each channel. When the window function length is N-points, the output stream The data flow is as shown in FIG. 4 .

The operating principle of this DMM 110 is that the stream data of the first 1 channel is converted to 4 stream data overlapped by 75% through the DMM 110 and reconstructed to an exact length suitable for the length of the set window function at the same time, The input signal is multiplied by the window function according to the length of the window function and input to the next stage. For example, when 1024-point STFT operation is to be performed, reconstructed 4-channel stream data is input to R4BM1 121 by MUX1 141 to perform 1024-point STFT operation. When the 256-point STFT operation is to be performed, the input stream data reconstructed for the 256-point STFT through the DMM 110 is input to the R4BM2 122 by the MUX2 142 to perform the 256-point STFT operation. When the 64-point STFT operation is to be performed, input stream data reconstructed for 64-point STFT through the DMM 110 is input to the R4BM3 123 by the MUX3 143 to perform the 64-point STFT operation. When the 16-point STFT operation is to be performed, the input stream data reconstructed for the 16-point STFT through the DMM 110 is input to the R4BM4 124 by the MUX4 144 to perform the 16-point STFT operation. When 4-point STFT operation is to be performed, input stream data reconstructed for 4-point STFT is inputted to R4BM5 (125) by MUX4 (145) through DMM 110, and 4-point STFT operation is performed. .

The structure of the STFT processor according to the present embodiment can reduce the hardware cost by reducing the number of complex multipliers by applying a radix-4 based 4-channel multi-path delay commutator (MDC) structure, and the implementation is simplified. In addition, the STFT processor according to the variable window function length proposes a hardware structure capable of reducing hardware complexity by sharing a commonly used operation block through an equation of an operation process performed for each point operation. In addition, the hardware efficiency is improved through operation using a plurality of input stream data instead of using a plurality of hardware resources, and the number of delay elements used in the DMM 110 is reduced to the delay used in the DMM 110 of the existing MDC structure. By reducing the number of elements by 2304, the area of the hardware was reduced.

The DMM 110 includes a first channel stream data (Channel1 or Output1), a second channel stream data (Channel2 or Output2), a third channel stream data (Channel3 or Output3), and a fourth channel stream data (Channel4 or Output4) A stream of 4 channels reconstructed according to the length of the window function set by multiplying with any one of the window functions according to the window length of 4, 16, 64, 256, and 1024 points in a state in which . Data (Output 1, 2, 3, 4) can be generated and output.

More specifically, the DMM 110 configures four streams of one channel data in parallel in a constant data alignment pattern using a delay element, multiplies the window function, and then pushes it to the next stage. The existing MDC-type FFT processor hardware structure has a problem in that the hardware area due to the delay element increases as the number of FFT points and data paths increases. In the existing structure, the area of the delay element of the DMM1 part that reconstructs data according to the R4BM and the DRM part that reconstructs and outputs the data according to the initial input structure has the largest area. In the case of 1024-point FFT of the existing radix-4 MDC structure, it receives 4 channels of input from DMM1 and reconstructs it into a pattern required for the next R4BM1 using 3072 delay elements, but the structure of the DMM 110 according to this embodiment In this case, it is possible to reduce the hardware area by receiving an input of one channel and reconfiguring it into a pattern required for the next R4BM1 (121) using 768 delay elements. In addition, since the DMM 110 according to the present embodiment must support a variable length of 4/16/64/256/1024-point, the data according to 4/16/64/256/1024-point using the MUX 140 is used. The alignment pattern may be determined, and the hardware structure of the DMM 110 among the DMM 110 is as shown in FIG. 5 .

The Radix-4 Butterfly Module (R4BM) 120 performs STFT (Short Time Fourier Transform) operation on the stream data output through the DMM 110 according to a preset type of window function to perform the STFT operation of the 4-channel stream data can be output.

More specifically, the R4BM 120 uses a 4-channel (Radix-4) MDC (Multi-path Delay Commutator) type FFT processor to support window lengths of 4, 16, 64, 256 and 1024 points, respectively. operation can be performed.

The window function plays an important role in preventing spectral loss, so it is important to be able to choose a window function that suits the situation. The FFT-based STFT processor according to the present embodiment satisfies these requirements. The N-point STFT operation is defined according to Equation 1 below,

[Formula 1]

은

을 나타내는 것으로, 복소 평면에서 km값이 증가함에 따라 N단계에 걸쳐 시계방향으로 회전할 때의 트위터 팩터(twiddle factor)이다. 수식 1에서 x[n+m]의 신호가 윈도우 함수인 w[m]과 곱셈 연산되어 x⁽ⁿ⁾[m]의 신호로 됨으로써, STFT 연산은 x⁽ⁿ⁾[m]의 신호에 대한 FFT 연산을 수행할 수 있다. 이와 같이 적절한 윈도우 함수 w[m]을 통해 신호 x[n]을 이동시키고 윈도우 함수 내의 샘플(포인트)들을 FFT 연산을 수행함으로써 시간에 따른 주파수를 측정할 수 있다.In Equation 1, n is the starting point of the abnormal signal, expressed as n=lN, l has a range of ∞≤l≤∞, k is a frequency index, m is a discrete variable, N represents the length of the window function, remind

silver

is a tweeter factor when rotating clockwise over N steps as the value of km increases in the complex plane. Whereby in the formula 1 into a signal of x [n + m] signal is calculated in w [m] window functions and the multiplication of ^{x (n) [m],} STFT operation FFT on the signals x ⁽ⁿ⁾ [m] operation can be performed. In this way, the frequency according to time can be measured by moving the signal x[n] through an appropriate window function w[m] and performing an FFT operation on the samples (points) in the window function.

For FFT algorithms used in STFT processors, radix-2 and radix-4 algorithms are commonly used. In the case of a pipeline structure, radix-4 can obtain a benefit in terms of yield compared to radix-2, but has a more complex structure in terms of hardware. That is, the larger k in radix-k, the less complex multiplication and the more complicated the hardware structure.

FFT hardware structures that can be considered for designing an STFT processor include a method using a single butterfly structure, a method using a pipeline structure, a method using a parallel structure, and the like. Although the parallel structure has the greatest advantage in terms of yield, it has the disadvantage that the hardware complexity becomes too large, and the single butterfly operator structure has the smallest hardware complexity but has a low yield. STFT processors used in a variety of systems require low complexity along with high yield characteristics.

Therefore, a pipeline method that best satisfies the trade-off between yield and complexity is suitable as a method for implementing the FFT processor used in the STFT processor.

A pipeline method for implementing the FFT processor used in the STFT processor is largely divided into a single-path delay feedback (SDF) and an MDC-type FFT processor. The SDF-type FFT processor transfers data through a single path and sorts the data through the modified butterfly operator. Since one complex multiplier is required per path, the complexity is reduced, but the yield is low due to the feature of a single path, and the structure of the butterfly operator is complicated, so it is difficult to control. The MDC-type FFT processor delivers data through multiple paths, and arranges data corresponding to the signal flow graph (SFG) with a delay switch. Due to these characteristics, it has an advantage of having a large yield and easy control, but it has a disadvantage of increasing complexity because it requires one complex multiplier per path.

Accordingly, in this embodiment, since a 4-channel STFT processor is implemented, when an SDF-type FFT processor is used, four FFT modules are required according to the number of paths, and the number of complex multiplications is increased accordingly, thereby increasing hardware complexity and area.

However, in the case of a 4-channel STFT processor, the radix-4 MDC FFT processor can be designed as a single processor, so it can process four data paths without significantly increasing hardware complexity and area, and can increase the yield. Therefore, the FFT processor of the 4-channel MDC method is effective for implementing the STFT processor.

In order to design a 4-channel STFT processor as a single processor, the radix-4 algorithm is used in this embodiment as described above. The FFT operation supporting the variable length of the window function can be performed using the Radix-4 algorithm, and complex multiplication that occurs at this time can be reduced. m and k in Equation 1 can be defined as in Equation 2 below using the index decomposition method.

[Formula 2]

The FFT operation having a window length of 1024 points is defined as in Equation 3 below by substituting Equation 2 into Equation 1,

[Equation 3]

In Equation 3, variable A has a value of A=256m ₁ +64m ₂ +16m ₃ +4m ₄ +m ₅ , and variable B has a value of B=k ₁ +4k ₂ +16k ₃ +64k ₄ +256k ₅ . can

In addition, an FFT operation having a window length of 256 points may be defined according to Equation 4 below.

[Equation 4]

Also, an FFT operation having a window length of 64 points may be defined according to Equation 5 below.

[Equation 5]

In addition, an FFT operation having a window length of 16 points may be defined according to Equation 6 below.

[Equation 6]

In addition, an FFT operation having a window length of 4 points may be defined according to Equation 7 below.

[Equation 7]

As described above, through Equation 3, the FFT operation having a window length of 1024 points is calculated by adding a radix-4 butterfly operation to Equation 4, and the FFT operation having a window length of 256 points through Equation 4 is radix in Equation 5 A -4 butterfly operation is added and calculated, and an FFT operation with a window length of 64 points through Equation 5 is calculated by adding a radix-4 butterfly operation to Equation 6, and an FFT operation with a window length of 16 points through Equation 6 The operation is calculated by adding a radix-4 butterfly operation to Equation 7, which means that FFT operations of various window function lengths (or sizes) can be supported (or performed) using one FFT processor.

The detailed structure of the R4BM 120 according to the present embodiment is as shown in FIG. 6, and consists of one radix-4 butterfly operator, three multipliers, and round & clip. The output of the 4 channels of the DMM 110 is input to the 4 channels of the R4BM 120 according to the 4/16/64/256/1024-point (window function length) setting, and the stream data of the 4 channels is one After performing the radix-4 butterfly operator, it passes through three multipliers and is output through round & clip.

The DRM (Data Reordering Module) 130 may receive the STFT-calculated stream data of 4 channels from the R4BM5 125 and reconstruct and output the stream data of one channel according to the input structure.

The DRM 130 may reconstruct and output the stream data of 4 channels on which the FFT operation is performed according to the initial input structure. The existing MDC-type FFT processor hardware structure has a problem in that it takes up a lot of area, so as shown in FIG. 7, a pre-commutator, a post-commutator, and four dual port RAMs are used instead of the delay element and commutator of the existing DMM. It is implemented in a reduced structure. Pre-commutator plays the role of reconfiguring the input data of 4 channels to fit the dual-port RAM. At this time, since a variable length of 4/16/64/256/1024-points must be supported, a data alignment pattern is determined according to each 4/16/64/256/1024-point FFT using the MUX 140 . The output of the dual port RAM is reconfigured according to the post-commutator structure, and the post-commutator is reconfigured according to the MDC structure using the MUX 140 like the pre-commutator.

The MUX (Multiplexer) 140 receives the stream data of 4 channels output through the DMM 110, and a window having 4/16/64/256/1024-points so that an STFT operation is performed according to the window length. Depending on the length setting of the function, one of R4BM1, 2, 3, 4, 5 (121, 122, 123, 124, 125) can be output. For example, when an operation for a window function having 1024-points is to be performed, 4-channel stream data is input to R4BM1, and then DMM2(112), R4BM2(122), DMM3(113), R4BM3(123) , DMM4 (114), R4BM4 (124), DMM5 (115), R4BM5 (125) can be input to the DRM 130 through the FFT operation and data alignment processing in the order.

Meanwhile, in the short-time Fourier transform apparatus 100 according to the present embodiment, the first output channel stream data, the second output channel stream data, the third output channel stream data, and the fourth output channel stream data output through the DRM 110 . Among them, if the first output channel stream data, the second output channel stream data, the third output channel stream data, and the fourth output channel stream data are selected in the order, an overlapping FFT result of 75% is provided, and the first output channel stream data is selected. and a third output channel stream data order provides an overlapping FFT result of 50%, and a first output channel stream data, a fourth output channel stream data, a third output channel stream data, and a second output channel stream data in the order Select to give 25% superimposed FFT result, and select only in first output channel stream data order to give 0% superimposed FFT result, variable overlap of 0%, 25%, 50% and 75% It is possible to provide an FFT for the size of 4-channel stream data.

As described above, N stream data of 1 channel and N stream data of 2 channels, N stream data of 2 channels and N stream data of 3 channels, N stream data of 3 channels and N streams of 4 channels Stream data, N stream data of 4 channels and N stream data of 1 channel of the next FFT operation result represent the output result of FFT operation overlapped by 75%, N stream data of 1 channel and N stream data of 3 channels Stream data and N stream data of 3 channels and N stream data of 1 channel of the next FFT operation result represent 50% overlapping FFT operation results. And N stream data of 1 channel and N stream data of 4 channels, N stream data of 3 channels of the next FFT operation result of N stream data of 4 channels, N stream data of 3 channels and the next FFT operation result N stream data of 2 channels, N stream data of 2 channels, and N stream data of 1 channel of the following FFT operation result indicate 25% overlapping FFT operation results. Indicates the operation result.

Therefore, if you select the output channels of the FFT processor in the order of 1, 2, 3, 4, channels, you can get a 75% overlapping FFT result. have. And if you select 1 channel, 4 channels, 3 channels, 2 channels in order, you can get 25% overlapping FFT results, and if you select only 1 channel, you can get 0% overlapping FFT results.

8 is a flowchart illustrating a short-time Fourier transform processing method according to an embodiment of the present invention.

Referring to FIG. 8 , the short-time Fourier transform processing method S110 according to an embodiment of the present invention is a short-time Fourier transform processing apparatus including a DMM 110 , an R4BM 120 , a DRM 130 and a MUX 140 . (100) relates to a method of processing a short-time Fourier transform using a data matching step (S110), an R4BM selection step (S120), an STFT operation step (S130), a data rearrangement step (S140), and a data variable overlap size and a selection step (S150).

In the data matching step (S110), by using the DMM (Data Matching Module) 110, one channel of stream data is received and sequentially delayed at different rates so that the delayed stream data is overlapped at a certain rate and mutually parallel. It is possible to generate sorted 4-channel stream data, multiply the 4-channel stream data with a window function of a type according to the window length, and output 4-channel stream data reconstructed according to the length of each window function.

Here, the DMM 110 supports the length of a variable window function to perform an FFT operation, and thus, five DMMs, namely DMM 110 , DMM2 112 , DMM3 113 , and DMM4 114 . , and DMM5 115 .

In particular, the DMM 110 receives, as shown in FIG. 2, stream data of one channel (Input), the first channel stream data (Output1) delayed by 75% compared to the input stream data of one channel (Input1), As shown in FIG. 3 , the first outputted first channel stream data (Output2) delayed by 50%, third channel stream data delayed by 25% (Output3), and fourth channel stream data delayed by 0% (Output4) are generated as shown in FIG. 3 . Between the channel stream data (Channel1) and the second channel stream data (Channel2), between the second channel stream data (Channel2) and the third channel stream data (Channel3), and between the third channel stream data (Channel3) and the fourth channel stream The data Channel4 may overlap each other by 75%.

In this embodiment, in order to implement an STFT processor with variable 0, 25, 50 and 75% overlap size, it is necessary to put an input with 75% overlap to each channel of the 4-channel FFT processor, and partially select the output channel of the FFT processor. Thus, the nesting size can be varied. As stream data enters the STFT processor through one channel, it can receive one stream data and create four stream data overlapping 75%, and when the window length is N-point, The flow is as shown in FIG. 1 . At this time, the 1-channel output stream data of the DMM is output with the input stream data delayed by 3N/4 cycles, the 2-channel output stream data is output with the input stream data delayed by N/2 cycles, and the 3-channel output stream data is output with the input stream data is output with N/4 cycle delay, and finally, 4 channel output stream data is output without input stream data delayed. FFT operation starts after the first data of 1 channel is delayed by 3N/4 cycle are each overlapped by 75%. That is, stream data superimposed 75% on each channel of the FFT processor enters the input. Stream data entered as input with 75% overlap in each channel of the FFT processor goes through the operation of the 4-channel FFT processor, and the output result is also overlapped by 75% in each channel. When the window function length is N-points, the output stream The data flow is as shown in FIG. 4 .

The operating principle of this DMM 110 is that the stream data of the first 1 channel is converted to 4 stream data overlapped by 75% through the DMM 110 and reconstructed to an exact length suitable for the length of the set window function at the same time, The input signal is multiplied by the window function according to the length of the window function and input to the next stage. For example, when 1024-point STFT operation is to be performed, reconstructed 4-channel stream data is input to R4BM1 121 by MUX1 141 to perform 1024-point STFT operation. When the 256-point STFT operation is to be performed, the input stream data reconstructed for the 256-point STFT through the DMM 110 is input to the R4BM2 122 by the MUX2 142 to perform the 256-point STFT operation. When the 64-point STFT operation is to be performed, input stream data reconstructed for 64-point STFT through the DMM 110 is input to the R4BM3 123 by the MUX3 143 to perform the 64-point STFT operation. When the 16-point STFT operation is to be performed, the input stream data reconstructed for the 16-point STFT through the DMM 110 is input to the R4BM4 124 by the MUX4 144 to perform the 16-point STFT operation. When 4-point STFT operation is to be performed, input stream data reconstructed for 4-point STFT is inputted to R4BM5 (125) by MUX4 (145) through DMM 110, and 4-point STFT operation is performed. .

The structure of the STFT processor according to the present embodiment can reduce the hardware cost by reducing the number of complex multipliers by applying a radix-4 based 4-channel multi-path delay commutator (MDC) structure, and the implementation is simplified. In addition, the STFT processor according to the variable window function length proposes a hardware structure capable of reducing hardware complexity by sharing a commonly used operation block through an equation of an operation process performed for each point operation. In addition, the hardware efficiency is improved through operation using a plurality of input stream data instead of using a plurality of hardware resources, and the number of delay elements used in the DMM 110 is reduced to the delay used in the DMM 110 of the existing MDC structure. By reducing the number of elements by 2304, the area of the hardware was reduced.

The DMM 110 includes a first channel stream data (Channel1 or Output1), a second channel stream data (Channel2 or Output2), a third channel stream data (Channel3 or Output3), and a fourth channel stream data (Channel4 or Output4) A stream of 4 channels reconstructed according to the length of the window function set by multiplying with any one of the window functions according to the window length of 4, 16, 64, 256, and 1024 points in a state in which . Data (Output 1, 2, 3, 4) can be generated and output.

More specifically, the DMM 110 configures four streams of one channel data in parallel in a constant data alignment pattern using a delay element, multiplies the window function, and then pushes it to the next stage. The existing MDC-type FFT processor hardware structure has a problem in that the hardware area due to the delay element increases as the number of FFT points and data paths increases. In the existing structure, the area of the delay element of the DMM1 part that reconstructs data according to the R4BM and the DRM part that reconstructs and outputs the data according to the initial input structure has the largest area. In the case of 1024-point FFT of the existing radix-4 MDC structure, it receives 4 channels of input from DMM1 and reconstructs it into a pattern required for the next R4BM1 using 3072 delay elements, but the structure of the DMM 110 according to this embodiment In this case, it is possible to reduce the hardware area by receiving an input of one channel and reconstructing it into a pattern required for the next R4BM 120 using 768 delay elements. In addition, since the DMM 110 according to the present embodiment must support a variable length of 4/16/64/256/1024-point, the data according to 4/16/64/256/1024-point using the MUX 140 is used. The alignment pattern may be determined, and the hardware structure of the DMM 120 is as shown in FIG. 5 .

In the R4BM selection step (S120), 4/16/64/ 4/16/64/ stream data output through the DMM 110 is received through the MUX (Multiplexer) 140, and STFT operation is performed according to the window length. Depending on the length setting of the window function with 256/1024-points, it can be output in any one of R4BM1, 2, 3, 4, 5 (121, 122, 123, 124, 125).

In the STFT operation step (S130), a Short Time Fourier Transform (STFT) operation according to a window function of a preset type is performed on the stream data output through the DMM 110 using a Radix-4 Butterfly Module (R4BM) 120 . By performing the STFT operation, 4-channel stream data can be output.

More specifically, in the R4BM selection step (S120), a window length of 4, 16, 64, 256, and 1024 points is supported using a 4-channel (Radix-4) multi-path delay commutator (MDC) type FFT processor, respectively. FFT operation can be performed.

The window function plays an important role in preventing spectral loss, so it is important to be able to choose a window function that suits the situation. The FFT-based STFT processor according to the present embodiment satisfies these requirements. The N-point STFT operation is defined according to Equation 1 below,

[Formula 1]

은

을 나타내는 것으로, 복소 평면에서 km값이 증가함에 따라 N단계에 걸쳐 시계방향으로 회전할 때의 트위터 팩터(twiddle factor)이다. 수식 1에서 x[n+m]의 신호가 윈도우 함수인 w[m]과 곱셈 연산되어 x⁽ⁿ⁾[m]의 신호로 됨으로써, STFT 연산은 x⁽ⁿ⁾[m]의 신호에 대한 FFT 연산을 수행할 수 있다. 이와 같이 적절한 윈도우 함수 w[m]을 통해 신호 x[n]을 이동시키고 윈도우 함수 내의 샘플(포인트)들을 FFT 연산을 수행함으로써 시간에 따른 주파수를 측정할 수 있다.In Equation 1, n is the starting point of the abnormal signal, expressed as n=lN, l has a range of ∞≤l≤∞, k is a frequency index, m is a discrete variable, N represents the length of the window function, remind

silver

is a tweeter factor when rotating clockwise over N steps as the value of km increases in the complex plane. Whereby in the formula 1 into a signal of x [n + m] signal is calculated in w [m] window functions and the multiplication of ^{x (n) [m],} STFT operation FFT on the signals x ⁽ⁿ⁾ [m] operation can be performed. In this way, the frequency according to time can be measured by moving the signal x[n] through an appropriate window function w[m] and performing an FFT operation on the samples (points) in the window function.

For FFT algorithms used in STFT processors, radix-2 and radix-4 algorithms are commonly used. In the case of a pipeline structure, radix-4 can obtain a benefit in terms of yield compared to radix-2, but has a more complex structure in terms of hardware. That is, the larger k in radix-k, the less complex multiplication and the more complicated the hardware structure.

FFT hardware structures that can be considered for designing an STFT processor include a method using a single butterfly structure, a method using a pipeline structure, a method using a parallel structure, and the like. Although the parallel structure has the greatest advantage in terms of yield, it has the disadvantage that the hardware complexity becomes too large, and the single butterfly operator structure has the smallest hardware complexity but has a low yield. STFT processors used in a variety of systems require low complexity along with high yield characteristics.

Therefore, a pipeline method that best satisfies the trade-off between yield and complexity is suitable as a method for implementing the FFT processor used in the STFT processor.

A pipeline method for implementing the FFT processor used in the STFT processor is largely divided into a single-path delay feedback (SDF) and an MDC-type FFT processor. The SDF-type FFT processor transfers data through a single path and sorts the data through the modified butterfly operator. Since one complex multiplier is required per path, the complexity is reduced, but the yield is low due to the feature of a single path, and the structure of the butterfly operator is complicated, so it is difficult to control. The MDC-type FFT processor delivers data through multiple paths, and arranges data corresponding to the signal flow graph (SFG) with a delay switch. Due to these characteristics, it has an advantage of having a large yield and easy control, but it has a disadvantage of increasing complexity because it requires one complex multiplier per path.

Accordingly, in this embodiment, since a 4-channel STFT processor is implemented, when an SDF-type FFT processor is used, four FFT modules are required according to the number of paths, and the number of complex multiplications is increased accordingly, thereby increasing hardware complexity and area.

However, in the case of a 4-channel STFT processor, the radix-4 MDC FFT processor can be designed as a single processor, so it can process four data paths without significantly increasing hardware complexity and area, and can increase the yield. Therefore, the FFT processor of the 4-channel MDC method is effective for implementing the STFT processor.

In order to design a 4-channel STFT processor as a single processor, the radix-4 algorithm is used in this embodiment as described above. The FFT operation supporting the variable length of the window function can be performed using the Radix-4 algorithm, and complex multiplication that occurs at this time can be reduced. m and k in Equation 1 can be defined as in Equation 2 below using the index decomposition method.

[Formula 2]

The FFT operation having a window length of 1024 points is defined as in Equation 3 below by substituting Equation 2 into Equation 1,

[Equation 3]

In Equation 3, variable A has a value of A=256m ₁ +64m ₂ +16m ₃ +4m ₄ +m ₅ , and variable B has a value of B=k ₁ +4k ₂ +16k ₃ +64k ₄ +256k ₅ . can

In addition, an FFT operation having a window length of 256 points may be defined according to Equation 4 below.

[Equation 4]

Also, an FFT operation having a window length of 64 points may be defined according to Equation 5 below.

[Equation 5]

In addition, an FFT operation having a window length of 16 points may be defined according to Equation 6 below.

[Equation 6]

In addition, an FFT operation having a window length of 4 points may be defined according to Equation 7 below.

[Equation 7]

As described above, through Equation 3, the FFT operation having a window length of 1024 points is calculated by adding a radix-4 butterfly operation to Equation 4, and the FFT operation having a window length of 256 points through Equation 4 is radix in Equation 5 A -4 butterfly operation is added and calculated, and an FFT operation with a window length of 64 points through Equation 5 is calculated by adding a radix-4 butterfly operation to Equation 6, and an FFT operation with a window length of 16 points through Equation 6 The operation is calculated by adding a radix-4 butterfly operation to Equation 7, which means that FFT operations of various window function lengths (or sizes) can be supported (or performed) using one FFT processor.

The detailed structure of the R4BM 120 according to the present embodiment is as shown in FIG. 6, and consists of one radix-4 butterfly operator, three multipliers, and round & clip. The output of the 4 channels of the DMM 110 is input to the 4 channels of the R4BM 120 according to the 4/16/64/256/1024-point (window function length) setting, and the stream data of the 4 channels is one After performing the radix-4 butterfly operator, it passes through three multipliers and is output through round & clip.

In the data rearrangement step (S140), using the DRM (Data Reordering Module) 130, the STFT-calculated stream data of 4 channels from the R4BM5 (125) disposed at the last stage among the plurality of R4BMs (120) is input. It can be reconstructed and output according to the input structure of the stream data of one channel.

The DRM 130 may reconstruct and output the stream data of 4 channels on which the FFT operation is performed according to the initial input structure. The existing MDC-type FFT processor hardware structure has a problem in that it takes up a lot of area, so as shown in FIG. 7, a pre-commutator, a post-commutator, and four dual port RAMs are used instead of the delay element and commutator of the existing DMM. It is implemented in a reduced structure. Pre-commutator plays the role of reconfiguring the input data of 4 channels to fit the dual-port RAM. At this time, since a variable length of 4/16/64/256/1024-points must be supported, a data alignment pattern is determined according to each 4/16/64/256/1024-point FFT using the MUX 140 . The output of the dual port RAM is reconfigured according to the post-commutator structure, and the post-commutator is reconfigured according to the MDC structure using the MUX 140 like the pre-commutator.

The MUX (Multiplexer) 140 receives the stream data of 4 channels output through the DMM 110, and a window having 4/16/64/256/1024-points so that an STFT operation is performed according to the window length. Depending on the length setting of the function, one of R4BM1, 2, 3, 4, 5 (121, 122, 123, 124, 125) can be output.

In the data variable overlap size selection step (S150), among the first output channel stream data, the second output channel stream data, the third output channel stream data, and the fourth output channel stream data output through the DRM 110, Selecting 1st output channel stream data, 2nd output channel stream data, 3rd output channel stream data, and 4th output channel stream data in this order provides an overlapping FFT result of 75%, first output channel stream data and third output channel stream data Selecting in the order of output channel stream data provides a 50% superimposed FFT result, selecting in the order of first output channel stream data, fourth output channel stream data, third output channel stream data, and second output channel stream data It provides 25% overlapped FFT results, and selection of only the first output channel stream data in order gives 0% overlapped FFT results, 4 with variable overlap sizes of 0%, 25%, 50% and 75%. An FFT for channel stream data may be provided.

As described above, N stream data of 1 channel and N stream data of 2 channels, N stream data of 2 channels and N stream data of 3 channels, N stream data of 3 channels and N streams of 4 channels Stream data, N stream data of 4 channels and N stream data of 1 channel of the next FFT operation result represent the output result of FFT operation overlapped by 75%, N stream data of 1 channel and N stream data of 3 channels Stream data and N stream data of 3 channels and N stream data of 1 channel of the next FFT operation result represent 50% overlapping FFT operation results. And N stream data of 1 channel and N stream data of 4 channels, N stream data of 3 channels of the next FFT operation result of N stream data of 4 channels, N stream data of 3 channels and the next FFT operation result N stream data of 2 channels, N stream data of 2 channels, and N stream data of 1 channel of the following FFT operation result indicate 25% overlapping FFT operation results. Indicates the operation result.

Therefore, if you select the output channels of the FFT processor in the order of 1, 2, 3, 4, channels, you can get a 75% overlapping FFT result. have. And if you select 1 channel, 4 channels, 3 channels, 2 channels in order, you can get 25% overlapping FFT results, and if you select only 1 channel, you can get 0% overlapping FFT results.

Table 1 below compares the number of hardware operators of the conventional FFT and the proposed radix-4 MDC FFT structure required to implement a 4-channel STFT processor in which the window function length and overlap size are variable.

[Table 1]

Table 1 above shows 4 channels, so k=4 and N=4 ^q , and the area of hardware is compared by comparing the complex multiplier, the complex adder, and the delay element. Compared with the existing radix-4 MDC structure, the proposed radix-4 MDC structure has the same number of complex multipliers and complex adders, but the number of delay elements is smaller than the proposed radix-4 MDC structure.

In addition, when the proposed radix-4 MDC structure and the conventional SDF structure are compared, the complex multiplier, complex adder, and delay element are all used less. That is, by using the FFT of the proposed MDC structure, the FFT operation of various points is supported, and it is efficient in terms of complexity by minimizing the number of complex multipliers and complex adders, and it is the most efficient in terms of hardware area by minimizing the number of delay elements. am.

In addition, in order to verify that the proposed STFT processor is efficient in terms of hardware complexity and area, a four-channel STFT processor with variable window function length and overlap size was developed with the raidx-4 SDF, radix-4 MDC structure and the proposed radix-4 Implemented and compared with the MDC structure. The real part and the imaginary part of the input data were set to 12 bits each so that the signal to quantization noise ratio (SQNR) could be 40 dB or more.

The three STFT processors are designed in Verilog-HDL and synthesized as gate-level circuits using a 65nm CMOS standard cell library. Table 2 below is arranged so that the number of logic gates can be compared. The STFT processor of the proposed radix-4 MDC structure can reduce the number of gates by 47% compared to the processor of the existing radix-4 MDC STFT structure, and reduce the number of gates by 56% compared to the STFT processor of the Radix-4 SDF structure. did it From this result, it can be seen that the proposed radix-4 MDC FFT structure for implementing a 4-channel STFT processor with variable window function length and overlapping size is the most efficient.

[Table 2]

In this embodiment, 4/16/64/256/1024-points are supported to provide various time-frequency resolutions, and 0, 25, 50 and 75 to minimize information loss according to the type of window function. A 4-channel STFT processor supporting % variable overlap size was implemented and verified in hardware.

Using the radix-4 MDC FFT structure according to this embodiment, a plurality of input data was processed by one FFT processor, and the number of delay elements, which occupies the largest portion in terms of area, was greatly reduced through the proposed DMM structure.

In addition, in order to compare the complexity of the STFT processor according to the present embodiment, an STFT processor having a radix-4 SDF structure, a radix-4 MDC structure, and a proposed radix-4 MDC structure is implemented.

As a result, the STFT processor according to this embodiment can reduce the number of gates by 56% compared to the STFT processor of the radix-4 SDF structure, and is implemented with the gates reduced by 47% compared to the STFT processor of the radix-4 MDC structure. By confirming that this is possible, the proposed radix-4 MDC structure is the most efficient in the implementation of the STFT processor that observes the frequency change according to the time change.

What has been described above is only one embodiment for implementing the low-complexity short-time Fourier transform processing apparatus and method according to the present invention, and the present invention is not limited to the above embodiment, and is claimed in the following claims. As described above, without departing from the gist of the present invention, it will be said that the technical spirit of the present invention exists to the extent that various modifications can be made by anyone with ordinary knowledge in the field to which the present invention belongs.

100: short-time Fourier transform processing unit
110: Data Matching Module (DMM) (or DMM1)
112: DMM2
113: DMM3
114: DMM4
115: DMM5
120: R4BM (Radix-4 Butterfly Module)
121: R4BM1
122: R4BM2
123: R4BM3
124: R4BM4
125: R4BM5
130: DRM (Data Reordering Module)
140: MUX (Multiplexer)
141: MUX1
142: MUX2
143: MUX3
144: MUX4
145: MUX5
S100: Short-time Fourier transform processing method
S110: data matching step
S120: R4BM selection step
S130: STFT operation step
S140: data rearrangement step
S150: data variable nesting size selection step

Claims (42)

Receives one-channel stream data and sequentially delays them at different rates to generate stream data of 4 channels that are overlapped at a certain rate between delayed stream data and arranged in parallel with each other, and the stream data of 4 channels according to the window length DMM (Data Matching Module) for outputting 4-channel stream data reconstructed according to the length of each window function by performing a multiplication operation with a type of window function;
a plurality of Radix-4 Butterfly Modules (R4BMs) that perform a Short Time Fourier Transform (STFT) operation on the stream data output through the DMM according to a preset type of window function to output STFT-calculated 4-channel stream data; and
and a DRM (Data Reordering Module) that receives the STFT-calculated stream data of 4 channels from the R4BM and reconstructs and outputs the stream data according to the input structure of the 1 channel stream data,
The DMM is
Receives one-channel stream data, 75% delayed first channel stream data, 50% delayed second channel stream data, 25% delayed third channel stream data, 0% delayed fourth channel compared to input one-channel stream data Stream data is generated between the first channel stream data and the second channel stream data, between the second channel stream data and the third channel stream data, and between the third channel stream data and the fourth channel stream data. A low-complexity short-time Fourier transform processing apparatus, characterized in that each overlaps by 75%.
According to claim 1,
The apparatus for processing a short-time Fourier transform of low complexity, characterized in that it further comprises a multiplexer (MUX) for outputting the stream data of 4 channels output through the DMM to the R4BM to perform an STFT operation according to a window length.
delete According to claim 1,
The DMM is
In a state in which the first channel stream data, the second channel stream data, the third channel stream data, and the fourth channel stream data are arranged in a mutually parallel pattern, a window length of 4, 16, 64, 256 and 1024 points A low-complexity short-time Fourier transform processing apparatus for generating and outputting stream data of 4 channels reconstructed according to the length of the set window function by performing a multiplication operation with any one of the window functions according to .
5. The method of claim 4,
The R4BM is,
Low complexity characterized by performing FFT operation supporting window lengths of 4, 16, 64, 256 and 1024 points, respectively, using a 4-channel (Radix-4) MDC (Multi-path Delay Commutator) FFT processor short-time Fourier transform processing unit.
6. The method of claim 5,
The STFT operation is defined according to Equation 1 below,
[Formula 1]

Where n is the starting point of the abnormal signal, represented by n = 1N,
wherein l has the range of -∞≤l≤∞,
where k is a frequency index,
wherein m is a discrete variable,
Wherein N represents the length of the window function,
remind

silver

is the tweeter factor when rotating clockwise over N steps as the value of km increases in the complex plane,
The signal of x[n+m] is multiplied with w[m], which is a window function, to become a signal of x ⁽ⁿ⁾ [m], so that the STFT operation is an FFT operation on the signal of ^x(n)[m]. A low-complexity short-time Fourier transform processing apparatus, characterized in that
7. The method of claim 6,
A low-complexity short-time Fourier transform processing apparatus, characterized in that m and k in Equation 1 are defined as in Equation 2 below using an index decomposition method.
[Formula 2]

8. The method of claim 7,
The FFT operation having a window length of 1024 points is defined as Equation 3 below by substituting Equation 2 into Equation 1,
[Equation 3]

The variable A has a value of A=256m ₁ +64m ₂ +16m ₃ +4m ₄ +m ₅ ,
wherein the variable B has a value of B=k ₁ +4k ₂ +16k ₃ +64k ₄ +256k ₅ .
9. The method of claim 8,
An FFT operation having a window length of 256 points is a low-complexity short-time Fourier transform processing apparatus, characterized in that it is defined according to Equation 4 below.
[Equation 4]

10. The method of claim 9,
A low-complexity short-time Fourier transform processing apparatus, characterized in that the FFT operation having a window length of 64 points is defined according to Equation 5 below.
[Equation 5]

11. The method of claim 10,
A low-complexity short-time Fourier transform processing apparatus, characterized in that the FFT operation having a window length of 16 points is defined according to Equation 6 below.
[Equation 6]

12. The method of claim 11,
A low-complexity short-time Fourier transform processing apparatus, characterized in that the FFT operation having a window length of 4 points is defined according to Equation 7 below.
[Equation 7]

13. The method of claim 12,
The FFT operation having a window length of 1024 points through Equation 3 is a low-complexity short-time Fourier transform processing apparatus, characterized in that the radix-4 butterfly operation is added to Equation 4 above.
14. The method of claim 13,
The FFT operation having a window length of 256 points through Equation 4 is a low-complexity short-time Fourier transform processing apparatus, characterized in that the radix-4 butterfly operation is added to Equation 5 above.
15. The method of claim 14,
The FFT operation having a window length of 64 points through Equation 5 is a low-complexity short-time Fourier transform processing apparatus, characterized in that the radix-4 butterfly operation is added to Equation 6 above.
16. The method of claim 15,
The low-complexity short-time Fourier transform processing apparatus according to Equation 6, wherein the FFT operation having a window length of 16 points is calculated by adding a radix-4 butterfly operation to Equation 7 above.
According to claim 1,
Among the first output channel stream data, second output channel stream data, third output channel stream data, and fourth output channel stream data output through the DRM, the first output channel stream data and the second output channel stream data .
18. The method of claim 17,
Among the first output channel stream data, second output channel stream data, third output channel stream data, and fourth output channel stream data output through the DRM, the first output channel stream data and the third output channel stream data A low-complexity short-time Fourier transform processing unit, characterized in that it provides a 50% superimposed FFT result when selected in order.
19. The method of claim 18,
Among the first output channel stream data, second output channel stream data, third output channel stream data, and fourth output channel stream data output through the DRM, the first output channel stream data and the fourth output channel stream data .
20. The method of claim 19,
From among the first output channel stream data, the second output channel stream data, the third output channel stream data, and the fourth output channel stream data output through the DRM, when only the first output channel stream data is selected in the order of 0% A low-complexity short-time Fourier transform processing apparatus, characterized in that it provides superimposed FFT results.
21. The method of claim 20,
When the first output channel stream data, the second output channel stream data, the third output channel stream data, and the fourth output channel stream data are selected in this order, an overlapping FFT result of 75% is provided, and the first output When the channel stream data and the third output channel stream data are selected in order, an overlapping FFT result of 50% is provided, and the first output channel stream data, the fourth output channel stream data, the third output channel stream data and Selecting in the order of the second output channel stream data provides an overlapping FFT result of 25%, and selecting only the first output channel stream data in order provides an overlapping FFT result of 0%, 0%, 25% , a low-complexity short-time Fourier transform processing apparatus, characterized in that it provides an FFT for 4-channel stream data with variable overlap sizes of 50% and 75%.
It relates to a method of processing a short-time Fourier transform using a short-time Fourier transform processing method including a Data Matching Module (DMM), a plurality of Radix-4 Butterfly Modules (R4BM), a Data Reordering Module (DRM), and a Multiplexer (MUX). ,
By using the DMM, one channel of stream data is received and sequentially delayed at different rates to generate stream data of 4 channels arranged in parallel and overlapped at a certain rate between the delayed stream data, and the stream of the 4 channels a data matching step of multiplying data with a type of window function according to a window length to output 4-channel stream data reconstructed according to the length of each window function;
an STFT operation step of outputting the STFT-calculated 4-channel stream data by performing an STFT (Short Time Fourier Transform) operation according to a preset type of window function using the R4BM on the stream data output through the DMM; and
and a data rearrangement step of receiving the STFT-calculated 4-channel stream data from the R4BM using the DRM, reconstructing it according to the input structure of the 1-channel stream data and outputting,
The data matching step is
By using the DMM, one channel of stream data is received, the first channel stream data delayed by 75% compared to the inputted one channel stream data, the second channel stream data delayed by 50%, the third channel stream data delayed by 25%, 4 channel stream data with a 0% delay is generated between the first channel stream data and the second channel stream data, between the second channel stream data and the third channel stream data, and between the third channel stream data and the A low-complexity short-time Fourier transform processing method, characterized in that each of the fourth channel stream data overlaps by 75%.
23. The method of claim 22,
Between the data matching step and the STFT operation step, the R4BM selection step of outputting the stream data of 4 channels output through the DMM to the R4BM using the MUX so that the STFT operation according to the window length is performed. A low-complexity short-time Fourier transform processing method, characterized in that.
delete 23. The method of claim 22,
The data matching step is
4, 16, 64, 256 in a state in which the first channel stream data, the second channel stream data, the third channel stream data, and the fourth channel stream data are arranged in a mutually parallel pattern using the DMM and low-complexity short-time Fourier transform processing, characterized in that the 4-channel stream data reconstructed according to the length of the set window function is generated and output by multiplication operation with any one of the window functions according to the window length of 1024 points. Way.
26. The method of claim 25,
The STFT operation step is
Using the R4BM, using an FFT processor of a 4-channel (Radix-4) MDC (Multi-path Delay Commutator) method to perform an FFT operation supporting window lengths of 4, 16, 64, 256 and 1024 points, respectively. A low-complexity short-time Fourier transform processing method, characterized in that.
27. The method of claim 26,
The STFT operation is defined according to Equation 1 below,
[Formula 1]

Where n is the starting point of the abnormal signal, represented by n = 1N,
wherein l has the range of -∞≤l≤∞,
where k is a frequency index,
wherein m is a discrete variable,
Wherein N represents the length of the window function,
remind

silver

is the tweeter factor when rotating clockwise over N steps as the value of km increases in the complex plane,
The signal of x[n+m] is multiplied with w[m], which is a window function, to become a signal of x ⁽ⁿ⁾ [m], so that the STFT operation is an FFT operation on the signal of ^x(n)[m]. A low-complexity short-time Fourier transform processing method, characterized in that
28. The method of claim 27,
A low-complexity short-time Fourier transform processing method, characterized in that the m and k of Equation 1 are defined as in Equation 2 below using an index decomposition method.
[Formula 2]

29. The method of claim 28,
The FFT operation having a window length of 1024 points is defined as Equation 3 below by substituting Equation 2 into Equation 1,
[Equation 3]

The variable A has a value of A=256m ₁ +64m ₂ +16m ₃ +4m ₄ +m ₅ ,
The variable B has a value of B=k ₁ +4k ₂ +16k ₃ +64k ₄ +256k _5. A low-complexity short-time Fourier transform processing method.
30. The method of claim 29,
A low-complexity short-time Fourier transform processing method, characterized in that the FFT operation having a window length of 256 points is defined according to Equation 4 below.
[Equation 4]

31. The method of claim 30,
An FFT operation having a window length of 64 points is a low-complexity short-time Fourier transform processing method, characterized in that it is defined according to Equation 5 below.
[Equation 5]

32. The method of claim 31,
A low-complexity short-time Fourier transform processing method, characterized in that the FFT operation having a window length of 16 points is defined according to Equation 6 below.
[Equation 6]

33. The method of claim 32,
A low-complexity short-time Fourier transform processing method, characterized in that the FFT operation having a window length of 4 points is defined according to Equation 7 below.
[Equation 7]

34. The method of claim 33,
The FFT operation having a window length of 1024 points through Equation 3 is a low-complexity short-time Fourier transform processing method, characterized in that the radix-4 butterfly operation is added to Equation 4 above.
35. The method of claim 34,
The FFT operation having a window length of 256 points through Equation 4 is a low-complexity short-time Fourier transform processing method, characterized in that the radix-4 butterfly operation is added to Equation 5 above.
36. The method of claim 35,
The FFT operation having a window length of 64 points through Equation 5 is a low-complexity short-time Fourier transform processing method, characterized in that the radix-4 butterfly operation is added to Equation 6 above.
37. The method of claim 36,
The FFT operation having a window length of 16 points through Equation 6 is a low-complexity short-time Fourier transform processing method, characterized in that the radix-4 butterfly operation is added to Equation 7 above.
23. The method of claim 22,
Among the first output channel stream data, second output channel stream data, third output channel stream data, and fourth output channel stream data output through the DRM, the first output channel stream data and the second output channel stream data .
39. The method of claim 38,
Among the first output channel stream data, second output channel stream data, third output channel stream data, and fourth output channel stream data output through the DRM, the first output channel stream data and the third output channel stream data A low-complexity short-time Fourier transform processing method, characterized in that it provides 50% superimposed FFT results when selected in order.
40. The method of claim 39,
Among the first output channel stream data, second output channel stream data, third output channel stream data, and fourth output channel stream data output through the DRM, the first output channel stream data and the fourth output channel stream data .
41. The method of claim 40,
From among the first output channel stream data, the second output channel stream data, the third output channel stream data, and the fourth output channel stream data output through the DRM, when only the first output channel stream data is selected in the order of 0% A method for processing a low-complexity short-time Fourier transform, characterized in that it provides a superimposed FFT result.
42. The method of claim 41,
When the first output channel stream data, the second output channel stream data, the third output channel stream data, and the fourth output channel stream data are selected in this order, an overlapping FFT result of 75% is provided, and the first output When the channel stream data and the third output channel stream data are selected in order, an overlapping FFT result of 50% is provided, and the first output channel stream data, the fourth output channel stream data, the third output channel stream data and Selecting in the order of the second output channel stream data provides an overlapping FFT result of 25%, and selecting only the first output channel stream data in order provides an overlapping FFT result of 0%, 0%, 25% , a short-time Fourier transform processing method of low complexity, characterized in that it provides an FFT for 4-channel stream data with variable overlap sizes of 50% and 75%.

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