KR102297765B1 - Method and Apparatus for Testing Submodule of MMC-HVDC System - Google Patents

Abstract

This embodiment includes a first circuit and a second circuit connected in parallel to each other, wherein the first circuit includes a first switch and a sub-module capacitor connected in series, and the second circuit includes a second switch. An apparatus for testing a level converter sub-module, comprising: an inverter for receiving a current of a DC power supply and generating an AC current; an inductor connected in series with the output of the inverter and the sub-module through which an inductor current flows; an auxiliary capacitor connected in series to the output of the inverter, the sub-module, and the inductor; an auxiliary power supply unit for providing auxiliary power output to both ends of the auxiliary capacitor so that the voltage of the auxiliary capacitor is kept constant; and a control unit controlling the circuit connection of the DC power supply by controlling the inverter, and controlling the circuit connection of the sub-module capacitor by controlling the first switch and the second switch. do.

Description

Method and Apparatus for Testing Submodule of MMC-HVDC System

The present embodiment relates to a method and an apparatus for testing a submodule of a Modular Multi-level Converter (MMC)-HVDC (High Voltage Direct Current) system.

The content described below merely provides background information related to the present embodiment and does not constitute the prior art.

1 is a diagram illustrating an MMC-HVDC system 100 having n submodules in one arm and a single submodule 110 having a half-bridge structure.

In order to confirm the reliability of the MMC-HVDC system 100 , a performance test of the sub-module 110 used in the arm of the MMC-HVDC system 100 is essential. Since one arm of the MMC-HVDC system 100 is generally composed of 100 or more sub-modules 110, considering the time and cost of the test circuit configuration for testing the MMC-HVDC system 100, a single sub-module It is common to test only the module 110 or perform the test in units of valves, which are units in which a plurality of sub-modules 110 are bundled.

In order to simulate the dark current, which is the current flowing through each arm of the MMC-HVDC system, a current including the second harmonic and DC offset component is generated in the test circuit to provide a situation similar to the operating state of the actual MMC-HVDC system. Needs to be.

In this way, when the dark current including the second harmonic and the DC offset component is simulated and generated, switching loss and distortion of the dark current are preferably minimized if possible.

The main purpose of this embodiment is to provide a test circuit that generates a test current that linearly simulates a dark current including a DC offset component and a second harmonic component necessary for testing a submodule of the MMC-HVDC system. There is this.

According to this embodiment, a first circuit and a second circuit connected in parallel to each other, wherein the first circuit includes a first switch and a sub-module capacitor connected in series, and the second circuit includes a second switch. An apparatus for testing a multi-level converter sub-module, comprising: an inverter for receiving a current of a DC power source and generating an AC current; an inductor connected in series with the output of the inverter and the sub-module through which an inductor current flows; an auxiliary capacitor connected in series to the output of the inverter, the sub-module, and the inductor; an auxiliary power supply unit for providing auxiliary power output to both ends of the auxiliary capacitor so that the voltage of the auxiliary capacitor is kept constant; and a control unit controlling the circuit connection of the DC power supply by controlling the inverter, and controlling the circuit connection of the sub-module capacitor by controlling the first switch and the second switch. do.

According to this embodiment, including a first circuit and a second circuit connected in parallel to each other, wherein the first circuit includes a first switch and a sub-module capacitor connected in series, and the second circuit includes a second switch. A method for testing a sub-module in an apparatus for testing a level converter sub-module, the method comprising: generating an AC current by receiving a current of a DC power supply from an inverter; a process in which an inductor current flows through an inductor connected to an output of the inverter; providing an auxiliary power output to both ends of the auxiliary capacitor so that the output of the inverter and the voltage of the auxiliary capacitor connected in series to the inductor are kept constant; and controlling the circuit connection of the DC power supply by controlling the inverter, and controlling the circuit connection of the sub-module capacitor by controlling the first switch and the second switch, wherein the sub-module includes the A method for testing a submodule connected in series to an output of an inverter and the inductor is provided.

According to this embodiment, there is an effect of generating a test current that linearly simulates a dark current including a DC offset component and a second harmonic component for testing a submodule of the MMC-HVDC system.

In addition, there is an effect of providing a test circuit in which switching loss is minimized by using a relatively low switching frequency in simulating and generating a dark current.

1 is a diagram illustrating an MMC-HVDC system having n submodules in one arm and a single submodule having a half-bridge structure.
2 is a view showing the structure of the sub-module testing apparatus according to the present embodiment.
3 is a view showing waveforms of current and voltage generated in the sub-module test apparatus according to the present embodiment.
4 is a view showing the values of _{v o} , v _sm , v _L and the slope of _{i L} according to the operation mode of the sub-module test apparatus.
5 is a diagram illustrating components that can be additionally implemented in a sub-module testing apparatus together with a control unit.
6 is a view showing the flow of current of the sub-module test apparatus in the case of mode 1.
7 is a view showing the flow of current of the sub-module test apparatus in mode 2;
8 is a view showing the current flow of the sub-module test apparatus in mode 3 and mode 5;
9 is a view showing the current flow of the sub-module test apparatus in the case of mode 4 and mode 6.
10 is a view showing the current flow of the sub-module test apparatus in the case of mode 7.
11 is a view showing the current flow of the sub-module test device in the case of mode 8.
12 is a diagram illustrating parameters for verifying the performance of the sub-module test apparatus according to the present embodiment.
13 is a diagram illustrating a steady-state simulation waveform when a dark current having a positive DC offset is simulated.
14 is a diagram illustrating a steady-state simulation waveform when a dark current having a negative DC offset is simulated.

Hereinafter, some embodiments of the present invention will be described in detail with reference to exemplary drawings. In adding reference numerals to the components of each drawing, it should be noted that the same components are given the same reference numerals as much as possible even though they are indicated on different drawings. In addition, in describing the present invention, if it is determined that a detailed description of a related known configuration or function may obscure the gist of the present invention, the detailed description thereof will be omitted.

2 is a view showing the structure of the sub-module test apparatus according to the present embodiment.

As shown in FIG. 2 , the sub-module testing apparatus 200 according to this embodiment includes a DC power supply 210 , an inverter 220 , an inductor 230 , an auxiliary capacitor 240 , an auxiliary power supply unit 250 and All or part of the control unit 260 is included.

The sub-module 110 includes a first circuit and a second circuit connected to each other in parallel at both ends. Here, the first circuit includes a first switch (S _T ) and a sub-module capacitor (C _sm ) connected in series, and the second circuit includes a second switch (S _B ). In addition, each switch (S _T , S _B ) of the sub-module 110 anti-parallel diodes (D _T , D _B ) are connected in parallel, respectively.

The inverter 220 is implemented in the form of a full-bridge, receives the output current of the DC power supply 210 and converts it into an AC to generate an AC current output.

The inverter 220 includes a first leg and a second leg connected in parallel. The first leg includes a first switch (S ₁ ) and a third switch (S ₃ ) connected in series in the same direction, and the second leg includes a second switch ( S ₂ ) and a fourth switch (S) connected in series in the same direction. ₄ ) is included.

The AC current output of the inverter 220 is generated from the contact point between the first switch S ₁ and the third switch S ₃ and the contact point between the second switch S ₂ and the fourth switch S _{4 .}

In addition, each switch (S ₁ , S ₂ , S ₃ , S ₄ ) has an anti-parallel diode ( D ₁ , D ₂ , D ₃ , D ₄ ) connected in parallel, respectively.

The inverter 220 generates an AC current output by controlling the switching of _{each of the switches S 1} , S ₂ , S ₃ , and S _{4 under} the control of the controller 260 , which will be described later.

An inductor 230 , an auxiliary capacitor 240 , and a sub-module 110 are connected in series to the output of the inverter 220 .

_{The inductor current i L} flows according to the voltage applied to both ends of the inductor 230 .

The auxiliary power supply unit 250 provides an auxiliary power output to the auxiliary capacitor 240 so that the voltage of the auxiliary capacitor 240 is kept constant.

The auxiliary power supply 250 converts the DC power 210 to DC-DC to generate an auxiliary power output, and both terminals of the generated auxiliary power output are connected in parallel to both terminals of the auxiliary capacitor 240 .

The controller 260 controls the circuit connection of the sub-module capacitor C _{sm by switching the first switch S T} and the second switch S _{B , and switches S 1} , S ₂ of the inverter 220 . , S ₃ , S ₄ ) to control the circuit connection of the DC power supply 210 by switching.

Hereinafter, in the description of the present embodiment, the expression connected to the circuit means that the inductor current of the inductor 230 is connected to flow. In addition, the expression of controlling the circuit connection means controlling the direction in which the inductor current flows or blocking the flow of the inductor current.

In the circuit of FIG. 2 , the inductor current i _L flowing through the inductor 230 is determined by the _{voltage v L} across the inductor 230 . The magnitude of v _L is determined by the output voltage v _o of the inverter 220 and the output voltage v _sm,o of the sub-module 110 and the voltage v _aux of the _{sub-module capacitor C sm , so v L} , v _o , v _{The relationship between sm, o} and v _aux can be expressed as in Equation (1).

The auxiliary power supply unit 250 generates an output for maintaining _{v aux} constant when the auxiliary capacitor 240 C _aux is charged/discharged _{due to the flow of i L .}

Here, the shape of the inductor current i _{L may vary according to the size of the output v aux} of the auxiliary power supply 250 , and details thereof will be described later.

3 is a diagram illustrating waveforms of current and voltage generated in the sub-module testing apparatus 200 according to the present embodiment.

I _L is the average value of v _sm as a linearizing the dark current flowing in the actual MMC-HVDC system in Figure 3 <v _sm> and v mean value of the _aux <v _aux> and the relationship between V _in when set as shown in equation (2) can be obtained

In other words, the control unit 260 controls the average voltage <v _{sm > of v sm,o} to be equal to the magnitude of the input voltage V _in of the DC power supply 210 in order to cancel the effect _{of v sm,o} on v _{L .} do.

In addition, the auxiliary power output voltage of the auxiliary power supply unit 250 is set to be smaller than the voltage level of the DC power source 210 . For example, as shown in Equation 2, the magnitude of the auxiliary power output voltage of the auxiliary power supply unit 250 is set to be 3/4 of the voltage level of the DC power supply 210 .

When the auxiliary power output voltage of the auxiliary power supply unit 250 is set to be smaller than the voltage level of the DC power supply 210, the direction of increase or decrease of the current applied by the DC power supply 210 and the auxiliary capacitor 240 to the inverter 220 is It is determined by the DC power supply 210 . This will be described in detail in the description of the eight operation modes to be described later.

The operation of the circuit of FIG. 2 can be divided into eight operation modes as shown in FIG. 4 according to _{the operation of each switch ST} and S _B of the submodule 110 and the value of the inverter current i _{L .}

4 is a view showing the values of _{v o} , v _sm , v _L and the direction of the inclination of _{i L} according to the operation mode of the sub-module testing apparatus 200 .

The flow of current in the circuit according to the operation mode shown in FIG. 4 will be described in detail below.

FIG. 5 is a diagram illustrating components that can be additionally implemented in the submodule testing apparatus 200 together with the control unit 260 .

As shown in FIG. 5 , the sub-module testing apparatus 200 may further include an average voltage calculating unit 510 .

The average voltage calculating unit 510 _{receives the voltage value v sm} at both ends of the submodule 110 and calculates the average value <v _{sm >.}

The control unit 260 receives the reference voltage v _sm,ref and <v _sm >, and according to the difference between _{v sm,ref} and <v _{sm >, each switch S T} , S _B of the submodule 110 and the inverter ( 220) of each switch (S ₁ ~ S ₄ ) to control the switching.

The control unit 260 controls the switching of each of the switches S _T and S _B of the sub-module 110 and each of the switches S ₁ to S _{4 of the inverter 220 according to the magnitude of the inductor current i L} .

The controller 260 performs hysteresis control on the _{inductor current i L .} Here, the hysteresis control means controlling the inductor current i _L to move between the lower peak point i _{peak (-)} and the upper peak point i _{peak (+) of the preset inductor current i L .}

The control unit 260 _{switches each switch (S T} , S _B ) of the sub-module 110 and each switch (S ₁ ~ S ₄ ) of the inverter 220 according to the size _{of i L and the value of <v sm >} The details of the operation of controlling , will be described later.

6 to 11 are diagrams illustrating the flow of current of the sub-module testing device 200 in the operation mode (mode 1 to mode 8) of the sub-module testing device 200 .

The sub-module test apparatus 200 operates while periodically repeating the operation modes (Mode 1 to Mode 8).

Hereinafter, operation modes (modes 1 to 8) of the sub-module test apparatus 200 will be described with reference to FIGS. 3 to 11 together.

6 to 11 , the inductor current flows through the path of the shaded portion on the circuit, and the direction in which the inductor current flows is the direction of the dark arrow indicated on the darkened path on the circuit.

For reference, the case shown to be a a S _T and S _B from Figure 3 does not mean only when the switch S _T and S _B switched on under the control of the controller 260, switch S _T and S _A case in which current flows through _{antiparallel diodes D T} and D _B respectively connected in parallel to B is also included.

_{In addition, substantially the value of the voltage v sm} at both ends of the sub-module 110 is not large compared to the value of <v _sm > whose amplitude is an average value, and the voltage v _aux of the sub-module capacitor C _sm is the average value. Since the range of change is small compared to the size of <v _aux >, it is assumed that Equation 3 is used in the description of FIGS. 6 to 11 .

(One) mode 1: [t _One ~t ₂ ] section, S _T on, S _B / S _One ~S ₄ off , i _L Increase.

6 is a view showing the flow of current of the sub-module test apparatus 200 in the case of mode 1.

As shown in FIG. 3 , the sub-module test apparatus 200 enters mode 1 at the time _{t 1 when the inductor current i L} continues to decrease and reaches the lower peak point.

At this time, the control unit 260 controls the DC power supply 210 to be circuitly connected to the sub-module capacitor C _sm and the auxiliary capacitor 240 C _aux . Here, the polarity of the DC power supply 210 is in the same direction as the polarity of the auxiliary capacitor 240 on the connected circuit.

In order to enter mode 1, the control unit 260 switches the inverter switches S ₁ to S ₄ to be OFF, the submodule switch S _T is ON, and the submodule switch S _B is OFF to switch the inductor current i _L to the antiparallel diode D _1, and controls so that the direct current power source 210, anti-parallel diode D _4, the auxiliary capacitor (240) C _aux, submodule capacitor C _sm and the sub-modules via the switch S _T to flow in the reverse direction.

_{When the sub-module switch S T} is turned on and the sub-module switch S _B is turned off by the switching of the control unit 260 _{, v sm,o} = v _sm .

_{Since all inverter switches S 1} to S ₄ are turned off by the switching of the controller 260 , the DC power supply 210 is connected to the circuit via the anti-parallel diodes D ₁ and D _{4 , so that v o} = V _in . In addition, since V _in = v _sm = v _{sm,o , v o} and v _sm,o having opposite polarities cancel each other to become inductor voltage v _L = v _aux . Therefore, the inductor current i _L rises as in Equation 4 in the period [t ₁ to t _{2 ].}

Here, L represents the inductance of the inductor 230 .

(2) mode 2: [t ₂ ~t ₃ ] section, S _T /S ₂ ~S ₄ off , S _B / S _One on, i _L Increase.

7 is a diagram illustrating the flow of current in mode 2;

As shown in FIG. 3 , the sub-module test apparatus 200 enters mode 2 at the time _{t 2 when the inductor current i L} reaches 0 from the negative state.

At this time, the controller 260 controls the DC power supply 210 and the sub-module capacitor C _{sm to be circuitly} cut off from the auxiliary capacitor 240 C aux .

In order to enter mode 2, the control unit 260 switches the inverter switch S ₁ on, the sub-module switch S _T is off, and the sub-module switch S _B is on, so that the inductor current i _L is the sub-module switch S _B , the auxiliary capacitor 240 C _aux , the antiparallel diode D ₂ and the inverter switch S ₁ to control the flow in the forward direction.

At this time, v _sm,o becomes 0 [V] and v _o becomes 0 [V], so v _L = v _aux and the inductor current i _L rises as in Equation 5 in the [t ₂ ~t _{3 ] section.} do.

(3) mode 3: [t ₃ ~t ₄ ] section, S _T / S _B / S _One ~S ₃ off , S ₄ on, i _L descent.

8 is a diagram illustrating a flow of current in mode 3;

As shown in FIG. 3 , the sub-module test apparatus 200 enters mode 3 at the time _{t 3 when the inductor current i L} increases and reaches the upper peak point.

At this time, the controller 260 controls the sub-module capacitor C _{sm to be circuitly} connected to the auxiliary capacitor 240 C aux and the DC power 210 to be _circuitly cut off from the auxiliary capacitor 240 C aux .

To enter mode 3, the control unit 260 switches the inverter switches S ₁ to S ₃ to be off, the inverter switch S ₄ to be on, and the submodule switches S _T and S _B to be off, so that the inductor current i _L is reversed. Parallel diode D _T , sub-module capacitor C _sm , auxiliary capacitor 240 C _aux , inverter switch S ₄ , DC power 210 and anti-parallel diode D ₃ are controlled to flow in the forward direction.

At this time, v _sm,o is the _{same as v sm} and vo becomes 0 [V], so v _L =v _aux -v _sm becomes and the inductor current i _L falls as in Equation 6 in the [t ₃ ~t _{4 ] section.} do.

(4) mode 4: [t ₄ ~t ₅ ] section, S _T /S _One ~S ₄ off , S _B on, i _L descent.

9 is a diagram illustrating the flow of current in mode 4;

As shown in FIG. 3 , the sub-module testing apparatus 200 enters the mode 4 at the time _{t 4} when the first preset time elapses after entering the mode 3 .

At this time, the control unit 260 controls the DC power supply 210 to be circuitly connected to the auxiliary capacitor 240 C _aux and the sub-module capacitor C _{sm to be circuitly} cut off from the auxiliary capacitor 240 C aux .

To enter mode 4, the control unit 260 switches the inverter switches S ₁ to S ₄ to be off, the sub-module switch S _T is turned off, and the sub-module switch S _{B is} to be on, so that the inductor current i _L is the sub-module switch S _B , auxiliary capacitor 240 C _aux , anti-parallel diode D ₂ , DC power 210 and anti-parallel diode D ₃ are controlled to flow in the forward direction.

Here, v _{sm, o} is 0 [V] is _in the v _o is -V, v _L = v _aux is -V _in the inductor current i _L is [t ₄ ~ t _5] Equation (7) in the interval since the go down together

(5) mode 5: [t ₅ ~t ₆ ] section, S _T /S _B /S _One ~S ₃ off, S ₄ on, i _L descent.

After entering mode 4, when the second preset time elapses, mode 5 is entered. Wherein the second preset time may be or the like, the time to reach the top of the peak value from a may have a value of 1/4 of the period, and thus the inductor current i _L is the lower peak value to an embodiment of the i _L.

The control unit 260 switches the inverter switches (S ₁ to S ₄ ) and the sub-module switches (S _T , S _B ) in the same state as in mode 5 .

Therefore, the current i _L falls as in Equation 8 in the period [t ₅ ~ t _{6 ].}

(6) mode 6: [t ₆ ~t ₇ ] section, S _T /S _One ~S ₄ off, S _B on, i _L descent.

After entering mode 5, when the first duration elapses, mode 6 is entered.

The first duration is a value set by the controller 260 . After the first duration is set to the preset initial value, the controller 260 updates the first duration according to a difference between the _{reference voltage v sm,ref} and the average voltage <v _{sm > of the sub-module 110 .}

For example, after the first duration is set to have the same value as the second preset time as the initial value, the controller 260 determines that the reference voltage v _sm,ref is the average voltage of the submodule 110 <v _sm > If greater, the first duration is increased. If the reference voltage v _{sm,ref is less than the average voltage <v sm} > of the sub-module 110 , the first duration is decreased.

Therefore, the time for switching to mode 3 and mode 5 after _{the inductor current i L} flowing through the inductor 230 reaches the upper peak point is the average voltage value of the _{sub-module capacitor C sm <v sm by the controller 260 .} It is determined according to the difference between > and the reference voltage value v _sm,ref.

In order to enter mode 6, the control unit 260 switches the inverter switches S ₁ to S ₄ and the sub-module switches S _T and S _{B in the} same state as in mode 4.

Therefore, the current i _L falls as in Equation 9 in the [t ₆ ~ t _{7 ] section.}

(7) Mode 7: [t ₇ ~t ₈ ] section, S _T /S _B /S _One /S ₄ off, S ₂ /S ₃ on, i _L descent.

10 is a diagram illustrating a flow of current in mode 7;

As shown in FIG. 3 , the sub-module test apparatus 200 enters mode 7 at the time _{t 7 when the inductor current i L} reaches 0 from the (+) state.

At this time, the control unit 260 controls the DC power supply 210 to be circuitly connected to the auxiliary capacitor 240 C _aux and the sub-module capacitor C _{sm to be circuitly} cut off from the auxiliary capacitor 240 C aux .

In order to enter mode 7, the control unit 260 switches the inverter switches S ₁ and S ₄ to be off, the inverter switches S ₂ and S ₃ to be on, and the submodule switches S _T and S _B to be off, so that the inductor current i _L is controlled to flow in the reverse direction via the inverter switch S ₃ , the DC power supply 210 , the inverter switch S ₂ , the auxiliary capacitor 240 C _aux and the antiparallel diode D _{B .}

Here, v _{sm, o} is 0 [V] is _in the v _o is -V, v _L = v _aux is -V _in the inductor current i _L is Equation (10) in the interval [t ₇ ~ t _8] Since the go down together

(8) Mode 8: [t ₈ ~t ₉ ] section, S _T /S ₃ on, S _B /S _One /S ₂ /S ₄ off, i _L descent.

11 is a diagram illustrating a flow of current in mode 8. FIG.

As shown in FIG. 3 , the sub-module test apparatus 200 enters the mode 8 at the time _{t 8} when the third preset time elapses after entering the mode 6 .

Here, the third preset time _{may have a value of 1/4 of one cycle of i L} , and according to an embodiment, the inductor current i _L may vary depending on the embodiment, such as the time from the lower peak value to the upper peak value. can have a value.

At this time, the controller 260 controls the sub-module capacitor C _{sm to be circuitly connected} to the auxiliary capacitor 240 C _aux and the DC power 210 to be _circuitly cut off from the auxiliary capacitor 240 C aux .

In order to enter mode 8, the controller 260 switches the inverter switches S ₁ , S ₂ and S ₄ off, the inverter switch S ₃ turns on, the sub-module switch S _T on, and the sub-module switch S _B to be off. and controls the inductor current i _L to flow in the reverse direction by way of the inverter switches S _3, the antiparallel diode D _4, the auxiliary capacitor (240) C _aux, submodule capacitor C _sm and the sub-module switch S _T.

At this time, v _sm,o becomes v _sm and v _o becomes 0 [V], so v _L =v _aux -v _sm becomes and the inductor current i _L becomes as in Equation 11 in the section [t ₈ ~ t _{9 ]} descend

As described above in the operation mode of the sub-module test apparatus 200, the control unit 260 controls the DC power supply 210 in the sections of mode 1 and mode 2 in which the _{inductor current i L increases from the lower peak point to the upper peak point.} And the sub-module capacitor (C _sm ) is circuitly connected to the inductor 230 or both the DC power supply 210 and the sub-module capacitor (C _sm ) are controlled not to be circuitly connected to the inductor 230 .

In addition, the control unit 260 is one of the DC power supply 210 and the sub-module capacitor (C _sm ) is connected to the inductor 230 in _{the sections of modes 3 to and mode 8 in which the inductor current i L decreases, and the DC power supply 210} ) and the other of the sub-module capacitor (C _sm ) is controlled to be cut off from the inductor 230 .

In addition, when the control unit 260 controls the DC power supply 210 to be circuitly connected in the section in which the _{inductor current i L} increases (that is, in mode 1), in the same direction as the polarity of _{the auxiliary capacitor 240 C aux .} In the case of controlling to be connected, but controlling the DC power supply 210 to be circuitly connected in the section where the inductor current i _{L decreases (ie, modes 4, 6, 7), the polarity of the auxiliary capacitor 240 C aux} is opposite to the polarity control to connect in the right direction.

12 is a diagram illustrating parameters for verifying the performance of the submodule testing apparatus 200 according to the present embodiment.

In order to verify the performance of the submodule test apparatus 200 according to the present embodiment, a simulation was performed by applying the parameters shown in FIG. 12 .

13 is a view showing a steady-state simulation waveform when a dark current having a positive DC offset is simulated, and FIG. 14 is a view showing a steady-state simulation waveform when a dark current having a negative DC offset is simulated. am.

As shown in FIGS. 13 and 14 , looking at the simulation waveform, the dark current of the MMC-HVDC system including the DC offset and the second harmonic component is linearly approximated while _{the average voltage v sm of the sub-module capacitor is constantly controlled.} It can be seen that one i _L is output without distortion.

In addition, while conventionally, switching in units of several tens of kHz is required to simulate a dark current of 60 Hz, in this embodiment, a dark current can be simulated only by switching of about 180 to 200 Hz, so the loss due to switching is reduced compared to the prior art. This has the effect of greatly reducing it.

The above description is merely illustrative of the technical idea of this embodiment, and various modifications and variations will be possible by those skilled in the art to which this embodiment belongs without departing from the essential characteristics of the present embodiment. Accordingly, the present embodiments are intended to explain rather than limit the technical spirit of the present embodiment, and the scope of the technical spirit of the present embodiment is not limited by these embodiments. The protection scope of this embodiment should be interpreted by the following claims, and all technical ideas within the equivalent range should be interpreted as being included in the scope of the present embodiment.

100: MMC-HVDC system 110: submodule
200: sub-module test device 210: DC power
220: inverter 230: inductor
240: auxiliary capacitor 250: auxiliary power supply
260: control unit 510: average voltage calculation unit

Claims (11)

A modular multi-level converter sub-module comprising a first circuit and a second circuit connected in parallel to each other, wherein the first circuit includes a first switch and a sub-module capacitor connected in series, and the second circuit includes a second switch In the device to be tested,
an inverter that receives a current from a DC power supply and generates an AC current;
an inductor connected in series with the output of the inverter and the sub-module through which an inductor current flows;
an auxiliary capacitor forming a loop with the output of the inverter, the inductor, and the output of the sub-module;
an auxiliary power supply unit for providing auxiliary power output to both ends of the auxiliary capacitor so that the voltage of the auxiliary capacitor is kept constant; and
A control unit controlling the circuit connection of the DC power supply by controlling the inverter, and controlling the circuit connection of the sub-module capacitor by controlling the first switch and the second switch
A sub-module test device comprising a. According to claim 1,
The auxiliary power supply unit,
The sub-module testing apparatus, characterized in that by converting the DC power to DC-DC to generate the auxiliary power output, both ends of the auxiliary power output are connected in parallel to both ends of the auxiliary capacitor. According to claim 1,
The voltage of the auxiliary power output is
Sub-module testing apparatus, characterized in that it is set to be smaller than the voltage level of the DC power. According to claim 1,
The control unit is
and controlling the DC power supply to be connected in series to the sub-module capacitor and the auxiliary capacitor when the inductor current reaches a lower peak point. According to claim 1,
The control unit is
When the value of the inductor current reaches 0 from a negative state, the sub-module testing apparatus according to claim 1, wherein the DC power supply and the sub-module capacitor are controlled so that the connection with the auxiliary capacitor is cut off. According to claim 1,
The control unit is
After the inductor current flowing through the inductor reaches the upper peak point, the sub-module capacitor is connected to the auxiliary capacitor for a preset time, and the DC power is controlled to be cut off from the auxiliary capacitor. . 7. The method of claim 6,
The control unit is
and determining the preset time according to a difference between an average voltage value of the sub-module capacitor and a reference voltage value. According to claim 1,
The control unit is
When the value of the inductor current reaches 0 from the (+) state, the connection direction of the DC power is switched to the opposite direction, and the sub-module test apparatus is controlled to be connected to the auxiliary capacitor. According to claim 1,
The control unit is
In a section in which the inductor current increases, the DC power supply and the sub-module capacitor are controlled to be connected to the inductor together or both the DC power and the sub-module capacitor are not connected to the inductor. 10. The method of claim 9,
The control unit is
In a section in which the inductor current decreases, one of the DC power supply and the sub-module capacitor is connected to the inductor and the other is controlled to be cut off from the inductor. A modular multi-level converter sub-module comprising a first circuit and a second circuit connected in parallel to each other, wherein the first circuit includes a first switch and a sub-module capacitor connected in series, and the second circuit includes a second switch A method for testing a submodule in a device to be tested, comprising:
A process of generating an AC current by receiving a current of a DC power supply from an inverter;
an inductor current flowing through an output of the inverter and an inductor connected in series with the sub-module;
providing an auxiliary power output at both ends of the auxiliary capacitor so that the voltage of the output of the inverter, the inductor, and the auxiliary capacitor forming a loop with the output of the sub-module is kept constant; and
A process of controlling the circuit connection of the DC power supply by controlling the inverter, and controlling the circuit connection of the sub-module capacitor by controlling the first switch and the second switch
Submodule test method including

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