KR102291651B1 - Readout circuit for ternary signal and operating method for reading ternary data using the same - Google Patents

Abstract

In a circuit for reading a ternary for reading ternary data stored in an SRAM cell using a signal applied through a treat line, the circuit for reading the ternary according to one embodiment of the present invention comprises: a preamplifier that generates an amplified voltage by amplifying a change voltage of the SRAM cell by a preset change rate when the SRAM cell is connected to the treat line; and a comparator that reads the ternary data by outputting the binary data by comparing a magnitude between the amplified voltage and a reference voltage. Therefore, the present invention is capable of reading ternary data without distortion.

Description

A ternary read circuit and a method of reading ternary data using it

The present invention relates to a ternary read circuit and a method for digitally reading ternary data using the same, and more particularly, a ternary read circuit including a preamplifier and a comparator, and a ternary read circuit using the same to convert ternary data into digital data It is about how to convert and read.

With the development of process technology, storage devices capable of storing more information in a small chip in the nanometer unit have been developed. However, the method of increasing the storage capacity by reducing the device size has a physical limitation that the device cannot be made smaller than the atomic size, and other technologies are needed to overcome this limitation. One of the methods is to change the digital method to the ternary method.

In the case of one conventional digital SRAM cell, information is stored as 0 and 1. In the case of a ternary cell (T-SRAM), information is tritted to 0, 1, 2 (or 0, 1/2, 1). ) information can be stored in one SRAM cell, so 1.5 times the storage capacity of the same size can be realized. That is, when a ternary device is used, an SRAM storage medium having more storage space can be made without reducing the size of the device.

In order to read the trit information stored in the T-SRAM, a separate circuit is required because the existing digital circuit-based SRAM read circuit handles only binary data. When the inverter is simply replaced with a ternary element, the middle voltage (eg, VDD/2) of the ternary data may be read, but accurate information may not be read according to the pre-charging voltage.

The present invention is to solve the above problems, in a ternary SRAM (T-SRAM) array, a ternary read by using a binary element to read ternary data stored in the T-SRAM without distortion An object of the present invention is to provide a circuit and a method of operating the same.

A ternary read circuit according to an embodiment of the present invention is a ternary read circuit for reading ternary data stored in an SRAM cell using a signal applied through a treat line, wherein the SRAM cell is connected to the treat line a preamplifier configured to amplify the change voltage of the SRAM cell by a preset change rate to generate an amplified voltage; and a comparator for reading the ternary data by outputting binary data by comparing the magnitude between the amplified voltage and the reference voltage.

The preamplifier may pre-charging the treat line to a first charging voltage.

the ternary read circuit includes a plurality of comparators including a first comparator and a second comparator, wherein the reference voltage includes a first reference voltage and a second reference voltage having a lower value than the first reference voltage; The first comparator compares the amplified voltage with the first reference voltage to output first high voltage data or first low voltage data, and the second comparator compares the amplified voltage with the second reference voltage to obtain a second comparator. 2 high voltage data or second low voltage data may be output.

When high voltage data or low voltage data is stored in the SRAM cell, both the first comparator and the second comparator may output high voltage data, or both of the first comparator may output low voltage data.

When middle voltage data is stored in the SRAM cell, the first comparator outputs the first high voltage data, the second comparator outputs the second low voltage data, or the first comparator outputs the first low voltage data. The voltage data may be output, and the second comparator may output the second high voltage data.

The ternary read circuit may further include a rewrite unit configured to restore existing data corresponding to the output value of the treatment line according to an output value of the comparator.

In the method of reading ternary data stored in an SRAM cell using a signal applied through a treat line according to an embodiment of the present invention, any one selected from high voltage data, low voltage data, and middle voltage data in the SRAM cell storing the data of generating an amplified voltage by amplifying a change voltage of the treatment line when the treatment line is connected to the SRAM cell by a preset change rate; and reading the ternary data by outputting binary data by comparing the magnitude between the amplified voltage and the reference voltage.

The method may further include, before generating the amplified voltage, pre-charging the treatment line with a first charging voltage.

The reference voltage includes a first reference voltage and a second reference voltage having a lower value than the first reference voltage, and the comparing and outputting binary data may include comparing the amplified voltage with the first reference voltage. a first comparison step of outputting first high voltage data or first low voltage data; and a second comparison step of outputting second high voltage data or second low voltage data by comparing the amplified voltage with the second reference voltage.

The comparing and outputting binary data may include outputting high voltage data in both the first comparing step and the second comparing step when the high voltage data or the low voltage data is stored in the SRAM cell; All of them may be characterized in that they output low voltage data.

The comparing and outputting binary data may include outputting the first high voltage data in the first comparing step and outputting the second high voltage data in the second comparing step when the middle voltage data is stored in the SRAM cell. Low voltage data may be output, or the first low voltage data may be output in the first comparison step, and the second high voltage data may be output in the second comparison step.

The method of reading the ternary data may further include restoring and rewriting existing data corresponding to the output value of the treatment line according to the output values of the first comparison step and the second comparison step.

The computer program according to an embodiment of the present invention may be stored in a medium in order to execute the above-described method of reading ternary data using a computer.

According to embodiments of the present invention, ternary data can be read without distortion by converting ternary data into binary data using the arrangement of existing binary elements through design of a preamplifier and a comparator.

In addition, it is possible to prevent data from being distorted after reading the ternary data through a rewrite logic.

1 is a diagram schematically illustrating a ternary SRAM array according to an embodiment of the present invention.
2 is a graph illustrating input/output characteristics of a ternary device according to an embodiment of the present invention.
3 is a diagram schematically illustrating a configuration of a ternary SRAM and a ternary read circuit connected thereto according to an embodiment of the present invention.
4 is a diagram for explaining a method of operating a ternary read circuit according to an embodiment of the present invention.
5 is a diagram for explaining another operation of a ternary read circuit according to an embodiment of the present invention.
6 is a diagram for explaining another operation of a ternary read circuit according to an embodiment of the present invention.
7 is a structural diagram illustrating an example of the configuration of a preamplifier according to an embodiment of the present invention.
8 is a structural diagram illustrating a part of a comparator according to an embodiment of the present invention.
9 is a schematic structural diagram for explaining a rewrite unit according to an embodiment of the present invention.
10 is a graph for explaining a method of operating a rewrite unit according to an embodiment of the present invention.

Since the present invention can apply various transformations and can have various embodiments, specific embodiments are illustrated in the drawings and described in detail in the detailed description. Effects and features of the present invention, and a method of achieving them, will become apparent with reference to the embodiments described below in detail in conjunction with the drawings. However, the present invention is not limited to the embodiments disclosed below and may be implemented in various forms.

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings, and when described with reference to the drawings, the same or corresponding components are given the same reference numerals, and the overlapping description thereof will be omitted. .

In the following embodiments, terms such as first, second, etc. are used for the purpose of distinguishing one component from another, not in a limiting sense. In the following examples, the singular expression includes the plural expression unless the context clearly dictates otherwise. In the following embodiments, terms such as include or have means that the features or components described in the specification are present, and the possibility of adding one or more other features or components is not excluded in advance. In the drawings, the size of the components may be exaggerated or reduced for convenience of description. For example, since the size and shape of each configuration shown in the drawings are arbitrarily indicated for convenience of description, the present invention is not necessarily limited to the illustrated bar.

Hereinafter, a ternary element array according to an embodiment of the present invention will be described with reference to FIGS. 1 and 2 . 1 is a diagram schematically illustrating a ternary SRAM array according to an embodiment of the present invention, and FIG. 2 is a graph showing input/output characteristics of a ternary device according to an embodiment of the present invention.

A ternary SRAM array according to an embodiment of the present invention includes a plurality of signal lines connected to the ternary read circuit unit 1000 , the word line controller 2000 , the ternary read circuit unit 1000 , and the word line controller 2000 . (TL, TLB, WL), and a plurality of SRAM cells 300 connected to the plurality of signal lines (TL, TLB, WL) may be included. Hereinafter, the ternary read circuit unit 1000 may be simply named and described as the read circuit unit 1000 .

The plurality of signal lines TL, TLB, and WL include n pairs of trit lines TL1, ..., TLn; TL, n are natural numbers) and trit bar lines TLB1, ... connected to the read circuit unit 1000 . , TLBn; TLB, n is a natural number) and word lines connected to the word line controller 2000 (W1, W2, ..., Wm; WL, m are natural numbers).

The treatment line TL and the treatment bar line TLB are alternately arranged in the first direction D1, so that the ith treatment line TLi and the ith treatment bar line TLBi (1≤i≤n) are one can be paired Hereinafter, the ith treatment line TLi and the ith treatment bar line TLBi may be bundled and named as a 'treat line pair TLi, TLBi'.

The word lines WL may be arranged in a second direction D2 crossing the first direction D1 . The j-th word line Wj (1≤j≤m) is connected to the treatment line TL and the treatment bar line TLB across the first direction D1 to be turned on or off according to the treatment line TL or It may serve to connect the treatment bar line TLB and the cell 300 connected to the corresponding lines TL and TLB.

The SRAM cells 300 may be connected to the plurality of signal lines TL, TLB, and WL and arranged in a matrix form arranged in each of the first direction D1 and the second direction D2 . The SRAM cell 300 may be a memory that stores ternary data including states of 0, 1, 2 (or 0, 1/2, 1) depending on the signal supplied by the treat line pair TLi, TLBi. have. In this specification, ternary data may be data having any one of a low voltage VL, a high voltage VH, and a middle voltage VM.

For example, the SRAM cell 300 may include six transistors. Referring to FIG. 1 , one SRAM cell 300 includes a first transistor T1 connected to a first treatment line TL1 , a second transistor T2 connected to a first treatment bar line TLB1 , and two transistors. A first inverter TI1 composed of CMOS including (not shown) and a second inverter TI2 composed of CMOS including the remaining two transistors (not shown) may be included.

Here, the SRAM cell 300 according to an embodiment of the present invention will be described in more detail using FIG. 2 together. The inverters TI1 and TI2 of the SRAM cell 300 may include a ternary device capable of processing ternary data.

Referring to FIG. 2 , input/output profiles G1 and G2 of two cases of a semiconductor device are shown. In the case of a binary device, as in profile G1, it shows input/output characteristics of writing and reading binary data of 0 or 1. On the other hand, the ternary device according to an embodiment of the present invention may exhibit input/output characteristics of writing and reading ternary data of 0(P1), 1/2(P2), and 1(P3) like the profile G2. In other words, in the case of the ternary inverters TI1 and TI2, it is possible to store trit information of 0, 1, and 2 per one SRAM cell 300, which has the advantage of having a storage space 1.5 times larger than that of a binary device of the same size. There is this.

An example of an operation of writing data into the SRAM cell 300 will be described. For example, when the word line W1 is turned on, the first and second transistors T1 and T2 may be turned on. Here, it is assumed that one of 0, 1, and 2 data is stored in the first treatment line TL1. If the stored value of the first treatment line TL1 is a high voltage (2 or VDD), the NMOS of the first inverter TI1 is turned on, and the stored value of the first treatment bar line TLB1 is a low voltage (0). or GND), so the PMOS of the second inverter TI2 may be turned on. Thereafter, when the word line W1 is turned off, a high voltage may be stored in an output terminal of the first inverter TI1 and a low voltage may be stored in an output terminal of the second inverter TI2 .

In a typical digital SRAM array, a comparator called a sense amplifier may be used to detect and amplify a difference between a bit line and a bit bar line to read binary data. If the ternary sense amplifier is designed by simply replacing the binary element in the sense amplifier with a ternary element, the middle voltage (VDD/2) data can also be read. However, in the case of pre-charging with the middle voltage, if a high voltage or a low voltage is stored in the SRAM cell 300 , the lines TL and TLB will have slightly higher and lower voltages from the middle voltage, respectively. In response to this voltage input, the ternary sense amplifier converges the voltage of the trit line pair (TLi, TLBi) to the middle voltage, so that information cannot be read properly, and the stored data of the cell 300 can also be changed to the middle voltage. . Even if the precharge voltage is changed, if the parasitic capacitors Cp1 and Cp2 of the treatment line TL and the treatment bar line TLB are much larger than the capacitors Cj1 and Cj2 in the SRAM cell 300 , they converge to the middle voltage or Regardless of the charging voltage, it may emit a high voltage, which may cause an error in data reading.

Accordingly, in the present invention, a ternary read circuit including a preamplifier and a comparator designed as a conventional binary element to read the ternary data stored in the T-SRAM 300 without distortion, and a method for reading ternary data through it would like to provide

The read circuit unit 1000 may include a plurality of read circuits 100-1, 100-2, ..., 100-n; 100 provided for each treatment line pair TLi and TLBi. The plurality of read circuits 100 may operate independently and/or mutually according to an applied clock signal. The read circuit 100 will be described in more detail with reference to FIG. 3 to be described later.

3 is a diagram schematically illustrating a configuration of a ternary SRAM 300 and a ternary read circuit 100 connected thereto according to an embodiment of the present invention. Hereinafter, descriptions of the same contents as those described above may be omitted or simplified.

The SRAM cell 300 may have cell parasitic capacitors Cj1, Cj2; Cj, which are parasitic capacitances, and the treat line TL or the treat bar line TLB may have line parasitic capacitors Cp1, Cp2; Cp. The line parasitic capacitor Cp may have a significantly larger value than the cell parasitic capacitor Cj.

When the treat line TL and the SRAM cell 300 are connected as the word line WL is turned on, the voltage stored in the treat line TL due to the capacitance difference between the cell parasitic capacitor Cj and the line parasitic capacitor Cp Since the change amount of is very small, the data of the treatment line TL can be read quickly and accurately only by amplifying the change amount of the voltage.

Accordingly, an object of the present invention is to be achieved through the read circuit 100 according to an embodiment of the present invention.

The read circuit 100 may include a preamplifier 10 , a comparator 20 , and a rewrite unit 30 .

The preamplifier 10 may amplify the voltage change amount of the cell 300 . The preamplifier 10 may be connected to the treatment line TL through the first node N1 , and the treatment bar line TLB may be connected through the second node N2 . The first and second nodes N1 and N2 may be described as input terminals N1 and N2 of the preamplifier 10 .

A sign displayed inside the preamplifier 10 indicates the direction of amplification. For example, when the initial voltage of the treatment line TL is lower than the initial voltage of the treatment bar line TLB, the preamplifier 10 reduces the initial voltage of the treatment line TL and reduces the initial voltage of the treatment bar line TLB. can increase Conversely, when the initial voltage of the treatment line TL is higher than the initial voltage of the treatment bar line TLB, the preamplifier 10 increases the initial voltage of the treatment line TL and increases the initial voltage of the treatment bar line TLB. can reduce

The preamplifier 10 may output the amplified voltage VA through the output terminals O1 and O2, and the amplified voltage VA is to be applied as an input of the comparator 20 to be described later along with the reference voltage Vr. can The operation and specific structure of the preamplifier 10 will be described in detail with reference to FIGS. 4 to 6 to be described later.

The comparator 20 may output binary data by comparing the amplified voltage VA with the reference voltage Vr. The reference voltage Vr may be input to the comparator 20 together with the above-described amplified voltage VA.

The comparator 20 may include a plurality of comparator pairs 20a and 20b. The amplified voltages VA1 and VA3 of the treatment line TL are input to the first comparator pair 20a, and the amplified voltages VA2 and VA4 of the treatment bar line TLB are input to the second comparator pair 20b. can

Specifically, the treat line TL is connected to one input terminal of one comparator of the first comparator pair 20a, the first reference voltage Vr1 is applied to the other input terminal, and the other of the first comparator pair 20a. A treat line TL may be connected to one input terminal of one comparator, and a second reference voltage Vr2 may be applied to the other input terminal. Similarly, the trip bar line TLB is connected to one input terminal of one of the second comparator pairs 20b, the first reference voltage Vr1 is applied to the other input terminal, and the other of the second comparator pairs 20b. A treat bar line TLB may be connected to one input terminal of one comparator, and a second reference voltage Vr2 may be applied to the other input terminal.

The first comparator pair 20a may output an output value Y1, Y2, and the second comparator pair 20b may output an output value Y3, Y4, and the output values Y1, Y2, Y3, Y4; Y) may be input to the rewrite unit 30 to be described later. The output values Y may be composed of binary data. For example, each of the output values Y may be expressed as a two-digit combination of binary data such as 00, 01, 10, 11, and the like.

The operation and specific structure of the comparator 20 will be described with reference to FIGS. 7 and 8 to be described later.

The rewrite unit (Rewrite Logic) 30 recovers the initial voltage of the treatment line pair (TL, TLB) by selectively operating a plurality of transistors according to the combination of the input output values (Y) to the treatment line pair (TL, TLB) TLB) can be rewritten. Through this, it is possible to prevent data corruption by returning the distorted data back to the original data in the process of reading the ternary data.

Hereinafter, the operation of the preamplifier 10 in the ternary read circuit 1000 according to an embodiment of the present invention will be mainly described with reference to FIGS. 4 and 5 . 4 is a diagram for explaining a method of operating a ternary read circuit according to an embodiment of the present invention, and FIG. 5 is a diagram for explaining another operation of the ternary read circuit according to an embodiment of the present invention.

Referring to FIG. 4 , a change profile of a voltage stored in the SRAM cell 300 according to circuit operation steps D1 , D2 , and D3 of the read circuit 1000 is illustrated. A horizontal axis indicates circuit operation steps D1 , D2 , and D3 of the read circuit 1000 , and a vertical axis indicates voltage levels. Voltage values represented on the vertical axis are a low voltage (VL), a middle voltage (VM), and a high voltage (VH). For example, the low voltage (VL) is the ground voltage (GND), and the high voltage (VH) is the driving voltage. (VDD) and the middle voltage VM may be a half driving voltage VDD/2. In this specification, the low voltage VL may be represented by '0' of binary data, and the high voltage VH may be represented by '1' of binary data.

Step D1 is a 'pre-charge step' of pre-charging a preset charging voltage to the treatment line TL. The line profile L1 represents a voltage profile of the treatment line TL precharged with a specific charging voltage or a line parasitic capacitor Cp1 (refer to FIG. 3 ) parasitic thereto. The specific charging voltage may be, for example, a middle voltage VM.

Meanwhile, data having a specific voltage may be stored in the SRAM cell 300 . The first cell profile S1 indicates a voltage profile of the cell 300 or the first cell parasitic capacitor Cj1 (refer to FIG. 3 ) parasitic thereto when the stored data of the cell 300 is 0 . The first cell parasitic capacitor Cj1 is a parasitic capacitance connected to the first cell node NC1 of the cell 300 . In this case, the initial voltage of the cell 300 may be described as a low voltage VL. The second cell profile S2 represents a voltage profile of the cell 300 or a second cell parasitic capacitor Cj2 (refer to FIG. 3 ) parasitic thereto when the stored data of the cell 300 is zero. The second cell parasitic capacitor Cj2 is a parasitic capacitance connected to the second cell node NC2 of the cell 300 . In this case, the initial voltage of the cell 300 may be described as a high voltage HL.

Step D2 will be described with reference to an enlarged view of part A on the right side of FIG. 4 . Step D2 is an 'amplification step' in which the word line WL is turned on and the cell 300 and the treatment line TL are connected to amplify the changed voltage of the cell 300 . The profile CM of the left graph represents a trigger operation in which the aforementioned cell 300 and the treatment line TL are 'connected'.

Specifically, when the storage voltage of the cell 300 is 0, the first cell profile S1 is the middle voltage VM when the cell 300 is connected to the treatment line TL precharged with the middle voltage VM. ) may be changed to have the first change voltage Vd1 as low as the first change amount dh1. Thereafter, the preamplifier 10 recognizes the first change amount dh1 and decreases the first change voltage Vd1 by the 1-1 change rate h1-1 compared to the first change voltage Vd1 according to a preset reference to thereby increase the first amplification voltage VA1. can create

Similarly, when the storage voltage of the cell 300 is 0, the second cell profile S2 is the middle voltage VM when the cell 300 is connected to the treatment line TL precharged with the middle voltage VM. The second change voltage Vd2 may be changed as high as the first change amount dh1 compared to the first change amount dh1 . Thereafter, the preamplifier 10 recognizes the first change amount dh1 and increases the second change voltage Vd2 by the 1-2 change rate h1-2 compared to the second change voltage Vd2 according to a preset reference to increase the second amplification voltage VA2. can create

In this case, the 1-1 rate of change h1-1 and the 1-2 rate of change h1-2 may be collectively referred to as a first rate of change h1, and the two rates of change h1-1 and h1-2 are mutually exclusive. may be the same.

The preamplifier 10 may generate the amplified voltage VA by decreasing or increasing and amplifying the first change rate h1 by the first change rate h1 when the change amount dh1 is equal to or greater than a predetermined level by preset logic.

Conversely, when the stored data of the cell 300 is 1 (not shown), the first and second cell profiles S1 and S2 are exchanged and the same operating principle may be applied.

In brief, when the storage voltage of the cell 300 is 1, contrary to the case described above, the voltage profile for the treatment bar line TLB in which the above-described first cell profile S1 is connected to the second cell node N2 . , and the second cell profile S2 may be applied as indicating a voltage profile for the treatment line TL connected to the first cell node N1 .

Thereafter, step D3 is a 'convergence' step in which the amplified voltage VA converges back to the middle voltage VM, which is the charging voltage. When the storage voltage of the cell 300 is 0 or 1, when the cell 300 storage data is read in step D2 and converges to the middle voltage VM, data distortion may occur. In order to prevent this, data distorted by the middle voltage VM may be returned back to the low voltage VL or high voltage VH through the rewrite unit 30 to be described later to be rewritten into the cell 300 . .

In summary, when the initial storage voltage of the cell 300 is 0, the first cell profile S1 has a low voltage VL value, is changed to the first change voltage Vd1 in step D2, and thereafter the free It may be amplified by the 1-1 th change rate h1-1 by the amplifier 10 to have the first amplified voltage VA1. Thereafter, it may converge to the initial charge value (middle voltage VM) again in step D3. Conversely, the second cell profile S2 has a high voltage VH value, is changed to the second change voltage Vd2 in step D2, and thereafter by the preamplifier 10, the 1-2 first change rate h1- 2) may be amplified to have the second amplified voltage VA2. Thereafter, it may converge to the initial charge value (middle voltage VM) again in step D3.

Next, referring to FIG. 5 , the treatment line TL or a parasitic line capacitor Cp1 parasitic thereto (see FIG. 3 ) is a specific charging voltage (middle voltage VM in FIG. 5 ) like the line profile L1 as in FIG. 4 . ) may be pre-charged.

Meanwhile, in FIG. 5 , unlike FIG. 4 , the storage data of the cell 300 is 1/2 instead of 0 and 1. In this case, both the first cell profile S1 and the second cell profile S2 may have the same middle voltage VM value as the charging voltage of the treat line VL in step D1.

Step D2 will be described with reference to an enlarged view of portion A' on the right side of FIG. 5 .

When the cell 300 and the treatment line TL are connected by the trigger CM operation, the first cell profile S1 has a third change voltage Vd3 as low as the second change amount dh2 compared to the middle voltage VM. may be subject to change. Thereafter, the preamplifier 10 recognizes the second change amount dh2 and reduces the third change voltage Vd3 by the 2-1 change rate h2-1 compared to the third change voltage Vd3 according to a preset reference to thereby increase the third amplification voltage VA3. can create

Similarly, the second cell profile S2 may be changed to have the fourth change voltage Vd4 as high as the second change amount dh2 compared to the middle voltage VM. Thereafter, the preamplifier 10 recognizes the second change amount dh2 and increases it by a 2-2 change rate h2-2 compared to the fourth change voltage Vd4 according to a preset reference to thereby increase the fourth amplification voltage VA4. can create

In this case, the 2-1 change rate h2-1 and the 2-2 change rate h2-2 may be collectively referred to as a second rate of change h2, and the two rates of change h2-1 and h2-2 are mutually exclusive. may be the same. In addition, since the first rate of change h1 and the second rate of change h2 are proportional to the first rate of change dh1 and the second rate of change dh2, respectively, the second rate of change h2 may be smaller than the above-described first rate of change h1. can That is, when the stored data of the cell 300 is 1/2, the degree of amplification of the change voltage Vd may be smaller than when the stored data is 0 or 1.

Thereafter, in step D3, after reading the data stored in the cell 300 in step D2, both cell profiles S1 and S2 converge to the middle voltage VM, and the array according to an embodiment of the present invention uses a ternary device. Therefore, the middle voltage (VM) converging to the value of the original data, that is, 1/2, can be read without distortion of data without rewriting.

In summary, when the initial storage voltage of the cell 300 is 1/2, the first and second cell profiles S1 and S2 have a middle voltage (VM) value in the D1 step, and then in the D2 step EH 4 It may be changed to the change voltages Vd3 and Vd4 with a smaller width than the embodiment, and then amplified by the second rate of change h2 by the preamplifier 10 to have the amplified voltages VA3 and VA4. Thereafter, it may converge to the initial charge value (middle voltage VM) again in step D3.

Hereinafter, the operation of the read circuit according to an embodiment of the present invention will be described with the addition of a function of the comparator 20 with reference to FIG. 6 . 6 is a diagram for explaining another operation of a ternary read circuit according to an embodiment of the present invention, and is a graph illustrating voltage profiles according to time on a horizontal axis. Hereinafter, it will be described with reference to FIG. 3 together.

Referring to FIG. 6 , the amplified voltage VA and reference voltages Vr1 and Vr2; Vr generated by the preamplifier 10 are shown. The first reference voltage Vr1 may be higher than the first charging voltage VM by a preset width, and the second reference voltage Vr2 may be lower than the first charging voltage VM by the width. For example, the reference voltage Vr may be a value spaced apart by a predetermined voltage Vx based on the initial charging voltage (middle voltage VM in FIG. 6 ) of the treatment line TL.

The comparator 20 may include a plurality of comparators, and any one of the amplified voltages VA is inputted to one input terminal of each comparator and any one of the reference voltages Vr is input to the other input terminal to obtain both voltages. can be compared.

For example, a case in which the stored data of the cell 300 is 0 (VA1, VA2) will be described first. Of the first comparator pair 20a, the first amplified voltage VA1 and the first reference voltage Vr1 are input to one comparator, and the first amplified voltage VA1 and the second reference voltage Vr2 are input to the other comparator. Thus, the first and second output values Y1 and Y2 indicating the magnitude relationship of the first amplified voltage VA1 with respect to each of the reference voltages Vr1 and Vr2 may be output through the first comparator pair 20a.

Similarly, the second amplified voltage VA2 and the first reference voltage Vr1 are input to one of the second comparator pairs 20b, and the second amplified voltage VA2 and the second reference voltage Vr2 are input to the other comparator. This is input, and the third and fourth output values Y3 and Y4 indicating the magnitude relationship of the second amplified voltage VA2 with respect to the respective reference voltages Vr1 and Vr2 may be output through the second comparator pair 20b. have.

At this time, the first amplified voltage VA1 is reduced and amplified by a 1-1 gain g1-1 compared to the initial charging voltage VM, and the second amplified voltage VA2 is a 1-th amplified voltage compared to the initial charging voltage VM. It may be a voltage amplified by an increase of 2 gains (g1-2). The first gains g1-1, g1-2; g1 are defined as a value obtained by multiplying the first change amount dh1 described above with reference to FIG. 3 by the first change rate h1.

Similarly, the case where the stored data of the cell 300 is 1/2 (VA3, VA4) will be described. Of the first comparator pair 20a, the third amplified voltage VA3 and the first reference voltage Vr1 are input to one comparator, and the third amplified voltage VA3 and the second reference voltage Vr2 are input to the other comparator. Thus, first and second output values Y1 and Y2 indicating the magnitude relationship of the third amplified voltage VA3 with respect to each of the reference voltages Vr1 and Vr2 may be output through the first comparator pair 20a.

Of the second comparator pair 20b, the fourth amplified voltage VA4 and the first reference voltage Vr1 are input to one comparator, and the fourth amplified voltage VA4 and the second reference voltage Vr2 are input to the other comparator. Thus, the third and fourth output values Y3 and Y4 indicating the magnitude relationship of the fourth amplified voltage VA4 with respect to each of the reference voltages Vr1 and Vr2 may be output through the second comparator pair 20b.

At this time, the third amplified voltage VA3 is reduced and amplified by the 2-1 gain g2-1 compared to the initial charging voltage VM, and the fourth amplified voltage VA4 is the second-second amplified voltage compared to the initial charging voltage VM. It may be a voltage amplified by increasing the gain by 2 (g2-2). The second gain g2-1, g2-2; g2 is defined as a value obtained by multiplying the second change amount dh2 described above with reference to FIG. 4 by the second change rate h2.

[Table 1] below together, in Example 1, when the stored data of the cell 300 is 0 (FIG. 4), in Example 2, when 1/2 (FIG. 5), and in Example 3, 1 case (inverse case of FIG. 4 ) is shown.

Y1 Y2 Y3 Y4 trit data Example 1 VL VL VH VH VL(0) Example 2 VL VH VL VH VM(1/2) Example 3 VH VH VL VL VH(1)

In the case of Example 1, the first and second amplified voltages VA1 and VA2 are shown as shown in FIG. 6 . Since both of the first amplified voltages VA1 have lower values compared to the two reference voltages Vr1 and Vr2, VLs are outputted from both the first and second output values Y1 and Y2. On the other hand, since the second amplified voltage VA2 has a higher value compared to the two reference voltages Vr1 and Vr2, VH is outputted to all of the third and fourth output values Y3 and Y4.

In the case of Example 2, the third and fourth amplified voltages VA3 and VA4 are shown as shown in FIG. 6 . Since the third amplified voltage VA3 has a lower value than the first reference voltage Vr1, the first output value Y1 has a higher value than VL and the second reference voltage Vr2, so the second output value Y2 is VH may be output. Similarly, since the fourth amplified voltage VA4 also has a lower value than the first reference voltage Vr1, the third output value Y3 has a higher value than VL and the second reference voltage Vr2, so the fourth output value Y4 ), VH may be output. In Example 2, on the contrary, the first and third output values Y1 and Y3 are VH, and the second and fourth output values Y2 and Y4 are VL output, so that the first output value Y1 and the second output value Y2 are outputted. , and a case in which the third output value Y3 and the fourth output value Y4 are alternately output may be included.

Example 3 is opposite to Example 1, and the first and second amplification voltages VA1 and VA2 are opposite to those of FIG. 6 . Then, since the first amplified voltage VA1 will have a higher value compared to the two reference voltages Vr1 and Vr2, VH is outputted to both the first and second output values Y1 and Y2. On the other hand, since both of the second amplified voltages VA2 will have lower values compared to the two reference voltages Vr1 and Vr2, VLs are outputted from all of the third and fourth output values Y3 and Y4.

In summary, the ternary read circuit 1000 according to an embodiment of the present invention precharges both the treatment line TL and the treatment bar line TLB to a specific voltage (eg, VM), and the cell 300 The ternary data may be read by amplifying the change voltage Vd, which is changed when it is connected to the lines TL and TLB, and comparing the amplified voltage VA with the reference voltage Vr in binary format.

As described above, according to the read circuit 1000 according to an embodiment of the present invention, ternary data can be read by converting ternary data into binary data using the arrangement of the existing binary elements through the design of the preamplifier and comparator. and, accordingly, it can be easily replaced with a low-power, high-capacity ternary semiconductor device.

7 is a structural diagram illustrating an example of the configuration of the preamplifier 10 according to an embodiment of the present invention.

The preamplifier 10 may operate in two stages: a first stage (Gain stage) ST1 as shown in FIG. 7(a) and a second stage (Reset stage) ST2 as shown in FIG. 7(b). First, the switches present at both ends of the second stage ST2 connect the input terminals N1 and N2 and the output terminals O1 and O2 of the preamplifier 10 to connect the input terminals N1 and N2 as well as the output terminals O1, O1, O2) may serve to pre-charging all of the middle voltage (VM). In this case, the input terminal N1 may be a node to which the treatment line TL is connected, and the input terminal N2 may be a node to which the treatment bar line TLB is connected. When the first stage ST1 operates in a state in which the output terminals O1 and O2 are charged with different voltages, when comparing the amplified voltage VA amplified through the first stage ST1 and the reference voltage Vr In order to prevent an error from occurring, the output terminals O1 and O2 of the preamplifier 10 may be equally charged with the middle voltage VM.

As described above, the second stage ST2 drives and/or precharges the voltages of the lines TL and TLB to the middle voltage VM, and the switch is disabled according to the applied clock signal clk. Then, the first stage ST1 to be described later may be activated and operated.

The word line WL is selected according to the clock signal clk to select the SRAM cell 300 . Then, in the first stage ST1, the precharged voltage applied to the input terminals N1 and N2 is connected to the cell 300 to detect the change amounts dh1 and dh2 of the changed changed voltage Vd, and the output terminal O1 , O2) may output the amplified voltage VA branched vertically from the precharged middle voltage VM.

At this time, the control transistors BT1 and BT2 of the first stage ST1 will be described with reference to FIG. 6 together. The control transistors BT1 and BT2 have a gain g2-1 and a second amplification when the first amplified voltage VA1 is reduced and amplified from the middle voltage VM through the biases bias1 and bias2 applied to each. The gain g2-2 when the voltage VA2 is increased and amplified from the middle voltage VM may be adjusted in the same manner. For example, if the two gains g2-1 and g2-2 are different so that the fall width of the first amplified voltage VA1 is relatively larger than the rise width of the second amplified voltage VA2, the output value of the comparator 20 is This is because there may be a problem in determining the data to be read through (Y).

The circuit structure of the preamplifier 10 according to an embodiment of the present invention is not limited to that shown in FIG. 7 , and various structures capable of performing functions for achieving the object of the present invention may be applied.

8 is a structural diagram illustrating a part of a comparator according to an embodiment of the present invention.

The single comparator of FIG. 8 may operate according to the applied clock signal clk, and may receive the amplified voltage VA and the reference voltage Vr of the preamplifier 10 through the two input terminals NN1 and NN2. have. The amplification voltage VA of the treat line TL is applied through the input terminal NN1 and the reference voltage Vr is applied through the input terminal NN2, and the magnitude relationship between the positive voltages VA1 and Vr1 through the indicated Y node. An output value (Y) with which A is compared may be output.

As described above, the ternary read circuit 100 according to an embodiment of the present invention may read the ternary data stored in the cell 300 using binary data output through the comparator 20 . Accordingly, a function of a ternary to binary converter (TBC) capable of communicating with an external device in the digital domain may be accompanied.

For example, the comparator 20 may be a dynamic latch comparator selectively operated only when necessary, but the structure of the comparator is not limited to that shown in FIG. 8 .

Hereinafter, an operation of the rewrite unit 30 according to an exemplary embodiment will be described with reference to FIGS. 9 and 10 . 9 is a schematic structural diagram for explaining the rewrite unit 30 according to an embodiment of the present invention, and FIG. 10 is a graph for explaining an operation method of the rewrite unit according to an embodiment of the present invention.

Referring to FIG. 9 together with FIG. 3 , the rewrite unit 30 may receive output values Y from the comparator 20 . The ternary data stored in the cell 300 can be read by the combination of the output values Y. As shown in the convergence step D3 of FIG. 4 , when the data stored in the cell 300 is 0 or 1, the read circuit ( 100) may erroneously converge to 1/2, resulting in data distortion. To prevent this, the changed data may be restored through the rewrite unit 30 and the transistors M1 , M2 , M3 and M4 connected thereto to rewrite the data into the lines TL and TLB. The output terminals of M1 and M2 are connected to the treatment line TL, and the output terminals of M3 and M4 are connected to the treatment bar line TLB, so that the restored data can be rewritten in the respective lines TL and TLB.

Hereinafter, with reference to [Table 1] described with reference to FIG. 6 will be described. When the first and second amplified voltages VA1 and VA2 appear as shown in FIG. 10(a) (Example 1), M1 and M4 are turned on, and the first and second amplified voltages VA1 and VA2 are shown in FIG. 10 ( In the case of the opposite of a) (Example 3), M2 and M3 may be turned on. In the case of Examples 1 and 3, since the amplified voltage VA is not large enough to diverge to the high voltage VH or the low voltage VL, the amplified gains g1 and g2 are converted to the middle voltage VM in step D3. can converge. Accordingly, the rewrite unit 30 operates as described above to restore the original data by making the data of the treatment line TL and the treatment bar line TLB equal to the original data (0 or 1).

On the other hand, when the third and fourth amplified voltages VA3 and VA4 appear as shown in Fig. 10(b) (Example 2) (the output values of Y1 and Y2 are opposite, the output values of Y3 and Y4 are output oppositely), Since M1, M2, M3, and M4 are all turned off, the rewrite unit 30 may not operate. When the data stored in the cell 300 is 1/2, data distortion does not occur, so the middle voltage VM is maintained even if the treatment line TL and the treatment bar line TLB are not adjusted. may not change.

In addition, although preferred embodiments of the present invention have been illustrated and described above, the present invention is not limited to the specific embodiments described above, and the technical field to which the present invention pertains without departing from the gist of the present invention as claimed in the claims In addition, various modifications are possible by those of ordinary skill in the art, and these modifications should not be individually understood from the technical spirit or perspective of the present invention.

Therefore, the spirit of the present invention should not be limited to the above-described embodiments, and not only the claims described below, but also all scopes equivalent to or changed from the claims described below are the scope of the spirit of the present invention. would be said to belong to the category.

1000: ternary read circuit unit
2000: word line control
100: ternary read circuit
300: SRAM cell
10: Preamplifier
20: comparison unit
30: rewrite part
TL: treatment line
TLB: Treat Bar Line
WL: word line
Cj1, Cj2: cell parasitic capacitors
Cp1, Cp2: line parasitic capacitors
S1: first cell profile
S2: second cell profile
L1: line profile
VA: amplified voltage
Vd: change voltage
Vr: reference voltage

Claims (12)

A ternary read circuit for reading ternary data stored in an SRAM cell using a signal applied through a treat line, the ternary read circuit comprising:
a preamplifier configured to amplify a change voltage of the SRAM cell by a preset change rate when the SRAM cell is connected to the treat line to generate an amplified voltage; and
a comparator for reading the ternary data by outputting binary data by comparing the magnitude between the amplified voltage and the reference voltage;
Including, ternary read circuit. According to claim 1,
The pre-amplifier pre-charging the treat line to a first charging voltage, a ternary read circuit. 3. The method of claim 2,
The ternary read circuit includes a plurality of comparators including a first comparator and a second comparator,
the reference voltage includes a first reference voltage and a second reference voltage having a lower value than the first reference voltage;
the first comparator compares the amplified voltage with the first reference voltage to output first high voltage data or first low voltage data;
and the second comparator compares the amplified voltage with the second reference voltage to output second high voltage data or second low voltage data. 4. The method of claim 3,
When high voltage data or low voltage data is stored in the SRAM cell,
The first comparator and the second comparator both output high voltage data or both output low voltage data. 4. The method of claim 3,
When middle voltage data is stored in the SRAM cell,
the first comparator outputs the first high voltage data and the second comparator outputs the second low voltage data;
The first comparator outputs the first low voltage data, and the second comparator outputs the second high voltage data. 4. The method of claim 3,
The ternary read circuit is
The ternary read circuit further comprising a rewrite unit for restoring the existing data corresponding to the output value of the treatment line according to the output value of the comparator. A method of reading ternary data stored in an SRAM cell using a signal applied through a treat line, the method comprising:
storing any one data selected from high voltage data, low voltage data, and middle voltage data in the SRAM cell;
generating an amplified voltage by amplifying a change voltage of the treatment line when the treatment line is connected to the SRAM cell by a preset change rate; and
reading the ternary data by outputting binary data by comparing the magnitude between the amplified voltage and the reference voltage;
A method of reading ternary data, including 8. The method of claim 7,
Before generating the amplified voltage,
Pre-charging the treatment line to a first charging voltage; further comprising, a method of reading ternary data. 9. The method of claim 8,
the reference voltage includes a first reference voltage and a second reference voltage having a lower value than the first reference voltage;
The step of comparing and outputting binary data comprises:
a first comparison step of comparing the amplified voltage with the first reference voltage and outputting first high voltage data or first low voltage data; and
and a second comparison step of outputting second high voltage data or second low voltage data by comparing the amplified voltage with the second reference voltage. 10. The method of claim 9,
The step of comparing and outputting binary data comprises:
When the high voltage data or the low voltage data is stored in the SRAM cell,
A method of reading ternary data, characterized in that both high voltage data or low voltage data are output in both of the first comparison step and the second comparison step. 10. The method of claim 9,
The step of comparing and outputting binary data comprises:
When the middle voltage data is stored in the SRAM cell,
outputting the first high voltage data in the first comparing step and outputting the second low voltage data in the second comparing step;
and outputting the first low voltage data in the first comparison step and outputting the second high voltage data in the second comparison step. 10. The method of claim 9,
How to read the ternary data,
Restoring and rewriting the existing data corresponding to the output value of the treatment line according to the output values of the first comparison step and the second comparison step;

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