KR102290469B1 - Flip-flop including 3-state inverter - Google Patents

Abstract

The present invention relates to flip-flops. The flip-flop of the present invention includes an input unit for receiving a signal and outputting the received signal in synchronization with a clock, a first inverter and a second inverter, and a first latch for storing a signal output from the input unit in synchronization with the clock , a third inverter for outputting the signal stored in the master latch in synchronization with the clock, and a fourth inverter and a fifth inverter, and a second latch for storing the signal output from the third inverter in synchronization with the clock. The third inverter and the fifth inverter include first transistors of a first type formed between a first power contact and a second power contact to which a power supply voltage is supplied on fins of the first type, and fins of a second type and second type second transistors formed between the first ground contact and the second ground contact to which the ground voltage is supplied.

Description

FLIP-FLOP INCLUDING 3-STATE INVERTER with 3-phase inverter

The present invention relates to a semiconductor circuit, and more particularly, to a flip-flop including an inverter.

A flip-flop is a semiconductor device that is generally used in various semiconductor circuits. As the miniaturization of the semiconductor process progresses, the size of the flip-flop has also decreased. As a Fin-FET-based semiconductor process is developed, it is being manufactured as a Fin-FET of semiconductor circuits. Therefore, flip-flops are also being manufactured as pin-pets. As flip-flops are manufactured as fin-pets, design restrictions due to unique process characteristics of fin-pets occur, which deteriorates characteristics of flip-flops and reduces yield.

An object of the present invention is to provide a fin-pet-based flip-flop in which deterioration of properties and reduction in yield are prevented. Another object of the present invention is to provide a flip-flop having improved layout efficiency.

A flip-flop according to an embodiment of the present invention includes an input unit that receives a signal and outputs the received signal in synchronization with a clock, a first inverter, and a second inverter, and receives a signal output from the input unit. a first latch for storing in synchronization with a clock, a third inverter for outputting a signal stored in the master latch in synchronization with the clock, and a fourth inverter and a fifth inverter, wherein the signal output from the third inverter is synchronized with the clock and a second latch for storing. The third inverter and the fifth inverter include first transistors of a first type formed between a first power contact and a second power contact to which a power supply voltage is supplied on fins of the first type, and fins of a second type and second type second transistors formed between the first ground contact and the second ground contact to which the ground voltage is supplied.

A flip-flop according to another embodiment of the present invention includes an input unit that receives a signal and outputs the received signal in synchronization with a clock, a first inverter, and a second inverter, and synchronizes a signal output from the input unit to the clock a first latch for storing; a third inverter for outputting a signal stored in the master latch in synchronization with the clock; a fourth inverter; and a fifth inverter. and a second latch for storing the signal output from the third inverter in synchronization with the clock, and a sixth inverter for inverting and outputting a signal between the third inverter and the second latch. The third inverter and the fifth inverter include first transistors of a first type formed between a first power contact and a second power contact to which a power supply voltage is supplied on fins of the first type, and fins of a second type and second type second transistors formed between the first ground contact and the second ground contact to which the ground voltage is supplied. A power supply voltage of at least one of the first power contact and the second power contact and a ground voltage of at least one of the first ground contact and the second ground contact are shared with one of the fourth inverter and the sixth inverter.

A flip-flop according to another embodiment of the present invention includes an input unit that receives a signal and outputs the received signal in synchronization with a clock, a first inverter, and a second inverter, and synchronizes a signal output from the input unit to the clock a first latch to be stored and stored, a third inverter to output a signal stored in the master latch in synchronization with the clock, a fourth inverter, and a fifth inverter to store a signal output from the third inverter in synchronization with the clock a latch, and a sixth inverter that inverts and outputs a signal between the third inverter and the second latch. The third inverter includes first and second PMOS transistors and first and second PMOS transistors. The fifth inverter includes third and fourth PMOS transistors and third and fourth PMOS transistors. First to fourth PMOS transistors are disposed between the first power contact and the second power contact to which the power voltage is supplied on the first type of fins. First to fourth NMOS transistors are disposed between the first ground contact and the second ground contact to which a ground voltage is supplied on the second type pins.

According to the present invention, a three-phase inverter is arranged between the master latch and the slave latch of a flip-flop. Since a taper is eliminated in the layout of the flip-flop, a flip-flop is provided that prevents deterioration of properties and a decrease in yield. A three-phase inverter is placed between the two power contacts and ground contacts with one inverter of the slave latch. Since the power contacts and ground contacts can be shared with other devices, a flip-flop with improved layout efficiency is provided.

1 is a circuit diagram showing a flip-flop according to an embodiment of the present invention.
FIG. 2 shows an example of a clock generator that supplies first and second clock signals to the flip-flop of FIG. 1 .
3 shows an example of a layout in which the third inverter and the fifth inverter are implemented as pin-pets.
FIG. 4 shows an example in which the fourth inverter shares the power supply voltage and the ground voltage of the third and fifth inverters of FIG. 3 .
5 shows an application example in which the third and fifth inverters are disposed.
FIG. 6 shows an example in which the power supply voltage and the ground voltage of the third and fifth inverters of FIG. 5 are shared.
7 shows an application example of the third and fifth inverters of FIG. 5 .
FIG. 8 shows an example in which the power supply voltage and the ground voltage of the third and fifth inverters of FIG. 7 are shared.
FIG. 9 shows an application example of the flip-flop of FIG. 1 .
FIG. 10 shows an application example of the flip-flop of FIG. 9 .
11 shows an example in which the fourth inverter of FIG. 10 shares a power supply voltage and a ground voltage with third and fifth inverters.
12 shows an application example in which the third to fifth inverters of FIG. 11 are disposed.
13 shows another application example in which the third to fifth inverters of FIG. 11 are disposed.
14 shows another application example of the flip-flop of FIG. 9 .
15 shows an example in which the fourth inverter of FIG. 14 shares a power supply voltage and a ground voltage with third and fifth inverters.
16 shows an application example in which the third to fifth inverters of FIG. 15 are disposed.
17 shows another application example in which the third to fifth inverters of FIG. 15 are disposed.

Hereinafter, embodiments of the present invention will be described clearly and in detail to the extent that those skilled in the art can easily practice the present invention.

1 is a circuit diagram showing a flip-flop 100 (Flip-Flop) according to an embodiment of the present invention. Referring to FIG. 1 , the flip-flop 100 includes an input unit 110 , a first inverter 130 , a second inverter 140 , a third inverter 150 , a fourth inverter 160 , and a fifth inverter ( 170 ), and a sixth inverter 180 .

The input unit 110 includes first to tenth input transistors 111 to 120 . The first and second input transistors 111 and 112 are connected in series between a power node to which the power voltage VDD is supplied and the fifth input transistor 115 . The first and second input transistors 111 and 112 may be P-type transistors. The input signal D may be transmitted to the gate of the first input transistor 111 and the scan enable signal SE may be transmitted to the gate of the second input transistor 112 .

)가 전달될 수 있다.The third and fourth input transistors 113 and 114 are connected in series between the power node and the fifth input transistor 115 . The third and fourth input transistors 113 and 114 may be connected in parallel with the first and second input transistors 111 and 112 between the fifth input transistor 115 and power nodes. The third and fourth input transistors 113 and 114 may be P-type transistors. The scan input signal SI is transmitted to the gate of the third input transistor 113 , and the scan enable inversion signal SI is transmitted to the gate of the fourth input transistor 114 .

) can be transmitted.

The fifth and sixth input transistors 115 and 116 are connected in series between the second and fourth input transistors 112 and 114 and the seventh and ninth input transistors 117 and 119 . The fifth input transistor 115 may be a P-type transistor. The sixth input transistor 116 may be an N-type transistor. The second clock signal b may be transmitted to the gate of the fifth input transistor 115 , and the first clock signal n may be transmitted to the gate of the sixth input transistor 116 .

)가 전달되고, 제8 입력 트랜지스터(118)의 게이트에 입력 신호(D)가 전달될 수 있다.The seventh and eighth input transistors 117 and 118 are connected in series between a ground node to which the ground voltage VSS is supplied and the sixth input transistor 116 . The seventh and eighth input transistors 117 and 118 may be N-type transistors. A scan enable inversion signal (

) may be transferred, and the input signal D may be transferred to the gate of the eighth input transistor 118 .

The ninth and tenth input transistors 119 and 120 are connected in series between the ground node and the sixth input transistor 116 . The ninth and tenth input transistors 119 and 120 may be connected in parallel with the sixth input transistor 116 and the seventh and eighth input transistors 117 and 118 between ground nodes. The ninth and tenth input transistors 119 and 120 may be N-type transistors. The scan enable signal SE may be transmitted to the gate of the ninth input transistor 119 , and the scan input signal SI may be transmitted to the gate of the tenth input transistor 120 .

A node between the fifth and sixth input transistors 115 and 116 may be an output of the input unit 110 . An output of the input unit 110 is connected to an input of the first inverter 130 and an output of the second inverter 140 .

The input unit 110 may operate in a first mode and a second mode. In the first mode, the scan enable signal SE may be inactive. For example, the scan enable signal SE may have a ground voltage VSS or a voltage lower than that. At this time, the second and seventh input transistors 112 and 117 are turned on, and the fourth and ninth input transistors 114 and 119 are turned off. The input unit 110 may block the scan input signal SI and output the input signal D to the first inverter 130 in synchronization with the first and second clock signals n and b.

In the second mode, the scan enable signal SE may be activated. For example, the scan enable signal SE may be the power supply voltage VSS or a positive voltage having a level similar thereto. At this time, the second and seventh input transistors 112 and 117 are turned off, and the fourth and ninth input transistors 114 and 119 are turned on. The input unit 110 may block the input signal D and output the scan input signal SI to the first inverter 130 in synchronization with the first and second clock signals n and b.

For example, the scan input signal SI may be used for a special purpose such as a scan test. The input signal D may be used for the original design purpose of the semiconductor circuit including the flip-flop 100 .

The first inverter 130 inverts the output signal of the input unit 110 and transmits the inverted signal to the second inverter 140 and the third inverter 150 . The first inverter 130 includes a first_1 transistor 131 and a first_2 transistor 132 . The first_1 and first_2 transistors 131 and 132 are connected in series between a power node and a ground node. Gates of the first and second transistors 131 and 132 are connected to an output of the input unit 110 and an output of the second inverter 140 . A node between the first and second transistors 131 and 132 may be an output of the first inverter 130 . An output of the first inverter 130 is connected to inputs of the second inverter 140 and the third inverter 150 .

The second inverter 130 inverts the output signal of the first inverter 130 and transmits it to the first inverter 130 . The second inverter 140 includes second_1 to second_4 transistors 141 to 144 . The second_1 to second_4 transistors 141 to 144 may be connected in series between a power node and a ground node. The output signal of the first inverter 130 is transmitted to the gates of the second_1 and second_4 transistors 141 and 144 . The first clock signal n is transmitted to the gate of the second_2 transistor 142 . The second clock signal b is transmitted to the gate of the second_3 transistor 143 . The second inverter 140 may be a three-phase inverter operating in synchronization with the first and second clock signals n and b. A node between the 2_2 and 2_3 transistors 142 and 143 may be an output of the second inverter 140 . The output of the second inverter 140 is connected to the input of the first inverter 130 .

The first and second inverters 130 and 140 may form a master latch of the flip-flop 100 .

The third inverter 150 inverts the output signal of the first inverter 130 and transmits it to the fourth inverter 160 . The third inverter 150 includes 3_1 to 3_4 transistors 151 to 154 . The 3_1 to 3_4 transistors 151 to 154 may be connected in series between a power node and a ground node. The output signal of the first inverter 130 is transmitted to the gates of the 3_1 and 3_4 transistors 151 and 154 . The first clock signal n is transmitted to the gate of the 3_2 transistor 152 . The second clock signal b is transmitted to the gate of the 3_3 transistor 153 . The third inverter 150 may be a three-phase inverter operating in synchronization with the first and second clock signals n and b. A node between the 3_2 and 3_3 transistors 152 and 153 may be an output of the third inverter 150 . The output of the third inverter 150 is connected to the input of the fourth inverter 160 .

The fourth inverter 160 inverts the output signal of the third inverter 150 and transmits it to the fifth inverter 170 and the sixth inverter 180 . The fourth inverter 160 includes a 4_1 transistor 161 and a 4_2 transistor 162 . The 4_1 and 4_2 transistors 161 and 162 are connected in series between the power node and the ground node. Gates of the 4_1 and 4_2 transistors 161 and 162 are connected to the output of the third inverter 150 and the output of the fifth inverter 170 . A node between the 4_1 and 4_2 transistors 161 and 162 may be an output of the fourth inverter 160 . An output of the fourth inverter 160 is connected to inputs of the fifth inverter 170 and the sixth inverter 180 .

The fifth inverter 170 inverts the output signal of the fourth inverter 160 and transmits the inverted signal to the input of the fourth inverter 160 . The fifth inverter 170 includes 5_1 to 5_4 transistors 171 to 174 . The 5_1 to 5_4 transistors 171 to 174 may be connected in series between the power node and the ground node. The output signal of the fourth inverter 160 is transmitted to the gates of the 5_1 and 5_4 transistors 171 and 174 . The second clock signal b is transmitted to the gate of the 5_2 transistor 172 . The first clock signal n is transmitted to the gate of the 5_3 transistor 173 . The fifth inverter 170 may be a three-phase inverter operating in synchronization with the first and second clock signals n and b. A node between the 5_2 and 5_3 transistors 172 and 173 may be an output of the fifth inverter 170 . The output of the fifth inverter 170 is connected to the input of the fourth inverter 160 .

The fourth and fifth inverters 160 and 170 may form a slave latch of the flip-flop 100 .

The sixth inverter 180 may invert the output signal of the third inverter 150 to output the output signal q. The sixth inverter 180 includes a 6_1 th transistor 181 and a 6_2 th transistor 182 . The 6_1 and 6_2 transistors 181 and 182 are connected in series between the power node and the ground node. Gates of the 6_1 and 6_2 transistors 181 and 182 are connected to the output of the third inverter 150 and the output of the fifth inverter 170 . A node between the 6_1 and 6_2 transistors 181 and 182 may be an output of the sixth inverter 180 .

According to an embodiment of the present invention, signal transfer between the master latch including the first and second inverters 130 and 140 and the slave latch including the fourth and fifth inverters 160 and 170 is the third This is performed by the inverter 150 .

Typically, in order to reduce the number of transistors, signal transfer between a master latch and a slave latch of a flip-flop is performed by a transfer gate that is synchronized with clock signals. At this time, in order to prevent an error in which the signal of the master latch is changed by the signal of the slave latch (that is, reverse flow of the signal), the first_1 and first_2 transistors 131 and 132 of the first inverter 130 of the master latch A sizing technique in which the size of is larger than the size of the 5_1 to 5_4 transistors 171 to 174 of the fifth inverter 170 of the slave latch may be used. However, in the fin-FET process, the sizing technique causes the number of fins used in the transistors to vary, thus causing a taper. The taper is a cause of deteriorating the characteristics of the flip-flop and lowering the yield.

In order to prevent such a problem, the flip-flop 100 according to the embodiment of the present invention uses the third inverter 150 to transfer a signal between the master latch and the slave latch. Accordingly, the reverse flow of the signal is prevented. In addition, since there is no need to use a sizing technique, taper is prevented.

The flip-flop 100 according to an embodiment of the present invention provides a layout that increases the layout efficiency of the flip-flop 100 including the third inverter 150 . Accordingly, even if the number of transistors is increased by the third inverter 150 , the overall size of the flip-flop 100 is prevented from increasing.

FIG. 2 shows an example of a clock generator 190 that supplies first and second clock signals n and b to the flip-flop 100 of FIG. 1 . Referring to FIG. 2 , the clock generator 190 includes first to fourth transistors 191 to 194 . The first and second transistors 191 and 192 are connected in series between a power node and a ground node. The third and fourth transistors 193 and 194 are connected in series between the power node and the ground node. The first and third transistors 191 and 193 may be P-type transistors, and the second and fourth transistors 192 and 194 may be N-type transistors.

The first and second transistors 191 and 192 may form an inverter. The first and second transistors 191 and 192 may invert the clock signal CLK to output the first clock signal n. The clock signal CLK may be a clock signal used in a semiconductor circuit including the flip-flop 100 . The third and fourth transistors 193 and 194 may form an inverter. The third and fourth transistors 193 and 194 may invert the first clock signal n to output the second clock signal b.

3 shows an example of a layout in which the third inverter 150 and the fifth inverter 170 are implemented as pin-pets. 1 and 3 , third and fifth inverters 150 and 170 may be formed in the first to fourth fins FIN1 to FIN4 . The first to fourth fins FIN1 to FIN4 may be disposed parallel to each other. The first and second fins FIN1 and FIN2 may form a P-type first active region R1 . The third and fourth fins FIN3 and FIN4 may form an N-type second active region R2 .

First to sixth gate patterns GP1 to GP6 may be disposed on the first to fourth fins FIN1 to FIN4 . The first to sixth gate patterns GP1 to GP6 may be disposed parallel to each other. The first to sixth gate patterns GP1 to GP6 may be disposed perpendicular to the first to fourth fins FIN1 to FIN4 .

A first power contact PC1 may be provided between the first and second gate patterns GP1 and GP2 in the first active region R1 . A second power contact PC2 may be provided between the fifth and sixth gate patterns GP5 and GP6 in the first active region R1 . The first and second power contacts PC1 and PC2 may extend in a direction perpendicular to the first active region R1 , and may be connected to wirings on the first and second active regions R1 and R2 . The first power contact PC1 may supply a power voltage VDD to a node (eg, a source or a drain) of the 3_1 transistor 151 . The second power contact PC2 may supply the power voltage VDD to a node (eg, a source or a drain) of the 5_1 th transistor 171 .

A first ground contact GC1 may be provided between the first and second gate patterns GP1 and GP2 in the second active region R2 . A second ground contact GC2 may be provided between the fifth and sixth gate patterns GP5 and GP6 in the second active region R2 . The first and second ground contacts GC1 and GC2 may extend in a direction perpendicular to the second active region R2 and may be connected to the wiring on the first and second active regions R1 and R2 . The first ground contact PC1 may supply a ground voltage VSS to a node (eg, a source or a drain) of the 3_4 transistor 154 . The second ground contact GC2 may supply a ground voltage VSS to a node (eg, a source or a drain) of the 5_4 transistor 174 .

In the first active region R1 , the second gate pattern GP2 may form a third_1 transistor 151 together with adjacent portions of the first active region R1 . In the first active region R1 , the third gate pattern GP3 may form a third_2 transistor 152 together with adjacent portions of the first active region R1 . The 3_1 and 3_2 transistors 151 and 152 may be connected in series.

In the second active region R2 , the second gate pattern GP2 may form a third_4 transistor 154 together with adjacent portions of the second active region R2 . In the second active region R2 , the third gate pattern GP3 may form a third_3 transistor 153 together with adjacent portions of the second active region R2 . The 3_3 and 3_4 transistors 153 and 154 may be connected in series.

A first contact C1 is provided to the second gate pattern GP2 of the 3_1 and 3_4 transistors 151 and 154 . The first contact C1 may extend in a direction perpendicular to the first and second active regions R1 and R2 and may be connected to the wiring on the first and second active regions R1 and R2 . The first contact C1 may be electrically connected to an output of the first inverter 130 and an input of the second inverter 140 .

The third gate pattern GP3 may be divided into a first portion corresponding to the first active region R1 and a second portion corresponding to the second active region R2 . A second contact C2 is provided on the first portion of the third gate pattern GP3 . The second contact C2 may extend in a direction perpendicular to the first and second active regions R1 and R2 and may be connected to the wiring over the first and second active regions R1 and R2 . The second contact C2 may supply the first clock signal n to the first portion of the third gate pattern GP3 .

A third contact C3 is provided on the second portion of the third gate pattern GP3 . The third contact C3 may extend in a direction perpendicular to the first and second active regions R1 and R2 and may be connected to the wiring on the first and second active regions R1 and R2 . The third contact C3 may supply the second clock signal b to the second portion of the third gate pattern GP3 .

In the first active region R1 , a fourth contact C4 is provided between the third and fourth gate patterns GP3 and GP4 . In the second active region R2 , a fifth contact C5 is provided between the third and fourth gate patterns GP3 and GP4 . The fourth and fifth contacts C4 and C5 extend in a direction perpendicular to the first and second active regions R1 and R2, and are common over the first and second active regions R1 and R2. can be connected to As the fourth and fifth contacts C4 and C5 are commonly connected, the 3_1 to 3_4 transistors 151 to 154 are connected to the first power contact PC1 to which the power voltage VDD is supplied and the ground voltage. It may be connected in series between the first ground contact GC1 to which VSS is supplied. The fourth and fifth contacts C4 and C5 may be electrically connected to inputs of the fourth inverter 160 and the sixth inverter 180 .

In the first active region R1 , the fifth gate pattern GP5 may form a 5_1 transistor 171 together with adjacent portions of the first active region R1 . In the first active region R1 , the fourth gate pattern GP4 may form a 5_2 transistor 172 together with adjacent portions of the first active region R1 . The 5_1 and 5_2 transistors 171 and 172 may be connected in series.

In the second active region R2 , the fifth gate pattern GP5 may form a 5_4 transistor 174 together with adjacent portions of the second active region R2 . In the second active region R2 , the fourth gate pattern GP4 may form a 5_3 transistor 173 together with adjacent portions of the second active region R2 . The 5_3 and 5_4 transistors 173 and 174 may be connected in series.

An eighth contact C8 is provided to the fifth gate pattern GP5 of the 5_1 and 5_4 transistors 171 and 174 . The eighth contact C8 may extend in a direction perpendicular to the first and second active regions R1 and R2 and may be connected to the wiring on the first and second active regions R1 and R2 . The eighth contact C8 may be electrically connected to the input of the fifth inverter 170 .

The fourth gate pattern GP4 may be divided into a first portion corresponding to the first active region R1 and a second portion corresponding to the second active region R2 . A sixth contact C6 is provided on the first portion of the fourth gate pattern GP4 . The sixth contact C6 may extend in a direction perpendicular to the first and second active regions R1 and R2 and may be connected to the wiring over the first and second active regions R1 and R2 . The sixth contact C6 may supply the second clock signal b to the first portion of the fourth gate pattern GP4 .

A seventh contact C7 is provided on the second portion of the fourth gate pattern GP4 . The seventh contact C7 may extend in a direction perpendicular to the first and second active regions R1 and R2 and may be connected to the wiring on the first and second active regions R1 and R2 . The seventh contact C7 may supply the first clock signal n to the second portion of the fourth gate pattern GP4 .

As the fourth and fifth contacts C4 and C5 are commonly connected, the 5_1 to 5_4 transistors 171 to 174 are connected to the second power contact PC2 to which the power voltage VDD is supplied and the ground voltage. It may be connected in series between the second ground contact GC2 to which VSS is supplied.

According to the layout of FIG. 3 , the third inverter 150 and the fifth inverter 170 have a power supply voltage on the first and second pins FIN1 and FIN2 forming the P-type first active region R1 . transistors 151 , 152 , 171 , 172 formed between the first power contact PC1 and the second power contact PC2 to which VDD is supplied, and the N-type second active region R2 , respectively. Transistors 153 , 154 , 173 formed between the first ground contact GC1 and the second ground contact GC2 to which the ground voltage VSS is supplied on the third and fourth fins FIN3 and FIN4 forming the transistors 153 , 154 , 173 ; 174) is implemented.

The first and second power contacts PC1 and PC2 and the first and second ground contacts GC1 and GC2 are disposed outside the layout of the third and fifth inverters 150 and 170 . Accordingly, the power supply voltage ( ) is applied to the first gate pattern GP1 and the sixth gate pattern GP6 through the first and second power contacts PC1 and PC2 and the first and second ground contacts GC1 and GC2 . VDD) and a ground voltage VSS are supplied. That is, another device that requires the power supply voltage VDD or the ground voltage VSS is supplied through the first and second power contacts PC1 and PC2 and the first and second ground contacts GC1 and GC2. The voltage VDD and the ground voltage VSS may be shared with the third and fifth inverters 150 and 170 . Accordingly, the layout efficiency of the flip-flop 100 including the third and fifth inverters 150 and 170 may be increased, and the size of the flip-flop 100 may be reduced.

FIG. 4 shows an example in which the fourth inverter 140 shares the power supply voltage VDD and the ground voltage VSS of the third and fifth inverters 130 and 150 of FIG. 3 . In FIG. 4 , configurations associated with third_1 to third_4 transistors 151 to 154 and 5_1 to 5_4 transistors 171 to 174 are the same as those shown in FIG. 3 . Accordingly, overlapping descriptions are omitted. Compared with FIG. 3 , a seventh gate pattern GP7 is added in FIG. 4 .

1 and 4 , the sixth gate pattern GP6 may form a 4_1 transistor 161 together with adjacent portions of the first active region R1 . The sixth gate pattern GP6 may form the 4_2 transistor 162 together with adjacent portions of the second active region R2 . A ninth contact C9 may be provided to the sixth gate pattern GP6 of the 4_1 and 4_2 transistors 161 and 162 . The ninth gate contact C1 may extend in a direction perpendicular to the first and second active regions R1 and R2 and may be connected to the wiring over the first and second active regions R1 and R2 . The ninth gate contact C9 may be an input of the fourth inverter 160 . The ninth gate contact C9 may be electrically connected to the fourth and fifth contacts C4 and C5 that are outputs of the third inverter 150 .

In the first active region R1 , a tenth contact C10 may be provided between the sixth and seventh gate patterns GP6 and GP7 . In the second active region R2 , an eleventh contact C11 may be provided between the sixth and seventh gate patterns GP6 and GP7 . The tenth and eleventh contacts C10 and C11 extend in a direction perpendicular to the first and second active regions R1 and R2 and are common over the first and second active regions R1 and R2. can be connected As the tenth and eleventh contacts C10 and C11 are commonly connected, the fourth_1 and fourth_2 transistors 161 and 152 are connected to the second power contact PC2 to which the power voltage VDD is supplied and the ground voltage. It may be connected in series between the second ground contact GC2 to which VSS is supplied. The ninth and tenth contacts C9 and C10 may be outputs of the fourth inverter 160 . The ninth and tenth contacts C9 and C10 may be electrically connected to the eighth contact C8 .

As shown in FIG. 4 , the fourth inverter 160 includes the fifth inverter 170 and the second power contact PC2 to which the power voltage VDD is supplied and the second ground contact to which the ground voltage VSS is supplied. It can be arranged to share (GC2). According to the layout of the present invention, the number of power contacts and the number of ground contacts that must be disposed when implementing the flip-flop 100 are reduced. Accordingly, the size of the flip-flop 100 is reduced.

For example, in FIG. 4 , the fourth inverter 160 is illustrated as sharing the power supply voltage VDD and the ground voltage VSS with the fifth inverter 170 . However, the fourth inverter 160 may be disposed to share the power voltage VDD and the ground voltage VSS with the third inverter 150 . For example, the first gate contact PC1 may be used as a gate of the 4_1 and 4_2 transistors 161 and 162 .

For example, in FIG. 4 , it is illustrated that the fourth inverter 160 shares the power supply voltage VDD and the ground voltage VSS with the fifth inverter 170 . However, instead of the fourth inverter 160 , the sixth inverter 180 may share the power voltage VDD and the ground voltage VSS with the fifth inverter 170 . For example, the sixth gate pattern GP6 forms a 6_1th transistor 181 together with adjacent portions of the first active region R1 , and a 6_2th transistor 181 together with adjacent portions of the second active region R2 . A transistor 182 may be formed.

Exemplarily, the fourth inverter 160 is disposed to share the power voltage VDD and the ground voltage VSS with the fifth inverter 170 or the third inverter 150 , and the sixth inverter 180 is the second inverter 150 . The third inverter 150 or the fifth inverter 170 may be disposed to share a power voltage VDD and a ground voltage VSS.

5 shows an application example in which the third and fifth inverters 150 and 170 are disposed. Compared with FIG. 3 , the third and fourth gate patterns GP3 and GP4 of FIG. 3 may be changed to the third to fifth gate patterns GP3 - GP5 of FIG. 4 . The fifth and sixth gate patterns GP5 and GP6 of FIG. 3 may correspond to the sixth and seventh gate patterns GP6 and GP7 of FIG. 5 , respectively.

1 and 5 , each of the third to fifth gate patterns GP3 to GP5 includes a first portion corresponding to the first active region R1 and a second portion corresponding to the second active region R2 , respectively. can be separated into parts.

A first portion of the third gate pattern GP3 may form a third_2 transistor 152 together with adjacent portions of the first active region R1 . The second portion of the third gate pattern GP3 may be ignored by the first jumper J1 . The first jumper J1 may electrically connect portions of the second active region R2 separated by the second portion of the third gate pattern GP3.

A first portion of the fourth gate pattern GP4 may form a fifth_2 transistor 172 together with adjacent portions of the first active region R1 . A second portion of the fourth gate pattern GP4 may form a third_3 transistor 153 together with adjacent portions of the second active region R2 .

The first portion of the fifth gate pattern GP4 may be ignored by the second jumper J2 . The second jumper J2 may electrically connect portions of the first active region R1 separated by the first portion of the third gate pattern GP3. A second portion of the fifth gate pattern GP4 may form a fifth_3 transistor 174 together with adjacent portions of the second active region R2 .

FIG. 6 shows an example in which the power supply voltage VDD and the ground voltage VSS of the third and fifth inverters 150 and 170 of FIG. 5 are shared. For example, the fourth inverter 160 or the sixth inverter 180 may share the power supply voltage VDD and the ground voltage VSS with the third and fifth inverters 150 and 170 .

The 3_1 to 3_4 transistors 151 to 154 and the 5_1 to 5_4 transistors 171 to 174 may be disposed in the same manner as illustrated in FIG. 5 . Compared with FIG. 5 , an eighth gate pattern GP8 may be added in FIG. 6 .

The seventh gate pattern GP7 may correspond to the sixth gate pattern GP6 of FIG. 4 . For example, the seventh gate pattern GP7 forms the 4_1 transistor 161 with adjacent portions of the first active region R1 , and adjacent portions of the second active region R2 and the 4_2 transistor 4_2 . 162) can be formed.

The fourth inverter 160 illustrated in FIG. 6 is exemplary. As described with reference to FIG. 4 , the fourth inverter 160 or the sixth inverter 180 connects the third inverter 150 or the fifth inverter 170 with the power supply voltage VDD and the ground voltage VSS. It can be arranged to share.

7 shows an application example of the third and fifth inverters 150 and 170 of FIG. 5 . Compared with FIG. 5 , in FIG. 7 , the fourth gate pattern GP4 may not be divided into a first portion and a second portion. The fourth gate pattern GP4 forms a 5_2 transistor 172 together with adjacent portions of the first active region R1 , and a third_3 transistor 153 together with adjacent portions of the second active region R2 . can form.

In FIG. 5 , the sixth contact C6 disposed on the first portion of the fourth gate pattern GP4 supplies the second clock signal b and is disposed on the second portion of the fourth gate pattern GP4 . The third contact C3 supplies the second clock signal b. Since the third and sixth contacts C3 and C6 transmit the same signal, one of the third and sixth contacts C3 and C6 may be removed without separating the fourth gate pattern GP4 . .

FIG. 8 shows an example in which the power supply voltage VDD and the ground voltage VSS of the third and fifth inverters 150 and 170 of FIG. 7 are shared. For example, the fourth inverter 160 or the sixth inverter 180 may share the power supply voltage VDD and the ground voltage VSS with the third and fifth inverters 150 and 170 .

The 3_1 to 3_4 transistors 151 to 154 and the 5_1 to 5_4 transistors 171 to 174 may be disposed in the same manner as illustrated in FIG. 7 . Compared with FIG. 7 , an eighth gate pattern GP8 may be added in FIG. 8 .

The seventh gate pattern GP7 may correspond to the sixth gate pattern GP6 of FIG. 4 . For example, the seventh gate pattern GP7 forms the 4_1 transistor 161 with adjacent portions of the first active region R1 , and adjacent portions of the second active region R2 and the 4_2 transistor 4_2 . 162) can be formed.

The fourth inverter 160 illustrated in FIG. 8 is exemplary. As described with reference to FIG. 4 , the fourth inverter 160 or the sixth inverter 180 connects the third inverter 150 or the fifth inverter 170 with the power supply voltage VDD and the ground voltage VSS. It can be arranged to share.

FIG. 9 shows an application example of the flip-flop 100 of FIG. 1 . Referring to FIG. 9 , the flip-flop 200 includes an input unit 210 and first to sixth inverters 230 to 280 .

The first to sixth inverters 230 to 280 are the same as the first to sixth inverters 130 to 180 described with reference to FIG. 1 . Accordingly, overlapping descriptions are omitted.

The input unit 210 inverts the input signal D in synchronization with the first and second clock signals n and b and transmits the inverted signal to the first inverter 130 . The input unit 210 and 210 include first to fourth input transistors 211 to 214 . The first to fourth input transistors 211 to 214 may be connected in series between a power node and a ground node. The first and second input transistors 211 and 212 may have a P-type, and the third and fourth input transistors 213 and 214 may have an N-type.

The input signal D is transmitted to the gates of the first and fourth input transistors 211 and 214 . The second clock signal b is transmitted to the gate of the second input transistor 212 . The first clock signal n is transmitted to the gate of the third input transistor 213 . The input unit 210 may be a three-phase inverter operating in synchronization with the first and second clock signals n and b. A node between the second and third input transistors 212 and 213 may be an output of the input unit 210 . An output of the input unit 210 is connected to an input of the first inverter 130 .

In FIG. 9 , the input unit 210 and the second inverter 240 have the same structure as the third and fifth inverters 250 and 270 except for the first and second clock signals n and b. and are connected in the same way. Accordingly, by exchanging contacts to which the first and second clock signals n and b are transmitted, the input unit 210 and the second inverter 240 are also shown in FIGS. 3, 5 or 7 . can be implemented. In addition, the first inverter 230 may share the power supply voltage VDD and the ground voltage VSS with the input unit 210 and the second inverter 240 as shown in FIGS. 4, 6 or 8 . .

The input unit 210 and the second inverter 240 are implemented as shown in Figs. 3, 5 or 7, and the third and fifth inverters 250 and 270 are shown in Figs. When implemented as shown, layout efficiency of the flip-flop 200 may be further improved, and the size of the flip-flop 200 may be further reduced.

FIG. 10 shows an application example of the flip-flop 200 of FIG. 9 . Referring to FIG. 10 , the flip-flop 300 includes an input unit 310 and first to sixth inverters 330 to 380 .

The input unit 310 and the second, third, fifth and sixth inverters 340 , 350 , 370 and 380 are connected to the input unit 210 and the second, third, fifth and sixth inverters ( ) of FIG. 9 . 240, 250, 270, 280). Accordingly, overlapping descriptions are omitted.

The first inverter 330 may include first_1 to first_4 transistors 331 to 334 . The first_1 and first_3 transistors 331 and 333 are connected in series between a power node to which the power voltage VDD is supplied and the first_4 transistor 334 . The first_1 and first_3 transistors 331 and 333 may have a P-type. The first_2 and first_4 transistors 332 and 334 are connected in parallel between the ground node to which the ground voltage VSS is supplied and the first_3 transistor 333 . The first_2 and first_4 transistors 332 and 334 may have an N-type.

The output of the input unit 310 is transmitted to the gates of the first_1 and first_2 transistors 331 and 332 . The reset signal R is transmitted to the gates of the first_3 and first_4 transistors 333 and 334 . When the reset signal R is activated, that is, when the reset signal R has the power supply voltage VDD or a similar level, the node between the first_3 and first_4 transistors 333 and 334 is connected to the ground voltage VSS. can be reset to When the reset signal R is inactive, that is, when the reset signal R has a ground voltage VSS or a lower level, the first_3 transistor 333 may maintain a turned-on state. The first_1 and first_2 transistors 331 and 332 may operate as inverters.

The fourth inverter 360 may include 4_1 to 4_4 transistors 361 to 364 . The 4_1 and 4_3 transistors 361 and 363 are connected in series between the power node to which the power voltage VDD is supplied and the 4_4 transistor 364 . The 4_1 and 4_3 transistors 361 and 363 may have a P-type. The 4_2 and 4_4 transistors 362 and 364 are connected in parallel between the ground node to which the ground voltage VSS is supplied and the 4_3 transistor 363 . The 4_2 and 4_4 transistors 362 and 364 may have an N-type.

The output of the third inverter 350 is transmitted to the gates of the 4_1 and 4_2 transistors 361 and 362 . The reset signal R is transmitted to the gates of the 4_3 and 4_4 transistors 363 and 364 . When the reset signal R is activated, the node between the first_3 and first_4 transistors 363 and 364 may be reset to the ground voltage VSS. When the reset signal R is deactivated, the 4_3 transistor 363 may maintain a turned-on state. The 4_1 and 4_2 transistors 361 and 362 may operate as inverters.

11 shows an example in which the fourth inverter 360 of FIG. 10 shares a power supply voltage and a ground voltage with the third and fifth inverters 350 and 370 . Compared with FIG. 3 , the 3_1 to 3_4 transistors 351 to 354 and the 5_1 to 5_4 transistors 371 to 374 are the 3_1 to 3_4 transistors 151 to 154 and the 5_1 to 5_4 transistors 171 to 174 are disposed in the same manner. Accordingly, overlapping descriptions are omitted.

Compared with FIG. 3 , seventh and eighth gate patterns GP7 and GP8 are added in FIG. 11 . The sixth gate pattern GP6 forms a 4_1 transistor 361 together with adjacent portions of the first active region R1 and a 4_2 transistor 362 together with adjacent portions of the second active region R2. to form The 4_1 transistor 361 may receive the power supply voltage VDD from the second power contact PC2 . The 4_2 transistor 362 may receive the ground voltage VSS from the second ground contact GC2 .

A ninth contact C9 may be provided to the sixth gate pattern GP6 of the 4_1 and 4_2 transistors 361 and 362 . The ninth contact C9 may extend in a direction perpendicular to the first and second active regions R1 and R2 and may be connected to the wiring on the first and second active regions R1 and R2 . The ninth contact C9 may be an input of the fourth inverter 360 .

The seventh gate pattern GP7 forms fourth_3 transistors 363 together with adjacent portions of the first active region R1 , and the fourth_4 transistor 364 together with adjacent portions of the second active region R2 . ) can be formed. An eleventh contact C11 is provided to the seventh gate pattern GP7 of the 4_3 and 4_4 transistors 363 and 364 . The eleventh contact C11 may extend in a direction perpendicular to the first and second active regions R1 and R2 and may be connected to the wiring on the first and second active regions R1 and R2 . The eleventh contact C11 may transmit a reset signal R to the 4_1 and 4_4 transistors 361 and 364 .

In the second active region R2 , a third ground contact GC3 is disposed between the seventh and eighth gate patterns GP7 and GP8 . The third ground contact GC3 may extend in a direction perpendicular to the first and second active regions R1 and R2 and may be connected to the wiring over the first and second active regions R1 and R2 . The 4_2 transistor 364 may receive the ground voltage VSS from the third ground contact GC3 .

A tenth contact C10 is provided between the sixth and seventh gate patterns GP6 and GP7 in the second active region R2 . A twelfth contact C12 is provided between the seventh and eighth gate patterns GP7 and GP8 in the first active region R1 . The tenth and twelfth contacts C10 and C12 extend in a direction perpendicular to the first and second active regions R1 and R2 and are common over the first and second active regions R1 and R2. can be connected to The tenth and twelfth contacts C10 and C12 may be outputs of the fourth inverter 360 .

The fourth inverter 360 illustrated in FIG. 11 is exemplary. As described with reference to FIG. 4 , the fourth inverter 360 or the sixth inverter 380 connects the third inverter 350 or the fifth inverter 370 with the power supply voltage VDD and the ground voltage VSS. It can be arranged to share.

The input unit 310 and the first and second inverters 330 and 340 may also be implemented as shown in FIG. 11 . For example, the sixth gate pattern GP6 forms a first_1 transistor 331 together with adjacent portions of the first active region R1 , and a first_2 first_2 transistor with adjacent portions of the second active region R2 . A transistor 332 may be formed. The ninth contact C9 may transmit the input signal D. The seventh gate pattern GP7 forms a first_3 transistor 333 together with adjacent portions of the first active region R1 and a first_4 transistor 334 together with adjacent portions of the second active region R2. can form. The eleventh contact C11 may transmit a reset signal R. Parts not mentioned may have the same configuration as those described with reference to the third to fifth inverters 350 to 370 .

12 shows an application example in which the third to fifth inverters 350 to 370 of FIG. 11 are disposed. Referring to FIG. 12 , 3_1 to 3_4 transistors 351 to 354 and 5_1 to 5_4 transistors 371 to 374 may be disposed in the same manner as illustrated in FIG. 5 . Compared with FIG. 5 , eighth and ninth gate patterns GP8 and GP9 may be added in FIG. 12 .

The seventh to ninth gate patterns GP7 to GP9 may respectively correspond to the sixth to eighth gate patterns GP6 to GP8 of FIG. 11 . For example, the seventh gate pattern GP7 may form the 4_1 and 4_2 transistors 361 and 362 . The eighth gate pattern GP8 may form fourth_3 and fourth_4 transistors 363 and 364 .

The fourth inverter 360 shown in FIG. 12 is exemplary. As described with reference to FIG. 4 , the fourth inverter 360 or the sixth inverter 380 connects the third inverter 350 or the fifth inverter 370 with the power supply voltage VDD and the ground voltage VSS. It can be arranged to share.

The input unit 310 and the first and second inverters 330 and 340 may also be implemented as shown in FIG. 12 . For example, the seventh gate pattern GP7 forms a first_1 transistor 331 together with adjacent portions of the first active region R1 and a first_2 first_2 transistor with adjacent portions of the second active region R2. A transistor 332 may be formed. The ninth contact C9 may transmit the input signal D. The eighth gate pattern GP8 forms the first_3 transistor 333 together with adjacent portions of the first active region R1 and the first_4 transistor 334 together with adjacent portions of the second active region R2. can form. The eleventh contact C11 may transmit a reset signal R. Parts not mentioned may have the same configuration as those described with reference to the third to fifth inverters 350 to 370 .

13 shows another application example in which the third to fifth inverters 350 to 370 of FIG. 11 are disposed. Referring to FIG. 13 , 3_1 to 3_4 transistors 351 to 354 and 5_1 to 5_4 transistors 371 to 374 may be disposed in the same manner as shown in FIG. 7 . Compared with FIG. 7 , eighth and ninth gate patterns GP8 and GP9 may be added in FIG. 13 .

The seventh to ninth gate patterns GP7 to GP9 may respectively correspond to the sixth to eighth gate patterns GP6 to GP8 of FIG. 11 . For example, the seventh gate pattern GP7 may form the 4_1 and 4_1 transistors 361 and 362 . The eighth gate pattern GP8 may form fourth_3 and fourth_4 transistors 363 and 364 .

The fourth inverter 360 shown in FIG. 13 is exemplary. As described with reference to FIG. 4 , the fourth inverter 360 or the sixth inverter 380 connects the third inverter 350 or the fifth inverter 370 with the power supply voltage VDD and the ground voltage VSS. It can be arranged to share.

The input unit 310 and the first and second inverters 330 and 340 may also be implemented as shown in FIG. 13 .

FIG. 14 shows another application example of the flip-flop 200 of FIG. 9 . Referring to FIG. 14 , the flip-flop 400 includes an input unit 410 and first to sixth inverters 430 to 480 .

The input unit 410 and the second, third, fifth and sixth inverters 440 , 450 , 470 and 480 are connected to the input unit 210 and the second, third, fifth and sixth inverters ( ) of FIG. 9 . 240, 250, 270, 280). Accordingly, overlapping descriptions are omitted.

The first inverter 430 may include first_1 to first_4 transistors 331 to 334 . The first_1 and first_3 transistors 431 and 433 are connected in parallel between a power node to which the power voltage VDD is supplied and the first_4 transistor 334 . The first_1 and first_3 transistors 431 and 433 may have a P-type. The first_2 and first_4 transistors 432 and 434 are connected in series between a ground node to which the ground voltage VSS is supplied and the first_3 transistor 333 . The first_2 and first_4 transistors 432 and 434 may have an N-type.

The output of the input unit 410 is transmitted to the gates of the first and second transistors 431 and 432 . The set signal S is transmitted to the gates of the first_3 and first_4 transistors 433 and 434 . When the set signal S is activated, that is, when the set signal S has the ground voltage VSS or a level lower than that, the node between the first_3 and first_4 transistors 433 and 434 becomes the power supply voltage VDD. can be set. When the set signal S is inactive, that is, when the set signal S has a power supply voltage VDD or a similar level, the first_4 transistor 434 may maintain a turned-on state. The first_1 and first_2 transistors 431 and 432 may operate as inverters.

The fourth inverter 460 may include 4_1 to 4_4 transistors 461 to 464 . The 4_1 and 4_3 transistors 461 and 463 are connected in parallel between a power node to which the power voltage VDD is supplied and the 4_2 transistor 462 . The 4_1 and 4_3 transistors 461 and 463 may have a P-type. The 4_2 and 4_4 transistors 462 and 464 are connected in series between the ground node to which the ground voltage VSS is supplied and the 4_3 transistor 463 . The 4_2 and 4_4 transistors 462 and 464 may have an N-type.

The output of the third inverter 450 is transmitted to the gates of the 4_1 and 4_2 transistors 461 and 462 . The set signal S is transmitted to the gates of the 4_3 and 4_4 transistors 463 and 464 . When the set signal S is activated, the node between the first_2 and first_3 transistors 462 and 463 may be reset to the power supply voltage VDD. When the set signal S is inactive, the 4_4 transistor 463 may maintain a turned-on state. The 4_1 and 4_2 transistors 461 and 462 may operate as inverters.

15 shows an example in which the fourth inverter 460 of FIG. 14 shares a power supply voltage and a ground voltage with the third and fifth inverters 450 and 470 . 3 , the 3_1 to 3_4 transistors 451 to 454 and the 5_1 to 5_4 transistors 471 to 474 are the 3_1 to 3_4 transistors 151 to 154 and the 5_1 to 5_4 transistors 171 to 174 are disposed in the same manner. Accordingly, overlapping descriptions are omitted.

Compared with FIG. 3 , seventh and eighth gate patterns GP7 and GP8 are added in FIG. 11 . The sixth gate pattern GP6 forms a 4_3 transistor 463 together with adjacent portions of the first active region R1 , and a 4_2 transistor 464 together with adjacent portions of the second active region R2 . to form The 4_3 transistor 463 may receive the power supply voltage VDD from the second power contact PC2 . The fourth_4 transistor 464 may receive the ground voltage VSS from the second ground contact GC2 .

A ninth contact C9 may be provided to the sixth gate pattern GP6 of the 4_3 and 4_4 transistors 463 and 464 . The ninth contact C9 may extend in a direction perpendicular to the first and second active regions R1 and R2 and may be connected to the wiring on the first and second active regions R1 and R2 . The ninth contact C9 may transmit the set signal S to the 4_3 and 4_4 transistors 463 and 464 .

The seventh gate pattern GP7 forms 4_1 transistors 461 together with adjacent portions of the first active region R1 and the fourth_2 transistor 462 together with adjacent portions of the second active region R2. ) can be formed. An eleventh contact C11 is provided to the seventh gate pattern GP7 of the 4_1 and 4_2 transistors 461 and 462 . The eleventh contact C11 may extend in a direction perpendicular to the first and second active regions R1 and R2 and may be connected to the wiring on the first and second active regions R1 and R2 . The eleventh contact C11 may be an input of the fourth inverter 460 .

In the first active region R1 , a third power contact PC3 is disposed between the seventh and eighth gate patterns GP7 and GP8 . The third power contact PC3 may extend in a direction perpendicular to the first and second active regions R1 and R2 and may be connected to the wiring over the first and second active regions R1 and R2 . The 4_1 transistor 461 may receive the power supply voltage VDD from the third power contact PC3 .

A tenth contact C10 is provided between the sixth and seventh gate patterns GP6 and GP7 in the first active region R2 . A twelfth contact C12 is provided between the seventh and eighth gate patterns GP7 and GP8 in the second active region R2 . The tenth and twelfth contacts C10 and C12 extend in a direction perpendicular to the first and second active regions R1 and R2 and are common over the first and second active regions R1 and R2. can be connected to The tenth and twelfth contacts C10 and C12 may be outputs of the fourth inverter 360 .

The fourth inverter 460 illustrated in FIG. 15 is exemplary. As described with reference to FIG. 4 , the fourth inverter 460 or the sixth inverter 480 connects the third inverter 450 or the fifth inverter 470 with the power supply voltage VDD and the ground voltage VSS. It can be arranged to share.

The input unit 410 and the first and second inverters 430 and 440 may also be implemented as shown in FIG. 15 . For example, the sixth gate pattern GP6 forms a first_3 transistor 433 together with adjacent portions of the first active region R1 , and a first_4th transistor 433 together with adjacent portions of the second active region R2 . A transistor 434 may be formed. The ninth contact C9 may transmit a set signal S. The seventh gate pattern GP7 forms a first_1 transistor 431 together with adjacent portions of the first active region R1 and a first_2 transistor 432 together with adjacent portions of the second active region R2. can form. The eleventh contact C11 may transmit an input signal D. Parts not mentioned may have the same configuration as described with reference to the third to fifth inverters 450 to 470 .

16 shows an application example in which the third to fifth inverters 450 to 470 of FIG. 15 are disposed. Referring to FIG. 16 , 3_1 to 3_4 transistors 451 to 454 and 5_1 to 5_4 transistors 471 to 474 may be disposed in the same manner as shown in FIG. 5 . Compared with FIG. 5 , eighth and ninth gate patterns GP8 and GP9 may be added in FIG. 16 .

The seventh to ninth gate patterns GP7 to GP9 may respectively correspond to the sixth to eighth gate patterns GP6 to GP8 of FIG. 15 . For example, the seventh gate pattern GP7 may form fourth_3 and fourth_4 transistors 463 and 464 . The eighth gate pattern GP8 may form 4_1 and 4_2 transistors 461 and 462 .

The fourth inverter 460 illustrated in FIG. 16 is exemplary. As described with reference to FIG. 4 , the fourth inverter 460 or the sixth inverter 480 connects the third inverter 450 or the fifth inverter 470 with the power supply voltage VDD and the ground voltage VSS. It can be arranged to share.

The input unit 310 and the first and second inverters 330 and 340 may also be implemented as shown in FIG. 16 . For example, the seventh gate pattern GP7 forms a first_1 transistor 431 together with adjacent portions of the first active region R1 , and a first_2 first_2 transistor with adjacent portions of the second active region R2 . A transistor 432 may be formed. The ninth contact C9 may transmit the input signal D. The eighth gate pattern GP8 forms a first_3 transistor 433 together with adjacent portions of the first active region R1 , and a first_4 transistor 434 together with adjacent portions of the second active region R2 . can form. The eleventh contact C11 may transmit the set signal S.

FIG. 17 shows another application example in which the third to fifth inverters 450 to 470 of FIG. 15 are disposed. Referring to FIG. 17 , 3_1 to 3_4 transistors 451 to 454 and 5_1 to 5_4 transistors 471 to 474 may be disposed in the same manner as shown in FIG. 7 . Compared with FIG. 7 , eighth and ninth gate patterns GP8 and GP9 may be added in FIG. 17 .

The seventh to ninth gate patterns GP7 to GP9 may respectively correspond to the sixth to eighth gate patterns GP6 to GP8 of FIG. 15 . For example, the seventh gate pattern GP7 may form fourth_3 and fourth_4 transistors 463 and 464 . The eighth gate pattern GP8 may form 4_1 and 4_2 transistors 461 and 462 .

The fourth inverter 460 illustrated in FIG. 17 is exemplary. As described with reference to FIG. 4 , the fourth inverter 460 or the sixth inverter 480 connects the third inverter 450 or the fifth inverter 470 with the power supply voltage VDD and the ground voltage VSS. It can be arranged to share.

The input unit 410 and the first and second inverters 430 and 440 may also be implemented as shown in FIG. 17 .

The contents described above are specific examples for carrying out the present invention. The present invention will include not only the above-described embodiments, but also simple design changes or easily changeable embodiments. In addition, the present invention will also include techniques that can be easily modified and implemented in the future using the above-described embodiments.

100, 200, 300, 400; flip-flop
110, 210, 310, 410; input
130, 230, 330, 430; first inverter
140, 240, 340, 440; 2nd inverter
150, 250, 350, 450; 3rd inverter
160, 260, 360, 460; 4th inverter
170, 270, 370, 470; 5th inverter
180, 280, 380, 480; 6th inverter
190; clock generator

Claims (20)

an input unit for receiving a signal and outputting the received signal in synchronization with a clock;
a first latch including a first inverter and a second inverter and storing a signal output from the input unit in synchronization with the clock;
a third inverter outputting the signal stored in the first latch in synchronization with the clock; and
a fourth inverter and a fifth inverter, and a second latch for storing a signal output from the third inverter in synchronization with the clock;
The third inverter and the fifth inverter are
first transistors of a first type formed between a first power contact to which a power voltage is supplied and a second power contact over fins of the first type; and
A flip-flop comprising: a first ground contact to which a ground voltage is supplied over pins of the second type; and second transistors of a second type formed between the second ground contact. According to claim 1,
no other power contact is disposed between the first power contact and the second power contact, and
A flip-flop in which no other ground contact is disposed between the first ground contact and the second ground contact. According to claim 1,
first to fourth gates are disposed between the first power contact and the second power contact;
fifth to eighth gates are disposed between the first ground contact and the second ground contact;
the first gate is connected to the fifth gate, and
and the fourth gate is a flip-flop connected to the eighth gate. 4. The method of claim 3,
an output of the first latch is connected to the first gate;
A flip-flop in which an output of the fourth inverter is connected to the fourth gate. 4. The method of claim 3,
The clock includes a first clock and a second clock,
the first clock is supplied to the second gate and the seventh gate;
a flip-flop to which the second clock is supplied to the third gate and the sixth gate. 4. The method of claim 3,
a ninth gate is disposed on a side of the second power contact opposite from the first power contact and on a side of the second ground contact opposite from the first ground contact;
and the ninth gate forms the fourth inverter together with the first type fins and the second type fins. 7. The method of claim 6,
The fins of the first type on the side opposite from the second power contact of the ninth gate and the fins of the second type on the side opposite from the second ground contact of the ninth gate are connected to the eighth gate and Connected flip-flops. 4. The method of claim 3,
a sixth inverter for inverting and outputting a signal between the third inverter and the second latch;
a ninth gate is disposed on a side of the second power contact opposite from the first power contact and on a side of the second ground contact opposite from the first ground contact;
and the ninth gate forms the sixth inverter together with the first type fins and the second type fins. 4. The method of claim 3,
ninth and tenth gates are disposed on a side of the second power contact opposite from the first power contact and on a side of the second ground contact opposite from the first ground contact;
a reset signal is supplied to the tenth gate;
The output of the third inverter is supplied to the ninth gate,
The first type fins on the side of the tenth gate are connected to the first gate,
a third ground contact to which a ground voltage is supplied to the second type pins on a side surface of the tenth gate is disposed;
The second type of fins between the ninth gate and the tenth gate are connected to the eighth gate. 4. The method of claim 3,
ninth and tenth gates are disposed on a side of the second power contact opposite from the first power contact and on a side of the second ground contact opposite from the first ground contact;
A set signal is supplied to the ninth gate,
The output of the third inverter is supplied to the tenth gate,
a third power contact to which a power voltage is supplied to the first type pins on a side surface of the tenth gate is disposed;
The second type of fins on the side surface of the tenth gate are connected to the first gate,
The first type fins between the ninth gate and the tenth gate are connected to the eighth gate. According to claim 1,
first to fifth gates are disposed between the first power contact and the second power contact;
sixth to tenth gates are disposed between the first ground contact and the second ground contact;
the first gate is connected to the sixth gate,
the fifth gate is connected to the tenth gate,
an output of the first latch is connected to the first gate;
an output of the fourth inverter is connected to the fifth gate,
The clock includes a first clock and a second clock,
the first clock is supplied to the second gate and the ninth gate;
a flip-flop to which the second clock is supplied to the third gate and the eighth gate. 12. The method of claim 11,
A first jumper is disposed on the fourth gate to electrically connect the fins of the first type, and
A flip-flop having a second jumper disposed on the seventh gate and electrically connecting the fins of the second type. 12. The method of claim 11,
and the third gate and the ninth gate are connected to each other. According to claim 1,
A flip-flop in which a power supply voltage of at least one of the first power contact and the second power contact and a ground voltage of at least one of the first ground contact and the second ground contact are shared with other components. According to claim 1,
The input unit includes a sixth inverter outputting the received signal in synchronization with a clock,
The second inverter and the sixth inverter are
third transistors of the first type formed between a third power contact to which a power supply voltage is supplied and a fourth power contact on the first type pins; and
and fourth transistors of the second type formed between a third ground contact to which a ground voltage is supplied and a fourth ground contact on the pins of the second type. 16. The method of claim 15,
first to fourth gates are disposed between the third power contact and the fourth power contact;
fifth to eighth gates are disposed between the third ground contact and the fourth ground contact;
the first gate is connected to the fifth gate, and
and the fourth gate is a flip-flop connected to the eighth gate. 17. The method of claim 16,
ninth and tenth gates are disposed on a side of the fourth power contact opposite from the third power contact and on a side of the fourth ground contact opposite from the third ground contact;
The output of the third inverter is supplied to the ninth gate,
a reset signal is supplied to the tenth gate;
The first type fins on the side surface of the tenth gate are connected to the eighth gate,
a fifth ground contact to which a ground voltage is supplied to the second type pins on a side surface of the tenth gate is disposed;
The second type of fins between the ninth gate and the tenth gate are connected to the eighth gate. 17. The method of claim 16,
ninth and tenth gates are disposed on a side of the fourth power contact opposite from the third power contact and on a side of the fourth ground contact opposite from the third ground contact;
The output of the third inverter is supplied to the tenth gate,
A set signal is supplied to the ninth gate,
a third power contact to which a power voltage is supplied to the first type pins on a side surface of the tenth gate is disposed;
The second type fins on the side surface of the tenth gate are connected to the eighth gate,
The first type fins between the ninth gate and the tenth gate are connected to the eighth gate. an input unit for receiving a signal and outputting the received signal in synchronization with a clock;
a first latch including a first inverter and a second inverter and storing a signal output from the input unit in synchronization with the clock;
a third inverter outputting the signal stored in the first latch in synchronization with the clock;
a second latch including a fourth inverter and a fifth inverter and storing a signal output from the third inverter in synchronization with the clock; and
a sixth inverter for inverting and outputting a signal between the third inverter and the second latch;
The third inverter and the fifth inverter are
first transistors of a first type formed between a first power contact and a second power contact to which a power voltage is supplied on fins of the first type; and
a second type of second transistors formed between a first ground contact to which a ground voltage is supplied and a second ground contact on pins of the second type;
A power voltage of at least one of the first power contact and the second power contact, and a ground voltage of at least one of the first ground contact and the second ground contact, are shared with one of the fourth inverter and the sixth inverter. being a flip-flop. an input unit for receiving a signal and outputting the received signal in synchronization with a clock;
a first latch including a first inverter and a second inverter and storing a signal output from the input unit in synchronization with the clock;
a third inverter outputting the signal stored in the first latch in synchronization with the clock;
a second latch including a fourth inverter and a fifth inverter and storing a signal output from the third inverter in synchronization with the clock; and
a sixth inverter for inverting and outputting a signal between the third inverter and the second latch;
the third inverter includes first and second PMOS transistors and first and second PMOS transistors;
the fifth inverter includes third and fourth PMOS transistors and third and fourth PMOS transistors;
The first to fourth PMOS transistors are disposed between a first power contact and a second power contact to which a power voltage is supplied on fins of a first type;
A flip-flop in which the first to fourth NMOS transistors are disposed between a first ground contact to which a ground voltage is supplied and a second ground contact on second type pins.

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