KR102284957B1 - 트랜잭션 데이터 처리 실행 모드에 대한 호출 스택 유지 - Google Patents

트랜잭션 데이터 처리 실행 모드에 대한 호출 스택 유지 Download PDF

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KR102284957B1
KR102284957B1 KR1020177003061A KR20177003061A KR102284957B1 KR 102284957 B1 KR102284957 B1 KR 102284957B1 KR 1020177003061 A KR1020177003061 A KR 1020177003061A KR 20177003061 A KR20177003061 A KR 20177003061A KR 102284957 B1 KR102284957 B1 KR 102284957B1
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stack
data processing
execution mode
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KR20170031708A (ko
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매튜 제임스 호스넬
스테판 디에스텔호스트
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에이알엠 리미티드
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    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/46—Multiprogramming arrangements
    • G06F9/466—Transaction processing
    • G06F9/467—Transactional memory
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/46—Multiprogramming arrangements
    • G06F9/466—Transaction processing
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/14—Error detection or correction of the data by redundancy in operations
    • G06F11/1474—Error detection or correction of the data by redundancy in operations in transactions
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0875—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches with dedicated cache, e.g. instruction or stack
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0891—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches using clearing, invalidating or resetting means
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/12—Replacement control
    • G06F12/121—Replacement control using replacement algorithms
    • G06F12/128—Replacement control using replacement algorithms adapted to multidimensional cache systems, e.g. set-associative, multicache, multiset or multilevel
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/46—Multiprogramming arrangements
    • G06F9/52—Program synchronisation; Mutual exclusion, e.g. by means of semaphores
    • G06F9/526—Mutual exclusion algorithms
    • G06F9/528—Mutual exclusion algorithms by using speculative mechanisms
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0806—Multiuser, multiprocessor or multiprocessing cache systems
    • G06F12/0811—Multiuser, multiprocessor or multiprocessing cache systems with multilevel cache hierarchies
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/10—Providing a specific technical effect
    • G06F2212/1032—Reliability improvement, data loss prevention, degraded operation etc
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/45—Caching of specific data in cache memory
    • G06F2212/451—Stack data
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/62—Details of cache specific to multiprocessor cache arrangements
    • G06F2212/621—Coherency control relating to peripheral accessing, e.g. from DMA or I/O device

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Software Systems (AREA)
  • Quality & Reliability (AREA)
  • Executing Machine-Instructions (AREA)
  • Advance Control (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
KR1020177003061A 2014-07-15 2015-06-09 트랜잭션 데이터 처리 실행 모드에 대한 호출 스택 유지 Active KR102284957B1 (ko)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
GB1412534.8 2014-07-15
GB1412534.8A GB2528270A (en) 2014-07-15 2014-07-15 Call stack maintenance for a transactional data processing execution mode
PCT/GB2015/051675 WO2016009168A1 (en) 2014-07-15 2015-06-09 Call stack maintenance for a transactional data processing execution mode

Publications (2)

Publication Number Publication Date
KR20170031708A KR20170031708A (ko) 2017-03-21
KR102284957B1 true KR102284957B1 (ko) 2021-08-04

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KR1020177003061A Active KR102284957B1 (ko) 2014-07-15 2015-06-09 트랜잭션 데이터 처리 실행 모드에 대한 호출 스택 유지

Country Status (8)

Country Link
US (1) US10002020B2 (https=)
EP (1) EP3170075B1 (https=)
JP (1) JP6568575B2 (https=)
KR (1) KR102284957B1 (https=)
CN (1) CN106663026B (https=)
GB (1) GB2528270A (https=)
IL (1) IL249697B (https=)
WO (1) WO2016009168A1 (https=)

Families Citing this family (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB2554096B (en) * 2016-09-20 2019-03-20 Advanced Risc Mach Ltd Handling of inter-element address hazards for vector instructions
CN107291480B (zh) * 2017-08-15 2020-12-15 中国农业银行股份有限公司 一种函数调用方法及装置
US10572259B2 (en) * 2018-01-22 2020-02-25 Arm Limited Hints in a data processing apparatus
US10698724B2 (en) * 2018-04-10 2020-06-30 Osisoft, Llc Managing shared resources in a distributed computing system
US11231932B2 (en) * 2019-03-05 2022-01-25 Arm Limited Transactional recovery storage for branch history and return addresses to partially or fully restore the return stack and branch history register on transaction aborts
US11334495B2 (en) * 2019-08-23 2022-05-17 Arm Limited Cache eviction
US11687519B2 (en) 2021-08-11 2023-06-27 T-Mobile Usa, Inc. Ensuring availability and integrity of a database across geographical regions
FR3147397A1 (fr) * 2023-03-28 2024-10-04 Stmicroelectronics International N.V. Système informatique configuré pour exécuter un programme d’ordinateur

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20080288819A1 (en) 2007-05-14 2008-11-20 International Business Machines Corporation Computing System with Transactional Memory Using Millicode Assists
US20100023703A1 (en) 2008-07-28 2010-01-28 Christie David S Hardware transactional memory support for protected and unprotected shared-memory accesses in a speculative section
US20110307689A1 (en) 2010-06-11 2011-12-15 Jaewoong Chung Processor support for hardware transactional memory
US20120304172A1 (en) 2011-04-29 2012-11-29 Bernd Greifeneder Method and System for Transaction Controlled Sampling of Distributed Hetereogeneous Transactions without Source Code Modifications
US20130151791A1 (en) 2011-12-13 2013-06-13 Advanced Micro Devices, Inc. Transactional memory conflict management

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8544020B1 (en) * 2004-09-14 2013-09-24 Azul Systems, Inc. Cooperative preemption
US7472261B2 (en) * 2005-11-08 2008-12-30 International Business Machines Corporation Method for performing externally assisted calls in a heterogeneous processing complex
US20080016325A1 (en) * 2006-07-12 2008-01-17 Laudon James P Using windowed register file to checkpoint register state
US7860930B2 (en) * 2006-12-19 2010-12-28 International Business Machines Corporation Communication between host systems using a transaction protocol and shared memories
US8739164B2 (en) * 2010-02-24 2014-05-27 Advanced Micro Devices, Inc. Automatic suspend atomic hardware transactional memory in response to detecting an implicit suspend condition and resume thereof

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20080288819A1 (en) 2007-05-14 2008-11-20 International Business Machines Corporation Computing System with Transactional Memory Using Millicode Assists
US20100023703A1 (en) 2008-07-28 2010-01-28 Christie David S Hardware transactional memory support for protected and unprotected shared-memory accesses in a speculative section
US20110307689A1 (en) 2010-06-11 2011-12-15 Jaewoong Chung Processor support for hardware transactional memory
US20120304172A1 (en) 2011-04-29 2012-11-29 Bernd Greifeneder Method and System for Transaction Controlled Sampling of Distributed Hetereogeneous Transactions without Source Code Modifications
US20130151791A1 (en) 2011-12-13 2013-06-13 Advanced Micro Devices, Inc. Transactional memory conflict management

Also Published As

Publication number Publication date
EP3170075A1 (en) 2017-05-24
IL249697A0 (en) 2017-02-28
EP3170075B1 (en) 2021-01-13
JP6568575B2 (ja) 2019-08-28
US10002020B2 (en) 2018-06-19
WO2016009168A1 (en) 2016-01-21
CN106663026B (zh) 2021-01-12
CN106663026A (zh) 2017-05-10
GB201412534D0 (en) 2014-08-27
JP2017520857A (ja) 2017-07-27
GB2528270A (en) 2016-01-20
US20170161095A1 (en) 2017-06-08
KR20170031708A (ko) 2017-03-21
IL249697B (en) 2020-01-30

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