KR102283059B1 - Semiconductor package and method of manufacturing the same - Google Patents

Abstract

A technical idea of the present disclosure is to provide a semiconductor package mounted on a circuit board, comprising: a body including a semiconductor chip and having first and second surfaces opposite to each other; and a structure including n insulating layers stacked on at least one of the first surface and the second surface of the body part, wherein the semiconductor package has a predetermined target coefficient of thermal expansion, and the n The insulating layer and the body portion have a thickness and a CTE satisfying a condition that the effective CTE of the semiconductor package is equal to the predetermined target CTE.

Description

Semiconductor package and its manufacturing method {SEMICONDUCTOR PACKAGE AND METHOD OF MANUFACTURING THE SAME}

The technical idea of the present disclosure relates to a semiconductor package and a manufacturing method thereof, and more particularly, to a wafer level semiconductor package having improved reliability and a manufacturing method thereof.

In general, a semiconductor package is manufactured by performing a semiconductor package process on semiconductor chips manufactured by performing various semiconductor processes on a wafer. Recently, in order to reduce the production cost of a semiconductor package, a wafer level package technology in which a semiconductor package process is performed at the wafer level and the semiconductor package at the wafer level that has undergone the semiconductor package process is individualized into individual units has been proposed.

In recent years, in accordance with the trend of light, thin and compact electronic devices, semiconductor packages are becoming smaller and thinner. In the case of a thin semiconductor package, there is a problem in that warpage occurs due to a difference in coefficient of thermal expansion between the semiconductor package and the circuit board on which the semiconductor package is mounted. Since the warpage phenomenon causes mechanical defects and electrical defects of the semiconductor package and/or the semiconductor module including the semiconductor package, various attempts have been made to suppress the warpage phenomenon of the semiconductor package and/or the semiconductor module.

SUMMARY The problem to be solved by the technical spirit of the present disclosure is to provide a semiconductor package with improved reliability and a manufacturing method thereof.

In order to solve the above problems, the technical idea of the present disclosure is to provide a semiconductor package mounted on a circuit board, comprising: a body portion including a semiconductor chip and having first and second surfaces opposite to each other; and a structure including n insulating layers (n is an integer greater than or equal to 2 and less than or equal to 100) stacked on at least one of the first surface and the second surface of the body part; With the determined target coefficient of thermal expansion (CTE), the semiconductor package has an effective CTE calculated using the following equation (1),

..............식(1)

...............Equation (1)

In Equation (1), A denotes the thickness of the body part, B denotes the CTE of the body part, Cn denotes the thickness of the n-th insulating layer belonging to the n insulating layers, and Dn denotes the n insulating layers. represents the CTE of an n-th insulating layer belonging to , wherein the n insulating layers and the body portion have a thickness and a CTE satisfying a condition that the effective CTE of the semiconductor package is equal to the predetermined target CTE, providing a semiconductor package do.

In example embodiments, the target CTE is between 60% and 90% of the CTE of the circuit board.

In exemplary embodiments, the structure includes a first insulating layer and a second insulating layer sequentially stacked on the first surface of the body portion, and a first conductive layer covered by the first insulating layer and the second insulating layer redistribution pattern; a first conductive redistribution pattern covered by the first insulating layer and the second insulating layer; and a third insulating layer covering the second surface of the body part.

In example embodiments, the body part further includes a molding layer covering a side surface of the semiconductor chip.

In example embodiments, the structure includes a first redistribution structure provided on the first surface of the body portion and a second redistribution structure provided on the second surface of the body portion, and the first redistribution structure The structure may include: a first insulating layer and a second insulating layer sequentially stacked on the first surface of the body part; and a first conductive redistribution pattern covered by the first insulating layer and the second insulating layer, wherein the second redistribution structure includes a fourth insulating layer sequentially stacked on the second surface of the body part. layer and a fifth insulating layer; and a second conductive redistribution pattern covered by the fourth insulating layer and the fifth insulating layer, wherein at least a portion of the body portion is covered by the molding layer, and the first conductive redistribution pattern and the second conductive redistribution pattern are covered by the molding layer. The display device further includes a frame including through electrodes electrically connecting the conductive redistribution patterns.

In example embodiments, the structure is an interposer, and the semiconductor chip is mounted on the interposer in a flip-chip manner.

In addition, in order to solve the above problems, the technical idea of the present disclosure is to determine a target CTE of a semiconductor package; determining a thickness and CTE of the body portion including the semiconductor chip; and n insulating layers (n is an integer greater than or equal to 2 and less than or equal to 100) laminated on at least one of the first and second surfaces of the body portion opposite to each other, each of the n insulating layers and determining the thickness and CTE of each of the n insulating layers, wherein the determining of the thickness and CTE of each of the n insulating layers includes the effective CTE of the semiconductor package calculated using the following equation (1) with the predetermined target CTE Adjusting the thickness and CTE of each of the n insulating layers to satisfy the same condition,

........ 식(1)

......... Equation (1)

In Equation (1), A denotes the thickness of the body part, B denotes the CTE of the body part, Cn denotes the thickness of the n-th insulating layer belonging to the n insulating layers, and Dn denotes the n insulating layers. It provides a method of manufacturing a semiconductor package showing the CTE of the n-th insulating layer belonging to.

In exemplary embodiments, the step of determining the CTE of each of the n insulating layers further includes adjusting the content of a filler contained in each insulating layer to adjust the CTE of each of the n insulating layers, , the content of the filler is between 0wt% and 88wt%.

In exemplary embodiments, the step of determining the CTE of each of the n insulating layers further includes adjusting the size of a filler contained in each insulating layer to adjust the CTE of each of the n insulating layers, , the size of the filler is greater than 0 micrometers and less than or equal to 10 micrometers.

In exemplary embodiments of the present disclosure, since the semiconductor package has a CTE equivalent to or similar to that of the circuit board on which the semiconductor package is mounted, deformation such as warpage caused by the difference in CTE between the semiconductor package and the circuit board can be suppressed. It is possible to prevent damage to the semiconductor package due to such deformation, damage to an external connection terminal connecting the semiconductor package to the circuit board, and the like. Accordingly, the reliability of the semiconductor package and the semiconductor module including the semiconductor package may be improved.

1 is a cross-sectional view illustrating a semiconductor package according to example embodiments of the present disclosure.
2 is a flowchart illustrating a method of manufacturing a semiconductor package according to exemplary embodiments of the present disclosure.
3 is a flowchart exemplarily illustrating step S200 of FIG. 2 .
4 is a cross-sectional view illustrating a semiconductor package according to example embodiments of the present disclosure.
5 is a cross-sectional view illustrating a semiconductor package according to example embodiments of the present disclosure.
6 is a cross-sectional view illustrating a semiconductor package according to example embodiments of the present disclosure.
7 is a cross-sectional view illustrating a semiconductor package according to example embodiments of the present disclosure.

Hereinafter, exemplary embodiments of the present disclosure will be described in detail with reference to the accompanying drawings. However, exemplary embodiments of the present disclosure may be modified in various other forms, and the scope of the present disclosure should not be construed as being limited by the embodiments described below. It is preferred that the exemplary embodiments of the present disclosure are provided to more fully explain the concepts of the present disclosure to those of ordinary skill in the art. The same symbols refer to the same elements from beginning to end. Furthermore, various elements and regions in the drawings are schematically drawn. Accordingly, the concept of the present disclosure is not limited by the relative size or spacing drawn in the accompanying drawings.

Terms such as first, second, etc. may be used to describe various elements, but the elements are not limited by the terms. The above terms are used only for the purpose of distinguishing one component from another. For example, without departing from the scope of the present disclosure, a first component may be referred to as a second component, and conversely, the second component may be referred to as a first component.

The terminology used in the present disclosure is used only to describe specific embodiments, and is not intended to limit the concept of the present disclosure. The singular expression includes the plural expression unless the context clearly dictates otherwise. In the present application, expressions such as “comprises” or “have” are intended to designate that a feature, number, step, operation, component, part, or combination thereof described in the specification is present, but one or more other features or It should be understood that the existence or addition of numbers, operations, components, parts or combinations thereof is not precluded in advance.

Unless defined otherwise, all terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which the concepts of this disclosure belong, including technical and scientific terms. Also, commonly used terms as defined in the dictionary should be construed as having a meaning consistent with what they mean in the context of the relevant technology, and unless explicitly defined herein, in an overly formal sense. It will be understood that they should not be construed.

1 is a cross-sectional view illustrating a semiconductor package 10 according to example embodiments of the present disclosure.

Referring to FIG. 1 , a semiconductor package 10 includes a first body part 100 including a first semiconductor chip 110 , and a first body part 100 provided on a first surface 108 of the first body part 100 . A redistribution structure 210 may be included. The semiconductor package 10 may be, for example, a semiconductor package having a Fan-In Wafer Level Package (FIWLP) structure.

In example embodiments, the first semiconductor chip 110 may be, for example, a memory semiconductor chip. The memory first semiconductor chip 110 may be, for example, a volatile memory semiconductor chip such as dynamic random access memory (DRAM) or static random access memory (SRAM), phase-change random access memory (PRAM), or magnetoresistive (MRAM). It may be a non-volatile memory semiconductor chip, such as a random access memory), a ferroelectric random access memory (FeRAM), or a resistive random access memory (RRAM). Alternatively, in example embodiments, the first semiconductor chip 110 may be a logic chip. For example, the first semiconductor chip 110 may be a central processor unit (CPU), a micro processor unit (MPU), a graphic processor unit (GPU), or an application processor (AP). A plurality of individual devices of various types may be formed on the first semiconductor chip 110 .

The first semiconductor chip 110 may include a front side and a back side opposite to each other. The front surface of the first semiconductor chip 110 may be a pad surface on which the chip pad 111 is provided. The chip pad 111 may be electrically connected to the semiconductor device formed on the first semiconductor chip 110 . In example embodiments, the front surface of the first semiconductor chip 110 may constitute the first surface 108 of the first body part 100 and may be in contact with the first redistribution structure 210 . Although not specifically illustrated, a passivation layer is formed on the front surface of the first semiconductor chip 110 , and the passivation layer may cover the front surface and include an opening exposing the chip pad 111 .

Also, although the semiconductor package 10 is illustrated as including one semiconductor chip in FIG. 1 , the semiconductor package 10 may include two or more semiconductor chips. For example, the first semiconductor chip 110 may be a chip stack in which two or more semiconductor chips are vertically stacked. The two or more semiconductor chips included in the semiconductor package 10 may be semiconductor chips of the same type or different types of semiconductor chips.

The first redistribution structure 210 is provided on the first surface 108 of the first body part 100 and may be a structure formed through a redistribution process. The first redistribution structure 210 may include a first redistribution insulating layer 211 and a first conductive redistribution pattern 213 .

The first redistribution insulating layer 211 may include a plurality of insulating layers sequentially stacked on the first surface 108 of the first body part 100 . For example, the first redistribution insulating layer 211 includes a first insulating layer 2111 and a second insulating layer 2113 sequentially stacked on the first surface 108 of the first body part 100 . can do. In example embodiments, each of the first insulating layer 2111 and the second insulating layer 2113 may have the same planar area as the first body part 100 . Unlike that illustrated in FIG. 1 , the first redistribution insulating layer 211 may have a structure in which one insulating layer or three or more insulating layers are stacked.

Each of the first insulating layer 2111 and the second insulating layer 2113 may be formed of an insulating polymer, an epoxy, or a combination thereof. For example, each of the first insulating layer 2111 and the second insulating layer 2113 may be formed from a material film made of an organic polymer material. For example, each of the first insulating layer 2111 and the second insulating layer 2113 may be formed of a material layer including a photosensitive material or a material layer including a non-photosensitive material. For example, each of the first insulating layer 2111 and the second insulating layer 2113 may be formed of photosensitive polyimide (PSPI) or non-photosensitive polyimide. Alternatively, each of the first insulating layer 2111 and the second insulating layer 2113 may include an oxide or a nitride. For example, each of the first insulating layer 2111 and the second insulating layer 2113 may include silicon oxide or silicon nitride.

The first insulating layer 2111 and the second insulating layer 2113 may be formed of the same material or different materials. Also, the first insulating layer 2111 and the second insulating layer 2113 may have the same coefficient of thermal expansion (CTE) or different CTEs. The CTE of each of the first insulating layer 2111 and the second insulating layer 2113 is the type of the polymer material film constituting the insulating layer or the type of filler contained in the polymer material film constituting the insulating layer. It can be adjusted by size and/or content. For example, the insulating layer may include a polymer material film and an inorganic filler contained in the polymer material film. In this case, in order to lower the CTE of the insulating layer, the content or size of the inorganic filler added to the polymer material film may be increased. Alternatively, in order to increase the CTE of the insulating layer, the content or size of the inorganic filler added to the polymer material layer may be decreased.

In example embodiments, the insulating layer includes a filler contained in a base material film made of a non-photosensitive material, and the size (or diameter) of the filler may be greater than 0 micrometers (μm) and less than or equal to 10 μm. In exemplary embodiments, the content of the filler may be between 0wt% and 88wt%.

The first conductive redistribution pattern 213 may be covered by the first redistribution insulating layer 211 . The first conductive redistribution pattern 213 may electrically connect the chip pad 111 of the first semiconductor chip 110 and the external connection terminal 290 . For example, the first conductive redistribution pattern 213 may include a first conductive pattern 2131 and a second conductive pattern 2133 .

The first conductive pattern 2131 includes a line pattern interposed between the first insulating layer 2111 and the second insulating layer 2113 and extending in a horizontal direction along the surface of the first insulating layer 2111, and a first semiconductor A via pattern extending through the opening of the first insulating layer 2111 configured to open the chip pad 111 of the chip 110 may be included. The via pattern of the first conductive pattern 2131 extends along the sidewall of the first insulating layer 2111 formed by the opening of the first insulating layer 2111 , and forms the line pattern of the first conductive pattern 2131 with the first It may be electrically connected to the chip pad 111 of the semiconductor chip 110 . The second conductive pattern 2133 may be physically/electrically connected to the first conductive pattern 2131 through the opening of the second insulating layer 2113 configured to partially open the first conductive pattern 2131 . For example, a portion of the second conductive pattern 2133 extends along a sidewall of the second insulating layer 2113 formed by the opening of the second insulating layer 2113 , and another portion of the second conductive pattern 2133 . may extend along the lower surface of the second insulating layer 2113 .

In example embodiments, the second conductive pattern 2133 functions as an external connection pad, and may be, for example, an under bump metal (UBM). An external connection terminal 290 may be disposed on the second conductive pattern 2133 .

The external connection terminal 290 may be, for example, a solder ball or a solder bump. The external connection terminal 290 may be electrically connected to the chip pad 111 of the first semiconductor chip 110 through the first conductive redistribution pattern 213 of the first redistribution structure 210 . In addition, when the semiconductor package 10 is mounted on the circuit board, the external connection terminal 290 is connected to the board pad of the circuit board, and may be configured to physically/electrically connect the semiconductor package 10 and the circuit board. there is. However, in some exemplary embodiments, the second conductive pattern 2133 may be omitted, and in this case, the external connection terminal 290 is the first conductive pattern ( 2133 ) exposed through the opening of the second insulating layer 2113 . 2131) may be directly connected to the phase.

For example, each of the first conductive pattern 2131 and the second conductive pattern 2133 may include copper (Cu), aluminum (Al), tungsten (W), titanium (Ti), tantalum (Ta), and indium (In). , molybdenum (Mo), manganese (Mn), cobalt (Co), tin (Sn), nickel (Ni), magnesium (Mg), rhenium (Re), beryllium (Be), gallium (Ga), ruthenium (Ru) , or a combination thereof. Each of the first conductive pattern 2131 and the second conductive pattern 2133 may be formed of the same material or different materials.

The semiconductor package 10 may include a third insulating layer 220 provided on the second surface 109 opposite to the first surface 108 of the first body portion 100 . The third insulating layer 220 may be, for example, a protective layer configured to cover and protect the rear surface of the first semiconductor chip 110 . In example embodiments, the third insulating layer 220 may have the same planar area as the first body part 100 .

In the present embodiment, the semiconductor package 10 includes a first body portion 100 and a structure provided on at least one surface of the first surface 108 and the second surface 109 of the first body portion 100 . It can be defined as including (200). The structure 200 of the semiconductor package 10 may be defined as including other structures of the semiconductor package 10 excluding the first body portion 100 . At this time, the structure 200 has n insulating layers (n is 2 or more and 100 or less) stacked on at least one surface of the first surface 108 and the second surface 109 of the first body part 100 . integer) may be included. For example, in the semiconductor package 10 illustrated in FIG. 1 , the structure 200 includes a first insulation layer 2111 and a second insulation layer 2113 of the first redistribution structure 210 , and a third insulation layer 220 .

At this time, at least one of the thickness 100T and CTE of the first body portion 100 of the semiconductor package 10 , and the first surface 108 and the second surface 109 of the first body portion 100 . Based on the thickness and CTE of each of the insulating layers stacked on the surface, an effective CTE representing the actual CTE of the semiconductor package 10 may be calculated. Specifically, the effective CTE of the semiconductor package 10 may be calculated using Equation (1) below.

..............식(1)

...............Equation (1)

In Equation (1), A is the thickness 100T of the first body portion 100 , B is the CTE of the first body portion 100 , and Cn is the n-th insulation belonging to the n insulating layers of the structure 200 . The thickness of the layer, Dn, represents the CTE of the nth insulating layer belonging to the n insulating layers of the structure 200 . Here, the thickness of one component is a thickness in a vertical direction, and may mean, for example, an average thickness in a direction perpendicular to the front surface of the first semiconductor chip 100 .

In some exemplary embodiments, in calculating the effective CTE of the semiconductor package 10 , in addition to the insulating layers of the first body portion 100 and the structure 200 , other components included in the structure 200 , For example, the first conductive redistribution pattern 213 may be further used.

In the present embodiment, the effective CTE of the semiconductor package 10 calculated by Equation (1) may be adjusted to have a value equal to or close to the CTE of the circuit board on which the semiconductor package 10 is mounted. Here, the circuit board may be, for example, a printed circuit board (PCB), but is not limited thereto. For example, the circuit board may be a circuit board such as a metal core PCB (MCPCB), a metal PCB (MPCB), or a flexible PCB (FPCB).

For example, the effective CTE of the semiconductor package 10 calculated by Equation (1) above may satisfy a condition that is equal to the predetermined target CTE of the semiconductor package 10 . For example, the thickness 100T and CTE of the first body portion 100 of the semiconductor package 10 and the first body portion ( The thickness and CTE of each of the insulating layers stacked on at least one of the first surface 108 and the second surface 109 of 100 may be adjusted.

The target CTE of the semiconductor package 10 may be determined based on the CTE of the circuit board on which the semiconductor package 10 is mounted. The target CTE may be between 50% and 150% of the CTE of the circuit board. In example embodiments, the target CTE may be determined as a value between 60% and 90% of the CTE of the circuit board. For example, when the CTE of the circuit board is 17 ppm/K, the target CTE may be determined to be a value between 10.2 ppm/K and 15.3 ppm/K.

In this embodiment, the semiconductor package 10 may have a CTE equivalent to or similar to that of the circuit board. Since deformation such as warpage caused by the CTE difference between the semiconductor package 10 and the circuit board can be suppressed, damage to the semiconductor package 10 due to such deformation and the semiconductor package 10 are connected to the circuit board damage to the external connection terminal 290 can be prevented. Accordingly, ultimately, the reliability of the semiconductor package 10 and the semiconductor module including the semiconductor package 10 may be improved.

2 is a flowchart illustrating a method of manufacturing a semiconductor package according to exemplary embodiments of the present disclosure. Hereinafter, a method of manufacturing the semiconductor package 10 according to exemplary embodiments of the present disclosure will be described with reference to FIGS. 1 and 2 .

1 and 2 , in the method of manufacturing the semiconductor package 10 according to exemplary embodiments of the present disclosure, in the step of determining a target CTE ( S100 ), the effective CTE of the semiconductor package 10 is determined in advance. The method may include adjusting the effective CTE of the semiconductor package 10 to satisfy a condition equal to the target CTE ( S200 ), and performing a wafer level packaging process ( S300 ).

First, in step S100 , the target CTE may be predetermined based on the CTE of the circuit board on which the semiconductor package 10 is mounted. In example embodiments, the target CTE may be determined as a value between 60% and 90% of the CTE of the circuit board.

Next, in the step S200 , the thickness 100T and CTE of the first body portion 100 of the semiconductor package 10 , and the first surface 108 and the second surface 109 of the first body portion 100 . ), the effective CTE of the semiconductor package 10 may be calculated based on the thickness and CTE of each of the insulating layers stacked on the surface of at least one. In the step S200 , the thickness 100T and CTE of the first body part 100 and the thickness of each of the insulating layers of the structure 200 so that the effective CTE of the semiconductor package 10 is equal to the predetermined target CTE and CTE.

Next, in step S300 , the semiconductor package 10 may be manufactured to satisfy the condition determined in step S200 . That is, the semiconductor package 10 may be manufactured to have the determined thickness 100T and CTE of the first body portion 100 and the determined thickness and CTE of each of the insulating layers of the structure 200 .

3 is a flowchart exemplarily illustrating step S200 of FIG. 2 .

1 to 3 , in exemplary embodiments of the present disclosure, the step S200 includes determining the thickness 100T and the CTE of the first body part 100 ( S210 ), the structure 200 . first determining the thickness and CTE of each of the insulating layers ( S220 ), calculating the effective CTE of the semiconductor package 10 , and whether the calculated effective CTE of the semiconductor package 10 is the same as the predetermined target CTE determining (S230), and adjusting the thickness and CTE of each of the insulating layers of the structure 200 to satisfy the condition that the calculated effective CTE of the semiconductor package 10 becomes equal to the predetermined target CTE (S240) ) may be included.

In step S210 , when the first body part 100 includes only the first semiconductor chip 110 like the semiconductor package 10 illustrated in FIG. 1 , the thickness 100T of the first body part 100 and The CTE may be determined by the thickness and CTE of the first semiconductor chip 110 .

In the step S220 , the thickness and CTE of each of the first insulating layer 2111 to the third insulating layer 2111 , 2113 , and 220 are primarily determined. In some example embodiments, the thicknesses 2111T, 2113T, and 220T of the first to third insulating layers 2111 , 2113 , and 220 may be of the first to third insulating layers 2111 , 2113 , 220 . The sum of the thicknesses 2111T, 2113T, and 220T and the thickness of the first body part 100 may be determined to be equal to a predetermined target thickness of the semiconductor package 10 .

In step S230, based on the determined thickness 100T and CTE of the first body portion 100, and the determined thickness and CTE of each of the first to third insulating layers 2111, 2113, and 220, the semiconductor package 10 Calculate the effective CTE. It may be determined whether the calculated effective CTE of the semiconductor package 10 is equal to the target CTE. Here, determining whether the calculated effective CTE of the semiconductor package 10 and the target CTE are the same may include: Determining whether the effective CTE of (10) has the same value as the predetermined target CTE or a value within an error range, or whether the calculated effective CTE of the semiconductor package 10 is within an allowable range of the predetermined target CTE may include judging

When it is determined that the effective CTE of the semiconductor package 10 calculated in step S230 is different from the target CTE, the insulating layers of the structure 200 satisfy the condition that the effective CTE of the semiconductor package 10 is equal to the target CTE. A step ( S240 ) of adjusting each thickness and CTE may be performed.

In operation S240 , the thickness and CTE of each of the insulating layers of the structure 200 may be adjusted so that the effective CTE of the semiconductor package 10 satisfies a condition that is equal to the target CTE.

In example embodiments, in operation S240 , the thickness of each of the insulating layers of the structure 200 may be adjusted so that the thickness of the semiconductor package 10 satisfies a predetermined target thickness. That is, in the semiconductor package 10 illustrated in FIG. 1 , the thickness of each of the first to third insulating layers 2111 , 2113 , 220 is the thickness of the first to third insulating layers 2111 , 2113 , 220 ( 2111T, 2113T, and 220T) and the thickness of the first body part 100 may be adjusted to satisfy a condition that is equal to a predetermined target thickness of the semiconductor package 10 .

In example embodiments, operation S240 may include adjusting the CTE of each of the insulating layers of the structure 200 such that the effective CTE of the semiconductor package 10 satisfies a condition that is equal to the target CTE. For example, in order to adjust the CTE of each of the insulating layers of the structure 200 , a material constituting each of the insulating layers of the structure 200 may be changed. For example, in order to adjust the CTE of each of the insulating layers of the structure 200 , the type, size, and/or content of the filler added to the polymer material film constituting the insulating layer may be adjusted. For example, the CTE of the insulating layer may be adjusted by adding an inorganic filler to the polymer material film constituting the insulating layer. For example, in order to lower the CTE of the insulating layer, the content of the inorganic filler added to the insulating layer may be increased.

If it is determined that the calculated effective CTE of the semiconductor package 10 is equal to the target CTE in step S230, a wafer level packaging process may be performed to satisfy the determined condition (S300). Through the wafer level packaging process, the semiconductor package 10 may be manufactured such that the insulating layers of the first body part 100 and the structure 200 have the previously determined thickness and CTE.

The following [Table 1] shows the thickness and CTE of the first semiconductor chip 110 determined through step S200 for the semiconductor package 10 illustrated in FIG. 1 , and the first to third insulating layers 2111, 2113, and 220 ) each thickness and CTE are exemplarily shown.

Thickness (㎛) CTE (ppm/K) first insulating layer 2111 10 40 second insulating layer 2113 30 33 first semiconductor chip 110 300 2.6 third insulating layer 220 50 60

First, in step S210 , as shown in Table 1 above, since the first body part 100 includes only the first semiconductor chip 110 , the thickness 100T of the first body part 100 is the first semiconductor chip. The thickness of 110 may be 300 μm, and the CTE of the first body part 100 may be 2.6 ppm/K, which is the CTE of the first semiconductor chip 110 . And, in step S220 , the thickness 2111T and CTE of the first insulating layer 2111 are determined to be 30 μm and 40 ppm/K, respectively, and the thickness 2113T and CTE of the second insulating layer 2113 are 30 μm, respectively. and 33 ppm/K, and the thickness 220T and CTE of the third insulating layer 220 may be determined to be 50 μm and 60 ppm/K, respectively. When the semiconductor package 10 satisfies the conditions of [Table 1], the effective CTE of the semiconductor package 10 obtained using Equation (1) is 13.3 ppm/K, which is close to the CTE of the circuit board. can be checked

In the present embodiment, components constituting the semiconductor package 10 to satisfy the condition that the effective CTE of the semiconductor package 10 is equal to the target CTE set based on the CTE of the circuit board on which the semiconductor package 10 is mounted. Their thickness and/or CTE can be designed. Accordingly, the semiconductor package 10 capable of improving reliability by suppressing warpage-like deformation can be manufactured.

4 is a cross-sectional view illustrating a semiconductor package 10a according to example embodiments of the present disclosure.

The semiconductor package 10a shown in FIG. 4 is similar to that described in FIG. 1 except that the first body part 100 further includes the first molding layer 120 and the third insulating layer 220 is omitted. It may be substantially the same as or similar to the semiconductor package 10 . Descriptions overlapping with those described above will be omitted or simplified.

Referring to FIG. 4 , the semiconductor package 10a includes a first body part 100 including a first semiconductor chip 110 and a first molding layer 120 , and a first surface of the first body part 100 . The first redistribution structure 210 provided on the 108 may be included. The semiconductor package 10a may be, for example, a semiconductor package having a Fan-Out Wafer Level Package (FOWLP) structure.

The first molding layer 120 of the first body part 100 may cover at least a portion of the first semiconductor chip 110 . As illustrated in FIG. 4 , the first molding layer 120 may cover the side surface of the first semiconductor chip 110 and cover the rear surface of the first semiconductor chip 110 . In other exemplary embodiments, the first molding layer 120 may be formed to cover the side surface of the first semiconductor chip 110 but not to cover the rear surface of the first semiconductor chip 110 .

For example, the first molding layer 120 may be formed of an epoxy molding compound. Of course, the first molding layer 120 is not limited to the epoxy molding compound and may be formed of various materials, for example, an epoxy-based material, a thermosetting material, a thermoplastic material, a UV treatment material, and the like.

In example embodiments, the CTE of the first body part 100 may be detected through simulation or experimentation. In example embodiments, the CTE of the first body part 100 may be between 3 ppm/K and 15 ppm/K.

In example embodiments, in the step of determining the CTE of the first body part 100 , in order to adjust the CTE of the first body part 100 , a material constituting the first molding layer 120 is changed or , the type of the polymer material film constituting the first molding layer 120 , or the type of filler contained in the polymer material film constituting the first molding layer 120 . It can be adjusted by size and/or content. For example, the first molding layer 120 may include a polymer material layer and an inorganic filler contained in the polymer material layer. In this case, in order to lower the CTE of the first molding layer 120 , the content of the inorganic filler added to the polymer material layer may be increased. Alternatively, in order to increase the CTE of the first molding layer 120 , the content of the inorganic filler added to the polymer material layer may be decreased.

In this embodiment, the structure 200 of the semiconductor package 10a may be defined as including the first redistribution structure 210 on the first surface 108 of the first body portion 100 . The structure 200 may include a first insulating layer 2111 and a second insulating layer 2113 stacked on the first surface 108 of the first body part 100 . In this case, the effective CTE of the semiconductor package 10a may be calculated based on the thickness and CTE of the first body part 100 and the thickness and CTE of each of the first and second insulating layers 2111 and 2113 .

5 is a cross-sectional view illustrating a semiconductor package 10b according to example embodiments of the present disclosure.

The semiconductor package 10b shown in FIG. 5 is described in FIG. 4 except that the first body part 100 further includes the frame 130 and the second redistribution structure 230 is further included. It may be substantially the same as or similar to the semiconductor package 10a. Descriptions overlapping with those described above will be omitted or simplified.

Referring to FIG. 5 , the first body part 100 may further include a frame 130 provided around the first semiconductor chip 110 . The frame 130 may be integrated with the first semiconductor chip 110 by the first molding layer 120 . For example, the frame 130 may have a ring shape extending along the side surface of the first semiconductor chip 110 to surround the side surface of the first semiconductor chip 110 . Alternatively, a plurality of frames 130 spaced apart from each other may be provided in the first body portion 100 . As shown in FIG. 5 , the side surface of the frame 130 may be exposed to the outside. In other exemplary embodiments, the side surface of the frame 130 may be covered by the first molding layer 120 .

In example embodiments, the frame 130 may include a frame body 131 and a through electrode 133 . The frame body 131 may include, for example, an insulating material. For example, the frame body 131 may include silicon, ceramic, plastic, polymer, glass, or the like. The through electrode 133 may pass through the frame body 131 . The through electrode 133 may include a conductive material. For example, the through electrode 133 may include a metal material such as copper (Cu), aluminum (Al), tungsten (W), or doped polysilicon. The through electrode 133 may electrically connect the first conductive redistribution pattern 213 of the first redistribution structure 210 and the second conductive redistribution pattern 233 of the second redistribution structure 230 to each other.

In example embodiments, the CTE of the first body part 100 may be detected through simulation or experimentation. In example embodiments, the CTE of the first body part 100 may be between 4 ppm/K and 15 ppm/K.

In example embodiments, in the step of determining the CTE of the first body part 100 , a material constituting the frame 130 may be changed to adjust the CTE of the first body part 100 .

The second redistribution structure 230 is provided on the second surface 109 of the first body part 100 and may be a structure formed through a redistribution process. The second redistribution structure 230 may include a second redistribution insulating layer 231 and a second conductive redistribution pattern 233 .

The second redistribution insulating layer 231 may include a plurality of insulating layers sequentially stacked on the second surface 109 of the first body part 100 . For example, the second redistribution insulating layer 231 includes a fourth insulating layer 2311 and a fifth insulating layer 2313 sequentially stacked on the second surface 109 of the first body part 100 . can do. In example embodiments, each of the fourth insulating layer 2311 and the fifth insulating layer 2313 may have the same planar area as the first body part 100 . 5 , the second redistribution insulating layer 231 may have a structure in which one insulating layer or three or more insulating layers are stacked.

Each of the fourth insulating layer 2311 and the fifth insulating layer 2313 may be formed of an insulating polymer, epoxy, or a combination thereof. For example, each of the fourth insulating layer 2311 and the fifth insulating layer 2313 may be formed from a material film made of an organic polymer material. For example, each of the fourth insulating layer 2311 and the fifth insulating layer 2313 may be formed of a material layer including a photosensitive material or a material layer including a non-photosensitive material. For example, each of the fourth insulating layer 2311 and the fifth insulating layer 2313 may be formed of photosensitive polyimide or non-photosensitive polyimide. Alternatively, each of the fourth insulating layer 2311 and the fifth insulating layer 2313 may include an oxide or a nitride. The fourth insulating layer 2311 and the fifth insulating layer 2313 may be formed of the same material or different materials.

The second conductive redistribution pattern 233 may be covered by the second redistribution insulating layer 231 . The second conductive redistribution pattern 233 is the chip of the first semiconductor chip 110 through the through electrode 133 of the frame 130 and the first conductive redistribution pattern 213 of the first redistribution structure 210 . It may be electrically connected to the pad 111 . For example, the second conductive redistribution pattern 233 may include a third conductive pattern 2331 and a fourth conductive pattern 2333 .

The third conductive pattern 2331 includes a line pattern interposed between the fourth insulating layer 2311 and the fifth insulating layer 2313 and extending in a horizontal direction along the surface of the fourth insulating layer 2311, and a through electrode ( A via pattern extending through the opening of the fourth insulating layer 2311 configured to open the upper end of the 133 may be included. The via pattern of the third conductive pattern 2331 extends along the sidewall of the fourth insulating layer 2311 formed by the opening of the fourth insulating layer 2311 , and passes the line pattern of the third conductive pattern 2331 through the through electrode. (133) can be electrically connected. The fourth conductive pattern 2333 may be physically/electrically connected to the third conductive pattern 2331 through the opening of the fifth insulating layer 2313 configured to partially open the third conductive pattern 2331 . For example, a part of the fourth conductive pattern 2333 extends along a sidewall of the fifth insulating layer 2313 formed by the opening of the fifth insulating layer 2313 , and another part of the fourth conductive pattern 2333 . may extend along the upper surface of the fifth insulating layer 2313 . In example embodiments, the fourth conductive pattern 2333 functions as an external connection pad and may be, for example, an under bump metal. An external connection terminal 290 may be disposed on the fourth conductive pattern 2333 .

For example, each of the third conductive pattern 2331 and the fourth conductive pattern 2333 may include copper (Cu), aluminum (Al), tungsten (W), titanium (Ti), tantalum (Ta), and indium (In). , molybdenum (Mo), manganese (Mn), cobalt (Co), tin (Sn), nickel (Ni), magnesium (Mg), rhenium (Re), beryllium (Be), gallium (Ga), ruthenium (Ru) , or a combination thereof. Each of the third conductive pattern 2331 and the fourth conductive pattern 2333 may be formed of the same material or different materials.

In the present embodiment, the structure 200 of the semiconductor package 10b includes a first redistribution structure 210 on the first surface 108 of the first body portion 100 and the second structure 200 of the first body portion 100 . It may be defined as including the second redistribution structure 230 on the surface 109 . The structure 200 includes a first insulating layer 2111 and a second insulating layer 2113 sequentially stacked on the first surface 108 of the first body part 100 , and the second insulating layer of the first body part 100 . A fourth insulating layer 2311 and a fifth insulating layer 2313 sequentially stacked on the two surfaces 109 may be included. In this case, the effective CTE of the semiconductor package 10b is the thickness and CTE of the first body portion 100 , the thickness and CTE of each of the first and second insulating layers 2111 and 2113 , and the fourth and fifth insulating layers (2311, 2313) can be calculated based on the thickness and CTE, respectively.

6 is a cross-sectional view illustrating a semiconductor package 10c according to example embodiments of the present disclosure.

Referring to FIG. 6 , the semiconductor package 10c may be a semiconductor package having a package on package structure in which an upper package 101U is stacked on a lower package 101L. For example, the upper package 101U may be stacked on the lower package 101L through the inter-package connection terminal 295 .

The lower package 101L may include a first body portion 100 , a first redistribution structure 210 , and a second redistribution structure 230 . Since the lower package 101L may be substantially the same as or similar to the semiconductor package 10b described with reference to FIG. 5 , a detailed description thereof will be omitted.

The upper package 101U includes a second body portion 100U including a second semiconductor chip 110U and a second molding layer 120U, and a third redistribution structure ( 240) may be included.

The second semiconductor chip 110U may be a semiconductor chip of the same type as the first semiconductor chip 110 included in the lower package 101L, or a semiconductor chip of a different type. The second molding layer 120U may be formed to cover at least a portion of the second semiconductor chip 110U. The second semiconductor chip 110U and the second molding layer 120U may constitute the second body portion 100U.

The third redistribution structure 240 includes a third redistribution insulating layer 241 including a sixth insulating layer 2411 and a seventh insulating layer 2413 sequentially stacked on the lower surface of the second body portion 100U. , and a third conductive redistribution pattern 243 covered by the third redistribution insulating layer 241 . The third conductive redistribution pattern 243 is interposed between the sixth insulating layer 2411 and the seventh insulating layer 2413 and is a chip pad of the second semiconductor chip 110U through the opening of the sixth insulating layer 2411 . The fifth conductive pattern 2431 electrically connected to the 111U, and the sixth conductive pattern connected to the fifth conductive pattern 2431 through the opening of the seventh insulating layer 2413 and connected to the inter-package connection terminal 295 (2433). The third conductive redistribution pattern 243 may electrically connect the chip pad 111U of the second semiconductor chip 110U to the inter-package connection terminal 295 .

In the present embodiment, the semiconductor package 10c includes a first body portion 100 and a second body portion 100U, and the structure 200 of the semiconductor package 10c includes a first redistribution structure 210 , It may be defined as including the second redistribution structure 230 and the third redistribution structure 240 . The structure 200 includes a first insulating layer 2111 , a second insulating layer 2113 , a fourth insulating layer 2311 , and a fifth insulating layer 2313 of a lower package 101L, and an upper package 101U. ) of a sixth insulating layer 2411 and a seventh insulating layer 2413 . In this case, the effective CTE of the semiconductor package 10c is the thickness and CTE of the first body portion 100 of the lower package 101L, the thickness and CTE of the second body portion 100U of the upper package 101U, and the first and the thickness and CTE of each of the second insulating layers 2111 and 2113, the thickness and CTE of each of the fourth and fifth insulating layers 2311 and 2313, and the thickness of each of the sixth and seventh insulating layers 2411 and 2413 and CTE.

7 is a cross-sectional view illustrating a semiconductor package 10d according to example embodiments of the present disclosure.

Referring to FIG. 7 , a semiconductor package 10d may include an interposer 250 and a first semiconductor chip 110 mounted on the interposer 250 . The first semiconductor chip 110 may be mounted on the interposer 250 in a flip-chip manner. That is, a chip connection terminal 113 such as a micro bump may be interposed between the first semiconductor chip 110 and the interposer 250 .

Also, the semiconductor package 10d may include a first molding layer 120 that covers at least a portion of the first semiconductor chip 110 and is filled between the first semiconductor chip 110 and the interposer 250 . A portion of the first molding layer 120 may surround the chip connection terminal 113 interposed between the first semiconductor chip 110 and the interposer 250 .

The interposer 250 may include insulating layers 2511 , 2513 , and 2515 stacked in a vertical direction, and a conductive pattern 253 covered by the insulating layers 2511 , 2513 , and 2515 . The conductive pattern 253 may electrically connect the chip connection terminal 113 and the external connection terminal 290 on the lower surface of the interposer 250 .

In this embodiment, the interposer 250 and the first molding layer 120 may constitute the first body portion 100 of the semiconductor package 10d, and the interposer 250 constitutes the structure 200 . can do. The structure 200 may include insulating layers 2511 , 2513 , and 2515 of the interposer 250 . In this case, the effective CTE of the semiconductor package 10d is calculated based on the thickness and CTE of the first body part 100 and the thickness and CTE of each of the insulating layers 2511 , 2513 , and 2515 of the interposer 250 . can be

Exemplary embodiments have been disclosed in the drawings and specification as described above. Although the embodiments have been described using specific terms in the present specification, these are only used for the purpose of explaining the technical spirit of the present disclosure, and are not used to limit the meaning or the scope of the present disclosure described in the claims. Therefore, it will be understood by those skilled in the art that various modifications and equivalent other embodiments are possible therefrom. Accordingly, the true technical protection scope of the present disclosure should be defined by the technical spirit of the appended claims.

10: semiconductor package 110: semiconductor chip
111: chip pad 210: first redistribution structure
211: first redistribution insulating layer 2111: first insulating layer
2113: second insulating layer 213: first conductive redistribution pattern
220: third insulating layer 290: external connection terminal

Claims (9)

A semiconductor package mounted on a circuit board, comprising:
a body portion including a semiconductor chip and having first and second surfaces opposite to each other; and
a structure including n insulating layers (n is an integer greater than or equal to 2 and less than or equal to 100) laminated on at least one of the first surface and the second surface of the body portion;
including,
The semiconductor package has a predetermined target coefficient of thermal expansion (Coefficient of Thermal Expansion, CTE),
The semiconductor package has an effective CTE calculated using the following equation (1),

...............Equation (1)
In Equation (1), A denotes the thickness of the body part, B denotes the CTE of the body part, Cn denotes the thickness of the n-th insulating layer belonging to the n insulating layers, and Dn denotes the n insulating layers. represents the CTE of the n-th insulating layer belonging to
The n insulating layers and the body portion have a thickness and a CTE that satisfy the condition that the effective CTE of the semiconductor package is equal to the predetermined target CTE,
A planar area of each of the n insulating layers is the same as a planar area of the body portion. The method of claim 1,
wherein the target CTE is between 60% and 90% of the CTE of the circuit board. The method of claim 1,
The structure is
a first insulating layer and a second insulating layer sequentially stacked on the first surface of the body part, and a first conductive redistribution pattern covered by the first insulating layer and the second insulating layer;
a first conductive redistribution pattern covered by the first insulating layer and the second insulating layer; and
a third insulating layer covering the second surface of the body part;
A semiconductor package comprising a. The method of claim 1,
The body portion may further include a molding layer covering a side surface of the semiconductor chip. 5. The method of claim 4,
The structure includes a first redistribution structure provided on the first surface of the body portion and a second redistribution structure provided on the second surface of the body portion,
The first redistribution structure may include: a first insulating layer and a second insulating layer sequentially stacked on the first surface of the body part; and a first conductive redistribution pattern covered by the first insulating layer and the second insulating layer;
The second redistribution structure may include: a fourth insulating layer and a fifth insulating layer sequentially stacked on the second surface of the body part; and a second conductive redistribution pattern covered by the fourth insulating layer and the fifth insulating layer;
The semiconductor package further comprising: a frame at least partially covered by the molding layer and including a through electrode for electrically connecting the first conductive redistribution pattern and the second conductive redistribution pattern. The method of claim 1,
The structure is an interposer, and the semiconductor chip is mounted on the interposer in a flip-chip manner. determining a target CTE of the semiconductor package;
determining a thickness and CTE of the body portion including the semiconductor chip; and
For a structure including n insulating layers (n is an integer greater than or equal to 2 and less than or equal to 100) laminated on at least one of the first and second surfaces of the body portion opposite to each other, each of the n insulating layers is determining the thickness and CTE;
including,
In the step of determining the thickness and CTE of each of the n insulating layers, the effective CTE of the semiconductor package calculated using the following equation (1) satisfies the condition in which the predetermined target CTE is equal to the predetermined target CTE of each of the n insulating layers. adjust thickness and CTE,

......... Equation (1)
In Equation (1), A denotes the thickness of the body part, B denotes the CTE of the body part, Cn denotes the thickness of the n-th insulating layer belonging to the n insulating layers, and Dn denotes the n insulating layers. represents the CTE of the n-th insulating layer belonging to
A planar area of each of the n insulating layers is the same as a planar area of the body portion. 8. The method of claim 7,
In the step of determining the CTE of each of the n insulating layers, further comprising the step of adjusting a content of a filler contained in each insulating layer to adjust the CTE of each of the n insulating layers, wherein the content of the filler is 0 wt. % to 88 wt%. 8. The method of claim 7,
In the step of determining the CTE of each of the n insulating layers, the method further comprising adjusting a size of a filler contained in each insulating layer to adjust the CTE of each of the n insulating layers, wherein the size of the filler is 0 A method of manufacturing a semiconductor package that is greater than or equal to 10 micrometers.

Images