KR102277758B1 - Method and apparatus for decoding in a system using binary serial concatenated code - Google Patents

Abstract

The present invention relates to a decoding method and apparatus in a system using a binary serial-connected code, and more particularly, to a decoding method and apparatus for reducing complexity in a system using a binary serial-connected code.
An apparatus according to an embodiment of the present invention performs iterative decoding using an external decoder and an internal decoder, and from a receiver of a system using a binary non-canonical iterative partial accumulation code to the internal decoder device, the bit received from the external decoder a first grouping unit for grouping columns according to decoding orders; An LLR symbol that calculates an index of grouped bits having a maximum probability value among the grouped bits, and selects and outputs a predetermined number of grouped bit LLR values using the index of the grouped bits having the maximum probability value selection part; an LLR symbol conversion unit for converting the grouped bit LLR value output from the LLR symbol selection unit into a symbol LLR value and outputting it; a BCJR processing unit that calculates the symbol LLR value using a BCJR (Bahl-Cocke-Jelinek-Raviv) algorithm; a bit LLR calculation unit converting the output of the BCJR processing unit into a bit LLR value; and a second bit grouping unit for grouping the bit LLR values in a predetermined bit unit.

Description

Decoding method and apparatus in a system using binary serial-connected codes {METHOD AND APPARATUS FOR DECODING IN A SYSTEM USING BINARY SERIAL CONCATENATED CODE}

The present invention relates to a decoding method and apparatus in a system using a binary serial-connected code, and more particularly, to a decoding method and apparatus for reducing complexity in a system using a binary serial-connected code.

As electronic technology develops, various methods for exchanging data between electronic devices are emerging. In particular, when data is transmitted and received using a wireless channel between electronic devices located at a distance, data is transmitted and received using modulation and encoding. As such, when transmitting and receiving data through a predetermined wireless channel between an electronic device, for example, a portable terminal and an electronic device such as a base station or an access point, a Gaussian assumption has been made with respect to the interference signal to operate the system with low complexity. In addition, the QAM modulation method has been used to make the characteristics of the interference signal as close to Gaussian characteristics as possible.

When comparing the environment of the Gaussian channel and the environment of the non-Gaussian channel in the wireless communication system, the non-Gaussian channel has a larger channel capacity than the Gaussian channel. As such, since the capacity of the non-Gaussian channel is larger than that of assuming a Gaussian channel, higher network throughput can be obtained in the non-Gaussian channel than in the Gaussian channel if the statistical characteristics of the interference signal are properly reflected during system operation.

Recently, as the evolution of a form capable of transmitting a larger amount of data more rapidly is required, it is necessary to develop a modulation scheme for making an interference signal have a non-Gaussian characteristic in order to increase the throughput of the system in a wireless communication system. As such, there is an FQAM method as a method proposed as a modulation method for making the channel interference characteristic have a non-Gaussian characteristic.

In addition, in order to obtain higher data throughput by applying the FQAM method, a channel encoding method suitable for the corresponding modulation method is required. In general, when a modulation method having a modulation order of the q order is used, if a coded modulation (CM) method using a non-binary channel code of the same order is applied, the channel capacity, which is a theoretical limit, can be satisfied. However, in general, there is a problem that the decoding complexity of a non-binary channel code is much more complicated than that of a binary code.

In the existing QAM-based modulation method, a performance close to the theoretical channel limit capacity can be obtained by using a bit-interleaved coded modulation (BICM) method to which Gray mapping is applied. However, in the FQAM method, the desired performance cannot be obtained when the BICM method is applied. As a method to solve this problem, a BICM-ID (BICM with Iterative Decoding) method, which is a method for performing iterative decoding between a decoder and a demodulator of a channel code, has been proposed. In the case of the FQAM method, if the BICM-ID method based on the binary irregular repeat partial accumulation (hereinafter referred to as "IRPA") code is applied, performance close to the theoretical limit can be obtained.

In this case, the BICM-ID type decoder based on the binary IRPA code may be divided into an internal decoder and an external decoder. In the receiver, a soft message is repeatedly decoded while exchanging the processed result between the internal decoder and the external decoder. The decoding method in the BICM-ID method based on the binary IRPA code configured as described above has a problem in that it has a very high complexity. For example, an external decoder that calculates a message node does not significantly affect complexity, but an internal decoder has a problem in that it has very high complexity.

Accordingly, the present invention provides an apparatus and method capable of reducing the complexity of a BICM-ID decoder based on a binary IRPA code.

In addition, the present invention provides an apparatus and method capable of reducing performance degradation while reducing the complexity of a BICM-ID decoder based on a binary IRPA code.

An apparatus according to an embodiment of the present invention performs iterative decoding using an external decoder and an internal decoder, and from a receiver of a system using a binary non-canonical iterative partial accumulation code to the internal decoder device, the bit received from the external decoder a first grouping unit for grouping columns according to decoding orders; An LLR symbol that calculates an index of grouped bits having a maximum probability value among the grouped bits, and selects and outputs a predetermined number of grouped bit LLR values using the index of the grouped bits having the maximum probability value selection part; an LLR symbol conversion unit for converting the grouped bit LLR value output from the LLR symbol selection unit into a symbol LLR value and outputting it; a BCJR processing unit that calculates the symbol LLR value using a BCJR (Bahl-Cocke-Jelinek-Raviv) algorithm; a bit LLR calculation unit converting the output of the BCJR processing unit into a bit LLR value; and a second bit grouping unit for grouping the bit LLR values in a predetermined bit unit.

An apparatus according to another embodiment of the present invention performs iterative decoding using an external decoder and an internal decoder, and from a receiver of a system using a binary non-canonical iterative partial accumulation code to the internal decoder device, the bit received from the external decoder a first grouping unit for grouping columns according to decoding orders; an LLR symbol converting unit converting the grouped bit stream into an LLR symbol; an LLR symbol cutting unit that sorts the elements of the vector of the LLR symbol-converted LLR symbols in order of magnitude and selects to output only a predetermined number of symbols in the order of LLR values; a BCJR processing unit for calculating the symbol LLR value output from the LLR symbol cutting unit using a BCJR (Bahl-Cocke-Jelinek-Raviv) algorithm; a bit LLR calculation unit converting the output of the BCJR processing unit into a bit LLR value; and a second bit grouping unit for grouping the bit LLR values in a predetermined bit unit.

A method according to an embodiment of the present invention performs iterative decoding using an external decoder and an internal decoder, and is a decoding method in the internal decoder device of a receiver of a system using a binary non-regular iterative partial accumulation code, from the external decoder grouping the received bit stream according to the decoding order; calculating an index of grouped bits having a maximum probability value among the grouped bits; selecting and outputting a predetermined number of grouped bit LLR values using the index of the grouped bits having the maximum probability value; converting the grouped bit LLR values into symbol LLR values and outputting them; calculating the symbol LLR value using a Bahl-Cocke-Jelinek-Raviv (BCJR) algorithm; converting the output of the BCJR processing unit into a bit LLR value; and grouping the bit LLR values in a predetermined bit unit.

A method according to another embodiment of the present invention performs iterative decoding using an external decoder and an internal decoder, and is a decoding method in the internal decoder device of a receiver of a system using a binary non-regular iterative partial accumulation code, from the external decoder. grouping the received bit stream according to the decoding order; converting the grouped bit stream into an LLR symbol; sorting elements of the vector of the LLR symbol-converted LLR symbols in order of magnitude, and selecting to output only a predetermined number of symbol LLR values in the order of magnitude; BCJR (Bahl-Cocke-Jelinek-Raviv) algorithm calculating the symbol LLR value output from the LLR symbol cutting unit; converting the output of the BCJR processing unit into a bit LLR value; and grouping the bit LLR values in a predetermined bit unit.

When the decoder of the BICM-ID scheme based on the binary IRPA code according to the present invention is used, complexity can be reduced, and performance degradation due to the reduction of complexity can be reduced. In addition, it is possible to implement a decoder of a parallel structure to have a high throughput.

1 is a conceptual diagram for explaining an FQAM scheme having a non-Gaussian characteristic.
2 is an internal block diagram of a binary IRPA code decoder to which an FQAM scheme can be applied according to an embodiment of the present invention.
3 is a conceptual diagram illustrating a method of truncating a symbol LLR message in an FQAM scheme according to an embodiment of the present invention.
4 is an internal block diagram of a binary IRPA code decoder to which an FQAM scheme can be applied according to another embodiment of the present invention.
5 is a conceptual diagram for explaining a method of truncating a symbol LLR message in an FQAM scheme according to an embodiment of the present invention.
6A and 6B are control flowcharts during a symbol decoding operation in a decoder according to an embodiment of the present invention.
7A and 7B are simulation graphs for comparing and analyzing the performance of the embodiments according to the present invention and the case of using the conventional decoder.

Hereinafter, various embodiments will be described in detail with reference to the accompanying drawings. In this case, it should be noted that the same components in the accompanying drawings are indicated by the same reference numerals as much as possible. In addition, it should be noted that the drawings of the present invention attached below are provided to help the understanding of the present invention, and the present invention is not limited to the form or arrangement illustrated in the drawings of the present invention. In addition, detailed descriptions of well-known functions and configurations that may obscure the gist of the present invention will be omitted. In the following description, only parts necessary for understanding the operation according to various embodiments of the present invention will be described, and it should be noted that descriptions of other parts will be omitted so as not to obscure the gist of the present invention.

1 is a conceptual diagram for explaining an FQAM scheme having a non-Gaussian characteristic.

1 shows three types of (a), (b), and (c) as examples. Referring to FIG. 1 , the form illustrated in (a) shows symbols 101, 102, 103, and 104 of the 4-QAM scheme as examples. _{In the 4-QAM method, S 1} (101), S ₂ (102), S ₃ (103), S mapped to the coordinates of the real (Re) axis and the imaginary (Im) axis as illustrated in (a) of FIG. 1 . _It is a form of transmitting data by mapping data to each symbol of 4 (104). In addition, the 4-FSK method illustrated in (b) is a method of mapping and transmitting data using a specific frequency band in four different frequency bands 111 , 112 , 113 , and 114 . For example, each of the frequency bands 111 , 112 , 113 , and 114 may be mapped to different data.

The FQAM method having non-Gaussian characteristics illustrated in FIG. 1(c) is a hybrid in which the 4-QAM method illustrated in FIG. 1(a) and the 4-FSK method illustrated in FIG. 1(b) are combined. ) is a modulation method. As illustrated in (c) of FIG. 1 , when data is mapped by combining the 4-QAM method and the 4-FSK method, the interference signal has a non-Gaussian characteristic similar to FSK. In addition, in the FQAM scheme illustrated in FIG. 1(c), the shapes of symbols 121, 122, 123, and 124 mapped to the 4-QAM scheme in each frequency band can be seen. Accordingly, the form illustrated in FIG. 1C is a 16-FQAM scheme. The FQAM modulation scheme can significantly improve spectral efficiency compared to the FSK modulation scheme by simultaneously applying the QAM modulation scheme.

In particular, in a cellular wireless communication method, a terminal located at an edge of a cell generally has a problem in that it is difficult to receive data at a high data rate. However, when the FQMA method is used, a statistical characteristic of inter-cell interference (hereinafter referred to as "ICI") in the terminal shows a non-Gaussian distribution. Since the channel capacity increases in the FQAM scheme as the non-Gaussian characteristic deepens, it is possible to enable data transmission with a higher capacity to the terminal located at the edge of the cell.

Then, a method of transmitting and receiving symbols using the above-described FQAM method will be described.

The binary IRPA code has a structure in which an outer code, which is a binary irregular repetition code, and an inner code composed of a trellis code having a code rate of 1 are connected through an interleaver. In this method, a message to be transmitted is received in bit units and all bits are repeated a predetermined number of times. In this case, the number of repetitions for each bit may not be uniform. These repeated bit streams are arbitrarily mixed through an interleaver, and then grouped by a predetermined number. The bit stream resulting from the grouping can be encoded using an internal encoder. That is, the binary IRPA encoder generates a binary non-canonical repeating code, is interleaved through an interleaver, and then is channel-encoded through a non-binary channel encoder. The coded codeword may be modulated through the FQAM modulator. The modulated signal may be transmitted to the receiver through a preset channel.

The receiver may demodulate the received signal in a demodulator to generate a soft message. The soft message generated in this way is decoded while iterating between the non-binary BCJR (Bahl-Cocke-Jelinek-Raviv) algorithm-based inner decoder and the binary outer decoder. In this case, the external decoder operates based on a bit log likelihood ratio (Bit Log Likelihood Ratio, hereinafter referred to as “LLR”) message and consists of a very simple calculation. In contrast, the inner decoder operates based on a symbol LLR vector that is a non-binary message.

Next, an internal configuration and operation of a decoder in a receiver receiving a signal according to the FQAM scheme according to the present invention will be described below.

2 is an internal block diagram of a binary IRPA code decoder to which an FQAM scheme can be applied according to an embodiment of the present invention.

Referring to FIG. 2 , it includes an external decoder 210 , an internal decoder 220 , an interleaver 201 , and a deinterleaver 202 . The external decoder 210 includes a message node calculation unit 211 , and the internal decoder 220 includes a first grouping unit 221 , an LLR symbol converting unit 222 , an LLR symbol cutting unit 223 , and a BJCR processing unit 224 . ), a bit LLR calculation unit 225 and a second bit grouping unit 226 .

Before describing the decoder of the present invention having such a configuration, let us briefly review the operation of the optimal internal decoding algorithm. In the optimal internal decoding algorithm calculation method, a grouping operation of messages exchanged with an external decoder is performed, and a lot of complex operations such as a look-up table are required for the BCJR algorithm operation of the internal decoder. In order to simplify this process, decoding may be performed using an approximation equation similar to a method used in a decoder of an existing turbo code and low density parity check (LDPC) code.

Then, with reference to FIG. 2, the operation of each block having the above configuration will be described. When the receiving apparatus receives the modulated signal and demodulation is performed, the demodulated signal is input to the BCJR processing unit 224 . It should be noted that the route through which the demodulated signal is received is not shown in FIG. 2 .

First, the BCJR (Bahl-Cocke-Jelinek-Raviv) algorithm is an algorithm for effectively calculating the posteriori LLR value of each code symbol in the inner decoder 220 . This LLR value includes information received from the channel and non-essential information of all symbols except for the symbol to be calculated, for example, LLR information received from the outer decoder 210 in the previous iteration. can be calculated as a combination of BCJR processing unit 224 is an algorithm that can effectively obtain post-processing (posteriori) LLR values through forward/backward recursion calculation similar to the Viterbi algorithm in the trellis of the inner code to be. Since the BCJR algorithm is a well-known algorithm, detailed operation descriptions will be omitted here.

Since there is no previous iteration in the state in which the first demodulated signal is input to the BCJR processing unit 224 , there is no information received from the external decoder 210 . Therefore, when receiving the first demodulated signal, the BCJR processing unit 224 may perform the algorithm by using only the demodulated signal or by setting the input of the external decoder to a specific value, for example, “0 (zero)”. As such, the value calculated according to the BCJR algorithm in the BCJR processing unit 224 is input to the bit LLR calculation unit 225 .

The bit LLR calculation unit 225 calculates the symbol LLR value calculated by the symbol BCJR algorithm in the BCJR processing unit 224 to become the bit LLR value. As such, the bit LLR value calculated as the bit LLR value by the bit LLR calculation unit 225 is input to the second bit grouping unit 226 . The second bit grouping unit 226 reduces the bit LLR value to a series of bit information, and outputs it to the deinterleaver 202 .

The deinterleaver 202 deinterleaves in a predetermined method, for example, the reverse of the method interleaved by the transmitter or the reverse of the method interleaved by the interleaver 201, and the deinterleaved bit information is converted into an external decoder. The message is output to the node calculation unit 211 of 210 . Then, the message node calculation unit 211 performs external decoding using the deinterleaved and input bit-by-bit information, and then outputs it to the interleaver 201 .

The result decoded by the external decoder 210 is input to the interleaver 201 . When the message calculated by the external decoder 210 is input, the interleaver 201 interleaves the demodulated signal using a preset interleaving method, for example, the same method as the method performed by the transmitter, and outputs it to the internal decoder 220 . In this case, the interleaver may perform interleaving in units of bits. Accordingly, the signal output from the interleaver 201 becomes an interleaved bit unit signal.

The first bit grouping unit 221 of the internal decoder 220 receives the interleaved bits from the interleaver 201 and groups them in a predetermined unit based on a preset method. This is a method for adjusting the code rate of the code. For example, 2 bits interleaved by the interleaver 201 may be grouped into one bit, 3 bits may be grouped into one bit, and 4 bits may be grouped into one bit. That is, a predetermined number of bits are grouped into one bit according to the code rate of the code.

The first bit grouping unit 221 converts the grouped data into LLR symbols. In this case, the first bit grouping unit 221 may approximate and use a message received from the external decoder 210 . For example, the first bit grouping unit 221 may perform logBP calculation by using a hypertangent (tanh), which is a non-linear function. In this case, the first bit grouping unit 221 may approximate and use the scaled min-sum method in a preset range used in the check node of the LDPC code. Calculation of a scaled min-sum method of a set range performed by the first bit grouping unit 221 may calculate a bit LLR value for each bit as shown in Equation 1 below.

In <Equation 1> a _n denotes the nth bit among grouped bits, c _{2n and} c _2n+1 denote bits before grouping, and Pr denotes a probability. In <Equation 1>, it is assumed that 2 bits are grouped. The LLR approximation of the grouped bits can be easily calculated by using the calculated value as in <Equation 1>.

In this case, the first bit grouping unit 221 may check whether decoding is successful through a parity check before determining the LLR value in units of bits. When there is no error in the information decoded through the parity check, interleaved data may be output as a decoding result. The parity error check for the decoding result may be performed every time iterative decoding is performed between the internal decoder 220 and the external decoder 210 .

As such, the information converted into the LLR symbol by the first bit grouping unit 221 is input to the LLR symbol converting unit 222 . The LLR symbol conversion unit 222 may calculate the LLR value of the m-bit symbol as shown in <Equation 2> by combining the probability values for each bit calculated in <Equation 1>.

The LLR symbol cutting unit 223 may sort the elements of the symbol LLR vector calculated by the LLR symbol converting unit 222 in the order of magnitude, and may select and cut _{n m messages in the order of the symbol LLR values.} That is, the LLR symbol cutting unit 223 may select and output only _{n m messages.} In this case, let us look at the elements that can adjust the _{n m selection values.}

First, when the channel environment is good, for example, when the SNR value is large, a small number of n _m values can be used. Conversely, when the channel environment is bad, a large number of n _m values must be used.

Second, when iterative decoding is performed between the outer decoder and the inner decoder, a large n _m value may be used in _{the first few iterations and a reduced n m} value may be used in subsequent iterations.

_{The n m} messages selected by the LLR symbol cutting unit 223 are processed by the BJCR algorithm in the BJCR processing unit 224 . _{As such, since only n m} messages inputted to the BJCR processing unit 224 are inputted from among symbol LLR vector messages, calculation complexity in the BCJR processing unit 224 can be reduced.

In this case, when the LLR symbol cutting unit 223 selects the LLR symbols, the elements of the calculated symbol LLR vector may be sorted and cut in the order of size as described above, and only _{n m arbitrarily in the q-ary symbol LLR vector are randomly cut.} Random truncation may also be performed. In the case of randomly truncating an arbitrary number _{of messages, it has the advantage that no additional complexity occurs in selecting n m} messages, but there are many cases where messages with high reliability are not selected, resulting in loss in performance. This can happen greatly. _{In addition, in the method of selecting n m} messages in large order after calculating q symbol LLR messages, the message with the highest reliability is selected, so if n _m values are appropriately selected, the performance loss is small. can occur On the other hand, additional complexity increases due to a sorting operation performed to select _{n m values in a large order.}

Subsequent operations of the bit LLR calculation unit 225 and the second bit grouping unit 226 are the same as described above. As such, when the decoding operation of the internal decoder 220 is completed, the deinterleaver 202 performs deinterleaving again, and then the external decoder 210 performs the external decoding. Iterative decoding between the external decoder 210 and the internal decoder 220 may be repeatedly performed until the decoding succeeds.

3 is a conceptual diagram illustrating a method of truncating a symbol LLR message in an FQAM scheme according to an embodiment of the present invention.

Referring to FIG. 3 , the grouped bit LLR messages 300 , 301 , 302 , 303 , and 304 have the same form as in Equation 1 described above. The bit LLR messages illustrated in FIG. 3 exemplify a case in which 5 bit LLR messages are configured as one group. However, 5 or more bit LLR messages may be configured in one group, and less than 5 bit LLR messages may be configured in one group.

As illustrated in FIG. 3 , probability values 310 , 311 , 312 , 313 and 314 of “0” and “1” may be extracted for each bit LLR message from each bit LLR message. After calculating the index as shown in reference numeral 320 by the combination of each bit index, it may be sequentially arranged or left as it is. _{Thereafter, by selecting n m} predetermined messages from among sequentially sorted or unsorted index values and truncating them as shown in reference numeral 330, only a selected part of the LLR messages can be extracted instead of all LLR messages.

4 is an internal block diagram of a binary IRPA code decoder to which an FQAM scheme can be applied according to another embodiment of the present invention.

Referring to FIG. 4 , it includes an external decoder 410 , an internal decoder 420 , an interleaver 401 and a deinterleaver 402 . The external decoder 410 includes a message node calculation unit 411, and the internal decoder 420 includes a first grouping unit 421, an LLR symbol selection unit 422, an LLR symbol converting unit 423, and a BJCR processing unit ( 424 ), a bit LLR calculation unit 425 , and a second bit grouping unit 426 .

Before describing the decoder of the present invention having such a configuration, let us briefly review the operation of the optimal internal decoding algorithm. In the optimal internal decoding algorithm calculation method, a grouping operation of messages exchanged with an external decoder is performed, and a lot of complex operations such as a look-up table are required for the BCJR algorithm operation of the internal decoder. In order to simplify this process, decoding may be performed using an approximation equation similar to a method used in a decoder of an existing turbo code and low density parity check (LDPC) code.

Then, with reference to FIG. 4, the operation of each block having the above configuration will be described. When the receiving apparatus receives the modulated signal and demodulation is performed, the demodulated signal is input to the BCJR processing unit 424 . It should be noted that the route through which the demodulated signal is received is not shown in FIG. 4 .

As described in FIG. 2 , the BCJR (Bahl-Cocke-Jelinek-Raviv) algorithm is an algorithm for effectively calculating the posteriori LLR value of each code symbol in the inner decoder 420 . This LLR value includes information received from the channel and non-essential information of all symbols except for the symbol to be calculated, for example, LLR information received from the outer decoder 410 in the previous iteration. can be calculated as a combination of The BCJR processing unit 424 is an algorithm that can effectively obtain a posteriori LLR value through forward/backward recursion calculation similar to the Viterbi algorithm in the trellis of the inner code. to be. Since the BCJR algorithm is a well-known algorithm, detailed operation descriptions will be omitted here.

In a state in which the first demodulated signal is input to the BCJR processing unit 424 , there is no previous iteration, so there is no information received from the external decoder 410 . Therefore, when receiving the first demodulated signal, the BCJR processing unit 424 may perform the algorithm by using only the demodulated signal or by setting the input of the external decoder to a specific value, for example, a value of “0 (zero)”. As such, the value calculated according to the BCJR algorithm in the BCJR processing unit 424 is input to the bit LLR calculation unit 225 .

The bit LLR calculation unit 425 calculates the symbol LLR value calculated by the symbol BCJR algorithm in the BCJR processing unit 424 to become the bit LLR value. As such, the bit LLR value calculated as the bit LLR value by the bit LLR calculation unit 425 is input to the second bit grouping unit 426 . The second bit grouping unit 426 reduces the bit LLR value to a series of bit information, and outputs it to the deinterleaver 402 .

The deinterleaver 402 deinterleaves in a predetermined method, for example, the reverse of the method interleaved by the transmitting device or the reverse of the method interleaved by the interleaver 401. The deinterleaved bit information is converted into an external decoder. It is output to the message node calculation unit 411 of 410 . Then, the message node calculator 411 performs external decoding using the deinterleaved and input bit-by-bit information, and then outputs it to the interleaver 201 .

The result decoded by the external decoder 410 is input to the interleaver 401 . When the message calculated by the external decoder 410 is input, the interleaver 401 interleaves the demodulated signal using a preset interleaving method, for example, the same method as the method performed by the transmitter, and outputs the interleaved signal to the internal decoder 420 . In this case, the interleaver may perform interleaving in units of bits. Accordingly, the signal output from the interleaver 401 becomes an interleaved bit unit signal.

The first bit grouping unit 421 of the internal decoder 420 receives the interleaved bits from the interleaver 401 and groups them in a predetermined unit based on a preset method. This is a method for adjusting the code rate of the code. For example, 2 bits interleaved in the interleaver 401 may be grouped into one bit, 3 bits may be grouped into one bit, and 4 bits may be grouped into one bit. That is, a predetermined number of bits are grouped into one bit according to the code rate of the code.

The first bit grouping unit 421 converts the grouped data into LLR symbols. In this case, the first bit grouping unit 421 may approximate and use a message received from the external decoder 410 . For example, the first bit grouping unit 421 may perform logBP calculation by using a hypertangent (tanh), which is a nonlinear function. In this case, the first bit grouping unit 421 may approximate and use the scaled min-sum method in a preset range used in the check node of the LDPC code. The calculation of the scaled min-sum method of the set range performed by the first bit grouping unit 421 may calculate the bit LLR value for each bit as in Equation 1 described above.

Also, at this time, the first bit grouping unit 421 may check whether decoding is successful through a parity check before determining the LLR value in units of bits. When there is no error in the information decoded through the parity check, interleaved data may be output as a decoding result. The parity error check for the decoding result may be performed every time iterative decoding is performed between the inner decoder 420 and the outer decoder 410 .

The LLR symbol selector 422 calculates the sign of the bit LLR using the calculated bit LLR value. The sign calculation of the bit LLR performed by the LLR symbol selector 422 may be performed as in Equation 3 below.

In <Equation 3>, pr denotes a probability value, and a _i denotes the i-th bit. Therefore, as in <Equation 3>, it is possible to determine which probability value is greater among the probability of being "0" and the probability of being "1" in the i-th bit by calculating the sign of the bit LLR value.

In the first bit grouping unit 421, grouping is performed in units of a specific number of bits, which is determined according to a code rate as described above. For example, when the modulation order is the fifth order, a 5-bit unit is mapped to one LLR symbol. Therefore, one LLR symbol unit may be 5 bits.

The LLR symbol selector 422 may select an index having a maximum value for each of the bits grouped in LLR symbol units as described above. Assuming that the modulation order is the fifth order, the sign of each bit LLR value grouped in units of 5 bits may be determined as illustrated in Equation 4 below.

For example, assuming that the value exemplified in <Equation 4> has the maximum value, the index value of <Equation 4> may be a value calculated from each bit. For example, a ₀ =0, a ₁ =1, a ₂ =1, a ₃ =0, a ₄ =0. Accordingly, since the index composed of (a _{4 ,a 3} ,a ₂ ,a ₁ ,a ₀ ) means a value of “00110”, index 6 becomes the symbol LLR value having the maximum value.

The LLR symbol selector 422 may _{store the index value S max} having the maximum value in a memory (not shown). In addition, the probability that the symbol LLR value of the index having as few bits as possible flipped from the index having the maximum value has a large value is increased. Accordingly, the LLR symbol selector 422 may select LLR symbols to be used in the BCJR algorithm by flipping some bits in the index value having the maximum value.

The LLR symbol selector 422 should output a predetermined number of grouped bit streams that are LLR symbol units. Accordingly, the LLR symbol selector 422 may output grouped bit streams in which only one bit is flipped or up to two bits are flipped in the index having the maximum value.

Then, the LLR symbol conversion unit 423 may convert the received bit LLR value into a symbol LLR and output the converted bit LLR value to the BJCR processing unit 424 .

The BJCR processing unit 424 receives the LLR symbols in which the symbols selected by the LLR symbol selection unit 422 are converted by the LLR symbol converting unit 423 and performs BJCR algorithm processing. The BJCR algorithm has already been described with reference to FIG. 2 described above, and since it is a well-known algorithm for other operations, detailed operation descriptions will be omitted here. As such, since only a predetermined number of messages input to the BJCR processing unit 424 is inputted from among all symbol LLR vector messages, calculation complexity in the BCJR processing unit 424 can be reduced.

Since the operations of the bit LLR calculation unit 425 and the second bit grouping unit 426 have already been described above, they will be omitted. In addition, iterative decoding between the external decoder 410 and the internal decoder 420 may be performed until the decoding succeeds or as many as a preset number of iterative decoding.

5 is a conceptual diagram for explaining a method of truncating a symbol LLR message in an FQAM scheme according to an embodiment of the present invention.

Referring to FIG. 5 , the grouped bit LLR messages 500 , 501 , 502 , 503 , and 504 have the same form as in Equation 1 described above. The bit LLR messages illustrated in FIG. 5 exemplify a case in which 5 bit LLR messages are configured as one group. However, 5 or more bit LLR messages may be configured in one group, and less than 5 bit LLR messages may be configured in one group. As such, a unit in which bit LLR messages are configured as one group may be determined according to a code rate.

As illustrated in FIG. 5 , sign values 510 , 511 , 512 , 513 , and 514 of the bit LLR may be extracted for each bit LLR message from each bit LLR message. An index (S value) having a maximum value among symbol LLR values as indicated by reference numeral 520 may be calculated for the extracted code values. Thereafter, an index of a symbol LLR to be calculated is determined as shown in reference numeral 530, and only a symbol LLR value corresponding to the determined index can be calculated as shown in reference numeral 540. Symbol LLR values corresponding to the determined index may be exemplified by reference numerals 550a, 550b, and 550c.

Let us take an example of the operation of Figs. 4 and 5 described above.

Assume that the modulation order q is 32 and the predetermined number of messages to be selected (n _m ) is 20. Then, when the modulation order is 32, the multiplier is 5 (2 ⁵ ) when calculated in binary code, so it has a 5-bit LLR value. In this case, it is assumed that the sign of each bit LLR value is determined as exemplified in Equation 4 described above.

As described above, when having a sign as exemplified in <Equation 4>, a combination having a maximum value should be selected, and according to <Equation 4>, the index value may be a value of “00110”.

In this case, since it is necessary to generate the required number of indexes, it is possible to generate indexes that flip all one bit, two bits, three bits, four bits, and five bits in the corresponding symbol index. As such, the indexes flipped for each bit can be exemplified as shown in Table 1 below.

As exemplified in <Table 1>, from the index of the symbol LLR having the maximum value, from the index of the symbol LLR having the maximum value, from the index of the symbol LLR having the maximum value after generating from the index that is flipped by 1 bit to the index where all of the 5 bits are flipped We can select _{n m} indices sequentially from the least flipped value. Let's take a look at the 1-bit flipped index in <Table 1> above.

The index having the maximum value becomes "00110". Therefore, flipping one bit means inverting only one bit of each bit of the index having the maximum value. Accordingly, if the least significant bit is flipped one bit at a time, the flipped bit groups in the order of "00111", "00100", "00010", "01110", and "10110" may be expressed. <Table 1> shows a case in which each bit is flipped and a case in which each bit is flipped in this order.

In the above example, since n _m is set to 20, the total number of 1-bit flipped indexes is 5, and thus does not satisfy the set number. Therefore, two-bit blipped indexes must be additionally considered. Since the total number of 2-bit flipped indexes is 10, even if all of the index having the maximum value, 1-bit flipped indexes, and 2-bit flipped indexes are all selected, only 16 groups in total can be selected. Therefore, it is necessary to additionally select 4 additional 3-bit flipped indexes.

However, as can be seen from <Table 1>, there are 10 3-bit flipped indexes. Therefore, if four are added in the order listed in <Table 1> in the 3-bit flipped indexes, indexes up to "01000" among the 3-bit flipped indexes of <Table 1> may be selected.

In this case, a method of selecting some of the symbol index values obtained by flipping the same number of bits will be described.

First, a necessary number may be randomly selected from among all target symbol indices in which the same number of bits is flipped.

Second, the bit having the largest value is obtained by comparing the absolute values of the LLR values of m bits. If the absolute value of the LLR of the i-th bit is the largest, the i-th bit may be sequentially selected from among all symbol indices in which the same number of bits is flipped.

Third, the absolute values of the m bit LLR values are arranged in order of magnitude. Among all symbol indices in which the same number of bits is flipped, values having a smaller absolute value may be selected first from the flipped symbol index.

Among the three methods described above, the first has the lowest complexity, and the second and third methods have the highest complexity. Also, there is little difference in decoding performance for the three methods.

Thereafter, in the operation of calculating the symbol LLR, only the symbol LLR value corresponding to the previously selected indices may be calculated using the LLR value of each bit. For example, it is calculated as shown in Table 2 below.

As shown in <Table 2>, both the selected index value and the symbol LLR value can be calculated and stored. The calculated symbol LLR value may then be calculated through the BCJR algorithm.

6 is a control flowchart of a symbol decoding operation in a decoder according to an embodiment of the present invention. In the description of FIG. 6 , it will be described using the block configuration of FIG. 4 .

Referring to FIG. 6 , a receiver receiving a signal transmitted from a transmitter may demodulate it. The BCJR processing unit 424 of the internal decoder 420 receives a demodulated signal from the demodulator in step 600 . Thereafter, the BCJR processing unit 424 performs a non-binary BCJR algorithm in step 602 . Since the non-binary BCJR algorithm is a well-known algorithm, it will not be described in detail here.

The non-binary BCJR algorithm-processed data in the BCJR processing unit 424 is input to the bit LLR calculation unit 425 to perform post-processing (posteriori) LLR message calculation in step 604 . Thereafter, the second bit grouping unit 426 performs grouping in a predetermined bit unit using the output of the bit LLR calculation unit 425 in step 606 .

Data grouped by the second bit grouping unit 426 is input to the deinterleaving unit 402 . The deinterleaver 402 deinterleaves bit by bit in step 608 and outputs the deinterleaved bit string to the external decoder 410 . In this case, the deinterleaving may be the reverse process of the interleaving method performed by the transmitting apparatus or the reverse process of the interleaving method performed by the interleaver 401 as described above.

The message node calculator 411 of the external decoder 410 calculates the message node in step 610 and outputs the calculated result to the interleaver 201 . The interleaver 401 performs interleaving in step 612 . The interleaving method in the interleaver 401 may be performed in the same manner as the interleaving method in the transmitting apparatus as described above.

The bit string interleaved by the interleaver 401 is input to the internal decoder 420 . The first bit grouping unit 421 of the internal decoder 420 may group bits of a predetermined unit, and the grouping unit may be determined according to a code rate. For example, as described above, it may be in units of 5 bits.

Thereafter, the first bit grouping unit 421 may perform a parity check using the grouped data in step 616 . If the first bit grouping unit 421 performs the parity check using the grouped data and the decoding is successful, the process proceeds to step 618 and outputs the decoding result.

On the other hand, if the first bit grouping unit 421 performs a parity check using the grouped data and the decoding fails, the process proceeds to step 620 . If the decoding fails, the LLR symbol converter 422 divides the bit LLR message into predetermined units, for example, m units, determines a sign, and calculates an index having the maximum symbol LLR value in step 620 . _{Thereafter, the LLR symbol converter 422 may calculate n m} indices to be used in the BCJR algorithm by using the flipping method of the index having the maximum symbol LLR value in step 622 . This can be done using the methods discussed in Table 2 above.

Thereafter, although not shown in FIG. 6 , the LLR symbol conversion unit 423 may convert _{LLR values corresponding to the selected n m} indexes into LLR symbols and output the LLR values to the BCJR processing unit 424 .

Let's take a look at the method described above with respect to complexity through an example.

It is assumed that the modulation order (q) is 32, the number of messages (n _m ) to be selected is 20, and the number of information bits is 960 bits. Also, assume that the code rate is 1/3.

In this case, a case in which 20 messages of a symbol LLR vector are selected using the method of sorting with a maximum value, which is the method of FIGS. 2 and 3 according to the first embodiment, will be described.

When 20 messages to select (n _m ) are selected, the amount of computation that is reduced due to message selection is reduced by about 23.7% of that of the existing algorithm. In addition, the amount of computation additionally generated due to the use of sorting increases by about 31.6% of that of the existing algorithm. Therefore, when there are 20 messages to select, the complexity increases by about 7.9% compared to the existing algorithm. The reason for this increase in complexity is that an additional operation due to sorting is required.

Next, a case in which the method of selecting and calculating only the symbol LLR described with reference to FIGS. 4 to 6, which is the second embodiment, is applied will be described.

In the case of the second embodiment, the amount of computation is reduced by about 33.1% compared to the existing algorithm due to the decrease in the number to be selected. In addition, the amount of computation additionally generated to select the symbol LLR computation index increases by about 2.5% compared to the computation amount of the existing algorithm. Therefore, overall, the complexity is reduced by about 30.6% compared to the existing algorithm. Therefore, it can be confirmed that, when the second embodiment is applied, the complexity of the decoder can be improved compared to the existing decoder.

7A and 7B are simulation graphs for comparing and analyzing the performance of the embodiments according to the present invention and the case of using the conventional decoder.

In FIG. 7A, the information bit was set to 960 bits, the modulation order was set to the 32nd order (4FSK+8PSK), and the doping period was set to 30. Also, the code rate was set to 1/3.

Referring to FIG. 7A , the existing decoder has coordinates of “Δ”, the scheme according to the first embodiment has coordinates of “○”, and the scheme according to the second embodiment has coordinates of “□”. It can be seen that in both the first and second embodiments, a performance loss of 0.1 dB or less occurs compared to the conventional decoder. Therefore, there is no significant performance degradation in both methods.

In FIG. 7b, the information bit was set to 960 bits, the modulation order was set to: 32 order (8FSK+4PSK), and the doping period was set to 30. Also, the code rate was set to 1/3.

Referring to FIG. 7B , the existing decoder has coordinates of “Δ”, the scheme according to the first embodiment has coordinates of “○”, and the scheme according to the second embodiment has coordinates of “□”. It can be seen that the method using the first embodiment causes a loss of about 0.3 dB compared to the case of using the conventional decoder, and the method using the second embodiment causes a loss of about 0.2 dB. Therefore, it can be seen that the performance degradation is less when the second embodiment is applied than when the first embodiment is applied.

The embodiments disclosed in the present specification and drawings described above are merely provided as specific examples to easily explain the contents of the present invention and help understanding, and are not intended to limit the scope of the present invention. Therefore, the scope of the present invention should be construed as including all changes or modifications derived based on the technical spirit of the present invention in addition to the embodiments disclosed herein are included in the scope of the present invention.

201, 401: interleaver 202, 402: deinterleaver
210, 410: external decoder 220, 420: internal decoder
211, 411: message node calculation unit 221, 421: first bit grouping unit
222, 423: LLR symbol conversion unit 223: LLR symbol cutting unit
224, 424: BCJR processing unit 225, 425: bit LLR calculation unit
226, 426: second bit grouping unit 422: LLR symbol index conversion unit

Claims (20)

In the internal decoder for decoding a signal received in a receiver device having an external decoder and an internal decoder in a system using a binary non-canonical repeating partial accumulation code, the internal decoder comprising:
BCJR (Bahl-Cocke-Jelinek-Raviv) algorithm calculation so that the received signal becomes a post-processing Log Likelihood Ratio (LLR) value of each code symbol or the output of the LLR symbol converter BCJR processing unit for receiving and calculating BCJR;
a bit LLR calculation unit converting the output of the BCJR processing unit into a bit LLR value;
a second bit grouping unit for grouping the bit LLR values in a predetermined bit unit and outputting them to the external decoder;
By grouping the bit string of the bit LLR message received from the external decoder into LLR symbols by grouping the number of bits according to the modulation order of the signal received at the receiver device, parity check of the converted LLR symbol is performed, a first grouping unit for determining whether decoding succeeds, and for determining bit LLR values of bits constituting each LLR symbol when decoding fails;
When decoding fails in the first grouping unit, for each of the bit LLR values of each bit constituting the LLR symbol for each received LLR symbol, the ratio of the probability that the LLR value of each bit is “0” to the probability that the LLR value is “1” to determine the sign of each bit LLR value, calculate the index of each LLR symbol by using the sign of the determined bit LLR value for each bit of each LLR symbol, and use the calculated LLR symbol index an LLR symbol selector for selecting and outputting bit LLR values so as to be a predetermined number of LLR symbols; and
The LLR symbol conversion unit for converting the bit LLR value output from the LLR symbol selection unit into a symbol LLR value and outputting the converted bit LLR value to the BCJR processing unit. A receiver device having an external decoder and an internal decoder for The method of claim 1, wherein the LLR symbol selector,
In a system using a binary non-regular repeating partial accumulation code, which generates flipped indexes by flipping the calculated LLR symbol index bit by bit until the calculated index of the LLR symbol becomes a preset number of indexes. A receiver device having an external decoder and an internal decoder for decoding a received signal. The method of claim 2, wherein the LLR symbol selector,
There are two or more flipped indexes generated by flipping the same number of bits among the generated indices, and when selecting the bit LLR values to become the predetermined number of LLR symbols, the same number of bits is flipped to When the predetermined number is satisfied when only a part of the flipped index is output among the generated flipped indices, the predetermined number in each of the flipped index bits of all the flipped indexes in which the same number of bits is flipped A receiver apparatus having an external decoder and an internal decoder for decoding a signal received in a system using a binary non-regular repeating partial accumulation code, which is randomly selected as many as necessary to satisfy . The method of claim 2, wherein the LLR symbol selector,
There are two or more flipped indexes generated by flipping the same number of bits among the generated indices, and when selecting the bit LLR values to become the predetermined number of LLR symbols, the same number of bits is flipped to When the predetermined number is satisfied when only a part of the flipped index is output among the generated flipped indexes, for each LLR symbol from among all the flipped index bits of all the flipped indexes flipping the same number The LLR symbols having the large absolute value of the bit LLR values constituting the LLR symbol are aligned, and the LLR symbol having the smallest absolute value from the flipped indices corresponding to the LLR symbol having the large absolute value. A receiver apparatus having an external decoder and an internal decoder for decoding a signal received in a system using a binary non-canonical iterative partial accumulation code, which sequentially selects the flipped indexes in order until the predetermined number of LLR symbols are satisfied . The method of claim 2, wherein the LLR symbol selector,
There are two or more flipped indexes generated by flipping the same number of bits among the generated indices, and when selecting the bit LLR values to become the predetermined number of LLR symbols, the same number of bits is flipped to When the predetermined number is satisfied when only a part of the flipped index is output among the generated flipped indexes, each LLR symbol in each of the flipped index bits of all the flipped indexes generated by flipping the same number sorts the LLR symbols having a small absolute value of bit LLR values constituting the LLR symbol with respect to , and from the flipped indices corresponding to the LLR symbol having a small absolute value, the absolute value is large. Having an external decoder and an internal decoder for decoding a signal received in a system using a binary non-canonical repeating partial accumulation code that sequentially selects the flipped indices until the predetermined number of LLR symbols are satisfied in the order of LLR symbols receiver device. According to claim 1,
The predetermined number of bit LLR values output from the LLR symbol selector is determined according to a channel environment, and a receiver having an external decoder and an internal decoder for decoding a signal received in a system using a binary non-regular repeating partial accumulation code. Device. delete A decoding method in the inner decoder for decoding a signal received in a receiver device having an outer decoder and an inner decoder in a system using a binary non-regular repeating partial accumulation code, the decoding method comprising:
BCJR (Bahl-Cocke-Jelinek-Raviv) algorithm calculation so that the received signal becomes a post-processing Log Likelihood Ratio (LLR) value of each code symbol or the output of the LLR symbol converter receiving and calculating BCJR;
converting a value calculated by the BCJR algorithm into a bit LLR value; and
grouping the bit LLR values in predetermined bit units and providing them to the external decoder;
converting the bit string of the bit LLR message received from the external decoder into LLR symbols by grouping the bit string into the number of bits according to the modulation order of the received signal at the receiver device;
determining whether decoding succeeds by performing a parity check on the converted LLR symbol;
determining bit LLR values of each bit constituting each LLR symbol when decoding fails as a result of the parity check;
When the decoding fails, for each of the bit LLR values of each bit constituting the LLR symbol for each received LLR symbol, each bit using a ratio of the probability that the LLR value of each bit is “0” to the probability that it is “1” determining the sign of the LLR value;
calculating an index of each LLR symbol by using the sign of the determined bit LLR value for each bit of each LLR symbol;
selecting bit LLR values to be a predetermined number of LLR symbols using the calculated LLR symbol index;
converting the selected bit LLR value into a symbol LLR value; and
Repeating the converted symbol LLR value to perform the BCJR algorithm calculation in the internal decoder of a receiver device having an external decoder and an internal decoder for iterative decoding in a system using a binary non-regular repeating partial accumulation code, including: Decryption method. 9. The method of claim 8,
When bit LLR values are selected to be the predetermined number of LLR symbols, the calculated LLR symbol index is flipped bit by bit to generate flipped indexes until the predetermined number is satisfied. A decoding method in an internal decoder of a receiver device having an external decoder and an internal decoder for decoding a signal received in a code-using system. 10. The method of claim 9,
When bit LLR values are selected to be the predetermined number of LLR symbols, the flipped index generated by flipping the same number of bits among the calculated LLR symbol indices is two or more, and the predetermined number of LLR symbols When the bit LLR values are selected, only a part of the flipped index among the flipped indexes generated by flipping the same number of bits is output to satisfy the predetermined number of bits in which the same number of bits is flipped External for decoding a signal received in a system using a binary non-normal repeating partial accumulation code, which randomly selects a necessary number to satisfy the predetermined number in each of the flipped index bits of all the flipped indexes A decoding method in an internal decoder of a receiver device having a decoder and an internal decoder. 10. The method of claim 9,
When bit LLR values are selected such that the predetermined number of LLR symbols are selected, the number of the flipped indexes generated by flipping the same number of bits among the calculated LLR symbol indices is two or more, and generated by flipping the same number of bits When the predetermined number is satisfied when only a part of the flipped index from among the flipped indices is output, the same number of flipped index bits among all the flipped index bits of the flipped index is the above for each LLR symbol. The LLR symbols having a large absolute value of bit LLR values constituting the LLR symbol are aligned, and LLR symbols having a small absolute value from the flipped indices corresponding to the LLR symbol having a large absolute value. A receiver device having an external decoder and an internal decoder for decoding a signal received in a system using a binary non-canonical iterative partial accumulation code, which sequentially selects the flipped indices until satisfying the predetermined number of LLR symbols in order Decoding method in internal decoder. 10. The method of claim 9,
When bit LLR values are selected so as to be the predetermined number of LLR symbols, the flipped index generated by flipping the same number of bits among the calculated indices of the LLR symbol is two or more, and the predetermined number of LLR symbols is When the bit LLR values are selected, only a part of the flipped index among the flipped indexes generated by flipping the same number of bits should be output so that the predetermined number is satisfied by flipping the same number In each of the flipped index bits of all the flipped indexes, for each LLR symbol, the LLR symbols having a small absolute value of bit LLR values constituting the LLR symbol are arranged, and the absolute value is small. A binary non-regular repeating partial accumulation code that sequentially selects the flipped indices until the predetermined number of LLR symbols are satisfied in the order of the LLR symbols having the largest absolute value from the flipped indexes corresponding to the LLR symbol having A decoding method in an internal decoder of a receiver device having an external decoder and an internal decoder for decoding a signal received in the system in use. 9. The method of claim 8,
The predetermined number of bit LLR values is determined according to a channel environment, and decoding in an internal decoder of a receiver device having an external decoder and an internal decoder for decoding a signal received in a system using a binary non-canonical repeating partial accumulation code Way. delete delete delete delete delete delete delete

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