KR102273622B1 - 거대한 페이지들을 지원하는 메모리 관리 - Google Patents

거대한 페이지들을 지원하는 메모리 관리 Download PDF

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KR102273622B1
KR102273622B1 KR1020197011367A KR20197011367A KR102273622B1 KR 102273622 B1 KR102273622 B1 KR 102273622B1 KR 1020197011367 A KR1020197011367 A KR 1020197011367A KR 20197011367 A KR20197011367 A KR 20197011367A KR 102273622 B1 KR102273622 B1 KR 102273622B1
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page
data
main memory
memory
size
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KR20190052106A (ko
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조엘 딜런 코번
알버트 보처스
크리스토퍼 라일 존슨
로버트 에스. 스프린클
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구글 엘엘씨
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    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0866—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches for peripheral storage systems, e.g. disk cache
    • G06F12/0873—Mapping of cache memory to specific storage devices or parts thereof
    • G—PHYSICS
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    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/10—Address translation
    • G06F12/1009—Address translation using page tables, e.g. page table structures
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    • G06F12/0223—User address space allocation, e.g. contiguous or non contiguous base addressing
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    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
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    • G06F12/0868—Data transfer between cache memory and other subsystems, e.g. storage devices or host systems
    • G—PHYSICS
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    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
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    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
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    • G06F12/0871—Allocation or management of cache space
    • G—PHYSICS
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    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0893—Caches characterised by their organisation or structure
    • G06F12/0897—Caches characterised by their organisation or structure with two or more cache hierarchy levels
    • G—PHYSICS
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    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/10—Address translation
    • G06F12/1027—Address translation using associative or pseudo-associative address translation means, e.g. translation look-aside buffer [TLB]
    • G—PHYSICS
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    • G06F12/12—Replacement control
    • G—PHYSICS
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    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0806—Multiuser, multiprocessor or multiprocessing cache systems
    • G06F12/0815—Cache consistency protocols
    • G—PHYSICS
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    • G06F2212/1016—Performance improvement
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    • G06F—ELECTRIC DIGITAL DATA PROCESSING
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    • G06F2212/10—Providing a specific technical effect
    • G06F2212/1016—Performance improvement
    • G06F2212/1024—Latency reduction
    • G—PHYSICS
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    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/15—Use in a specific computing environment
    • G06F2212/152—Virtualized environment, e.g. logically partitioned system
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/30—Providing cache or TLB in specific location of a processing system
    • G06F2212/304—In main memory subsystem
    • G06F2212/3042—In main memory subsystem being part of a memory device, e.g. cache DRAM
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/30—Providing cache or TLB in specific location of a processing system
    • G06F2212/305—Providing cache or TLB in specific location of a processing system being part of a memory device, e.g. cache DRAM
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/60—Details of cache memory
    • G06F2212/604—Details relating to cache allocation
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/65—Details of virtual memory and virtual address translation
    • G06F2212/652—Page size control

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
KR1020197011367A 2016-09-22 2017-08-25 거대한 페이지들을 지원하는 메모리 관리 Active KR102273622B1 (ko)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US15/273,433 2016-09-22
US15/273,433 US10108550B2 (en) 2016-09-22 2016-09-22 Memory management supporting huge pages
PCT/US2017/048663 WO2018057235A1 (en) 2016-09-22 2017-08-25 Memory management supporting huge pages

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Publication Number Publication Date
KR20190052106A KR20190052106A (ko) 2019-05-15
KR102273622B1 true KR102273622B1 (ko) 2021-07-06

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US (2) US10108550B2 (https=)
EP (1) EP3516526B1 (https=)
JP (1) JP6719027B2 (https=)
KR (1) KR102273622B1 (https=)
CN (2) CN116701250A (https=)
DK (1) DK3516526T3 (https=)
IE (2) IE20170188A1 (https=)
SG (2) SG10201903332RA (https=)
WO (1) WO2018057235A1 (https=)

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CN111913893A (zh) * 2020-06-22 2020-11-10 成都菁蓉联创科技有限公司 保留内存的映射方法和装置、设备和存储介质
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CN112148736B (zh) * 2020-09-23 2024-03-12 抖音视界有限公司 缓存数据的方法、设备及存储介质
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CN113608866B (zh) * 2021-07-13 2024-10-25 阿里巴巴创新公司 内存分配方法及装置
CN115904642A (zh) * 2021-08-19 2023-04-04 北京字节跳动网络技术有限公司 云服务器控制方法、装置、存储介质及电子设备
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DK3516526T3 (da) 2020-11-30
US20180081816A1 (en) 2018-03-22
WO2018057235A1 (en) 2018-03-29
CN109791523B (zh) 2023-07-14
SG10201903332RA (en) 2019-05-30
JP2019532450A (ja) 2019-11-07
EP3516526A1 (en) 2019-07-31
US10108550B2 (en) 2018-10-23
IE20170188A1 (en) 2018-04-04
KR20190052106A (ko) 2019-05-15
JP6719027B2 (ja) 2020-07-08
IE20180302A1 (en) 2018-10-31
SG10201707699VA (en) 2018-04-27
US10474580B2 (en) 2019-11-12
CN116701250A (zh) 2023-09-05
US20180365157A1 (en) 2018-12-20
CN109791523A (zh) 2019-05-21
IE87058B1 (en) 2019-10-16
EP3516526B1 (en) 2020-10-14

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